Manufacturing method for nitride semiconductor multilayer reflector, vertical cavity surface emitting laser wafer, and vertical cavity surface emitting laser

Abstract

Provided is a manufacturing method for a semiconductor multilayer reflector, the method involving stacking semiconductor layers with mutually different refractive indices on a substrate. The substrate is a GaN substrate on which AlInN layers and GaN layers are alternately grown. The In composition of AlInN is within a range of 18.9-20.0 % in which lattice mismatch occurs with respect to the GaN layers at room temperature.

Description

Method for manufacturing nitride semiconductor multilayer reflector, vertical cavity surface emitting laser wafer, and vertical cavity surface emitting laser

[0001] The present invention relates to a method for manufacturing a nitride semiconductor multilayer reflector, a vertical cavity surface emitting laser wafer, and a vertical cavity surface emitting laser.

[0002] BACKGROUND ART Conventionally, vertical cavity light emitting devices such as vertical cavity surface emitting lasers (VCSELs) have been known which have a structure in which light is resonated perpendicular to a substrate surface and emitted in a direction perpendicular to the substrate surface.

[0003] A vertical cavity light emitting diode (VCSEL) uses a semiconductor distributed Bragg reflector (DBR), which is a semiconductor multilayer film reflector, to form a cavity.

[0004] Conventionally, nitride semiconductor multilayer reflecting mirrors have been known in which a plurality of pairs of AlInN layers and GaN layers having different refractive indices are stacked. For example, Patent Document 1 discloses that the AlInN layers stacked first to last have the same In composition and are lattice-matched to the GaN layer, controlling the growth conditions.

[0005] Furthermore, Patent Document 2 describes that in a multilayer film reflector of a vertical cavity light emitting device, when the In composition of the AlInN film is 18%, the lattice constants of the AlInN film and the GaN film become approximately the same, and that the In composition of the AlInN film is preferably less than 18%. Patent Document 3 describes that InAlN is lattice matched with GaN when the In composition is 17% to 18%.

[0006] JP 2021-34632 A JP 2018-73853 A JP 2018-56299 A

[0007] The In composition range of AlInN for lattice matching with GaN at room temperature that has been the focus of attention in the past has been approximately 17% to 18%, and so research and development has been carried out on this In composition range for the semiconductor DBR of vertical-cavity surface-emitting lasers.

[0008] However, it has been found that when crystal growth of a semiconductor DBR is carried out under lattice-matching conditions at room temperature, stress in the growth layer causes warping of the DBR substrate, which is unacceptable for a device.

[0009] The present invention was made based on this finding, and aims to provide a method for manufacturing a nitride semiconductor multilayer reflector that can obtain a DBR substrate that is small in warp, flat, and has a uniform reflection wavelength within the substrate surface, and also aims to provide a vertical cavity surface emitting laser wafer that has a DBR substrate that is flat and has a uniform reflection wavelength within the substrate surface, and has a uniform emission wavelength, and a high-performance vertical cavity surface emitting laser with small variations in resonance wavelength.

[0010] A method for manufacturing a nitride semiconductor multilayer reflector according to one embodiment of the present invention is a method for manufacturing a semiconductor multilayer reflector by stacking semiconductor layers having refractive indices different from each other on a substrate, wherein the substrate is a GaN substrate, and AlInN layers and GaN layers are grown alternately on the substrate, and the In composition of the AlInN layers is within a range of 18.9% to 20.0%, at which lattice mismatch occurs with the GaN layer at room temperature.

[0011] According to another embodiment of the present invention, there is provided a vertical cavity surface emitting laser wafer having a nitride semiconductor multilayer reflector formed on a substrate, the vertical cavity surface emitting laser wafer having: a first semiconductor layer of a first conductivity type, a second semiconductor layer of a conductivity type opposite to the first conductivity type, and an active layer sandwiched between the first semiconductor layer and the second semiconductor layer, all formed on the nitride semiconductor multilayer reflector; the substrate is a GaN substrate; the nitride semiconductor multilayer reflector is configured by alternately stacking AlInN layers and GaN layers; and the In composition of the AlInN layer is within a range of 18.9% to 20.0%, at which lattice mismatch with the GaN layer occurs at room temperature.

[0012] According to yet another embodiment of the present invention, there is provided a vertical cavity surface emitting laser having a nitride semiconductor multilayer reflector formed on a substrate, the vertical cavity surface emitting laser comprising: a first semiconductor layer of a first conductivity type formed on the nitride semiconductor multilayer reflector; a second semiconductor layer of a conductivity type opposite to the first conductivity type; an active layer sandwiched between the first semiconductor layer and the second semiconductor layer; and a multilayer reflector formed on the second semiconductor layer and constituting a resonator together with the nitride semiconductor multilayer reflector; wherein the substrate is a GaN substrate; the nitride semiconductor multilayer reflector is formed by alternately stacking AlInN layers and GaN layers; and the In composition of the AlInN layer is within a range of 18.9% to 20.0%, at which lattice mismatch with the GaN layer occurs at room temperature.

[0013] 1 is a cross-sectional view schematically showing the structure of a semiconductor DBR substrate according to a first embodiment of the present invention; FIG. 2 is a cross-sectional view schematically showing a tray used in crystal growth of a semiconductor DBR and a cross-section of a growth substrate placed on the tray; FIG. 3 is a diagram showing the structure of a tray in a top view; FIG. 4 is a flowchart showing a method for manufacturing a semiconductor DBR substrate; FIG. 5 is a diagram showing plots of the amount of warpage in the X and Y directions of epitaxial layer 1; FIG. 6 is a diagram showing plots of the amount of warpage in the X and Y directions of epitaxial layer 2; FIG. 7 is a top view showing measurement points of the reflection spectrum of a semiconductor DBR substrate; FIG. 8 is a diagram showing an overlapping of the reflection spectrum at each measurement point of epitaxial layer 1; FIG. 9 is a diagram showing an overlapping of the reflection spectrum at each measurement point of epitaxial layer 2; FIG. 10 is a diagram showing an overlapping of the reflection spectrum at each measurement point of epitaxial layer 3; and FIG. 11 is a diagram showing the lattice matching condition of AlInN to GaN versus growth temperature. A top view schematically showing a vertical cavity surface emitting laser wafer according to a second embodiment. FIG. 10 is a cross-sectional view schematically showing the structure of a vertical-cavity surface-emitting laser according to a third embodiment.

[0014] In the following, preferred embodiments of the present invention will be described, but these may be modified and combined as appropriate. In the following description and accompanying drawings, substantially the same or equivalent parts are designated by the same reference numerals.

[0015] [First Embodiment] (1) Structure of Semiconductor Multilayer Reflector Substrate FIG. 1 is a cross-sectional view schematically showing the structure of a substrate 10 on which a nitride semiconductor multilayer reflector according to a first embodiment of the present invention is formed (hereinafter referred to as a semiconductor DBR substrate).

[0016] The growth substrate 11 used for crystal growth is a C-plane GaN substrate whose crystal growth surface is the C-plane. Specifically, it is a C-plane GaN substrate, which is a so-called off-substrate, in which the crystal growth surface is tilted from the C-plane by 0.5° toward the M-plane and by 0±0.1° toward the A-plane. Note that the substrate is not limited to an off-substrate, and may also be a so-called just-substrate.

[0017] The growth substrate 11 had a circular shape with a diameter of 2 inches and a thickness of 400 μm. It is more preferable that the growth substrate 11 has a diameter of 2 inches or more.

[0018] Crystal growth of the semiconductor DBR 12 was performed by metalorganic vapor phase epitaxy (MOVPE) on the growth substrate 11. The semiconductor DBR 12 is formed by alternately stacking AlInN layers (first thin films) 12A and GaN layers (second thin films) 12B, which are semiconductor layers with different refractive indices and an optical film thickness of ¼ wavelength.

[0019] More specifically, the semiconductor DBR 12 is configured by laminating k pairs (k is a natural number) of AlInN layers 12A and GaN layers 12B. Here, the semiconductor DBR 12 is made up of 46 pairs (k=46) of AlInN layers 12A and GaN layers 12B.

[0020] The AlInN layer 12A and the GaN layer 12B have thicknesses that result in a central reflection wavelength of 450 nm. Specifically, the AlInN layer 12A has a thickness of 50 nm, and the GaN layer 12B has a thickness of 45.0 nm. The total thickness of the semiconductor DBR 12 is 4.39 μm.

[0021] FIG. 2 is a cross-sectional view showing a tray 100 used for crystal growth of a semiconductor DBR 12 and a cross section of a growth substrate 11 placed on the tray 100, and FIG. 3 is a diagram showing the structure of the tray 100 as viewed from above.

[0022] In this embodiment, a tray 100 is used to hold a growth substrate 11 in a crystal growth furnace. More specifically, the tray 100 has a circular counterbore on the substrate mounting surface side, and as shown in Fig. 3, the tray 100 is provided with a mounting portion 101 that protrudes into the counterbore. The mounting portion 101 is annular, with its center C as the center of the circle, and is provided at a position lower than the upper surface of the tray 100.

[0023] The growth substrate 11 is placed on the mounting portion 101, whereby it is mounted and held on the tray 100. At this time, a hollow portion 103 is formed between the growth substrate 11 and the bottom portion 102 of the tray 100, and a gap TG is formed between the back surface of the growth substrate 11 and the upper surface of the bottom portion 102. Note that the gap TG can be set appropriately in order to control the temperature of the growth substrate 11. In this embodiment, the gap TG is set to 0.1 mm, but it may be set to, for example, 0.2 mm or more.

[0024] A heater 110 for heating the tray 100 and the growth substrate 11 is disposed on the rear side of the bottom 102 of the tray 100. A resistance heating system is used for the heater 110, but other heating systems such as high-frequency induction heating and lamp heating can also be used.

[0025] (2) Method for Manufacturing Semiconductor DBR Substrate FIG. 4 is a flowchart showing a method for manufacturing the semiconductor DBR substrate 10. Each step of the method for manufacturing the semiconductor DBR substrate 10 will be described below with reference to FIG. 4. (S1) Loading of Growth Substrate A growth substrate 11, which is a 2-inch diameter C-plane GaN substrate, is loaded onto a tray 100 in a crystal growth furnace. Note that a growth substrate larger than 2 inches diameter can also be used. This method is particularly suitable for circular growth substrates.

[0026] Although a tray in which the mounting portion 101 is provided to support the outer periphery of the growth substrate 11 is used, the present invention is not limited to this. A tray or susceptor that holds the entire back surface of the growth substrate 11 in contact with it may also be used.

[0027] (S2) Growth of Underlayer The temperature (growth temperature) of the growth substrate 11 is set to 1100° C., and hydrogen (H) is used as the carrier gas. Trimethylgallium (TMG) and ammonia (NH ３) was supplied to grow an underlayer 11A made of undoped GaN. The thickness of the underlayer 11A was set to 100 nm. That is, in this embodiment, the underlayer 11A is formed as the first layer grown on the growth substrate 11. Here, the growth temperature refers to the temperature measured by a thermocouple (not shown) installed near the heater 110 in the crystal growth furnace.

[0028] The underlayer 11A is preferably made of the same crystal (GaN) as the growth substrate 11, but it is also possible to use a buffer layer or a superlattice structure layer having a different composition from that of the growth substrate 11. The underlayer 11A does not necessarily have to be provided.

[0029] (S3) Formation of Semiconductor DBR The growth of the first thin film and the second thin film was alternately repeated as follows to form a semiconductor DBR 12 in which 46 pairs of the first thin film and the second thin film were stacked. (S3-1) Growth of First Thin Film The temperature of the growth substrate 11 was lowered from 1100°C to 844°C, and the carrier gas was changed from hydrogen (H2) to nitrogen (N2). After the temperature was stabilized, trimethylindium (TMI), trimethylaluminum (TMA), and ammonia (NH ３ ) was supplied to grow an AlInN layer 12A as a first thin film on the underlayer 11A to a thickness of 50 nm. After the growth, the supply of metal organic materials (hereinafter also referred to as MO materials) TMI and TMA was stopped.

[0030] (S3-2) Growth of Second Thin Film (i) Growth of Cap Layer (GaN Protective Layer) After the growth of the AlInN layer 12A (first thin film), triethylgallium (TEG) and ammonia (NH ３ ) was supplied, and a GaN layer was grown on the AlInN layer 12A as a cap layer to a thickness of 0.3 nm. After growth, the supply of the MO material was stopped. The cap layer (GaN) protects the surface of the AlInN layer 12A against the rise in growth temperature. (ii) Growth of GaN Layer Next, the carrier gas was changed from N2 to H2, and the temperature of the growth substrate 11 was raised from 844°C to 1100°C. After the temperature rise, TMG and NH ３The GaN layer was grown to a thickness of 44.7 nm. After growth, the supply of the MO material was stopped. The temperature during GaN growth may be within the range of 800°C to 1200°C.

[0031] Therefore, together with the cap layer (GaN), a GaN layer 12B (second thin film) having a thickness of 45.0 nm was formed on the AlInN layer 12A (first thin film).

[0032] (S3-3) Repeated Growth Steps (S3-1) and (S3-2) were repeated until k pairs (k=46) of AlInN layers 12A and GaN layers 12B were stacked to form a semiconductor DBR 12 consisting of an AlInN layer / GaN layer stack. In the repeated growth, the In composition of each layer of the AlInN layer 12A was adjusted to 19.1%.

[0033] The organometallic material (MO material) is not limited to the above-mentioned materials, but triethylindium (TEI), triethylaluminum (TEA), etc. may also be used.

[0034] Through the above steps, the semiconductor DBR substrate 10 was formed, in which the layered structure of the semiconductor DBR 12 was formed on the growth substrate 11 .

[0035] (3) Warpage of Semiconductor DBR Substrate Using the above manufacturing method, the In composition was changed to manufacture the semiconductor DBR substrate 10. Specifically, three types of semiconductor DBR substrates 10 with In compositions of 18.6% (epi-1, EPI-1), 19.1% (epi-2, EPI-2), and 19.6% (epi-3, EPI-3) were manufactured and evaluated.

[0036] 5A, 5B, and 5C are plots showing the amount of warpage (μm) in the X and Y directions for epitaxial wafers 1 (In composition: 18.6%), 2 (In composition: 19.1%), and 3 (In composition: 19.6%), respectively. The X and Y directions are parallel and perpendicular to the orientation flat (O.F.), respectively. The negative (-) direction on the vertical axis corresponds to the direction of the tray 100.

[0037] Epi-1 is a semiconductor DBR substrate 10 in which the semiconductor DBR 12 is crystal-grown with an In composition (18.6%) such that the AlInN layer 12A lattice-matches with the GaN layer 12B at room temperature (RT). Fig. 5A shows the amount of warpage of epi-1 when returned to room temperature. Despite the condition of lattice matching at room temperature, the semiconductor DBR substrate 10 exhibited a large amount of warpage that was convex downward (concave).

[0038] That is, when the In composition of the AlInN layer 12A is smaller than the In composition that lattice matches with the GaN layer 12B, tensile strain occurs, and the semiconductor DBR substrate 10 appears to have a downward convex warp.

[0039] More specifically, when downward convex (concave) warpage occurs in the semiconductor DBR substrate as crystal growth progresses, the distance between the center of the semiconductor DBR substrate and the bottom surface of the tray 100 becomes smaller than that of the outer periphery of the substrate, and the temperature of the center of the semiconductor DBR substrate increases. As a result, more In is released, the In composition in the center becomes lower, and downward convex warpage is exhibited. In other words, the In composition gradually decreases from the center to the outer periphery. It is thought that as crystal growth continues, the In composition further decreases, causing the warpage to increase.

[0040] Epi-2 is a semiconductor DBR substrate 10 in which a semiconductor DBR is crystal-grown with an In composition (19.1%) that is lattice-matched at the growth temperature. Fig. 5B shows the amount of warpage of epi-2 when returned to room temperature. Although the condition at room temperature results in lattice mismatch, epi-2 has a substantially flat shape compared to epi-1 at room temperature.

[0041] Epi-3 is a semiconductor DBR substrate 10 in which a semiconductor DBR is crystal-grown with an In composition (19.6%) slightly larger than the In composition that provides lattice matching at the growth temperature. Figure 5C shows the amount of warpage of epi-3 when returned to room temperature, which indicates a slight upward convexity (convex shape). Specifically, the amount of warpage of epi-3 (the difference between the peripheral warpage and the central warpage) is 30 μm or less, which is within the allowable range for a semiconductor DBR substrate with a diameter of 2 inches.

[0042] It is believed that when the In composition of the AlInN layer 12A is larger than the In composition that lattice-matches with the GaN layer 12B, compressive strain occurs, causing the semiconductor DBR substrate 10 to warp in an upwardly convex shape.

[0043] The results of epitaxial growth 2 show that the AlInN layer 12A satisfies the lattice matching condition with the GaN layer 12B, and the In composition remains unchanged (the In composition of each layer is equal), resulting in the formation of the semiconductor DBR substrate 10. At this time, no thermal stress is generated. When the temperature is returned to room temperature, the lattice constants of the layers constituting the semiconductor DBR 12 become mismatched, but the evaluation results described above indicate that the structure of the semiconductor DBR 12 at room temperature remains unchanged from the structure at the time of crystal growth.

[0044] In addition, in epitaxial growth 3, slight warping occurred in the semiconductor DBR substrate 10, but it was substantially flat and within the allowable range for a semiconductor DBR substrate having a size of 2 inches φ. For a substrate having a size of 2 inches φ (diameter: 5.8 cm), the warping of the semiconductor DBR substrate 10 is preferably within 30 μm.

[0045] More specifically, the curvature Z (= 1 / R) at this time is 9×10 －８ (μm －１ ) Therefore, the curvature Z of the semiconductor DBR substrate 10 is 9×10 －８ (μm －１ ) or less. This makes it possible to provide a semiconductor DBR with a uniform reflection wavelength for a vertical cavity surface emitting laser. The above-mentioned range of curvature values ​​can also be applied when a dielectric DBR is used.

[0046] As explained above, by growing the crystal so that the AlInN layer 12A (first thin film) satisfies the lattice matching condition with the GaN layer (second thin film) 12B at the temperature during crystal growth, the composition period of the semiconductor DBR 12 becomes constant, and it has been found that the semiconductor DBR substrate 10 maintains flatness even when the layers constituting the semiconductor DBR 12 are in a lattice-mismatched condition when the temperature is returned to room temperature (RT). This makes it possible to provide a nitride semiconductor multilayer reflector and a vertical-cavity surface-emitting laser that can provide a DBR substrate that is small in warp, flat, and has a uniform reflection wavelength within the substrate surface.

[0047] (4) Reflection Spectrum of Semiconductor DBR Substrate Fig. 6 is a top view showing measurement points of the reflection spectrum of the semiconductor DBR substrate 10. For each of the epitaxial 1, epitaxial 2, and epitaxial 3 semiconductor DBR substrates 10, the reflection spectrum was measured at 25 equally spaced locations (r0, r1, ..., r24) in the radial direction (X direction) from the center C toward the outer periphery.

[0048] 7A, 7B, and 7C are diagrams showing overlapping reflection spectra at measurement points of epitaxial layer 1, epitaxial layer 2, and epitaxial layer 3, respectively.

[0049] As shown in FIG. 7A, in the case of epitaxial layer 1 (In composition: 18.6%), the reflection center wavelength at the outer periphery of the semiconductor DBR substrate 10 is significantly shifted toward the longer wavelength side from the designed center wavelength (450 nm), and the wavelength becomes shorter toward the center, gradually approaching the reflection spectrum at the center.

[0050] That is, in epitaxial layer 1, the central reflection wavelength of the reflection spectrum is non-uniform within the substrate surface, and when applied to a vertical cavity surface emitting laser, the emission wavelength and oscillation characteristics (threshold, efficiency) become non-uniform.

[0051] As shown in FIG. 7B, in epitaxial layer 2 (In composition: 19.1%), the reflection spectrum is uniform within the substrate surface, and it is found that a semiconductor DBR substrate 10 with a highly uniform reflection spectrum is obtained.

[0052] Furthermore, as shown in FIG. 7C, in the case of epitaxial layer 3 (In composition: 19.6%), the deviation of the reflection center wavelength is slightly larger than that of epitaxial layer 1 in a small part of the outer periphery, but the reflection spectrum of the semiconductor DBR substrate 10 is highly uniform.

[0053] Furthermore, if the center and outer periphery of the substrate are −3 nm or more and 3 nm or less from the designed central wavelength, the laser characteristics are not affected and uniformity of the reflection spectrum can be achieved.

[0054] (5) In composition of AlInN layer Figure 8 shows the lattice matching condition of AlInN to GaN as a function of growth temperature. The vertical axis represents the lattice constant of the a-axis of GaN. More specifically, the graph shows the lattice constant of GaN (solid line) and the In composition of AlInN lattice-matched to it (dash-dotted line) as a function of growth temperature. For the lattice constant of GaN, see M. Miyoshi et al. (Jpn. J. Appl. Phys. 58, (2019) SC1006), and for the lattice constants of AlN and InN, see S.L. Rumyantsev et al. (Int. J. High Speed ​​Electron. Syst. 14 (2004) 1). For the thermal expansion coefficients of GaN, AlN, and InN, see M. Miyoshi et al. (Jpn. J. Appl. Phys. 58, (2019) SC1006), and the lattice mismatch was calculated from the a-axis lengths of AlInN and GaN at each temperature.

[0055] The reason why the amount of warpage and the reflection spectrum differed greatly among the epi-1 (EPI-1), epi-2 (EPI-2), and epi-3 (EPI-3) is that the strain changed depending on the composition of AlInN.

[0056] Referring to FIG. 8, when the In composition of the AlInN layer 12A is larger than the In composition (dotted line) that lattice matches with the GaN layer 12B, compressive strain occurs, and when it is smaller, tensile strain occurs.

[0057] At a growth temperature in the range of 800° C. to 900° C., which is suitable for growing AlInN, the AlInN layer 12A lattice-matches with the GaN layer 12B when the In composition of the AlInN layer 12A is around 19%.

[0058] Considering the results of the warpage and reflection spectrum described above, the In composition of the AlInN layer 12A is preferably 18.9% to 20.0%, and more preferably 18.9% to 19.6%. As mentioned above, this In composition is a condition that results in lattice mismatch at room temperature. Here, if the In composition is less than 18.9%, the reflection spectrum due to substrate warpage may grow unevenly across the substrate surface, resulting in unacceptable growth. Furthermore, if the In composition exceeds 20%, pits may occur. Therefore, the In composition of the AlInN layer 12A is preferably 18.9% to 20.0%.

[0059] As described above in detail, the present invention can provide a method for manufacturing a nitride semiconductor multilayer film reflector that can produce a DBR substrate that is small in warp, flat, and has a uniform reflection wavelength within the substrate surface.

[0060] In the above embodiment, the semiconductor DBR 12 has a reflection center wavelength of 450 nm, but this is not limiting. Semiconductor DBRs in the blue band (e.g., 430 to 490 nm), green band (e.g., 490 to 550 nm), violet to near-ultraviolet band (e.g., 380 to 430 nm), etc. can also be used.

[0061] Second Embodiment (1) Vertical Cavity Surface Emitting Laser Wafer FIG. 9A is a top view schematically showing a vertical cavity surface emitting laser wafer 50 according to a second embodiment of the present invention, and FIG. 9B is a cross-sectional view schematically showing the structure of the vertical cavity surface emitting laser wafer 50.

[0062] As shown in FIG. 9A, the vertical cavity surface-emitting laser wafer 50 is formed so that it can be divided into a plurality of vertical cavity surface-emitting lasers 55, for example, by dividing the vertical cavity surface-emitting laser wafer 50 in a matrix pattern.

[0063] 9B , the vertical cavity surface emitting laser wafer 50 is formed by successively growing crystals of the first semiconductor layer 13, the active layer 15, and the second semiconductor layer 19 in this order on the semiconductor DBR substrate 10 of the first embodiment. The first semiconductor layer 13, the second semiconductor layer 19, and the active layer 15 sandwiched between the second semiconductor layer 19 function as a light emitting functional layer.

[0064] The first semiconductor layer 13, the active layer 15, and the second semiconductor layer 19 may be formed by continuing crystal growth on the semiconductor DBR 12 after the growth of the semiconductor DBR 12 is completed.

[0065] Also, a second reflecting mirror 25 is formed on the second semiconductor layer 19, which constitutes a vertical cavity together with the semiconductor DBR 12 of the semiconductor DBR substrate 10.

[0066] Although FIG. 9B does not show the current injection structure for the vertical cavity surface emitting laser, such as electrodes and insulating films, these may be provided as appropriate depending on the desired device structure.

[0067] By dividing the vertical cavity surface emitting laser wafer 50 into individual pieces as shown in FIG. 9A, individual vertical cavity surface emitting lasers 55 are obtained.

[0068] The vertical-cavity surface-emitting lasers 55 cut out from the vertical-cavity surface-emitting laser wafer 50 have high uniformity in oscillation wavelength and small variation in resonance wavelength within the element surface, so that a vertical-cavity surface-emitting laser with low threshold and high efficiency can be obtained.

[0069] 10 is a cross-sectional view schematically showing the structure of a vertical cavity surface emitting laser (VCSEL) 55 according to a third embodiment of the present invention. In this embodiment, the vertical cavity surface emitting laser 55 is a nitride surface emitting laser made of III-V nitride-based semiconductor layers.

[0070] The vertical cavity surface emitting laser 55 is formed by successively growing crystals of the first semiconductor layer 13, the active layer 15, and the second semiconductor layer 19 in this order on the semiconductor DBR substrate 10 of the first embodiment.

[0071] Also, a case will be described in which the first semiconductor layer 13 is made of an n-type (first conductivity type) semiconductor layer and the second semiconductor layer 19 is made of a p-type (second conductivity type that is the opposite conductivity type of the first conductivity type) semiconductor layer.

[0072] The active layer 15 is made of a multiple quantum well (MQW), and the second semiconductor layer 19 includes an intermediate layer 16 , an electron barrier layer (EBL) 17 and a p-type semiconductor layer 18 .

[0073] The following is a specific description of the manufacturing method and structure of the vertical cavity surface emitting laser 55. Crystal growth of the semiconductor layers was performed by metal organic vapor phase epitaxy (MOVPE), similar to the first embodiment. After the growth of the semiconductor DBR 12 was completed (step S3-3), crystal growth continued on the semiconductor DBR 12 to form the vertical cavity surface emitting laser wafer 50.

[0074] An underlayer 11A (GaN layer) having a thickness of about 1 μm was grown on a substrate 11, and a semiconductor DBR 12 was formed on the underlayer 11A.

[0075] The semiconductor DBR 12 (first reflecting mirror) was formed by stacking 46 pairs of n-type AlInN layers 12A and GaN layers 12B. Each semiconductor layer of the semiconductor DBR 12 had a thickness of λ / 4n (n is the refractive index of each semiconductor film) of the emission wavelength λ of the active layer 15.

[0076] On the semiconductor DBR 12 (first reflecting mirror) of the semiconductor DBR substrate 10, a first semiconductor layer 13 (n-type semiconductor layer) (layer thickness: 350 nm) which is an n-type GaN layer doped with Si (silicon) was grown.

[0077] Barrier layers and quantum well layers were alternately formed on the first semiconductor layer 13 (n-type semiconductor layer) to form an active layer 15 having four quantum well layers. The barrier layers were made of GaInN (thickness: 3 nm), and the well layers were made of GaN (thickness: 4 nm). The compositions and thicknesses of the barrier layers and well layers can be appropriately selected depending on the desired emission wavelength, emission characteristics, etc.

[0078] An intermediate layer 16, which is a final barrier layer, made of undoped GaN was grown to a thickness of 120 nm on the final well layer, which is the final layer of the active layer 15. That is, the intermediate layer 16 is a layer between the active layer 15 and the electron barrier layer (EBL) 17.

[0079] Next, Mg (magnesium) doped Al ｘ Ga １－ｘ An electron barrier layer (EBL) 17 made of N (Al composition: x) was grown.

[0080] Subsequently, a Mg-doped p-GaN layer was grown as a p-type semiconductor layer 18 on the electron barrier layer 17 (p-AlGaN) to a thickness of 83 nm.

[0081] As described above, crystal growth was performed on the semiconductor DBR substrate 10 to form the surface-emitting laser wafer 50 on which the semiconductor laminated body constituting the vertical-cavity surface-emitting laser 55 was formed.

[0082] The surface-emitting laser wafer was etched at its outer periphery so as to reach the inside of the first semiconductor layer 13 (n-type semiconductor layer), thereby forming a mesa portion 55M, which is a cylindrical mesa protrusion.

[0083] The p-type semiconductor layer 18, which is the uppermost semiconductor layer of the mesa portion 55M, was dry-etched to a depth of about 20 nm at its outer periphery to form a recess, thereby forming the p-type semiconductor layer 18 having the cylindrical mesa portion 55M.

[0084] An insulating film (SiO ２ ) 21 was deposited to a thickness of 20 nm. As a result, the recess of the p-type semiconductor layer 18 was flattened, a current confinement structure was formed, and a cylindrical (central axis: CX) current injection region was formed.

[0085] Next, an ITO (indium tin oxide) film was formed as a transparent conductive film 22 on the p-type semiconductor layer 18 and the insulating film 21 to a thickness of 20 nm.

[0086] Next, a dielectric (Nb ２ O ５The spacer layer 24 functions as a phase adjustment layer.

[0087] Furthermore, a dielectric DBR 25 (second reflecting mirror) which is a dielectric multilayer film reflecting mirror was formed on the spacer layer 24. The dielectric DBR 25 is made of SiO ２ (11 layers) and Nb ２ O ５ The dielectric DBR 25 is made up of 10.5 pairs (10 layers). The dielectric DBR 25 forms a resonator together with the semiconductor DBR 12. It is preferable that the dielectric DBR 25 is formed so as to be coaxial with the cylindrical mesa portion 55M of the p-type semiconductor layer 18.

[0088] Furthermore, since dielectrics have low optical absorption (optical loss) and a high refractive index, a reflective mirror with high reflectivity and a wide reflection band can be obtained with a smaller number of stacked layers (number of pairs) than a semiconductor DBR, thereby achieving a vertical-cavity surface-emitting laser with improved threshold and efficiency.

[0089] Next, an n-electrode 27 was formed on the recessed portion of the outer periphery of the first semiconductor layer 13 (n-type semiconductor layer), and a p-electrode 28 was formed on the transparent conductive film 22. The back surface of the substrate 11 was polished, and a Nb ２ O ５ / SiO ２ An anti-reflection coating 29 (anti-reflection film) consisting of the above two layers was formed.

[0090] This completes the formation of the vertical cavity surface-emitting laser wafer 50 on which a plurality of vertical cavity surface-emitting lasers 55 are arranged. By dividing (singulating) the vertical cavity surface-emitting laser wafer 50 into individual elements, individual vertical cavity surface-emitting lasers 55 having the structure shown in FIG. 10 are obtained.

[0091] The above-described composition and thickness of the intermediate layer 16 are merely examples. Although the intermediate layer 16 has been described as a GaN layer, nitride semiconductor layers of other compositions, such as InGaN, AlGaN, or InAlGaN, may also be used. Furthermore, although the intermediate layer 16 is described as an undoped layer, it may contain a dopant diffused from the electron barrier layer 17 or the p-type semiconductor layer 18.

[0092] The thickness of the electron barrier layer 17 is merely an example. The electron barrier layer 17 may have a thickness of, for example, 3 to 30 nm. The electron barrier layer 17 is made of a nitride semiconductor containing Al in its composition. Furthermore, the electron barrier layer 17 may be formed as a compositionally graded layer in which the Al composition changes in the thickness direction.

[0093] Although the electron barrier layer 17 has been described as a p-type semiconductor layer (p-AlGaN), it may be a p-type semiconductor layer containing Al in its composition, grown as an i-layer and mixed with impurities (Mg) diffused from the p-type semiconductor layer 18.

[0094] Although the active layer 15 is a quantum well active layer having four quantum well layers 15W, it is sufficient that the active layer 15 has at least one quantum well layer. The active layer 15 is not limited to a quantum well active layer. An active layer having a so-called bulk structure may also be used.

[0095] Furthermore, the first semiconductor layer 13 and the second semiconductor layer 19 may be composed of a plurality of semiconductor layers including layers with different compositions and / or doping concentrations, and an undoped layer (i-layer).

[0096] The dielectric DBR 25 is made of SiO ２ Membrane and Nb ２ O ５ However, the DBR may be made of other combinations of dielectric films with mutually different refractive indices, or may be made of a semiconductor DBR made of semiconductor films with mutually different refractive indices.

[0097] As explained above in detail, according to this embodiment, the variation in the resonant wavelength within the device surface is small, so that a vertical cavity surface emitting laser with a low threshold and high efficiency can be obtained.

[0098] The embodiments of the present invention have been described in detail above. According to the present invention, it is possible to provide a method for manufacturing a nitride semiconductor multilayer reflector that can obtain a DBR substrate that is small in warp, flat, and has a uniform reflection wavelength within the substrate surface. It is also possible to provide a vertical cavity surface emitting laser wafer that has a DBR substrate that is flat and has a uniform reflection wavelength within the substrate surface, and has a uniform emission wavelength, and a high-performance vertical cavity surface emitting laser with small variations in resonance wavelength.

[0099] 10: Semiconductor DBR substrate 11: Growth substrate 12: Semiconductor DBR 12A: AlInN layer (first thin film) 12B: GaN layer (second thin film) 13: First semiconductor layer (n-type semiconductor layer) 19: Second semiconductor layer (p-type semiconductor layer) 25: Dielectric DBR (second reflecting mirror) 50: Vertical cavity surface emitting laser wafer 55: Vertical cavity surface emitting laser 100: Tray r0 to r24: Reflection spectrum measurement points

Claims

1. A method for manufacturing a semiconductor multilayer reflector by stacking semiconductor layers having different refractive indices on a substrate, wherein the substrate is a GaN substrate, and AlInN layers and GaN layers are grown alternately on the substrate, and the In composition of the AlInN layers is within the range of 18.9% to 20.0%, at which a lattice mismatch occurs with the GaN layers at room temperature.

2. A method for manufacturing a semiconductor multilayer reflector by stacking semiconductor layers having different refractive indices on a substrate, wherein the substrate is a GaN substrate, and AlInN layers and GaN layers are alternately grown on the substrate, the growth temperature during growth of the AlInN layers is within a range of 800°C to 900°C, and the AlInN layers are grown with an In composition that lattice matches the GaN layers within the growth temperature range.

3. A method for manufacturing a nitride semiconductor multilayer reflector according to claim 2, wherein the In composition that lattice matches with the GaN layer is within a range that produces a lattice mismatch of 18.9% to 20.0% at room temperature.

4. The curvature of the semiconductor multilayer reflector is 9 x 10 －８ (μm －１ 3. The method for manufacturing a nitride semiconductor multilayer mirror according to claim 1, wherein the thickness of said nitride semiconductor multilayer mirror is within 100 μm.

5. A method for manufacturing a nitride semiconductor multilayer reflector according to claim 1 or 2, wherein the semiconductor multilayer reflector is warped in a convex shape.

6. The method for manufacturing a nitride semiconductor multilayer reflector according to claim 1 or 2, wherein the substrate has a circular shape with a diameter of 2 inches or more.

7. A vertical cavity surface emitting laser wafer having a nitride semiconductor multilayer reflector formed on a substrate, the vertical cavity surface emitting laser wafer having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a conductivity type opposite to the first conductivity type, and an active layer sandwiched between the first semiconductor layer and the second semiconductor layer, all formed on the nitride semiconductor multilayer reflector, the substrate being a GaN substrate, the nitride semiconductor multilayer reflector being constructed by alternately stacking AlInN layers and GaN layers, and the In composition of the AlInN layer being within a range of 18.9% to 20.0%, at which lattice mismatch with the GaN layer occurs at room temperature.

8. A vertical cavity surface emitting laser wafer according to claim 7, wherein said substrate has a circular shape with a diameter of 2 inches or more.

9. A vertical cavity surface emitting laser wafer according to claim 7, further comprising a dielectric multilayer reflector formed on said second semiconductor layer and constituting a resonator together with said nitride semiconductor multilayer reflector.

10. A vertical cavity surface emitting laser having a nitride semiconductor multilayer reflector formed on a substrate, comprising: a first semiconductor layer of a first conductivity type formed on the nitride semiconductor multilayer reflector; a second semiconductor layer of a conductivity type opposite to the first conductivity type; an active layer sandwiched between the first semiconductor layer and the second semiconductor layer; and a multilayer reflector formed on the second semiconductor layer and constituting a resonator together with the nitride semiconductor multilayer reflector; wherein the substrate is a GaN substrate; the nitride semiconductor multilayer reflector is constructed by alternately stacking AlInN layers and GaN layers; and the In composition of the AlInN layer is within a range of 18.9% to 20.0%, which causes lattice mismatch with the GaN layer at room temperature.

11. A vertical cavity surface emitting laser according to claim 10, wherein said multilayer reflector is a dielectric multilayer reflector.

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