Method and system for controlling a single-phase two-stage inverter for minimizing a ripple current in a DC-link capacitor thereof

Abstract

A method of controlling a single-phase two-stage inverter (SPTSI) for minimizing a ripple current in a DC-link capacitor thereof is provided. The SPTSI includes a DC-DC boost converter at a first stage, a H-bridge inverter at a second stage, and the DC-link capacitor connected to and between the DC-DC boost converter and the H-bridge inverter. The method includes: determining a relative direction between an output current of the DC-DC boost converter and an input current of the H-bridge inverter; setting a phase difference between a first carrier signal for the DC-DC boost converter and a second carrier signal for the H-bridge inverter based on the determined relative direction between the output current of the DC-DC boost converter and the input current of the H-bridge inverter; generating the first and second carrier signals having the set phase difference therebetween; and sending the first and second carrier signals to a first switching signal generator and a second switching signal generator, respectively. In this regard, the first switching signal generator is configured to generate a first switching signal based on the first carrier signal for controlling a first set of switches of the DC- DC boost converter. The second switching signal generator is configured to generate a second switching signal and a third switching signal based on the second carrier signal for controlling a second set of switches and a third set of switches, respectively, of the H-bridge inverter. There is also provided a corresponding system for controlling the SPTSI for minimizing a ripple current in the DC-link capacitor thereof.

Description

METHOD AND SYSTEM FOR CONTROLLING A SINGLE-PHASE TWO-STAGEINVERTER FOR MINIMIZING A RIPPLE CURRENT IN A DC-LINK CAPACITORTHEREOFCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority of Singapore Patent Application No. 10202400807U filed on 21 March 2024, the content of which being hereby incorporated by reference in its entirety for all purposes.TECHNICAL FIELD

[0002] The present invention generally relates to a method of controlling a single-phase two-stage inverter (SPTSI), and a system thereof, and more particularly, for minimizing a ripple current in a DC-link capacitor of the SPTSI for enhancing a lifespan of the DC-link capacitor.BACKGROUND100031 The global energy and transportation sectors are in the midst of a substantial transformation, attributing to the widespread adoption of renewable energy resources, energy storage systems, and electric vehicles. Power electronic converters (PECs) are essential for the deployment of these technologies. For instance, the single-phase two-stage inverter (SPTSI) 110 shown in FIG. 1 A is commonly applied in residential photovoltaic (PV) and energy storage applications. In particular, FIG. 1 A shows a circuit diagram of the SPTS1 1 10 The front stage is a DC-DC boost converter 120 (which may be herein simply referred to as a boost converter) that may be connected to PV panels or batteries, whereby the upper switch S3may be replaced with a diode in unidirectional applications. The second stage is an H-bridge inverter 130 whose output is connected to an ac grid or ac loads. Moreover, multiple SPTSIs 1 10 may be cascaded to form a cascaded H-bridge (CHB) converter, as shown in FIG. IB, for medium / high-voltage applications. In particular, FIG. IB shows a circuit diagram of multiple SPTSIs connected in series.

[0004] Capacitors represent one of the most vulnerable components in PECs. Some PEC topologies without DC-link capacitors have been proposed, including the matrix converter, current source inverter, and so on. Nonetheless, most of PECs still require DC-link capacitors and the extension of the capacitor lifespan is important or essential to improve their reliability. Generally, the lifespan of capacitors decreases exponentially with the temperature, which isproportional to the square of the rms (root mean square) value of the capacitor current. Therefore, the capacitor lifespan can be extended by reducing the capacitor current.

[0005] Despite the SPTSI 110 being a popular topology, a significant research gap remains in the development of methods or strategies to minimize (e.g., attenuate) ripple current in the DC-link capacitor 140 of the SPTSI 1 10 shown in FIG. 1 A. In sight of this research gap, a need therefore exists to provide a method of controlling a SPTSI, and a system thereof, for minimizing (e.g., reducing) a ripple current in a DC-link capacitor of the SPTSI in an effective and practical manner for enhancing a lifespan of the DC-link capacitor in the SPTSI, and thus the reliability of the SPTSI. It is against this background that the present invention has been developed.SUMMARY

[0006] According to a first aspect of the present invention, there is provided a method of controlling a single-phase two-stage inverter for minimizing a ripple current in a DC-link capacitor thereof, the single-phase two-stage inverter comprising a DC-DC boost converter at a first stage, a H-bridge inverter at a second stage, and the DC-link capacitor connected to and between the DC-DC boost converter and the H-bridge inverter, the method comprising: determining a relative direction between an output current of the DC-DC boost converter and an input current of the H-bridge inverter; setting a phase difference between a first carrier signal for the DC-DC boost converter and a second carrier signal for the H-bridge inverter based on the determined relative direction between the output current of the DC-DC boost converter and the input current of the H-bridge inverter; generating the first and second carrier signals having the set phase difference therebetween; and sending the first and second carrier signals to a first switching signal generator and a second switching signal generator, respectively, the first switching signal generator being configured to generate a first switching signal based on the first carrier signal for controlling a first set of switches of the DC-DC boost converter and the second switching signal generator being configured to generate a second switching signal and a third switching signal based on the second carrier signal for controlling a second set of switches and a third set of switches, respectively, of the H-bridge inverter.

[0007] According to a second aspect of the present invention, there is provided a system for controlling a single-phase two-stage inverter for minimizing a ripple current in a DC-link capacitor thereof, the single-phase two-stage inverter comprising a DC-DC boost converter at a first stage, a H-bridge inverter at a second stage, and the DC-link capacitor connected to and between the DC-DC boost converter and the H-bridge inverter, the system comprising: at least one memory; and at least one processor communicatively coupled to the at least one memory and configured to: determine a relative direction between an output current of the DC-DC boost converter and an input current of the H-bridge inverter; set a phase difference between a first carrier signal for the DC-DC boost converter and a second carrier signal for the H-bridge inverter based on the determined relative direction between the output current of the DC-DC boost converter and the input current of the H-bridge inverter; generate the first and second carrier signals having the set phase difference therebetween; and send the first and second carrier signals to a first switching signal generator and a second switching signal generator, respectively, the first switching signal generator being configured to generate a first switching signal based on the first carrier signal for controlling a first set of switches of the DC-DC boost converter and the second switching signal generator being configured to generate a second switching signal and a third switching signal based on the second carrier signal for controlling a second set of switches and a third set of switches, respectively, of the H-bridge inverter.

[0008] According to a third aspect of the present invention, there is provided a computer program product, embodied in one or more non-transitory computer-readable storage mediums, comprising instructions executable by at least one processor to perform the method of controlling a single-phase two-stage inverter for minimizing a ripple current in a DC-link capacitor thereof according to the above-mentioned first aspect of the present invention.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present invention will be better understood and readily apparent to one of ordinary skill in the art from the following written description, by way of example only, and in conjunction with the drawings, in which:FIG. 1 A shows a circuit diagram of a single-phase two-stage inverter (SPTSI);FIG. IB shows a circuit diagram of multiple SPTSIs connected in series;FIG. 2 depicts a schematic flow diagram of a method of controlling a SPTSI for minimizing a ripple current in a DC-link capacitor thereof, according to various embodiments of the present invention;FIG. 3 depicts a schematic block diagram of a system (or a control system) for controlling a SPTSI for minimizing a ripple current in a DC-link capacitor thereof, according to various embodiments of the present invention;FIGs. 4A to 4D show circuit diagrams of various power electronic converters (PECs);FIGs. 5A to 5C show waveforms of the H-bridge inverter under unipolar modulation for: carrier signal cHand duty cyclesand d2(FIG. 5A); switches statusand S2(FIG. 5B); and inverter output load current iacand input current iHof the H-bridge inverter (FIG. 5C);FIGs. 6A and 6B show waveforms of the boost converter for: carrier signal cB, duty cycle d3and switch S3(FIG. 6A); and input inductor current iLand output current iBof the boost converter (FIG. 6B);FIG. 7 shows current waveforms of one pulse of the current iHof the H-bridge inverter and the output current iBof the boost converter;FIGs. 8A, 8C and 8E illustrate the carrier waveforms and the consequent current waveforms of iH, iB, and icobtained with carrier signals cHand cBgenerated using the method of controlling a SPTSI according to various example embodiments of the present invention when iHPiL> 0;FIGs. 8B, 8D and 8F illustrate the carrier waveforms and the consequent current waveforms of iH, iB, and icobtained with carrier signals cHand cBgenerated using the method of controlling a SPTSI according to various example embodiments of the present invention when iHPiL< 0;FIGs. 9A and 9B show current waveforms of iH, iB, and icobtained with carrier signals different from the carrier signals cHand cBshown in FIG. 8Awhen iHpi-L 0;FIGs. 10A and 10B show current waveforms of iH, iB, and icobtained with carrier signals different from the carrier signals cHand cBshown in FIG. 8B when iHPiL< 0;FIG 11 A depicts a schematic flow diagram of an example method of controlling a SPTSI for minimizing a ripple current in a DC-link capacitor thereof, according to various example embodiments of the present invention;FIG. 11B depicts a schematic flow diagram of a conventional method of controlling aSPTSI;FIG. 12A shows an overview of an example prototype for controlling a SPTSI, according to various example embodiments of the present invention;FIG. 12B shows a table (T able 1 ) including various parameters of the example prototype shown in FIG. 12A,FIGs. 13 A and 13B show recorded experimental waveforms using the example method of controlling a SPTSI according to various example embodiments of the present invention for: overall waveforms (FIG. 13A) and current waveforms of ic, iB, and iHwhen miaciLchanges from positive to negative (FIG. 13B);FIGs. 14A, 14B and 14C provide the recorded experimental waveforms of vac, ic, iH, and iBfor three experimental cases (Case I where the example method of controlling a SPTSI according to various example embodiments of the present invention is implemented, and Case II and Case III where conventional methods were implemented), respectively;FIGs. 15 A, 15B and 15C show the frequency spectrum of current iB, iH, and icin the three experimental cases (Case I, Case II, Case III), respectively;FIG. 16 illustrates the capacitor lifespan for the three experimental cases (Case 1, Case II, Case III) under various ESR (capacitor equivalent series resistance) values; andFIG. 17 shows a table (Table II) which summarizes comparisons of various parameters of the three experimental cases (Case I, Case II, Case III).DETAILED DESCRIPTION

[0010] Various embodiments of the present invention relate to a method of controlling a single-phase two-stage inverter (SPTSI), and a system thereof, and more particularly, for minimizing (e.g., reducing) a ripple current in a DC-link capacitor of the SPTSI for enhancing a lifespan of the DC-link capacitor.

[0011] A SPTSI is a common energy conversion unit for emerging decarbonization applications, such as residential photovoltaic (PV) systems. FIG. 1A depicts a circuit diagram illustrating an architecture of a SPTSI 110 known in the art. The SPTSI 110 comprises a DC- DC boost converter 120 at a first stage of the SPTSI 110, a H-bridge inverter 130 (which may also be referred to as a full-bridge inverter) at a second stage of the SPTSI 110, and a DC-link capacitor 140 connected to and between the DC-DC boost converter 120 and the H-bridge inverter 130. The DC-DC boost converter 120 comprises a set of switches (e g., a pair ofswitches S3,S3) and the H-bridge inverter 130 comprises two sets of switches (two pairs of switches S1FSxand S2, S2). In particular, the DC-DC boost converter 120 and the H-bridge inverter 130 are connected back-to-back with the DC-link capacitor 140 connected therebetween serving as an energy buffer. The architecture / structure and operations of the SPTSI 110 are well known in the art and thus need not be described herein in detail for conciseness.

[0012] As described in the background, capacitors represent one of the most vulnerable components in PECs, and thus, the extension of the DC-link capacitor lifespan is important or essential to improve their reliability. Generally, the lifespan of capacitors decreases exponentially with the temperature, which is proportional to the square of the rms value of the capacitor current. Therefore, the capacitor lifespan can be extended by reducing the capacitor current. In this regard, despite the SPTSI 110 being a popular topology, a significant research gap remains in the development of methods or strategies to minimize (e.g., attenuate) ripple current in the DC-link capacitor 140 of the SPTSI 110. In sight of this research gap, various embodiments of the present invention provide a method of controlling a SPTSI 1 10, and a system thereof, for minimizing (e.g., reducing) a ripple current in a DC-link capacitor 140 of the SPTSI 110 in an effective and practical manner for enhancing a lifespan of the DC-link capacitor 140 in the SPTSI 110, and thus the reliability of the SPTSI 110.

[0013] FIG. 2 depicts a schematic flow diagram of a method 200 of controlling a SPTSI 110 for minimizing a ripple current in a DC-link capacitor 140 thereof, according to various embodiments of the present invention. The SPTSI 110 comprises a DC-DC boost converter 120 at a first stage, a H-bridge inverter 130 at a second stage, and the DC-link capacitor 140 connected to and between the DC-DC boost converter 120 and the H-bridge inverter 130. The method 200 comprises: determining (at 206) a relative direction between an output current iBof the DC-DC boost converter 120 and an input current iHof the H-bridge inverter 130; setting (at 208) a phase difference between a first carrier signal for the DC-DC boost converter 120 and a second carrier signal for the H-bridge inverter 130 based on the determined relative direction between the output current iBof the DC-DC boost converter 120 and the input current iHof the H-bridge inverter 130; generating (at 210) the first and second carrier signals having the set phase difference therebetween; and sending (at 212) the first and second carrier signals to a first switching signal generator (or a first switching signal generating module) and a second switching signal generator (or a second switching signal generating module), respectively. In this regard, the first switching signal generator is configured to generate a first switching signalbased on the first carrier signal for controlling a first set of switches (e.g., a first pair of switches S3,S3) of the DC-DC boost converter 120. The second switching signal generator is configured to generate a second switching signal and a third switching signal based on the second carrier signal for controlling a second set of switches (e.g., a second pair of switches S±) and a third set of switches (e.g., a third pair of switches S2, S2), respectively, of the H-bridge inverter 130.

[0014] Accordingly, the method 200 of controlling a SPTSI 110 advantageously minimizes (e.g., reduces) a ripple current in a DC-link capacitor 140 of the SPTSI 1 10 in an effective and practical manner for enhancing a lifespan of the DC-link capacitor 140 in the SPTSI 110, and thus the reliability of the SPTSI 110. In particular, a relative direction between an output current iBof the DC-DC boost converter 120 and an input current iHof the H-bridge inverter 130 is determined and then a phase difference between a first carrier signal for the DC-DC boost converter 120 and a second carrier signal for the H-bridge inverter 130 is set based on the determined relative direction. Therefore, the method 200 advantageously controls the phase difference between the first and second carrier signals based on the relative direction between the output current iBof the DC-DC boost converter 120 and the input current iHof the H-bridge inverter 130 for effectively minimizing the ripple current in the DC-link capacitor 140 of the SPTSI 110. These advantages or technical effects, and / or other advantages or technical effects, will become more apparent to a person skilled in the art as the method 100 of controlling a SPTSI 110, as well as the corresponding system for controlling a SPTSI 110, is described in more detail according to various embodiments and example embodiments of the present invention.

[0015] In various embodiments, the method 200 further comprises setting a frequency for the first carrier signal and a frequency for the second carrier signal such that a pulse period of the first carrier signal and a pulse period of the second carrier signal are the same. That is, the frequency for the first carrier signal and the frequency for the second carrier signal are set such that the first and second carrier signals have the same pulse period. In this regard, the above- mentioned generating (at 210) the first and second carrier signals comprises generating the first carrier signal having the set frequency for the first carrier signal and generating the second carrier signal having the set frequency for the second carrier signal. Therefore, the first and second carrier signals are generated to have the set phase difference therebetween and the respective set frequency.

[0016] In various embodiments, the set frequency for the first carrier signal is twice the set frequency for the second carrier signal. That is, in various embodiments, to configure orgenerate the first and second carrier signals having the same pulse period, the set frequency for the first carrier signal is twice the set frequency for the second carrier signal. Accordingly, in various embodiments, the frequency of the first carrier signal and the frequency of the second carrier signal have a predefined relationship therebetween.

[0017] Tn various embodiments, the relative direction determined between the output current iBof the DC-DC boost converter 120 and the input current iHof the H-bridge inverter 130 is one of a same direction and an opposite direction.

[0018] In various embodiments, the phase difference between the first and second carrier signals is set to in phase based on determining that the relative direction between the output current iBof the DC-DC boost converter 120 and the input current iHof the H-bridge inverter 130 is the same direction. Furthermore, the phase difference between the first and second carrier signals is set to out of phase based on determining that the relative direction between the output current iBof the DC-DC boost converter 120 and the input current iHof the H-bridge inverter 130 is the opposite direction.

[0019] In various embodiments, the phase difference between the first and second carrier signals being set to in phase is setting the phase difference to 0. In various embodiments, the phase difference refers to the difference between the positions of minimum values (i.e., 0) of the first and second carrier signals. For example, as will be described herein later according to various example embodiments, FIG. 8A illustrates an example of the phase difference between the first and second carrier signals (cBand cH) being set to in phase, for example, being set to 0 whereby the difference between the positions of minimum values (i.e., 0) of the first and second carrier signals (cBand cB) is 0. Furthermore, the phase difference between the first and second carrier signals being set to out of phase is setting the phase difference to half of a pulse period of the first or second carrier signal. For example, as will be described herein later according to various example embodiments, FIG. 8B illustrates an example of the phase difference between the first and second carrier signals (cBand cH) being set to out of phase, for example, being set to half of a pulse period (e.g., TH) of the second carrier signal whereby the difference between the positions of minimum values (i.e., 0) of the first and second carrier signals ( cBand cH) is TH / 2 . In this regard, as described above according to various embodiments, the first and second carrier signals have the same pulse period (i.e., TB— TH~).

[0020] In various embodiments, the relative direction between the output current iBof the DC-DC boost converter 120 and the input current iHof the H-bridge inverter 130 is determinedbased on an input inductor current iLof the DC-DC boost converter 120 and an inverter output load current iacof the H-bridge inverter 130.

[0021] In various embodiments, the relative direction between the output current iBof the DC-DC boost converter 120 and the input current iHof the H-bridge inverter 130 is determined based on a sign of a product of the input inductor current iL, the inverter output load current iacand a modulation reference signal of the H-bridge inverter 130.

[0022] In various embodiments, the relative direction between the output current iBof the DC-DC boost converter 120 and the input current iHof the H-bridge inverter 130 is determined as the same direction based on determining that the sign of the product of the input inductor current iL, the inverter output load current iacand the modulation reference signal is positive. Furthermore, the relative direction between the output current iBof the DC-DC boost converter 120 and the input current iHof the H-bridge inverter 130 is determined as the opposite direction based on determining that the sign of the product of the input inductor current iL, the inverter output load current iacand the modulation reference signal is negative.

[0023] In various embodiments, the set phase difference between the first and second carrier signals may be obtained or achieved by: (i) adjusting the first carrier signal while maintaining the second carrier signal to achieve the set phase difference therebetween; (ii) adjusting the second carrier signal while maintaining the first carrier signal to achieve the set phase difference therebetween, or (iii) adjusting both the first and second carrier signals to achieve the set phase difference therebetween.

[0024] In various embodiments, the method 200 further comprises: generating, using the first switching signal generator, the first switching signal based on the first carrier signal for controlling the first set of switches (e.g., the first pair of switches S3, S ) of the DC-DC boost converter 120; and generating, using the second switching signal generator, the second switching signal and the third switching signal based on the second carrier signal for controlling the second set of switches (e g., the second pair of switchesand the third set of switches (e g., the third pair of switches S2,S2), respectively, of the H-bridge inverter 130.

[0025] In various embodiments, the first switching signal is generated based on the first carrier signal and a first duty cycle signal for the first set of switches of the DC-DC boost converter 120. The second switching signal is generated based on the second carrier signal and a second duty cycle signal for the second set of switches of the H-bridge inverter 130. The third switching signal is generated based on the second carrier signal and a third duty cycle signal for the third set of switches of the H-bridge inverter 130.

[0026] In various embodiments, the first and second carrier signals each has a triangular carrier waveform.

[0027] In various embodiments, the ripple current in the DC-link capacitor 140 comprises a low-frequency ripple current and high-frequency ripple current (e.g., at the switching frequency and its odd multiples), and the method 200 of controlling the SPTSI 1 10 is configured for minimizing (e g., reducing) the high-frequency ripple current in the DC-link capacitor 140. |0028| FIG. 3 depicts a schematic block diagram of a system 300 (or a control system) for controlling a SPTSI 110 for minimizing a ripple current in a DC-link capacitor 140 thereof, according to various embodiments of the present invention, corresponding to the above- mentioned method 200 of controlling a SPTSI 110 for minimizing a ripple current in a DC-link capacitor 140 thereof as described hereinbefore with reference to FIG. 2 according to various embodiments of the present invention. The system 300 comprises: at least one memory 302; and at least one processor 304 communicatively coupled to the at least one memory 302 and configured to: determine a relative direction between an output current iBof the DC-DC boost converter 120 and an input current iHof the H-bridge inverter 130; set a phase difference between a first carrier signal for the DC-DC boost converter 120 and a second carrier signal for the H-bridge inverter 130 based on the determined relative direction between the output current iBof the DC-DC boost converter 120 and the input current iHof the H-bridge inverter 130; generate the first and second carrier signals having the set frequency and phase difference therebetween; and send the first and second carrier signals to a first switching signal generator (or a first switching signal generating module) and a second switching signal generator (or a second switching signal generating module), respectively. In this regard, the first switching signal generator is configured to generate a first switching signal based on the first carrier signal for controlling a first set of switches (e.g., a first pair of switches S3,S3) of the DC-DC boost converter 120. The second switching signal generator is configured to generate a second switching signal and a third switching signal based on the second carrier signal for controlling a second set of switches (e.g., a second pair of switchesS±) and a third set of switches (e.g., a third pair of switches S2, S2), respectively, of the H-bridge inverter 130.

[0029] It will be appreciated by a person skilled in the art that the at least one processor 304 may be configured to perform various functions or operations through set(s) of instructions (e.g., software modules) executable by the at least one processor 304 to perform various functions or operations. Accordingly, as shown in FIG. 3, the system 300 may comprise: a direction determining module (or a direction determining circuit) 306 configured to determinea relative direction between an output current iBof the DC-DC boost converter 120 and an input current iHof the H-bridge inverter 130; a phase difference setting module (or a phase difference setting circuit) 308 configured to set a phase difference between a first carrier signal for the DC-DC boost converter 120 and a second carrier signal for the H-bridge inverter 130 based on the determined relative direction between the output current iBof the DC-DC boost converter 120 and the input current iHof the H-bridge inverter 130; a carrier signal generating module (or a carrier signal generating circuit) 310 configured to generate the first and second carrier signals having the set phase difference therebetween; and a carrier signal sending module (or a carrier signal sending circuit) 312 configured to send the first and second carrier signals to the first switching signal generator and the second switching signal generator, respectively.

[0030] It will be appreciated by a person skilled in the art that the above-mentioned modules are not necessarily separate modules, and two or more modules may be realized by or implemented as one functional module (e.g., a circuit or a software program) as desired or as appropriate without deviating from the scope of the present invention. For example, two or more of the direction determining module 306, the phase difference setting module 308, the carrier signal generating module 310, and the carrier signal sending module 312 may be realized (e.g., compiled together) as one executable software program (e.g., embedded control firmware), which for example may be stored in the at least one memory 302 and executable by the at least one processor 304 to perform the corresponding functions or operations as described herein according to various embodiments of the present invention.

[0031] In various embodiments, the system 300 for controlling a SPTSI 110 for minimizing a ripple current in a DC-link capacitor 140 thereof corresponds to the method 200 of controlling a SPTSI 110 as described hereinbefore with reference to FIG. 2, therefore, various operations, functions or steps configured to be performed by the least one processor 304 may correspond to various operations, functions or steps of the method 200 described hereinbefore according to various embodiments, and thus need not be repeated with respect to the system 300 for clarity and conciseness. In other words, various embodiments described herein in context of methods (e.g., the method 200 of controlling a SPTSI for minimizing a ripple current in a DC-link capacitor thereof) are analogously valid for the corresponding systems or devices (e g., the system 300 for controlling a SPTSI for minimizing a ripple current in a DC-link capacitor thereof), and vice versa. For example, in various embodiments, the at least one memory 302 may have stored therein the direction determining module 306, the phase difference setting module 308, the carrier signal generating module 310, and / or the carrier signal sending module312, which respectively correspond to various operations, functions or steps of the method 200 of controlling a SPTSI for minimizing a ripple current in a DC-link capacitor thereof as described hereinbefore according to various embodiments, which are executable by the at least one processor 304 to perform the corresponding operations, functions or steps as described herein.

[0032] In various embodiments, the system 300 further comprises: the first switching signal generator configured to generate the first switching signal based on the first carrier signal for controlling the first set of switches of the DC-DC boost converter 120; and the second switching signal generator being configured to generate the second switching signal and the third switching signal based on the second carrier signal for controlling the second set of switches and the third set of switches, respectively, of the H-bridge inverter 130. In various embodiments, the first and second switching signal generators may be implemented as a first switching signal generating module and a second switching signal generating module, respectively. In this regard, the at least one processor 304 may be configured to generate, based on the first switching signal generating module, the first switching signal based on the first carrier signal for controlling the first set of switches of the DC-DC boost converter 120, and generate, based on the second switching signal generating module, generate the second switching signal and the third switching signal based on the second carrier signal for controlling the second set of switches and the third set of switches, respectively, of the H-bridge inverter 130.

[0033] In various embodiments, the first switching signal generator is further configured to generate the first switching signal based on the first carrier signal and a first duty cycle signal for the first set of switches of the DC-DC boost converter 120. The second switching signal generator is further configured to generate the second switching signal based on the second carrier signal and a second duty cycle signal for the second set of switches of the H-bridge inverter 130, and generate the third switching signal based on the second carrier signal and a third duty cycle signal for the third set of switches of the H-bridge inverter 130.

[0034] A computing system, a controller, a microcontroller or any other system providing a processing capability may be provided according to various embodiments in the present invention. Such a system may be taken to include one or more processors and one or more computer-readable storage mediums. For example, the system 300 described hereinbefore may include at least one processor 304 and at least one computer-readable storage medium (or memory) 302 which are for example used in various processing carried out therein as describedherein. A memory or computer-readable storage medium used in various embodiments may be a volatile memory, for example a DRAM (Dynamic Random Access Memory) or a non-volatile memory, for example a PROM (Programmable Read Only Memory), an EPROM (Erasable PROM), EEPROM (Electrically Erasable PROM), or a flash memory, e.g., a floating gate memory, a charge trapping memory, an MRAM (Magnetoresistive Random Access Memory) or a PCRAM (Phase Change Random Access Memory).|0035| In various embodiments, a “circuit" may be understood as any kind of a logic implementing entity, which may be special purpose circuitry or a processor executing software stored in a memory, firmware, or any combination thereof. Thus, in an embodiment, a “circuit” may be a hard-wired logic circuit or a programmable logic circuit such as a programmable processor, e.g., a microprocessor (e.g., a Complex Instruction Set Computer (CISC) processor or a Reduced Instruction Set Computer (RISC) processor). A “circuit” may also be a processor executing software, e.g., any kind of computer program, e.g., a computer program using a virtual machine code, e g., Java. Any other kind of implementation of various functions or operations may also be understood as a “circuit” in accordance with various other embodiments. Similarly, a “module” may be a portion of a system according to various embodiments in the present invention and may encompass a “circuit” as above, or may be understood to be any kind of a logic-implementing entity therefrom.

[0036] Some portions of the present disclosure may be explicitly or implicitly presented in terms of algorithms and functional or symbolic representations of operations on data within a computer memory. These algorithmic descriptions and functional or symbolic representations are the means used by those skilled in the data processing arts to convey most effectively the substance of their work to others skilled in the art. An algorithm may be, and generally, conceived to be a self-consi stent sequence of steps leading to a desired result.

[0037] The present specification also discloses a system (e.g., which may also be embodied as one or more devices or apparatuses), such as the system 300, for performing various operations, functions or steps of various methods described herein. Such a system may be specially constructed for the required purposes or may comprise a general purpose computer system selectively activated or reconfigured by a computer program stored in the computer system. In general, various algorithms that may be presented herein are not limited to being implemented or executed by any particular computer system. Alternatively, the construction of more specialized computer system to perform various operations, functions or steps of variousmethods described herein may be provided as desired or as appropriate without going beyond the scope of the present invention.

[0038] In addition, the present specification also at least implicitly discloses computer program(s) or software / functional module(s), in that it would be apparent to a person skilled in the art that various operations, functions or steps of various methods described herein may be put into effect by computer code. The computer program(s) is not intended to be limited to any particular programming language and implementation thereof, and it will be appreciated by a person skilled in the art that a variety of programming languages and coding thereof may be used to implement the computer program(s). Moreover, the computer program(s) is not intended to be limited to any particular control flow as there are a variety of programming languages which can use different control flows. It will be appreciated by a person skilled in the art that a computer program may be stored on any computer-readable storage medium (non- transitory computer-readable storage medium), such as but not limited to, a magnetic disk, an optical disk or a memory chip. For example, a computer program stored on a computer-readable storage medium may be loaded and executed on a computer system to implement various operations, functions or steps of various methods described herein according to various embodiments of the present invention.

[0039] Accordingly, in various embodiments, there is provided a computer program product, embodied in one or more computer-readable storage mediums (non-transitory computer-readable storage medium), comprising instructions (e g., the direction determining module 306, the phase difference setting module 308, the carrier signal generating module 310, and / or the carrier signal sending module 312) executable by one or more computer processors to perform a method 200 of controlling a SPTSI for minimizing a ripple current in a DC-link capacitor thereof as described hereinbefore with reference to FIG. 2 according to various embodiments of the present invention. Accordingly, various computer programs or software modules described herein may be stored in a computer program product receivable by a system therein, such as the system 300 as shown in FIG. 3, for execution by at least one processor 304 of the system 300 to perform various operations, functions or steps of various methods described herein according to various embodiments of the present invention.

[0040] It will be appreciated by a person skilled in the art that various modules described herein (e g , the direction determining module 306, the phase difference setting module 308, the carrier signal generating module 310, and / or the carrier signal sending module 312) may be software module(s) realized by computer program(s) or set(s) of instructionsexecutable by a computer processor to perform various functions or operations. Various modules described herein (e.g., the direction determining module 306, the phase difference setting module 308, the carrier signal generating module 310, and / or the carrier signal sending module 312), together with the at least one processor 304 and the at least one memory 302, may also be implemented as hardware module(s) being functional hardware unit(s) designed to perform various functions or operations. More particularly, in the hardware sense, a module is a functional hardware unit designed for use with other components or modules. For example, a module may be implemented using discrete electronic components, or it can form a portion of an entire electronic circuit such as an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA). Numerous other possibilities exist It will also be appreciated by a person skilled in the art that a combination of hardware and software modules may be implemented. Furthermore, various operations, functions or steps of various methods described herein may be performed in parallel rather than sequentially as desired or as appropriate (e g., as long as it does not render the method(s) inoperable or unsatisfactory for its intended purpose).

[0041] It will be appreciated by a person skilled in the art that the terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise It will be further understood that the terms “comprises” and / or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0042] Any reference to an element or a feature herein using a designation such as “first”, “second” and so forth does not limit the quantity or order of such elements or features, unless stated or the context requires otherwise. For example, such designations may be used herein as a convenient way of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not necessarily mean that only two elements can be employed, or that the first element must precede the second element, unless stated or the context requires otherwise. In addition, a phrase referring to “at least one of’ a list of items refers to any single item therein or any combination of two or more items therein.

[0043] In order that the present invention may be readily understood and put into practical effect, various example embodiments of the present invention will be described hereinafter byway of examples only and not limitations. It will be appreciated by a person skilled in the art that the present invention may, however, be embodied in various different forms or configurations and should not be construed as limited to the example embodiments set forth hereinafter. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.|0044] Various example embodiments of the present invention enable ripple current minimization (e g., reduction) in a DC-link capacitor 140 for a SPTSI 110. The SPTSI 110 is a common energy conversion unit for emerging decarbonization applications, such as residential PV systems As shown in FIG. 1 A and described in the background, in the SPTSI 110, a DC- DC boost converter 120 and a H-bridge inverter 130 are connected back-to-back with a DC- link capacitor 140 therebetween serving as an energy buffer. The reliability of the SPTSI 1 10 depends on the lifespan of the DC-link capacitor 140, which decreases significantly with the nns value of the DC-link capacitor current. In this regard, various example embodiments of the present invention provide a simple yet effective method to minimize (e.g., reduce) the switching-frequency capacitor ripple current, thereby extending the DC-link capacitor lifespan and enhancing the reliability of the SPTSI 110. In various example embodiments, the method manipulates the switching pattern of the DC-DC boost converter 120 by modifying its carrier signal Since the duty cycle is unaffected, the method is advantageously compatible with any existing carrier-based control scheme for the SPTSI 110. Experimental results are obtained and will be discussed later below to verify the method of controlling the SPTSI 110 for minimizing a ripple current in a DC-link capacitor 140 of the SPTSI 110 according to various example embodiments of the present invention.

[0045] The capacitor current in the DC-link capacitor 140 of an SPTSI 110 comprises a low-frequency ripple current at twice AC-side fundamental frequency and high-frequency ripple current at the switching frequency of the SPTSI 110 and its multiples. The low-frequency ripple current originates from the single-phase grid connection and must be absorbed by either the DC-link capacitor 140 or the DC energy source (e g., PV or batteries). Due to the negative effect of the low-frequency ripple current on the battery lifespan or the PV power generation, it is preferable that the DC-link capacitor 140 absorbs this low-frequency ripple, which can be achieved with dedicated feedforward compensation strategies (such as described in Jianguo et al., “Research on input current ripple reduction of two-stage single-phase PV grid inverter,” 16th European Conference Power Electronics and Applications, pp. 1-8, August 2014(hereinafter referred to as the Jianguo reference) and Shi et al., “Low-frequency input current ripple reduction based on load current feedforward in a two-stage single-phase inverter,” IEEE Transactions on Power Electronics, vol. 31, no. 11, pp. 7972-7985, November 2016 (hereinafter referred to as the Shi reference)). In contrast, the high-frequency ripple current originates from the switching of the boost converter 120 and the H-bridge inverter 130. In this regard, according to various example embodiments, by coordinating the behavior of the boost converter 120 and the H-bridge inverter 130, their high-frequency ripple currents can at least partially cancel each other out, reducing the high-frequency ripple current in the DC-link capacitor 140. While the practice of reducing ripple current has been explored in several PEC topologies, various example embodiments find no existing practice or method for doing so for the SPTSI 110.

[0046] For example, in Alcaide et al., “Capacitor lifetime extension of interleaved dc-dc converters for multistring PV systems,” IEEE Transactions on Industrial Electronics, vol. 70, no. 5, pp. 4854-4864, May 2023, Monopoli, et al., “Applications and modulation methods for modular converters enabling unequal cell power sharing: Carrier variable-angle phasedisplacement modulation methods,” IEEE Industrial Electronics Magazine, vol. 16, no. 1, pp. 19-30, March 2022, and Alcaide et al., “Common dc-link capacitor lifetime extension in modular dc / dc converters for electric vehicle fast chargers via variable-angle interleaved operation,” IEEE Transactions on Industrial Electronics, vol 70, no. 1 1, pp. 10765-10774, November 2023, control methods are developed to reduce the high-frequency ripple current in the DC-link capacitor for the interleaved boost converter shown in FIG. 4A. In particular, FIG. 4A shows a circuit diagram of a PEC with interleaved boost converters. In this topology, the capacitor current is equal to the sum of output currents of the individual boost converters. By applying carrier-based pulse-width modulation (PWM) and properly phasing the carrier signals, the high-frequency components in the converter output currents will be partially cancelled out, thus reducing the ripple current of the capacitor.

[0047] A discontinuous pulse-width modulation (DPWM) is proposed in Tcai et al., “DC- link ripple reduction in a DPWM-based two-level VSI,” Energies, vol. 11, no. 11, p. 3008, October 2018, to reduce the capacitor ripple current for a three-phase two-level inverter (TPTLI), as shown in FIG. 4B. In particular, FIG. 4B shows a circuit diagram of a PEC with a three-phase inverter. By employing the DPWM, only two legs will switch in each switching period. The DPWM introduces two reversed carrier waveforms for the switching legs to preventall the high-side or low-side switches being on simultaneously, which reduces the capacitor ripple current.

[0048] In Lu et al., “A carrier modulation method for minimizing the de link capacitor current ripple of the HEV dc-dc converter and inverter systems,” 26th Annual IEEE Applied Power Electronics Conference Exposition (APEC), pp. 800-807, March 201 1 (hereinafter referred to as the Lu 2011 reference), and Lu et al., “Theoretical analysis of de link capacitor current ripple reduction in the HEV dc-dc converter and inverter system using a carrier modulation method,” IEEE Energy Conversion Congress and Exposition (ECCE), pp. 2833- 2839, September 2012 (hereinafter referred to as the Lu 2012 reference), the optimal switching behaviour to minimize the capacitor ripple current is studied for the three-phase dc-ac inverter shown in FIG. 4C, with a boost converter as the first stage and a TPTLI (three-phase three-leg inverter) as the second stage. In particular, FIG. 4C shows a circuit diagram of a PEC with a two-stage inverter. According to the studies, the boost converter should switch at twice the frequency of the TPTLI, while the phase angles of the carrier waveforms need to be adjusted at every sampling period. Various example embodiments note that the analysis in the Lu 2011 reference and the Lu 2012 reference assumes the DC-link currents from the boost converter and the TPTLI (iBand iT) have the same sign always.

[0049] In Qin et al., “Investigation into the control methods to reduce the dc-link capacitor ripple current in a back-to-back converter,” IEEE Energy Conversion Congress and Exposition (ECCE), pp. 203-210, September 2014 (hereinafter referred to as the Qin reference), Shen et al., “Active dc-link capacitor harmonic current reduction in two-level back-to-back converter,” IEEE Transactions on Power Electronics, vol. 31, no. 10, pp. 6947-6954, October 2016 (hereinafter referred to as the Shen reference), and Tcai etal., “DC-link capacitor-current ripple reduction in DPWM-based back-to-back converters,” IEEE Transactions on Industrial Electronics, vol. 65, no. 3, pp. 1897-1907, March 2018 (hereinafter referred to as the Tcai reference), the capacitor ripple current is reduced for the ac-dc-ac converter shown in FIG 4D, by coordinating the switching behaviours of the two back-to-back TPTLIs. In particular, FIG. 4D shows a circuit diagram of a PEC with a three-phase ac-dc-ac converter. Particularly, the analysis in the Qin reference and the Shen reference considers sinusoidal PWM and manipulates the carrier waveforms, while the Tcai reference proposes a DPWM that manipulates the clamping behaviour of the two TPTLIs.

[0050] Furthermore, there exist research on reducing the capacitor ripple current for other PEC topologies, including the three-level T-type inverter, multidrive systems, active neutral-point-clamped converter, and so on. However, none of the aforementioned existing methods are readily applicable to the SPTSI 110, shown in FIG. 1A, due to the topology difference, which changes the operating principle and the ripple current. For instance, the existing methods as described with reference to FIG. 4A are not applicable since there is no interleaved boost converter in the SPTSI and their analysis neglects the ripple current from the inverter. As another example, the analysis in the Lu 2011 reference and the Lu 2012 reference as described with reference to FIG. 4C assumes the current from the boost converter and the inverter (iBand iTas shown in FIG. 4C) have the same sign always. In this regard, various example embodiments note that the same sign occurs in the SPTSI 110 only if the H-bridge inverter 130 operates at unity power factor. When the H-bridge inverter 130 does not operate at unity power factor, applying the methods in the Lu 2011 reference and the Lu 2012 reference to the SPTSI 110 can lead to relatively large high-frequency ripple current in the DC-link capacitor 140. |0051| Accordingly, despite being a popular topology, various example embodiments found that a significant research gap remains in the development of methods or strategies to minimize (e.g., attenuate) high-frequency ripple current in the DC-link capacitor 140 of the SPTSI 110 shown in FIG. 1A. The existing control methods are limited to the mitigation of low-frequency ripple in the de energy source (e.g., the methods described in the Jianguo reference and the Shi reference) In sight of this research gap, various example embodiments of the present invention provide a method of controlling a SPTSI 110, and a system thereof, for minimizing (e.g., reducing) a ripple current (or more particularly, the high-frequency ripple current) in a DC-link capacitor 140 of the SPTSI 110 in an effective and practical manner for enhancing a lifespan of the DC-link capacitor 140 in the SPTSI 110, and thus the reliability of the SPTSI 110. In various example embodiments, the method merely modifies the switching behaviour of the boost converter 120 by manipulating its carrier waveform in a particular manner without affecting the duty cycle. Thus, the method is compatible with conventional carried-based control schemes for the SPTSI 110, such as the carrier-based control scheme described in the Jianguo reference to regulate the output power and capacitor voltage. The method is applicable to operations at any power factor. In addition, the method can be extended to the cascaded H-bridge (CHB) converter with multiple SPTSIs cascaded in series, such as shown in FIG. IB.

[0052] For better understanding, the capacitor lifespan and the capacitor ripple current in the SPTSI 1 10, including an example mathematical model for the DC-link capacitor 140, willnow be described. In particular, the established lifespan model of capacitors and the capacitor ripple current within the SPTSI 110 are described.Capacitor Lifespan

[0053] An established lifetime model for aluminium electrolytic capacitors is given as:(Equation 1) where Lo, Vo, and Torefer to the lifetime, capacitor voltage, and temperature under the nominal condition, respectively, n is the voltage stress parameter, while Vcand T refer to the actual capacitor voltage and temperature, respectively. The temperature change, i.e., T — To, corresponds to:T — To— fmsRRT,(Equation 2) where Irmsrefers to the rms value of capacitor current ic, R and Rrrefer to the capacitor equivalent series resistance (ESR) and capacitor thermal resistance, respectively. As can be observed from Equations (1) and (2), the capacitor lifespan is significantly affected by the capacitor current ic.Capacitor Ripple Current

[0054] As shown in FIG. 1A, the capacitor current icin the SPTSI 110 corresponds to:(Equation 3) where iBrefers to the output current of the boost converter 120 while iHrefers to the dc-side current (or the input current) of the H-bridge inverter 130.

[0055] Note that iHand iBdepend on the status of switches Sx, with Sxe {0, 1} and x 6 {1, 2, 3} referring to the switch index in FIG. 1 A. If Sx— 1, the switch Sxis on while Sxis off, and vice versa. Accordingly, Equation (3) can be rewritten as:(Equation 4) where iLrefers to the inductor current of the boost converter 120 and iacrefers to the inverter AC-side current (or the inverter output load current), as shown in FIG. 1 A. The values of Sxisdecided or determined by its corresponding duty cycle dxand carrier waveform, as will be described later below.

[0056] Regarding the H-bridge inverter 130, its duty cycles depend on whether bipolar or unipolar modulation technique is utilized. In various example embodiments, the unipolar modulation technique is considered as it yields a lower rms value of iH. Accordingly, the duty cycles for switches Stand S2may be given as:(Equation 5) where m E [—1, 1] refers to the modulation reference of the H-bridge inverter 130 For illustration, the left plot of FIG. 5 A provides the waveforms ofd2and the carrier waveform of the carrier signal cHin a period of the AC-side voltage (T), while the right plot shows a zoom-in view of the waveforms. The consequent waveforms of S1and S2are provided in FIG. 5B, while the waveforms of iacand iHare shown in FIG. 5C. In particular, FIGs. 5A to 5C show waveforms of the H-bridge inverter 130 under unipolar modulation for: carrier signal cHand duty cycles d1and d2(FIG. 5A); switches status 5^ and S2(FIG. 5B); and lacand iH(FIG. 5C). As observed, denoting the frequency of cHas fCH, the pulse period of iHcorresponds to:1TH~ WH(Equation 6)

[0057] Regarding the boost converter 120, the duty cycle of switch .S'3is decided or determined by the output current controller, denoted as d3E [0, 1], For illustration, FIG. 6A shows the waveforms of d3, S3and the carrier waveform of the carrier signal cB. FIG. 6B shows the consequent waveform of iB. In particular, FIGs. 6A and 6B show waveforms of the boost converter 120 for: carrier signal cB, duty cycle d3and switch S3(FIG. 6A); and iLand iB(FIG. 6B). As can be observed, denoting the frequency of cBas fCB, the pulse period of iBcorresponds to:(Equation 7)

[0058] For better understanding and without limitation, technical analysis and derivations associated with the method for controlling a SPTSI 110 for minimizing (e.g., reducing) a ripple current (or more particularly, the high-frequency ripples in ic, thus reducing its rms value) in the DC-link capacitor 140 of the SPTSI 110 will now be described according to various exampleembodiments of the present invention (e g., corresponding to the method 200 of controlling a SPTSI 110 as described hereinbefore according to various embodiments of the present invention). In various example embodiments, the technical analysis assumes iLand iacare almost constant within the switching period, since ripples in iLare normally suppressed and the inverter switching frequency is much higher than the fundamental frequency of iac.

[0059] From Equation (3), icrefers to the difference between iHand iB, which are both pulse waveforms. For illustration and better understanding, FIG. 7 shows waveforms of one pulse of iHand iB, where the respective dash line in the middle represents the symmetry axis of iHand tB, respectively. In this regard, various example embodiments found that iHand iBcan be at least partially cancelled out by coordinating their pulses, leading to a reduced ic, as will be further analyzed below. Although FIG 7 assumes iH> iBand they have the same polarity, the technical analysis below according to various example embodiments of the present invention is applicable to other scenarios without losing generality.

[0060] From FIG. 7, the Fourier series of iHwithin one switching period ( t G [t0— TH / 2 , t0+ TJJ / 2]) corresponds to:(Equation 8) where dHrefers to the duty cycle of the pulse, iHPrefers to the peak value of iHwithin this switching period, and ancorresponds to:(Equation 9) where n refers to the harmonic index with respect to the switching frequency. According to FIGs. 5A to 5C, both dHand iHPcan change along the fundamental period due to the modulation of the H-bridge inverter 130:(Equation 10)Therefore, the Fourier series of iHin Equation (8) also changes along the fundamental period.[0061 J Similarly, the Fourier series of iBcorresponds to:(Equation 11) where At refers to the time shift between the symmetry axis of iHand iB, as depicted in FIG. 7, and bncorresponds to:(Equation 12)Note that in the steady state, both iLand d3are constant along the fundamental period.

[0062] Combining Equations (3), (8) and (11), icmay be given as: (ig — ig)(Equation 13) where iBand ip refer to the / nh-order AC component in iBand iH. respectively:(Equation 14)According to Equations (13) and (14), the DC component of icis independent from the carrier waveforms but the AC components are affected by the carrier waveforms via TH, TB, and At, which represent the degrees of freedom to minimize the AC components in ic.

[0063] From Equation (14), will have the same periodicity. Then,with an appropriate value of nd ip can at least partly cancel out, which can thusminimize the rms value of ic.

[0064] According to Equations (6) and (7), to have TH— TB, there should be:(Equation 15)which defines the relationship between the frequencies of carrier signals cBand cH. Accordingly, in various example embodiments, to configure or generate the carrier signals cBand cHhaving the same pulse period, the set frequency fCBfor the carrier signal cBis twice the set frequency fCHfor the carrier signalWhen Equation (15) is satisfied, i.e., ation (13) can be rewritten using trigonometry as:(Equation 16) with(Equation 18)

[0065] Accordingly, the rms value of icmay be given as:(Equation 19)

[0066] From Equation (17), the values of cnare affected by At, and thus, according to various example embodiments of the present invention, At can be manipulated or controlled to minimize cn.

[0067] According to Equations (9) and (12), various example embodiments of the present invention found that both anand bncan be either positive or negative, thus their directions can change with n. When anand bnhave the same direction, from Equation (17), the value of cnwill be minimized if:(Equation 20)

[0068] Meanwhile, when anand bnhave different directions, from Equation (17), the value of cnwill be minimized with:(Equation 21)

[0069] Combining Equations (20) and (21), the optimal At to minimize cn, denoted as Atn, corresponds to:(Equation 22) which indicates that the optimal At can be different for various n (i.e., depending on n). In this regard, various example embodiments of the present invention note that anbn> 0 for n = i does not guarantee that anbn> 0 for n #= i. Nevertheless, as it can be observed from Equations (9) and (12), both anand bnare inversely proportional to n, thus arand b3are the dominant components. Accordingly, At can be decided or determined as the one that minimizes c15i.e.,(Equation 23)

[0070] From Equations ( correspond to:(Equation 24) where 0 < dH< 1 and 0 < d3< 1, indicating sin(dH7t) > 0 and sin(d37t) > 0. Therefore, Equation (23) can be rewritten as:(Equation 25)

[0071] Combining Equations (10) and (25) yields:(Equation 26) where m, iac, and iLare available variables within the control of the SPTSI 110. As the sign of miaciLcan change along the fundamental period of the ac-side of the SPTSI 110 (e.g., 20ms if the SPTSI is connected to Singapore ac grid), in various example embodiments of the present invention, At may be computed at the same frequency as the switching frequency of the boost converter 120. Accordingly, in various example embodiments, the method of controlling a SPTSI 110 according to various example embodiments may be performed at the samefrequency as the switching frequency of the boost converter 120. For example, At may be computed by the phase difference setting module 308 as described hereinbefore according to various embodiments. Notably, although At in Equation (26) is chosen to minimize ct(the switching-frequency harmonic), it also leads to the minimum irms, as will be explained below.

[0072] FIGs. 8A, 8C and 8E illustrate the carrier waveforms and the consequent current waveforms of iH, iB, and icobtained with carrier signals cHand cBgenerated using the method of controlling a SPTSI 110 according to various example embodiments of the present invention (according to the above technical analysis) when iHPiL> 0 . FIG. 8A shows the carrier waveforms, which satisfy Equation (15) and At = 0, that is, the phase difference between the carrier signals cHand cBis 0. For example, as can be seen in FIG. 8A, the difference between the positions of minimum values (i.e., 0) of the carrier signals cBand cHis 0. The consequent iHand iB(At = 0) are shown in FIG. 8C and the consequent ic(J-HPIL 0) is shown in FIG. 8E. As can be observed, the carrier signals cHand cBaccording to various example embodiments of the present invention maximize the shaded interval where both iBand icare nonzero. That is, the overlapping period or region of the non-zero portions of iBand icare maximized. Denoting the length of shaded interval within one switching period (TH) as d-NZ^H, the rms value of iccan be calculated with:(Equation 27)

[0073] Accordingly, lrmscorresponds to:(Equation 28) which indicates that Irmsdecreases with dNZ. Since the carriers according to various example embodiments of the present invention maximize dNZwhen i.HPiL> 0, Irmsis minimized in this scenario.

[0074] Similarly, FIGs. 8B, 8D and 8F illustrate the carrier waveforms and the consequent current waveforms of iH, iB, and icobtained with carrier signals cHand cBgenerated using the method of controlling a SPTSI 110 according to various example embodiments of the present invention (according to the above technical analysis) when iHPiL< 0. FIG. 8B shows the carrier waveforms, which satisfy Equation (15) and At = TH / 2. that is, the phase difference between the carrier signals cHand cBis TH / 2. For example, as can be seen in FIG. 8B, the difference between the positions of minimum values (i e , 0) of the carrier signals cBand cHisTHI2. The consequent tHand iB(At — TH / 2) are shown in FIG. 8D and the consequent ic(ifipi-L < 0) is shown in FIG. 8F As can be observed, the carrier signals cHand cBaccording to various example embodiments of the present invention minimize the shaded interval where both iBand icare nonzero, i.e., minimizing dNZTH. That is, the overlapping period or region of the non-zero portions of iBand tcare minimized. Note that when iHpi-L < 0, Irms corresponds to:(Equation 29) which indicates that Irmsincreases with dNZand lrmsis thus minimized with the carrier signals generated according to various example embodiments of the present invention. Furthermore, according to Equations (28) and (29), the optimal pair of carriers for iHPiL> 0 is the worst for inpi-L < 0 , andviceversa. Therefore, in various example embodiments, the carriers are modified during the operation to avoid increasing Irmsunnecessarily.

[0075] To verify the above technical analysis (i.e., the method of controlling a SPTSI 110 according to various example embodiments of the present invention), FIGs. 9A and 9B show current waveforms of iH, iB, and icobtained with different carrier signals (different from the carrier signals cHand cBgenerated using the method of controlling a SPTSI 1 10 according to various example embodiments of the present invention) when iHPiL> 0. FIG. 9 A shows the current waveforms of iH, iB, and icwhen the implemented carrier signals have the same frequency but different phase difference as those carrier signals generated using the method of controlling a SPTSI 110 according to various example embodiments of the present invention. Specifically, with the method of controlling a SPTSI 110 according to various example embodiments of the present invention, the phase difference between the carrier signals cHand cBis 0. However, in the case of FIG. 9A, the phase difference between the carrier signals cHand cBis TH / 2. In particular, as can be observed from FIG. 9A, the shaded intervals with both iBand icnonzero are minimized, yielding a large icwith an rms value of 7.47 A. FIG. 9B shows the current waveforms with a common carrier for both the H-bridge inverter 130 and the boost converter 120, i.e., Equation (15) is not satisfied The consequent rms value of icis 5.60 A. In comparison, according to the above technical analysis, the optimal carrier signals are the ones shown in FIGs. 8A. The consequent iH, iB, and icare shown in FIGs. 8C and 8E, yielding a 2.80-A rms value for ic.

[0076] Similarly, FIGs. 10A and 10B show current waveforms of iH, iB, and icobtained with different carrier signals (different from the carrier signals cHand cBgenerated using the method of controlling a SPTSI 110 according to various example embodiments of the present invention) when iHPiL< 0. FIG. 10A shows the current waveforms of iH, iBand icwhen the implemented carrier signals have the same frequency but different phase difference as those carrier signals generated using the method of controlling a SPTSI 1 10 according to various example embodiments of the present invention. Specifically, with the method of controlling a SPTSI 110 according to various example embodiments of the present invention, the phase difference between the carrier signals cHand cBis TH / 2. However, in the case of FIG. 10A, the phase difference between the carrier signals cHand cBis 0. FIG. 10B shows the current waveforms of iH, iB, and icwith a common carrier for both the H-bridge inverter and the boost converter, i.e., Equation (15) is not satisfied. The rms values of icunder these two cases are 4.98A and 4.59 A, respectively. In comparison, according to the above technical analysis, the optimal carrier signals are the ones shown in FIG. 8B. The consequent iH, iB, and icare shown in FIGs. 8D and 8F, yielding a 4.20-A rms value for ic. Therefore, the results in FIGs 9A, 9B, 10A and 10B verify the capability of the method of controlling a SPTSI 110 according to various example embodiments of the present invention to minimize (e g , reduce) the rms value of the ripple current icin the DC-link capacitor of the SPTSI 110.

[0077] Accordingly, various example embodiments of the present invention provide a method of controlling a SPTSI 110 which seeks to minimize the ripple current of the DC-link capacitor 140 of the SPTSI 110 by manipulating or controlling the switching behaviours of the H-bridge inverter 130 and the booster converter 120 based on the relative direction of the current iBand iH. In particular, the method first makes iBand iHhave the same pulse period. Then, if iBand iHhave the same direction, the switching behaviours of the H-bridge inverter 130 and the boost converter 120 are manipulated or controlled to maximize the overlapping period or region of the non-zero portions of iBand iH(as discussed above with reference to FIGs. 8A, 8C and 8E). On the other hand, if iBand iHhave different directions, the switching behaviours of the H-bridge inverter 130 and the boost converter 120 are manipulated or controlled to minimize the overlapping period or region of the non-zero portions of iBand iH(as discussed above with reference to FIGs. 8B, 8D and 8F). Therefore, it will be appreciated by a person skilled in the art that any method of controlling a SPTSI 110 configured to control the switching behaviours of the H-bridge inverter 130 and the booster converter 120 in themanner described above to minimize the ripple current of the DC-link capacitor 140 of the SPTSI 110 is within the scope of the present invention, regardless of implementation details.

[0078] FIG 11A depicts a schematic block diagram of an example method 1100 of controlling a SPTSI 110 for minimizing a ripple current in a DC-link capacitor 140 thereof, according to various example embodiments of the present invention (e g , corresponding to the method 200 of controlling a SPTSI 110 as described hereinbefore according to various embodiments of the present invention). The method 1100 comprises: determining a relative direction between an output current iBof the DC-DC boost converter 120 and an input current iHof the H-bridge inverter 1 0; setting a phase difference between a first carrier signal cBfor the DC-DC boost converter 120 and a second carrier signal cHfor the H-bridge inverter 130 based on the determined relative direction between the output current iBof the DC-DC boost converter 120 and the input current iHof the H-bridge inverter 130; generating the first and second carrier signals cBand cHhaving the set phase difference therebetween, and sending the first and second carrier signals to a first switching signal generator (or a first switching signal generating module) 1142 and a second switching signal generator (or a second switching signal generating module) 1152, respectively. In this regard, the first switching signal generator 1142 is configured to generate a first switching signal based on the first carrier signal cBfor controlling a first set of switches (e.g., a first pair of switches S3, S3~) of the DC-DC boost converter 120. The second switching signal generator 1152 is configured to generate a second switching signal and a third switching signal based on the second carrier signal cHfor controlling a second set of switches (e.g., a second pair of switches S^Si) and a third set of switches (e.g., a third pair of switches S2, S2), respectively, of the H-bridge inverter 130.

[0079] In various example embodiments, the method 1100 further comprises setting a frequency fCBfor the first carrier signal cBand a frequency fCHfor the second carrier signal cHsuch that a pulse period TBof the first carrier signal cBand a pulse period THof the second carrier signal cHare the same. That is, the frequency fCBfor the first carrier signal cBand the frequency fCHfor the second carrier signal cHare set such that the first and second carrier signals cBand cHhave the same pulse period (i.e., TB= TH). In this regard, the above- mentioned generating (at 210) the first and second carrier signals comprises generating the first carrier signal cBand cHhaving the set frequency fCBfor the first carrier signal cBand generating the second carrier signal cHhaving the set frequency fCHfor the second carrier signal cH. Therefore, the first and second carrier signals cBand cHare generated to have the set phase difference therebetween and the respective set frequency.

[0080] In various example embodiments, the set frequency fCBfor the first carrier signal cBis twice the set frequency fCHfor the second carrier signal cH. Accordingly, in various example embodiments, the frequency fCBof the first carrier signal cBand the frequency fCHof the second carrier signal cHhave a predefined relationship therebetween, namely, fCB— fCH / 2 (i.e., according to the above-mentioned Equation 15).

[0081] In various example embodiments, the relative direction determined between the output current iBof the DC-DC boost converter 120 and the input current iHof the H-bridge inverter 130 is one of a same direction and an opposite direction.

[0082] In various example embodiments, as illustrated in FIG. 11 A, the phase difference between the first and second carrier signals cBand cHis set to in phase based on detennining that the relative direction between the output current iBof the DC-DC boost converter 120 and the input current iHof the H-bridge inverter 130 is the same direction. Furthermore, as also illustrated in FIG. 11 A, the phase difference between the first and second carrier signals cBand cHis set to out of phase based on determining that the relative direction between the output current iBof the DC-DC boost converter 120 and the input current iHof the H-bridge inverter 130 is the opposite direction In various example embodiments, the phase difference between the first and second carrier signals cBand cHbeing set to in phase is setting the phase difference to 0. For example, as described above according to various example embodiments, FIG 8A illustrates an example of the phase difference between the first and second carrier signals (cBand c;f) being set to in phase, and more particularly, being set to 0 whereby the difference between the positions of minimum values (i.e., 0) of the first and second carrier signals (cBand cH) is 0. Furthermore, the phase difference between the first and second carrier signals being set to out of phase is setting the phase difference to half of a pulse period of the first or second carrier signal cBor cH. For example, as described above according to various example embodiments, FIG. 8B illustrates an example of the phase difference between the first and second carrier signals (cBand cH) being set to out of phase, and more particularly, being set to half of a pulse period (e.g., Tlf) of the second carrier signal whereby the difference between the positions of minimum values (i.e., 0) of the first and second carrier signals (cBand cw) is TH / 2.

[0083] In various example embodiments, as illustrated in FIG. 11 A, the relative direction between the output current iBof the DC-DC boost converter 120 and the input current iHof the H-bridge inverter 130 is determined based on an input inductor current iLof the DC-DC boost converter 120 and an inverter output load current iacof the H-bridge inverter 130 In various example embodiments, the relative direction is determined based on a sign of a product of theinput inductor current iL, the inverter output load current iacand a modulation reference signal m of the H-bridge inverter 130. In various example embodiments, the relative direction between the output current iBof the DC-DC boost converter 120 and the input current iHof the H-bridge inverter 130 is determined as the same direction based on determining that the sign of the product of the input inductor current iL, the inverter output load current iacand the modulation reference signal is positive (e.g., iacm^L > 0 as illustrated in FIG. 11 A). Furthermore, the relative direction between the output current iBof the DC-DC boost converter 120 and the input current iHof the H-bridge inverter 130 is determined as the opposite direction based on determining that the sign of the product of the input inductor current iLthe inverter output load current iacand the modulation reference signal is negative (e.g., iacmiL< 0 as illustrated in FIG. 11 A).

[0084] In various example embodiments, the set phase difference between the first and second carrier signals cBand cHmay be obtained or achieved by: (i) adjusting (e g., shifting) the first carrier signal cBwhile maintaining the second carrier signal cHto achieve the set phase difference therebetween, (ii) adjusting the second carrier signal cHwhile maintaining the first carrier signal cBto achieve the set phase difference therebetween, or (iii) adjusting both the first and second carrier signals cBand cHto achieve the set phase difference therebetween.

[0085] In various example embodiments, the method 1100 further comprises: generating, using the first switching signal generator 1142, the first switching signal based on the first carrier signal cBfor controlling the first set of switches (e.g., the first pair of switches S3,S3) of the DC-DC boost converter 120; and generating, using the second switching signal generator 1152, the second switching signal and the third switching signal based on the second carrier signal cBfor controlling the second set of switches (e.g., the second pair of switches SltSx) and the third set of switches (e.g., the third pair of switches S2, S2), respectively, of the H-bridge inverter 130. In various example embodiments, the first switching signal is generated based on the first carrier signal cBand a first duty cycle signal d3for the first set of switches of the DC- DC boost converter 120. The second switching signal is generated based on the second carrier signal cHand a second duty cycle signal dtfor the second set of switches of the H-bridge inverter 130. The third switching signal is generated based on the second carrier signal cHand a third duty cycle signal d2for the third set of switches of the H-bridge inverter 130. For example, the first duty cycle signal d3may be generated by a boost converter controller 1140. The second and third duty cycles dx, d2may be generated by a duty cycle signal generator 1151(e g., according to the above-mentioned Equation (5) based on the modulation reference signal m from a H-bridge inverter controller 1150.

[0086] For example, based on the duty cycle signal ds and the carrier signal CB, the first switching signal generator 1142 generates the switching signal for switches (S3and S3) of the boost converter 120 by comparing the duty cycle signal ds and the carrier signal cB. If the duty cycle signal ds is higher than carrier signal cB, the lower switch S3is turned on while the upper switch S3is turned off. If the duty cycle signal ds is not higher than carrier signal cB, the lower switch S3is turned off while the upper switch S3is turned on. In a similar manner, the second switching signal generator 1152 generates the switching signal for switches S2and S2of the H- bridge inverter 130 by comparing the duty cycle signal ds and the carrier signal CH. In a similar manner, the second switching signal generator 1152 generates the switching signal for switches S and S±of the H-bridge inverter 130 by comparing the duty cycle signal di and the carrier signal CH. It will be appreciated by a person skilled in the art that the duty cycle signals (t / i, ds, ds) and the switching signals (Si and S , S2and S2, S3and S3) are not limited to being generated in the manner as described above and may be generated using different methods as desired or as appropriate without going beyond the scope of the present invention.

[0087] Accordingly, the method 1100 reduces the rms value of icby manipulating the carrier waveforms cBand / or cHin the manner as described above according to various example embodiments of the present invention. In various example embodiments, the method 1100 controls the H-bridge inverter 130 to switch at half the switching frequency of the boost converter 120, to satisfy the above-mentioned Equation (15). In addition, according to various example embodiments, depending on whether miaciL> 0 holds true or not, the method 1100 adjusts the phase difference between carrier signals cBand cH, for example, by shifting carrier signal cBwhile retaining carrier signal cB. If miaciL> 0 , the carrier signals cBand cHgenerated are as shown in FIG. 8A. Otherwise, the carrier signals cBand cHgenerated are as shown in FIG. 8B. In various example embodiments, as shown in FIGs. 8A and 8B, the first and second carrier signals cBand cHeach has a triangular carrier waveform. Accordingly, the carrier waveforms of the carrier signals cBand cHfor the boost converter 120 and the H-bridge inverter 130, respectively, are determined according to whether iBand iHhave the same direction Thus, the carrier waveforms of the carrier signals cBand cHare coupled according to the method 1100, which differs from the conventional practices as shown in FIG. 11B where the carrier signals cBand cHare decoupled. Conventionally, the boost converter may switch at the same frequency as the inverter or twice the switching frequency of the inverter, but withouttaking into account the effect of switching behaviours on the ripples of ic. In addition, the conventional practices do not leverage the phase difference between carrier signals cBand cH, which has a significant effect on ic. Comparing FIGs. 11 A and 1 IB, applying the method 1100 according to various example embodiments of the present invention, a simple block 1160 may simply be added to manipulate (e.g., shift) the carrier signal cBbased on the sign of miaciL, and thus it is simple and cost effective to implement. Furthermore, in various example embodiments, the method 1100 does not affect the duty cycles (dx, d2and d3), making it compatible with existing controllers for the SPTSI 110 that use carrier-based PWM. For instance, the method 1100 is compatible with feedforward compensation strategies disclosed in the above Jianguo reference and the Shi reference to suppress the low-frequency ripple in the boost inductor current.

[0088] Accordingly, a system (or a control system) corresponding to the method 1 100 for controlling a SPTSI 110 for minimizing a ripple current in a DC-link capacitor 140 thereof, is also provided according to various example embodiments of the present invention. The system may comprise a carrier signal generator 1160 configured to generate the first and second carrier signals cBand cHin the manner as described herein according to various example embodiments of the present invention. The system may further comprise the first switching signal generator 1142 configured to generate the first switching signal based on the first carrier signal cBfor controlling the first set of switches (e.g., the first pair of switches S3,S3) of the DC-DC boost converter 120; and the second switching signal generator 1152 configured to generate the second switching signal and the third switching signal based on the second carrier signal cHfor controlling the second set of switches (e.g., the second pair of switches S^Sj) and the third set of switches (e.g., the third pair of switches S2,S2), respectively, of the H-bridge inverter 130. In various example embodiments, the system may further comprise a boost converter controller 1140 configured to generate the first duty cycle signal d3. In this regard, the first switching signal may be generated based on the first carrier signal cBand the first duty cycle signal d3for the first set of switches of the DC-DC boost converter 120. The system may further comprise a H-bridge inverter controller 1 150 configured to generate the modulation reference signal m; and a duty cycle signal generator 1151 configured to generate the second and third duty cycle signals dx, d2based on the modulation reference signal m. In this regard, the second switching signal may be generated based on the second carrier signal cHand the second duty cycle signal d1for the second set of switches of the H-bridge inverter 130. The third switching signal may be generated based on the second carrier signal cHand the third duty cycle signal d2for thethird set of switches of the H-bridge inverter 130. In various example embodiments, various modules of the system (e.g., the carrier signal generator 1160, the H-bridge inverter controller 1150, the duty cycle signal generator 1151, the second switching signal generator 1152, the boost converter controller 1140 and the first switching signal generator 1142) may be implemented as software modules realized by computer programs or sets of instructions executable by a computer processor to perform the corresponding functions or operations, such as in the form of control codes (also referred to as embedded control firmware) on a control unit (e g., TI C2000 series microcontrollers). The control unit may be communicatively coupled with the SPTSI 110 for enabling data communication therebetween, such as obtaining various measurements from the SPTSI 110 and sending control instructions (e g., switching signals) to the SPTSI 110. As another example, various modules of the system may be implemented in the form of simulation files on various simulation platform (e g., MATLAB SIMULINK) for simulation purposes. As a further example, various modules of the system may be implemented as hardware modules, such as in an analog manner via operational amplifiers and various passive components.Experimental Verification

[0089] To verify the capacitor ripple current reduction of the method 1100 according to various example embodiments of the present invention, experimental results are obtained using an example prototype of the SPTSI 110 of FIG. 1A. FIG. 12A shows an overview of the example prototype for controlling the SPTSI 110, while various parameters of the example prototype are provided in Table I shown in FIG. 12B. A 75-V de voltage source is connected to the input of the boost converter 120, while the DC-link capacitor voltage is controlled to 150 V with d3= 0.5. A resistive-inductive load is connected to the AC-side of the H-bridge inverter 130, whose normalized reference signal is given as m — 0.8 cos(1007Tt). The switching signals are generated by standard PWM techniques as explained hereinbefore. When the method 1100 is applied, the boost converter 120 and H-bridge inverter 130 switch at 20 kHz and 10 kHz, respectively, to satisfy Equation (15).

[0090] FIG. 13 A presents the recorded experimental waveforms using the method 1100 over 2.5 fundamental cycles. At the bottom of FIG 13A, the Channel 8 waveform indicates the direction of miaciL, while the dashed line marks the corresponding zero axis. As depicted in FIG. 13A, carrier signals cBand cHtoggle between two patterns when the sign of miaciLchanges, occurring four times per fundamental cycle.

[0091] FIG. 13B shows a zoom-in version of current waveforms ic, iB, and iHwhen miaciLchanges from positive to negative. As can be observed, when miaciLis positive, iHand iBare in the same direction and in phase to minimize ic, which matches the technical analysis in FIGs. 8C and 8E. Conversely, when miaciLbecomes negative, iHand iBhave opposite directions and are out of phase to minimize ic, which is consistent with the technical analysis outlined in FIGs. 8D and 8F.

[0092] To demonstrate the capacitor ripple current reduction of the method 1100 according to various example embodiments of the present invention, a comparison study was conducted with three experimental cases. In Case I, the present method 1100 is applied. Case II follows the practice in Tafti et al., “An adaptive control scheme for flexible power point tracking in photovoltaic systems, IEEE Transactions on Power Electronics, vol. 34, no. 6, pp. 5451-5463, June 2019, where the boost converter switches at twice the switching frequency of the H-bridge inverter without a specified At. Thus, the converter and inverter switch at 20 kHz and 10 kHz, respectively, with At = TH / 2 as shown in FIG. 8B. Case III follows the practice in the above- mentioned Jianguo reference, where the boost converter and H-bridge inverter switch at the same frequency without a specified At. Thus, both the converter and inverter switch at 20 kHz with At = 0.

[0093] FIGs. 14A, 14B and 14C provide the recorded experimental waveforms of vac, ic, iH, and iBfor the three experimental cases (Case I, Case II, Case III), respectively, within five fundamental periods (0.1 s). The current waveforms for ic, iHand iBare shown. FIG. 14A provides the current waveforms in Case I with the present method 1100, where the left bottom and right bottom provide a zoomed-in version of the waveforms when vacis negative and positive, respectively. As can be observed, iHand iBhave the same pulse period, i.e., TH=TB, and they become zero or nonzero almost simultaneously and partly cancel out, yielding a relatively small icwith an rms value of 1.95 A. FIG. 14B provides the current waveforms in Case II In this case, as can be observed, iHand iBalso have the same pulse period. However, iHand iBare nonzero at different interval and do not cancel out, yielding a relatively large icwith an rms value of 3.18 A. Compared to Case I, the rms value of icincreases by 63%. FIG. 14C provides the current waveforms in Case III As can be observed, the pulse period of iBis twice the pulse period of iH, i.e., TB= 2TH. Consequently, iHand iBonly cancel out during a few intervals, yielding an icwith an rms value of 2.53 A. This represents a 30% increase in the rms value of icwith respect to Case I.

[0094] For a further investigation into the ripple current reduction, FIGs. 15 A, 15B and 15C show the frequency spectrum of iB, iH, and icin the three experimental cases (Case I, Case II, Case III), respectively. FIG. 15A provides the results in Case I. As can be observed, iBhas a relatively large harmonic component at 20 kHz (2.21 A), corresponding to the switching frequency of the boost converter 120. Current iHhas main harmonic components at 100 Hz (1.84 A) and 20 kHz (1.49 A), corresponding to twice the fundamental frequency and the equivalent switching frequency of the inverter, respectively. Note that the equivalent switching frequency of the H-bridge inverter is twice of its actual switching frequency with the unipolar modulation scheme. Since iccorresponds to the difference between iBand iH, it has main harmonic components at 100 Hz (1.85 A) and 20 kHz (0.78 A). Nonetheless, the 20-kHz harmonic of icis significantly smaller than those in iBand iH, demonstrating that 20-kHz harmonics in iBand iHpartly cancel out with the present method 1100. FIG. 15B provides the results for Case II, which are similar to those in Case I except that the 20-kHz harmonic of ic(3.72 A) is approximately 377% larger. The results indicate that without a proper phase difference At as determined in the present method 1100, the switching-frequency harmonic in icdramatically increases. FIG. 15C provides the results for Case III, where iBis similar to that in Case I while iHhas its main harmonic component at 40 kHz (2.29 A) as the inverter switches at 20 kHz. Consequently, tchas large harmonic components of 100 Hz (1.77 A), 20 kHz (2.12 A), and 40 kHz (1.37 A). The results show that without proper switching frequencies, the harmonic content in icincreases. Accordingly, it has been demonstrated that the present method 1100 reduces the switching-frequency harmonic content in ic, thus leading to a lower rms value.

[0095] With the recorded rms values of icin the three experimental cases, the corresponding capacitor lifespan can be calculated using Equations (1) and (2). According to the datasheet of aluminium capacitor from KEMET Corporation, which are used in the experiments, the nominal ESR can be up to a few hundred m£l, while the actual ESR can be twice higher than the nominal value due to degradation. According to Alcaide et al. , “Capacitor lifetime extension of interleaved dc-dc converters for multistring PV systems,” IEEE Transactions on Industrial Electronics, vol. 70, no. 5, pp. 4854-4864, May 2023, the thermal resistance of capacitors without a heatsink is assumed as 5 K / W. FIG. 16 illustrates the capacitor lifespan for the three experimental cases under various ESR (capacitor equivalent series resistance) values, where Lcdenotes the expected lifespan with zero ic. As observed, the present method 1 100 (Case I) significantly improves capacitor lifespan compared to the othercases, especially under high ESR conditions. Since the ESR of capacitors tends to increase due to degradation over time, the benefits of applying the proposed method become more pronounced as the system ages.

[0096] FIG. 17 shows a table (Table II) which summarizes the comparison among the three experimental cases. As can be observed, Case I with the present method 1 100 shows a significantly better performance than the other two cases without increasing the switching frequencies.

[0097] Therefore, various example embodiments of the present invention provide an effective and practical method 1100 for controlling a SPTSI 110 for minimizing (e g., reducing) a ripple current in a DC-link capacitor thereof The present method 1100 is able increase the capacitor lifespan and improve the system reliability. As described hereinbefore according to various example embodiments, the present method 1 100 coordinates the switching behaviours of the boost converter 120 and the H-bridge inverter 130, resulting in at least partial cancellation of their pulsed-width modulated currents. In various example embodiments, the present method 1100 simply manipulates the carrier waveform of the boost converter 120 without changing its duty cycle and thus, it is compatible with conventional carrier-based control schemes. In the experimental case studies, it was demonstrated that the present method 1100 reduced the rms value of the capacitor ripple current by more than 60%, which can effectively increase the capacitor lifespan depending on the capacitor ESR value.

[0098] Accordingly, the present method 1100 is able to enhance the reliability of a general SPTSI 110 as shown in FIG. 1A, whose front stage (boost converter 120) is connected to a DC source / load while the second stage (H-bridge inverter 130) is connected to an AC source / load. For example, this topology has been commonly used in commercial residential PV and ES products, and it can be extended to medium-voltage utility applications. Therefore, the present method 1100, as well as the corresponding system, for invention can be applied to in practical applications to control a SPTSI 110 for minimizing a ripple current in a DC-link capacitor 140 thereof.

[0099] While embodiments of the invention have been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

Claims

CLAIMS1. A method of controlling a single-phase two-stage inverter for minimizing a ripple current in a DC-link capacitor thereof, the single-phase two-stage inverter comprising a DC- DC boost converter at a first stage, a H-bridge inverter at a second stage, and the DC-link capacitor connected to and between the DC-DC boost converter and the H-bridge inverter, the method comprising: determining a relative direction between an output current of the DC-DC boost converter and an input current of the H-bridge inverter; setting a phase difference between a first carrier signal for the DC-DC boost converter and a second carrier signal for the H-bridge inverter based on the determined relative direction between the output current of the DC-DC boost converter and the input current of the H-bridge inverter; generating the first and second carrier signals having the set phase difference therebetween; and sending the first and second carrier signals to a first switching signal generator and a second switching signal generator, respectively, the first switching signal generator being configured to generate a first switching signal based on the first carrier signal for controlling a first set of switches of the DC-DC boost converter and the second switching signal generator being configured to generate a second switching signal and a third switching signal based on the second carrier signal for controlling a second set of switches and a third set of switches, respectively, of the H-bridge inverter.

2. The method according to claim 1, further comprising: setting a frequency for the first carrier signal and a frequency for the second carrier signal such that a pulse period of the first carrier signal and a pulse period of the second carrier signal are the same, wherein said generating the first and second carrier signals comprises generating the first carrier signal having the set frequency for the first carrier signal and generating the second carrier signal having the set frequency for the second carrier signal.

3. The method according to claim 2, wherein the set frequency for the first carrier signal is twice the set frequency for the second carrier signal.

4. The method according to any one of claims 1 to 3, wherein the relative direction determined between the output current of the DC-DC boost converter and the input current of the H-bridge inverter is one of a same direction and an opposite direction.

5. The method according to claim 4, wherein the phase difference between the first and second carrier signals is set to in phase based on determining that the relative direction between the output current of the DC-DC boost converter and the input current of the H-bridge inverter is the same direction, and the phase difference between the first and second carrier signals is set to out of phase based on determining that the relative direction between the output current of the DC-DC boost converter and the input current of the H-bridge inverter is the opposite direction.

6. The method according to claim 5, wherein the phase difference between the first and second carrier signals being set to in phase is setting the phase difference to 0, and the phase difference between the first and second carrier signals being set to out of phase is setting the phase difference to half of a pulse period of the first or second carrier signal.

7. The method according to any one of claims 4 to 6, wherein the relative direction between the output current of the DC-DC boost converter and the input current of the H-bridge inverter is determined based on an input inductor current of the DC-DC boost converter and an inverter output load current of the H-bridge inverter.

8. The method according to claim 7, wherein the relative direction between the output current of the DC-DC boost converter and the input current of the H-bridge inverter is determined based on a sign of a product of the input inductor current, the inverter output load current and a modulation reference signal of the H-bridge inverter.

9. The method according to claim 8, wherein the relative direction between the output current of the DC-DC boost converter and the input current of the H-bridge inverter is determined as the same direction based on determiningthat the sign of the product of the input inductor current, the inverter output load current and the modulation reference signal is positive, and the relative direction between the output current of the DC-DC boost converter and the input current of the H-bridge inverter is determined as the opposite direction based on determining that the sign of the product of the input inductor current, the inverter output load current and the modulation reference signal is negative.

10. The method according to any one of claims 1 to 9, further comprising: generating, using the first switching signal generator, the first switching signal based on the first carrier signal for controlling the first set of switches of the DC-DC boost converter; and generating, using the second switching signal generator, the second switching signal and the third switching signal based on the second carrier signal for controlling the second set of switches and the third set of switches, respectively, of the H-bridge inverter.

11. The method according to claim 10, wherein the first switching signal is generated based on the first carrier signal and a first duty cycle signal for the first set of switches of the DC-DC boost converter, the second switching signal is generated based on the second carrier signal and a second duty cycle signal for the second set of switches of the H-bridge inverter, and the third switching signal is generated based on the second carrier signal and a third duty cycle signal for the third set of switches of the H-bridge inverter.

12. The method according to any one of claims 1 to 11, wherein the first and second carrier signals each has a triangular carrier waveform.

13. A system for controlling a single-phase two-stage inverter for minimizing a ripple current in a DC-link capacitor thereof, the single-phase two-stage inverter comprising a DC- DC boost converter at a first stage, a H-bridge inverter at a second stage, and the DC-link capacitor connected to and between the DC-DC boost converter and the H-bridge inverter, the system comprising: at least one memory; andat least one processor communicatively coupled to the at least one memory and configured to: determine a relative direction between an output current of the DC-DC boost converter and an input current of the H-bridge inverter; set a phase difference between a first carrier signal for the DC-DC boost converter and a second carrier signal for the H-bridge inverter based on the determined relative direction between the output current of the DC-DC boost converter and the input current of the H-bridge inverter; generate the first and second carrier signals having the set phase difference therebetween; and send the first and second carrier signals to a first switching signal generator and a second switching signal generator, respectively, the first switching signal generator being configured to generate a first switching signal based on the first carrier signal for controlling a first set of switches of the DC-DC boost converter and the second switching signal generator being configured to generate a second switching signal and a third switching signal based on the second carrier signal for controlling a second set of switches and a third set of switches, respectively, of the H-bridge inverter.

14. The system according to claim 13, wherein the at least one processor is further configured to: set a frequency for the first carrier signal and a frequency for the second carrier signal such that a pulse period of the first carrier signal and a pulse period of the second carrier signal are the same, wherein said generate the first and second carrier signals comprises generating the first carrier signal having the set frequency for the first carrier signal and generating the second carrier signal having the set frequency for the second carrier signal.

15. The system according to claim 14, wherein the set frequency for the first carrier signal is twice the set frequency for the second carrier signal.

16. The system according to any one of claims 13 to 15, wherein the relative direction determined between the output current of the DC-DC boost converter and the input current of the H-bridge inverter is one of a same direction and an opposite direction.

17. The system according to claim 16, wherein the phase difference between the first and second carrier signals is set to in phase based on determining that the relative direction between the output current of the DC-DC boost converter and the input current of the H-bridge inverter is the same direction, and the phase difference between the first and second carrier signals is set to out of phase based on determining that the relative direction between the output current of the DC-DC boost converter and the input current of the H-bridge inverter is the opposite direction.

18. The system according to claim 17, wherein the phase difference between the first and second carrier signals being set to in phase is setting the phase difference to 0, and the phase difference between the first and second carrier signals being set to out of phase is setting the phase difference to half of a pulse period of the first or second carrier signal.

19. The system according to any one of claims 16 to 18, wherein the relative direction between the output current of the DC-DC boost converter and the input current of the H-bridge inverter is determined based on an input inductor current of the DC-DC boost converter and an inverter output load current of the H-bridge inverter.

20. The system according to claim 19, wherein the relative direction between the output current of the DC-DC boost converter and the input current of the H-bridge inverter is determined based on a sign of a product of the input inductor current, the inverter output load current and a modulation reference signal of the H-bridge inverter21. The system according to claim 20, wherein the relative direction between the output current of the DC-DC boost converter and the input current of the H-bridge inverter is determined as the same direction based on determining that the sign of the product of the input inductor current, the inverter output load current and the modulation reference signal is positive, and the relative direction between the output current of the DC-DC boost converter and the input current of the H-bridge inverter is determined as the opposite direction based ondetermining that the sign of the product of the input inductor current, the inverter output load current and the modulation reference signal is negative.

22. The system according to any one of claims 13 to 21, further comprising: the first switching signal generator configured to generate the first switching signal based on the first carrier signal for controlling the first set of switches of the DC-DC boost converter; and the second switching signal generator being configured to generate the second switching signal and the third switching signal based on the second carrier signal for controlling the second set of switches and the third set of switches, respectively, of the H-bridge inverter.

23. The system according to claim 22, wherein the first switching signal generator is further configured to generate the first switching signal based on the first carrier signal and a first duty cycle signal for the first set of switches of the DC-DC boost converter, and the second switching signal generator is further configured to generate the second switching signal based on the second carrier signal and a second duty cycle signal for the second set of switches of the H-bridge inverter, and generate the third switching signal based on the second carrier signal and a third duty cycle signal for the third set of switches of the H-bridge inverter.

24. The system according to any one of claims 13 to 23, wherein the first and second carrier signals each has a triangular carrier waveform.

25. A computer program product, embodied in one or more non-transitory computer- readable storage mediums, comprising instructions executable by at least one processor to perform the method of controlling a single-phase two-stage inverter for minimizing a ripple current in a DC-link capacitor thereof according to any one of claims 1 to 12.

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