Display module and preparation method therefor, and display panel

Abstract

The present application relates to the technical field of display. Disclosed are a display module and a preparation method therefor, and a display panel. The display module comprises: a base substrate; a plurality of pixel units and a touch-control film layer, which are located in a display region of the base substrate; and a plurality of binding interfaces and a plurality of connecting traces, which are located in a binding region of the base substrate, wherein the plurality of binding interfaces are connected to touch-control electrodes in the touch-control film layer, and first ends of the connecting traces are connected to the binding interfaces; and the width of first target parts in the connecting traces is less than the width of the binding interfaces, and the distance between adjacent first target parts is less than the distance between adjacent binding interfaces. Therefore, when the connecting traces are obtained by means of cutting, even though the connecting traces generate a carbonized substance due to the high temperature during cutting, the carbonized substance cannot fully fill the gaps between the first target parts of adjacent connecting traces, such that the risk of a short circuit between the adjacent connecting traces is reduced, thereby improving the yield of a display panel.

Description

Display module and manufacturing method thereof, and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display module and a preparation method thereof, and a display panel. Background Art

[0002] A display panel includes a display module and a flexible circuit board connected to the display module. The display module includes a base substrate and multiple pixel units located on the base substrate. The flexible circuit board is used to provide drive signals to the multiple pixel units in the display module, which are driven by the drive signals to emit light.

[0003] Summary of the Invention

[0004] This application provides a display module and a manufacturing method thereof, and a display panel. The technical solutions are as follows:

[0005] In one aspect, a display module is provided, comprising:

[0006] a base substrate, the base substrate having a display area and a peripheral area surrounding the display area, the peripheral area including a binding area located on one side of the display area;

[0007] a plurality of pixel units, wherein the plurality of pixel units are located in the display area;

[0008] A touch film layer, the touch film layer is located on a side of the plurality of pixel units away from the base substrate, and the touch film layer at least includes a touch electrode;

[0009] a plurality of binding interfaces, the plurality of binding interfaces being located in the binding area and connected to the touch electrodes;

[0010] and a plurality of connecting traces, wherein first ends of the connecting traces are connected to the binding interface, a width of a first target portion of the connecting traces is smaller than a width of the binding interface, and a distance between adjacent first target portions of the connecting traces is greater than a distance between adjacent binding interfaces;

[0011] The first target portion is located at a side of the first end of the connecting wire away from the display area, and the end of the first target portion away from the display area is obtained by cutting.

[0012] Optionally, the width of the first target portion of the connecting trace is greater than or equal to 1.8 microns.

[0013] Optionally, the width of the first end of the connecting line is greater than the width of the first target portion of the connecting line.

[0014] Optionally, the first central axis of the first target portion of the connecting line and the second central axis of the first end of the connecting line both extend along the extension direction of the connecting line.

[0015] Optionally, the first central axis and the second central axis are collinear.

[0016] Optionally, the first target portion of the connecting line has a first boundary and a second boundary that are opposite to each other, and the first end of the connecting line has a third boundary and a fourth boundary that are opposite to each other;

[0017] The first boundary and the third boundary are collinear and constitute a common boundary of the connecting trace, and the second boundary is closer to the common boundary than the fourth boundary;

[0018] The first boundary, the second boundary, the third boundary, and the fourth boundary all extend along the extending direction of the connecting line.

[0019] Optionally, the connecting line further includes a transition portion located between the first target portion and the first end of the connecting line;

[0020] The width of the transition portion close to the first end of the connecting trace is equal to the width of the first end of the connecting trace, the width of the transition portion close to the first target portion is equal to the width of the first target portion, and the width of the transition portion decreases as the distance from the first end increases.

[0021] Optionally, the transition portion has a fifth boundary and a sixth boundary opposite to each other;

[0022] At least one of the fifth boundary and the sixth boundary intersects with an extension direction of the connecting line.

[0023] Optionally, the fifth boundary and the sixth boundary are both straight lines, and the angle between the boundary of the fifth boundary and the sixth boundary that intersects with the extension direction of the connecting line and the extension direction of the connecting line is an obtuse angle.

[0024] Optionally, the first target portion of the connecting trace includes a first sub-trace and a second sub-trace spaced apart along an extending direction of the connecting trace;

[0025] The display module also includes: a switching transistor and a signal transmission line, the first electrode of the switching transistor is connected to the first sub-line, the second electrode of the switching transistor is connected to the second sub-line, and the gate of the switching transistor is connected to the signal transmission line. The switching transistor is used to receive a shutdown signal provided from the signal transmission line during the display stage and is in an off state under the action of the shutdown signal.

[0026] Optionally, the display module includes an active layer, a gate insulating layer, and a gate layer stacked on the base substrate; the connecting wire is located in the gate layer;

[0027] The switching transistor includes an active pattern located in the active layer; an orthographic projection of a first end of the active pattern on the base substrate overlaps with an orthographic projection of the first sub-route on the base substrate, and the first end of the active pattern serves as a first electrode of the switching transistor and is connected to the first sub-route through a first via in the gate insulating layer; an orthographic projection of a second end of the active pattern on the base substrate overlaps with an orthographic projection of the second sub-route on the base substrate, and the second end of the active pattern serves as a second electrode of the switching transistor and is connected to the second sub-route through a second via in the gate insulating layer;

[0028] The switching transistor further includes a gate pattern located in the gate layer, the orthographic projection of the gate pattern on the base substrate overlaps with the orthographic projection of the active pattern on the base substrate, and the gate pattern serves as the gate of the switching transistor and is connected to the signal transmission line.

[0029] Optionally, the number of the first via holes and the number of the second via holes are both negatively correlated with the width of the first target portion of the connecting trace.

[0030] Optionally, the display module further includes an interlayer dielectric layer and a first source-drain layer located on a side of the gate layer away from the base substrate; the signal transmission line is located in the first source-drain layer;

[0031] An orthographic projection of the signal transmission line on the base substrate overlaps with an orthographic projection of the gate pattern on the base substrate, and the gate pattern is connected to the signal transmission line through a third via hole in the interlayer dielectric layer.

[0032] Optionally, the switching transistor is further configured to receive a start signal provided by the signal transmission line during a test phase, and be in a turn-on state under the action of the start signal.

[0033] Optionally, the display module includes an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, a first source and drain electrode layer, a first planar layer, a second source and drain electrode layer, a second planar layer, an anode layer, a pixel defining layer, a light-emitting layer, a cathode layer, and an encapsulation layer stacked on the base substrate; the touch film layer is located on a side of the encapsulation layer away from the base substrate, the touch film layer includes: a first touch layer, a touch insulating layer, and a second touch layer, and the touch electrodes are located on the first touch layer and the second touch layer;

[0034] Wherein, the anode layer, the light-emitting layer, and the cathode layer are used to constitute the plurality of pixel units;

[0035] The connecting wire is located on the gate layer, the bonding interface is located on the second touch layer, and a first end of the connecting wire is connected to the bonding interface through a via in an insulating film layer between the gate layer and the second touch layer.

[0036] Optionally, the display module further includes a first connecting portion located on the first source-drain electrode layer, and a second connecting portion located on the second source-drain electrode layer;

[0037] The first end of the connecting trace is connected to the first connecting portion through a via in the interlayer dielectric layer, the first connecting portion and the second connecting portion are connected through a via in the first flat layer, and the second connecting portion is connected through a via in the second flat layer, the pixel defining layer, the encapsulation layer and the touch insulating layer.

[0038] In another aspect, a display module is provided, comprising: a base substrate having a display area and a peripheral area surrounding the display area, the peripheral area including a binding area located on one side of the display area;

[0039] a plurality of pixel units, wherein the plurality of pixel units are located in the display area;

[0040] A touch film layer, the touch film layer is located on a side of the plurality of pixel units away from the base substrate, and the touch film layer at least includes a touch electrode;

[0041] a plurality of binding interfaces, the plurality of binding interfaces being located in the binding area and connected to the touch electrodes;

[0042] and a plurality of connecting traces, wherein a first end of the connecting trace is connected to the binding interface, a first target portion of the connecting trace comprises a first sub-trace and a second sub-trace spaced apart along an extension direction of the connecting trace, the first target portion is located on a side of the first end of the connecting trace away from the display area, and an end of the first target portion away from the display area is obtained by cutting;

[0043] The display module also includes: a switching transistor and a signal transmission line, the first electrode of the switching transistor is connected to the first sub-line, the second electrode of the switching transistor is connected to the second sub-line, and the gate of the switching transistor is connected to the signal transmission line. The switching transistor is used to receive a shutdown signal provided from the signal transmission line during the display stage and is in an off state under the action of the shutdown signal.

[0044] In another aspect, a method for preparing a display module is provided, for preparing the display module described in the above aspect; the method comprising:

[0045] Obtain an initial display module, the initial display module comprising: an initial base substrate, the initial base substrate having a display area and a peripheral area surrounding the display area, the peripheral area comprising a binding area located on one side of the display area and an area to be cut located on a side of the binding area away from the display area; a plurality of pixel units, the plurality of pixel units being located in the display area; a touch film layer, the touch film layer being located on a side of the plurality of pixel units away from the base substrate, the touch film layer comprising at least touch electrodes; a plurality of binding interfaces, the plurality of binding interfaces being located in the binding area, the plurality of binding interfaces being connected to the touch electrodes; a plurality of initial connection traces, the first ends and first target portions of the initial connection traces being located in the binding area, the first ends of the initial connection traces being connected to the binding interfaces; a plurality of test circuits and a plurality of test interfaces, the plurality of test circuits, the plurality of test interfaces, and the second target portions and second ends of the initial connection traces being located in the area to be cut, the test circuits being connected to the second ends of the initial connection traces and to the test interfaces;

[0046] Using a test device to sequentially provide a detection signal to the touch electrode through the test interface, the test circuit, the initial connection line, and the binding interface to test the touch performance of the display module;

[0047] A cutting device is used to cut along the cutting path between the first end of the initial connecting trace and the second end of the initial connecting trace, and the area to be cut of the initial substrate, the test circuit, the test interface and the portion of the initial connecting trace located in the area to be cut are cut off. The portion of the initial connecting trace that is not cut off is the connecting trace, and the first end of the initial connecting trace is the first end of the connecting trace.

[0048] Optionally, the first target portion is a portion of the initial connection line that has not been cut off, and the second target portion is a portion of the initial connection line that has been cut off;

[0049] The first target portion and the second target portion are directly connected, and the width of the first target portion is equal to the width of the second target portion.

[0050] In another aspect, a display panel is provided, comprising: a flexible circuit board, and the display module according to the above aspect;

[0051] The display module has a relative display side and a non-display side, and the flexible circuit board includes a plurality of signal interfaces located on the display side, and the plurality of signal interfaces are correspondingly connected to a plurality of binding interfaces in the display module; at least a portion of the flexible circuit board is located on the non-display side of the display module. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0053] FIG1 is a partial schematic diagram of a display module in the related art;

[0054] FIG2 is a schematic diagram of a short circuit of a connection line provided in an embodiment of the present application;

[0055] FIG3 is a top view of a display module provided in an embodiment of the present application;

[0056] FIG4 is a partial schematic diagram of a display module provided in an embodiment of the present application;

[0057] FIG5 is a partial schematic diagram of a display module before being cut into pieces according to an embodiment of the present application;

[0058] FIG6 is a partial schematic diagram of another display module provided in an embodiment of the present application;

[0059] FIG7 is a partial schematic diagram of another display module provided in an embodiment of the present application;

[0060] FIG8 is a schematic diagram of a connection wiring provided by an embodiment of the present application;

[0061] FIG9 is a schematic diagram of another connection wiring provided in an embodiment of the present application;

[0062] FIG10 is a partial cross-sectional schematic diagram of a display module located in a display area provided by an embodiment of the present application;

[0063] FIG11 is a schematic diagram of a touch electrode provided in an embodiment of the present application;

[0064] FIG12 is a partial schematic diagram of a touch film layer provided in an embodiment of the present application;

[0065] FIG13 is a cross-sectional view taken along the AA' direction in FIG4;

[0066] FIG14 is a partial schematic diagram of another display module provided in an embodiment of the present application;

[0067] FIG15 is a cross-sectional view of FIG14 along the BB' direction;

[0068] FIG16 is a partial schematic diagram of another display module provided in an embodiment of the present application;

[0069] FIG17 is a cross-sectional view of FIG16 taken along the CC' direction;

[0070] FIG18 is a cross-sectional view of FIG16 along the DD' direction;

[0071] FIG19 is a flow chart of a method for preparing a display module provided in an embodiment of the present application;

[0072] FIG20 is a top view of an initial display module provided in an embodiment of the present application;

[0073] FIG21 is a partial schematic diagram of an initial display module provided in an embodiment of the present application;

[0074] FIG22 is a partial schematic diagram of another initial display module provided in an embodiment of the present application;

[0075] FIG23 is a partial schematic diagram of another initial display module provided in an embodiment of the present application;

[0076] FIG24 is a partial schematic diagram of another initial display module provided in an embodiment of the present application;

[0077] FIG25 is a partial schematic diagram of another initial display module provided in an embodiment of the present application;

[0078] FIG26 is a cross-sectional view of FIG21 along the EE' direction;

[0079] FIG27 is a schematic diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0080] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0081] In the related art, the display panel is obtained by binding a flexible circuit board to a display module after the display module is prepared. In order to ensure the yield of the prepared display panel, it is necessary to perform a performance test on the display module before binding the flexible circuit board, such as a touch performance test or a display performance test. In order to test the performance of the display module, it is necessary to reserve a test interface and a test circuit during the preparation of the display module. The test interface is connected to the test circuit, and the test circuit is connected to a binding interface in the display module for binding with the flexible circuit board through a connecting line. The test equipment provides test signals to the binding interface in the display module through the test interface, the test circuit and the connecting line in turn, thereby realizing the test of the display module performance. After the test is completed, it is necessary to use a cutting device to cut off the test interface along the cutting path, and the cutting path is located on the connecting line.

[0082] However, during the cutting process along the cutting lanes, the connecting wires are prone to generate carbonized materials due to the high temperature. The carbonized materials gather between adjacent connecting wires, which can easily cause short circuits between the adjacent connecting wires, thereby reducing the yield of the display panel.

[0083] During the display module manufacturing process, the display module is lit multiple times to test for various performance defects. If a defect is found, the subsequent processing of the display module can be discontinued, avoiding waste of materials, manpower, and production lines in the subsequent process. In order to conduct performance testing, it is necessary to add test interfaces (including touch test interfaces and display test interfaces) to the outer periphery of the display module. These test interfaces require binding interfaces (binding interfaces are interfaces that are subsequently bonded to the flexible circuit board), and these test interfaces are cut off after the test is completed.

[0084] Figure 1 is a partial schematic diagram of a display module in the related art. Referring to Figure 1, the width of the binding interface and the connecting traces in the display module are equal. Consequently, referring to Figure 2, the distance between adjacent connecting traces is small. During the module cutting process, the connecting traces can produce carbonized material due to the high temperature. This carbonized material can connect adjacent connecting traces, causing signal short circuits and defects.

[0085] FIG3 is a top view of a display module according to an embodiment of the present application. Referring to FIG3 , the display module (MDL) 100 includes: a substrate 101 , a plurality of pixel units 102 , a touch film layer (not shown in FIG3 ), a plurality of bonding interfaces (pins) 103 , and a plurality of connecting traces 104 .

[0086] The base substrate 101 has a display area (also referred to as an AA area) 101a and a peripheral area 101b surrounding the display area 101a. The peripheral area 101b includes a binding area 101b1 located on one side of the display area 101a.

[0087] Figure 4 is a partial schematic diagram of a display module provided in an embodiment of the present application. In combination with Figures 3 and 4, a plurality of pixel units 102 can be located in the display area 101a, and the plurality of pixel units 102 can be used to display images. The touch film layer is located on the side of the plurality of pixel units 102 away from the base substrate 101, and the touch film layer includes at least touch electrodes. A plurality of binding interfaces 103 are located in the binding area 101b1, and the plurality of binding interfaces 103 are connected to the touch electrodes in the touch film layer. The first end z1 of the connecting trace 104 is connected to the binding interface 103, and the width h1 of the first target portion z2 of the connecting trace 104 is smaller than the width h2 of the binding interface 103. In addition, the distance h3 between the first target portions z2 of adjacent connecting traces 104 is greater than the distance h4 between adjacent binding interfaces 103.

[0088] The first target portion z2 is located on a side of the first end z1 of the connecting trace 104 away from the display area 101 a , and the end of the first target portion z2 away from the display area 101 a is obtained by cutting.

[0089] In an embodiment of the present application, referring to FIG5 , before cutting to obtain the connecting trace 104, the test circuit and test interface can be located on the side of the binding area 101b1 away from the display area 101a. A testing device can be connected to the test interface, providing a test signal to the connecting trace 104 via the test interface and test circuit, thereby testing the performance of the display module 100. After the test is completed, a cutting device is used to remove the test interface and test circuit along the cutting path to obtain the connecting trace 104. The end of the first target portion z2 of the connecting trace 104 away from the display area 101a is the end obtained by the cutting device along the cutting path.

[0090] Among them, the width of the first target portion z2 of the connecting trace 104 is smaller than the width of the binding interface 103, and the distance h3 between the first target portions z2 of adjacent connecting traces 104 is smaller than the distance h4 between adjacent binding interfaces 103. This can make the width of the first target portion z2 of the connecting trace 104 smaller, ensure that the distance between adjacent first target portions z2 is larger, and avoid short circuit of the first target portions z2 of adjacent connecting traces 104.

[0091] During the cutting process along the dicing street, even if the connecting traces 104 generate carbonized material due to the high temperature, the distance between the first target portions z2 of adjacent connecting traces 104 is large, so the carbonized material generated by the cutting will be concentrated in a large gap. Furthermore, the total amount of carbonized material is insufficient to fill the large gap, thereby reducing the risk of short circuits.

[0092] In summary, an embodiment of the present application provides a display module, which includes a base substrate, a plurality of pixel units and a touch film layer located in the display area of ​​the base substrate, and a plurality of binding interfaces and a plurality of connecting wires located in the binding area of ​​the base substrate. The plurality of binding interfaces are connected to the touch electrodes in the touch film layer, and the first end of the connecting wire is connected to the binding interface. The width of the first target portion of the connecting wire located at the first end away from the display area is smaller than the width of the binding interface, and the distance between the first target portions of adjacent connecting wires is smaller than the distance between adjacent binding interfaces. Therefore, when the connecting wire is cut to obtain the connecting wire, even if the connecting wire produces carbonized material due to the high temperature during cutting, the distance between the first target portions of adjacent connecting wires is large, so the carbonized material cannot fill the spacing between the first target portions of adjacent connecting wires, thereby reducing the risk of short circuit of adjacent connecting wires, thereby improving the yield of the display panel.

[0093] In the embodiment of the present application, during the testing phase, the test equipment needs to transmit signals to the binding interface 103 through the test interface, test circuit, and connecting trace 104. If the width of the first target portion z2 of the connecting trace 104 is too small, the reliability of the signal transmission will be affected, and the performance test results will be poor. Therefore, the width of the first target portion z2 of the connecting trace 104 can be designed to be greater than or equal to 1.8 μm (micrometers), which can ensure the reliability of signal transmission.

[0094] Optionally, the width of the first end z1 of the connecting trace 104 is greater than the width of the first target portion z2 of the connecting trace 104. This ensures that the first end z1 of the connecting trace 104 and the binding interface 103 have sufficient connection area, ensuring connection reliability. For example, the width of the first end z1 of the connecting trace 104 can be equal to the width of the binding interface 103.

[0095] 4 , the first central axis z21 of the first target portion z2 of the connecting line 104 and the second central axis z11 of the first end z1 of the connecting line 104 both extend along the extension direction of the connecting line 104. That is, the first central axis z21 and the second central axis z11 are parallel.

[0096] Alternatively, referring to Figure 4 , the first central axis z21 and the second central axis z11 are collinear. That is, the first target portion z2 of the connecting trace 104 can be located in the middle of the first end z1 of the connecting trace 104. In this case, both boundaries (z2a and z2b) of the first target portion z2 of the connecting trace 104 along its extension direction are indented relative to the first end z1 of the connecting trace 104, and the indentations are equal.

[0097] For example, the first target portion z2 of the connecting trace 104 has a first boundary z2a and a second boundary z2b that are opposite to each other. The first end z1 of the connecting trace 104 has a third boundary z1a and a fourth boundary z1b that are opposite to each other. The first boundary z2a, the second boundary z2b, the third boundary z1a, and the fourth boundary z1b all extend along the extension direction of the connecting trace 104.

[0098] The first boundary z2a is closer to the third boundary z1a than the second boundary z2b, and the second boundary z2b is closer to the fourth boundary z1b than the first boundary z2a. The distance m1 between the first boundary z2a and the third boundary z1a along the target direction M can be equal to the distance m2 between the second boundary z2b and the fourth boundary z1b along the target direction M. The target direction M can be perpendicular to the extension direction of the connecting trace 104.

[0099] Optionally, referring to Figures 6 and 7 , the first boundary z2a and the third boundary z1a are collinear and constitute the common boundary of the connecting trace 104. The second boundary z2b is closer to the common boundary than the fourth boundary z1b. This allows the distance between the second boundary z2b and the common boundary along the target direction M to be smaller than the distance between the fourth boundary z1b and the common boundary along the target direction M. In other words, the width of the first target portion z2 of the connecting trace 104 can be smaller than the width of the first end z1 of the connecting trace 104.

[0100] Alternatively, the common boundary of the multiple connecting traces 104 may be located on the same side, with the first target portion z2 on the other side being indented relative to the first end. For example, referring to FIG6 , the common boundary of the multiple connecting traces 104 is the right boundary of the connecting trace 104, while the first target portion z2 on the left boundary is indented relative to the first end. Alternatively, referring to FIG7 , the common boundary of the multiple connecting traces 104 is the left boundary of the connecting trace 104, while the first target portion z2 on the right boundary is indented relative to the first end.

[0101] Optionally, the third boundary z1a and the fourth boundary z1b of the first end z1 of the connecting line 104 , and the first boundary z2a and the second boundary z2b of the first target portion z2 of the connecting line 104 may all be straight lines.

[0102] In the embodiment of the present application, referring to Figures 4, 6, and 7, the connecting trace 104 further includes a transition portion z3 located between the first target portion z2 and the first end z1 of the connecting trace 104. The width of the transition portion z3 near the first end z1 of the connecting trace 104 is equal to the width of the first end z1 of the connecting trace 104. The width of the transition portion z3 near the first target portion z2 is equal to the width of the first target portion z2. The width of the transition portion z3 decreases as the distance from the first end increases.

[0103] That is, the inward contraction design of the first target portion z2 of the connecting wire 104 relative to the first end z1 of the connecting wire 104 may gradually change at the transition portion z3, thereby avoiding stress concentration and static electricity concentration and improving the reliability of the connecting wire 104.

[0104] 8 and 9 , the transition portion z3 has a fifth boundary z3a and a sixth boundary z3b opposite to each other, and at least one of the fifth boundary z3a and the sixth boundary z3b intersects with the extending direction of the connection trace 104 .

[0105] For example, referring to FIG8 , when the first target portion z2 of the connecting trace 104 is retracted on both sides relative to the first end z1 of the connecting trace 104, the fifth boundary z3a and the sixth boundary z3b both intersect the extension direction Y of the connecting trace 104. Alternatively, referring to FIG9 , when the first target portion z2 of the connecting trace 104 is retracted on one side relative to the first end z1 of the connecting trace 104, the fifth boundary z3a may form a common boundary with the first boundary z2a and the third boundary z1a, and the sixth boundary z3b may intersect the extension direction Y of the connecting trace 104.

[0106] Optionally, the fifth boundary z3a and the sixth boundary z3b are both straight lines, and the angle α between the boundary of the fifth boundary z3a and the boundary of the sixth boundary z3b that intersects the extension direction of the connecting line 104 and the extension direction of the connecting line 104 is an obtuse angle. That is, the angle between the boundary of the fifth boundary z3a and the boundary of the sixth boundary z3b that intersects the extension direction of the connecting line 104 and the extension direction of the connecting line 104 is greater than 90 degrees.

[0107] For example, in Figure 8 , the angles between the fifth boundary z3a and the sixth boundary z3b and the extending direction of the connection line 104 are both obtuse angles. Alternatively, in Figure 9 , the angle between the sixth boundary z3b and the extending direction of the connection line 104 is also obtuse.

[0108] Optionally, the fifth boundary z3a and the sixth boundary z3b may also be curves or broken lines, which is not limited in this embodiment of the present application.

[0109] Figure 10 is a partial cross-sectional schematic diagram of a display module located in the display area provided by an embodiment of the present application. Referring to Figure 10 , the display module 100 includes a buffer layer (buffer) n1, an active layer (poly) n2, a gate insulator (GI) n3, a gate layer (gate) n4, an inter-level dielectric (ILD) n5, a first source and drain electrode layer n6, a first planarization layer (PLN) n7, a second source and drain electrode layer n8, a second planarization layer n9, an anode layer n10, a pixel definition layer n11, a light-emitting layer n12, a cathode layer n13, and an encapsulation layer n14, stacked in sequence. The touch film layer 105 includes a first touch layer 1051, a touch insulation layer 1052, and a second touch layer 1053.

[0110] The display module 100 also includes a pixel circuit connected to the pixel unit 102 and providing a drive signal to the pixel unit 102. The active layer n2, gate insulating layer n3, gate layer n4, interlayer dielectric layer n5, first source and drain electrode layer n6, first planar layer n7, and second source and drain electrode layer n8 can be used to form the pixel circuit. The anode layer, light-emitting layer, and cathode layer are used to form the pixel unit 102.

[0111] Optionally, the pixel circuit may include a plurality of thin film transistors (TFTs) and at least one storage capacitor. Optionally, the pixel circuit may include seven thin film transistors and one storage capacitor, that is, the pixel circuit is a 7T1C driving circuit. Alternatively, the pixel circuit may include other numbers of thin film transistors and other numbers of storage capacitors. The embodiments of the present application do not limit the number of thin film transistors included in the pixel circuit and the number of storage capacitors included.

[0112] Each thin film transistor includes a gate, a source, and a drain. The pixel circuit in each pixel unit includes a plurality of thin film transistors that are interconnected to achieve the function of driving the light-emitting unit in the pixel unit to emit light.

[0113] The active layer includes multiple active patterns corresponding to multiple thin film transistors, each active pattern including a source region, a drain region, and a channel region. The source and drain of the thin film transistor are located in the first source-drain layer, and the source of the thin film transistor is connected to the source region, and the drain is connected to the drain region.

[0114] The first gate layer includes a plurality of gate patterns corresponding to the plurality of thin film transistors. The channel region is an overlapping region of an orthographic projection of the gate pattern on the base substrate and an orthographic projection of the active pattern on the base substrate.

[0115] 10 , the encapsulation layer n14 includes a first film layer n141 , a second film layer n142 , and a third film layer n143 stacked in a direction away from the base substrate 101 .

[0116] Optionally, the first film layer n141 and the third film layer n143 may be made of an inorganic material, and the second film layer n142 may be made of an organic material. For example, the first film layer n141 and the third film layer n143 may be made of one or more inorganic oxides such as SiNx (silicon nitride), SiOx (silicon oxide), and SiOxNy (silicon oxynitride). The second film layer n142 may be made of a resin material. The resin may be a thermoplastic resin or a thermoplastic resin, the thermoplastic resin may include an acrylic (PMMA) resin, and the thermosetting resin may include an epoxy resin.

[0117] Optionally, the second film layer n142 may be manufactured by ink jet printing (IJP) and the first film layer n141 and the third film layer n143 may be manufactured by chemical vapor deposition (CVD).

[0118] It should be noted that, referring to FIG10 , the touch electrodes S can be located on the first touch layer 1051 and the second touch layer 1052 . For example, referring to FIG11 , the touch electrodes S include multiple first touch electrodes s1 and multiple second touch electrodes s2 . One of the first touch layers 1051 and the second touch layer 1053 includes a main electrode s11 of the first touch electrode s1 and a second touch electrode s2 . The other of the first touch layers 1051 and the second touch layer 1052 includes a bridge electrode s12 of the first touch electrode s1 . The main electrode s11 and the bridge electrode s12 are electrically connected via vias in the touch insulating layer 1052 .

[0119] Referring to Figure 11 , a plurality of first touch electrodes s1 are arranged along a second direction Q, and a plurality of second touch electrodes s2 are arranged along a first direction W. Furthermore, the bridging electrode s12 of the first touch electrode s1 is located in a region where it overlaps with the orthographic projection of the second touch electrode s2. The first direction W may be the direction of pixel rows in the display module 100, and the second direction Q may be the direction of pixel columns in the display module 100.

[0120] 12 , assuming that the first touch layer 1051 includes the bridge electrode s12 of the first touch electrode s1, and the second touch layer 1053 includes the main electrode s11 of the first touch electrode s1 and the second touch electrode s2, in this case, the main electrode s11 of the first touch electrode s1 in the second touch layer 1053 is connected via a via in the touch insulation layer 1052.

[0121] Optionally, one of the first touch electrode s1 and the second touch electrode s2 may be a transmitting (TX) electrode, and the other may be a sensing (RX) electrode.

[0122] Display module 100 also includes a touch drive circuit and a touch detection circuit located in peripheral area 101b. The touch drive circuit can be connected to the transmitting electrode to provide a touch drive signal to the transmitting electrode. The touch detection circuit can be connected to the sensing electrode to receive a sensing signal between the transmitting electrode and the sensing electrode. If a user's finger approaches display module 100, the touch detection circuit can detect a change in the sensing signal at the location of the user's finger and determine the location of the change in the sensing signal as the touch location.

[0123] In an embodiment of the present application, the touch panel (TP) test of the display module can be performed during the testing phase. Figure 13 is a cross-sectional view of Figure 4 along the AA' direction. Referring to Figure 13 , the connecting traces 104 and the bonding interface 103 can be located in different film layers among the multiple film layers of the display module 100. For example, the connecting traces 104 can be located in the gate layer n4 of the display module 100, and the bonding interface 103 can be located in the second touch layer 1053 of the display module 100.

[0124] The display module 100 further includes a first connecting portion 106 located on the first source / drain layer n6 and a second connecting portion 107 located on the second source / drain layer n8 . The first end z1 of the connecting trace 104 is connected to the bonding interface 103 via the first connecting portion 106 and the second connecting portion 107 .

[0125] Specifically, the first end of the connecting trace 104 is connected to the first connecting portion 106 through a via in the interlayer dielectric layer n5, the first connecting portion 106 and the second connecting portion 107 are connected through a via in the first flat layer n7, and the second connecting portion 107 is connected through a via in the second flat layer n9, the encapsulation layer n14 and the touch insulation layer 1052.

[0126] 14 , the first target portion z2 of the connection trace 104 may include a first sub-trace 1041 and a second sub-trace 1042 spaced apart along the extending direction of the connection trace 104 . The display module 100 further includes a switch transistor T and a signal transmission line 108 .

[0127] The switching transistor T includes a gate, a first electrode, and a second electrode. The first electrode is connected to the first sub-trace 1041, and the second electrode is connected to the second sub-trace 1042. The gate is connected to the signal transmission line 108. The switching transistor T is configured to receive a shutdown signal from the signal transmission line 108 during the display phase. The switching transistor T is configured to be in an off state under the action of the shutdown signal.

[0128] In this case, since the switch transistor T is in the off state, signal transmission between the first electrode and the second electrode is prevented. Even if the first target portion z2 of the adjacent connecting trace 104 is short-circuited on the side away from the first end (i.e., the second sub-trace 1042 is short-circuited), the short-circuit signal will not be transmitted to the first end z1 of the connecting trace 104, thereby preventing different bonding interfaces 103 from short-circuiting.

[0129] Figure 15 is a cross-sectional view of Figure 14 along the BB' direction. Referring to Figure 15 , the switching transistor T includes an active pattern n21 located in the active layer n2. The orthographic projection of the first end of the active pattern n21 on the base substrate 101 overlaps with the orthographic projection of the first sub-trace 1041 on the base substrate 101. The first end of the active pattern n21 can serve as the first electrode of the switching transistor T and is connected to the first sub-trace 1041 via a first via k1 in the gate insulating layer n3. The orthographic projection of the second end of the active pattern n21 on the base substrate 101 overlaps with the orthographic projection of the second sub-trace 1042 on the base substrate 101. The second end of the active pattern n21 can serve as the second electrode of the switching transistor T and is connected to the second sub-trace 1042 via a second via k2 in the gate insulating layer n3.

[0130] Optionally, the number of first vias k1 and the number of second vias k2 are both negatively correlated with the width of the first target portion z2 of the connection trace 104. That is, the smaller the width of the first target portion z2, the greater the number of first vias k1 and the number of second vias k2; and the larger the width of the first target portion z2, the fewer the number of first vias k1 and the number of second vias k2.

[0131] The first via k1 is used to connect the active pattern n21 of the switching transistor T and the first sub-route 1041. To ensure the reliability of the connection between the active pattern n21 and the first sub-route 1041, a certain connection area must be provided between the active pattern n21 and the first sub-route 1041. If the width of the first target portion z2 is small, a larger number of first vias k1 can be designed to increase the connection area between the active pattern n21 and the first sub-route 1041.

[0132] The second via k2 is used to connect the active pattern n21 of the switching transistor T to the second sub-trace 1042. To ensure the reliability of the connection between the active pattern n21 and the second sub-trace 1042, a certain connection area must be maintained between the active pattern n21 and the second sub-trace 1042. If the width of the first target portion z2 is small, a larger number of second vias k2 can be designed to increase the connection area between the active pattern n21 and the second sub-trace 1042.

[0133] 15 , the gate insulating layer n3 of the display module 100 has two first vias k1 and two second vias k2 , the active pattern n21 and the first sub-wiring 1041 are connected through the two first vias k1 , and the active pattern and the second sub-wiring 1042 are connected through the two second vias k2 .

[0134] The switching transistor T further includes a gate pattern n41 located on the gate layer n4. The orthographic projection of the gate pattern n41 on the base substrate 101 overlaps with the orthographic projection of the active pattern n21 on the base substrate 101. The gate pattern n41 can serve as the gate of the switching transistor T and be connected to the signal transmission line 108.

[0135] Assuming that the signal transmission line 108 provides an on signal to the gate of the switching transistor T, the first and second electrodes of the switching transistor T are turned on, and the signal from the second electrode of the switching transistor T can be transmitted to the first electrode of the switching transistor T, and then transmitted to the bonding interface 103. Assuming that the signal transmission line 108 provides an off signal to the gate of the switching transistor T, the signal between the first and second electrodes of the switching transistor T is disconnected, and the signal from the second electrode of the switching transistor T cannot be transmitted to the first electrode of the switching transistor T, nor can it be transmitted to the bonding interface 103.

[0136] During the testing phase, the test equipment needs to provide a detection signal to the bonding interface 103 through the test interface, test circuit, and connection line 104, so the signal needs to be turned on. In this case, the signal transmission line 108 can provide an on signal to the gate of the switching transistor T, so that the switching transistor T is in the on state, thereby allowing the detection signal to be transmitted to the bonding interface 103 through the switching transistor T.

[0137] After the test phase, cutting equipment is required to cut along the cutting path. The connecting traces 104 will produce carbonized substances due to the high temperature during cutting, which may cause adjacent connecting traces 104 to short-circuit (for example, the second sub-traces 1042 of adjacent connecting traces 104 to short-circuit).

[0138] Therefore, in the display stage, in order to prevent the short-circuit signal from being transmitted to the binding interface 103 , the signal transmission line 108 may provide a turn-off signal to the gate of the switch transistor T, so that the switch transistor T is in the turn-off state.

[0139] Referring to Figure 15 , the connecting trace 104 is located on the gate layer n4 of the display module 100. The gate pattern n41 of the switching transistor T is also located on the gate layer n4 of the display module 100. Both the first sub-trace 1041 and the second sub-trace 1042 of the connecting trace 104 have a gap with the gate pattern n41 of the switching transistor T. Furthermore, the bonding interface 103 may be located on the second touch layer 1053. The first end z1 of the connecting trace 104 is connected to the bonding interface 103 via the first connecting portion 106 and the second connecting portion 107.

[0140] Optionally, because the first source / drain layer n6 has a lower resistance than the gate layer n4 and is more efficient in signal transmission, the signal transmission line 108 can be located in the first source / drain layer n6. The orthographic projection of the signal transmission line 108 on the base substrate 101 overlaps with the orthographic projection of the gate pattern n41 on the base substrate 101, and the gate pattern n41 is connected to the signal transmission line 108 via a third via k3 in the second gate insulating layer n2.

[0141] Furthermore, referring to FIG14 , the width of the gate pattern n41 of the switching transistor T can be equal to the width of the first target portion z2. To ensure the reliability of the connection between the signal transmission line 108 and the gate pattern n41, a certain connection area between the signal transmission line 108 and the gate pattern n41 is required. If the width of the gate pattern n41 is small, the connection area between the gate pattern n41 and the signal transmission line 108 can be increased by designing a larger number of third vias k3.

[0142] Referring to Figure 14, the display module 100 also includes a signal transmission interface 109 and a signal transmission connection line 110. Among them, the signal transmission interface 109 can be located in the same layer as the binding interface 103, such as located in the second touch layer 1053. The signal transmission connection line 110 can be located in the same layer as the connection line 104, such as located in the gate layer n4. The signal transmission interface 109 and the signal transmission connection line 110 can be connected through the first connection part 106 and the second connection part 107. The end of the signal transmission connection line 110 away from the signal transmission interface 109 is also connected to the signal transmission line 108. In addition, since the signal transmission connection line 110 (gate layer n4) and the signal transmission line 108 (first source and drain layer n6) are located in different layers, they can be connected through the fourth via k4 in the interlayer dielectric layer n5.

[0143] Optionally, the width and indentation design of the signal transmission connection trace 110, except for the end portion connected to the signal transmission interface 109, can be the same as those of the connection trace 104. In other words, the width of the signal transmission connection trace 110 is also smaller, thereby increasing the connection area between the signal transmission connection trace 110 and the signal transmission line 108 by designing a larger number of fourth vias k4, thereby improving the reliability of the connection.

[0144] Optionally, the extension direction of the signal transmission connection trace 110 may be parallel to the extension direction of the connection trace 104, and the extension direction of the signal transmission line 108 may be parallel to the arrangement direction of the plurality of connection traces 104. For example, the plurality of connection traces 104 may be arranged along the pixel row direction of the display module 100, and the extension direction of the signal transmission line 108 may be the pixel row direction.

[0145] In addition, the width of the active pattern n21 may also be equal to the width of the first target portion z2, which is not limited in this embodiment of the present application.

[0146] It should be noted that the signal transmission line 108 can also be located in the second source-drain layer n8. In this case, the signal transmission line 108 can be connected to the gate pattern n41 of the switching transistor T through vias in the interlayer dielectric layer and the second gate insulation layer n2. Alternatively, the signal transmission line 108 can also be located in the gate layer n4. In this case, the gate patterns n41 of the multiple switching transistors T arranged along the target direction M can be an integrated structure, and this integrated structure is spaced apart from the first sub-routing 1041 and the second sub-routing 1042.

[0147] In the embodiment of the present application, referring to FIG5 , the display module 100 further includes a plurality of signal traces 111 , one end of each signal trace 111 being connected to the binding interface 103 and the other end being connected to the touch electrodes located in the display area 101 a . This allows the touch electrodes to receive touch test signals during the test phase.

[0148] Optionally, the signal trace 111 may include a first signal sub-trace located in the first touch layer and a second signal sub-trace located in the second touch layer. The first signal sub-trace and the second signal sub-trace are connected through a via in the touch insulating layer.

[0149] It should be noted that during the testing phase, the display function of the display module 100 can also be tested. In this case, the display module 100 also includes multiple display binding interfaces, multiple display connection lines, and multiple display signal lines. For example, referring to Figure 5, the binding interface 103 in the figure is replaced with a display binding interface, the connection lines in the figure are replaced with display connection lines, and the signal lines in the figure are replaced with display signal lines.

[0150] For example, the display connection trace can be connected to the display binding interface, and the design of the display connection trace can be the same as that of the connection trace 104. That is, the width of the portion of the display connection trace near the scribe line is smaller than the width of the display binding interface, and the distance between adjacent portions of the display connection trace near the scribe line is greater than the distance between adjacent display binding interfaces. Alternatively, a switching transistor can be designed in the display connection trace, and the switching transistor is turned on during the test phase and turned off during the display phase.

[0151] Furthermore, one end of the display signal line is connected to the display binding interface, and the other end is used to connect to the pixel unit, so that the pixel unit can receive the display test signal during the test phase.

[0152] Optionally, the display connection trace may be located in the gate layer, and the display bonding interface may be located in the second touch layer. The display signal trace may include a first display signal sub-trace located in the first gate layer, a second display signal sub-trace located in the first source / drain layer, and a third display signal sub-trace located in the second source / drain layer. The first display signal sub-trace and the second display signal sub-trace are connected via a via in the second gate insulation layer, and the second display signal sub-trace and the third display signal sub-trace are connected via a via in the interlayer dielectric layer.

[0153] In the embodiment of the present application, the display module can be an organic light emitting diode (OLED) equipped with flexible multi-layer on-cell (FMLOC) touch technology. This display module is lighter and thinner, making it suitable for foldable and rollable products.

[0154] As can be seen from FIG3 , the display module 100 may further include a driver integrated circuit (IC) 112. This driver integrated circuit may be referred to as a driver chip. The driver integrated circuit 112 may be connected to the plurality of pixel units 102 and the binding interface 103. Its primary function is to control the signals provided to the pixel units 102 by the flexible printed circuit board.

[0155] In summary, an embodiment of the present application provides a display module, which includes a base substrate, a plurality of pixel units and a touch film layer located in the display area of ​​the base substrate, and a plurality of binding interfaces and a plurality of connecting wires located in the binding area of ​​the base substrate. The plurality of binding interfaces are connected to the touch film layer, and the first end of the connecting wire is connected to the binding interface. The width of the first target portion of the connecting wire located at the first end away from the display area is smaller than the width of the binding interface, and the distance between adjacent first target portions is smaller than the distance between adjacent binding interfaces. Therefore, when the connecting wire is cut to obtain the connecting wire, even if the connecting wire produces carbonized material due to the high temperature during cutting, the distance between the first target portions of adjacent connecting wires is large, so the carbonized material cannot fill the spacing between the first target portions of adjacent connecting wires, thereby reducing the risk of short circuit of adjacent connecting wires, thereby improving the yield of the display panel.

[0156] FIG16 is a schematic diagram of another display module provided by an embodiment of the present application. Referring to FIG16 , the display module 100 includes: a base substrate 101 , a plurality of pixel units 102 , a touch film layer (not shown in FIG16 ), a plurality of bonding interfaces 103 , and a plurality of connecting traces 104 .

[0157] 2 , the base substrate 101 has a display area 101 a and a peripheral area 101 b surrounding the display area 101 a. The peripheral area 101 b includes a binding area 101 b 1 located on one side of the display area 101 a.

[0158] In conjunction with Figures 5, 11, and 16, multiple pixel units 102 can be located in the display area 101a, and the multiple pixel units 102 can be used to display images. The touch film layer is located on the side of the multiple pixel units 102 away from the base substrate 101, and the touch film layer includes at least touch electrodes. Multiple binding interfaces 103 are located in the binding area 101b1, and the multiple binding interfaces 103 are connected to the touch electrodes in the touch film layer. The first end z1 of the connecting trace 104 is connected to the binding interface 103. The first target portion z2 of the connecting trace 104 includes a first sub-trace 1041 and a second sub-trace 1042 spaced apart along the extension direction of the connecting trace 104. The first target portion z2 is located on the side of the first end z1 of the connecting trace 104 away from the display area 101a, and the end of the first target portion z2 away from the display area 101a is obtained by cutting.

[0159] In an embodiment of the present application, referring to FIG5 , before cutting to obtain the connecting trace 104, the test circuit and test interface can be located on the side of the binding area 101b1 away from the display area 101a. A testing device can be connected to the test interface, providing a test signal to the connecting trace 104 via the test interface and test circuit, thereby testing the performance of the display module 100. After the test is completed, a cutting device is used to remove the test interface and test circuit along the cutting path to obtain the connecting trace 104. The end of the first target portion z2 of the connecting trace 104 away from the display area 101a is the end obtained by the cutting device along the cutting path.

[0160] The display module 100 also includes a switching transistor T and a signal transmission line 108. The switching transistor T includes a gate, a first electrode, and a second electrode. The first electrode is connected to the first sub-trace 1041, and the second electrode is connected to the second sub-trace 1042. The gate is connected to the signal transmission line 108. During the display phase, the switching transistor T receives a shutdown signal from the signal transmission line 108 and is turned off by the shutdown signal.

[0161] During the testing phase, the test equipment needs to provide a detection signal to the bonding interface 103 through the test interface, test circuit, and connection line 104, so the signal needs to be turned on. In this case, the signal transmission line 108 can provide an on signal to the gate of the switching transistor T, so that the switching transistor T is in the on state, thereby allowing the detection signal to be transmitted to the bonding interface 103 through the switching transistor T.

[0162] After the testing phase, cutting equipment is required to cut along the cutting path. The connecting trace 104 will produce carbonized substances due to the high temperature during cutting, which may cause the adjacent connecting traces 104 near the cutting path to short-circuit (for example, the second sub-trace 1042 of the adjacent connecting trace 104 is short-circuited).

[0163] Therefore, during the display phase, to prevent the short-circuit signal from being transmitted to the bonding interface 103, the signal transmission line 108 can provide a shutdown signal to the gate of the switching transistor T, thereby turning the switching transistor T off. In this case, since the switching transistor T is in the off state, signal transmission between the first and second electrodes can be prevented. Even if the second sub-line 1042 of the adjacent connecting line 104 is short-circuited, the short-circuit signal will not be transmitted to the first end z1 of the connecting line 104, thus preventing short circuits between different bonding interfaces 103.

[0164] In summary, an embodiment of the present application provides a display module, which includes a base substrate, a plurality of pixel units and a touch film layer located in the display area of ​​the base substrate, and a plurality of binding interfaces and a plurality of connecting wires located in the binding area of ​​the base substrate. The plurality of binding interfaces are connected to the touch electrodes in the touch film layer, and the first end of the connecting wire is connected to the binding interface. When the connecting wire is cut, even if the connecting wire produces carbonized material due to the high temperature during cutting, causing the second sub-wire close to the cutting path to short-circuit, in the display stage, the switching transistor between the first sub-wire and the second sub-wire included in the first target part of the connecting wire is in an off state. In this way, the short-circuit signal can be prevented from being transmitted to the binding interface, and the short-circuit of different binding interfaces can be avoided, thereby improving the yield of the display panel.

[0165] Referring to FIG16 , the width of each position in the connecting trace 104 is equal. In other words, the first target portion z2 of the connecting trace 104 does not need to be designed to be inward relative to the first end. Optionally, the width of the connecting trace 104 can be equal to the width of the binding interface 103.

[0166] FIG17 is a cross-sectional view taken along the CC' direction of FIG16 . Referring to FIG17 , the connection traces 104 and the bonding interface 103 can be located in different layers of the multiple layers of the display module 100. For example, referring to FIG11 , the display module 100 includes a buffer layer (buffer) n1, an active layer (poly) n2, a gate insulator (GI) n3, a gate layer (gate) n4, an inter-level dielectric (ILD) n5, a first source and drain layer n6, a first planarization layer (PLN) n7, a second source and drain layer n8, a second planarization layer n9, an anode layer n10, a pixel defining layer n11, light-emitting layers n1 and n2, a cathode layer n13, and an encapsulation layer n14, which are stacked in sequence. The touch film layer 105 includes a first touch layer 1051, a touch insulating layer 1052, and a second touch layer 1053.

[0167] The display module 100 also includes a pixel circuit for driving the pixel unit 102 to emit light. The active layer n2, gate insulating layer n3, gate layer n4, interlayer dielectric layer n5, first source and drain electrode layer n6, first planarizing layer n7, and second source and drain electrode layer n8 can be used to form the pixel circuit. The anode layer, light-emitting layer, and cathode layer are used to form the pixel unit 102.

[0168] Optionally, the pixel circuit may include a plurality of thin film transistors (TFTs) and at least one storage capacitor. Optionally, the pixel circuit may include seven thin film transistors and one storage capacitor, that is, the pixel circuit is a 7T1C driving circuit. Alternatively, the pixel circuit may include other numbers of thin film transistors and other numbers of storage capacitors. The embodiments of the present application do not limit the number of thin film transistors included in the pixel circuit and the number of storage capacitors included.

[0169] Each thin film transistor includes a gate, a source, and a drain. The pixel circuit in each pixel unit includes a plurality of thin film transistors that are interconnected to achieve the function of driving the light-emitting unit in the pixel unit to emit light.

[0170] The active layer includes multiple active patterns corresponding to multiple thin film transistors, each active pattern including a source region, a drain region, and a channel region. The source and drain of the thin film transistor are located in the first source-drain layer, and the source of the thin film transistor is connected to the source region, and the drain is connected to the drain region.

[0171] The first gate layer includes a plurality of gate patterns corresponding to the plurality of thin film transistors. The channel region is an overlapping region of an orthographic projection of the gate pattern on the base substrate and an orthographic projection of the active pattern on the base substrate.

[0172] It should be noted that, referring to FIG. 12 , the touch electrodes S may be located on the first touch layer 1051 and the second touch layer 1052 . For example, the touch electrodes S include a plurality of first touch electrodes s1 and a plurality of second touch electrodes s2 . One of the first touch layer 1051 and the second touch layer 1053 includes a main electrode s11 of the first touch electrode s1 and a second touch electrode s2 . The other of the first touch layer 1051 and the second touch layer 1052 includes a bridge electrode s12 of the first touch electrode s1 . The main electrode s11 and the bridge electrode s12 are electrically connected via vias in the touch insulating layer 1052 .

[0173] Referring to Figure 12 , a plurality of first touch electrodes s1 are arranged along a second direction Q, and a plurality of second touch electrodes s2 are arranged along a first direction W. Furthermore, the bridging electrode s12 of the first touch electrode s1 is located in a region where it overlaps with the orthographic projection of the second touch electrode s2. The first direction W may be the direction of pixel rows in the display module 100, and the second direction Q may be the direction of pixel columns in the display module 100.

[0174] 13 , assuming that the first touch layer 1051 includes the bridge electrode s12 of the first touch electrode s1, and the second touch layer 1053 includes the main electrode s11 of the first touch electrode s1 and the second touch electrode s2, in this case, the main electrode s11 of the first touch electrode s1 in the second touch layer 1053 is connected via a via in the touch insulation layer 1052.

[0175] Optionally, one of the first touch electrode s1 and the second touch electrode s2 may be a transmitting (TX) electrode, and the other may be a sensing (RX) electrode.

[0176] In the display module, the display module 100 also includes a touch drive circuit and a touch detection circuit located in the peripheral area 101b. The touch drive circuit can be connected to the transmitting electrode to provide a touch drive signal to the transmitting electrode. The touch detection circuit can be connected to the sensing electrode to receive the sensing signal between the transmitting electrode and the sensing electrode. If a user's finger approaches the display module, the touch detection circuit can detect a change in the sensing signal at the location of the user's finger and determine the location of the change in the sensing signal as the touch location.

[0177] In the embodiment of the present application, the touch function of the display module 100 can be tested during the testing phase. Referring to Figure 17 , the connecting trace 104 is located on the gate layer n4 of the display module 100, and the bonding interface 103 can be located on the second touch layer 1053 of the display module 100. The display module 100 also includes a first connecting portion 106 located on the first source and drain layer n6, and a second connecting portion 107 located on the second source and drain layer n8. The first end z1 of the connecting trace 104 is connected to the bonding interface 103 via the first connecting portion 106 and the second connecting portion 107.

[0178] Specifically, the first end of the connecting trace 104 is connected to the first connecting portion 106 through a via in the interlayer dielectric layer n5, the first connecting portion 106 and the second connecting portion 107 are connected through a via in the first flat layer n7, and the second connecting portion 107 is connected through a via in the second flat layer n9, the encapsulation layer n14 and the touch insulation layer 1052.

[0179] Referring to Figure 17 , the switching transistor T includes an active pattern n21 located in the active layer n2. The orthographic projection of the first end of the active pattern n21 on the base substrate 101 overlaps with the orthographic projection of the first sub-route 1041 on the base substrate 101. The first end of the active pattern n21 can serve as the first electrode of the switching transistor T and is connected to the first sub-route 1041 via a first via k1 in the gate insulating layer n3. The orthographic projection of the second end of the active pattern n21 on the base substrate 101 overlaps with the orthographic projection of the second sub-route 1042 on the base substrate 101. The second end of the active pattern n21 can serve as the second electrode of the switching transistor T and is connected to the second sub-route 1042 via a second via k2 in the gate insulating layer n3.

[0180] 17 , a first via hole k1 and a second via hole k2 are formed in the gate insulating layer n3 of the display module 100. The active pattern and the first sub-trace 1041 are connected through the first via hole k1, and the active pattern and the second sub-trace 1042 are connected through the second via hole k2.

[0181] The switching transistor T further includes a gate pattern n41 located on the gate layer n4. The orthographic projection of the gate pattern n41 on the base substrate 101 overlaps with the orthographic projection of the active pattern n21 on the base substrate 101. The gate pattern n41 can serve as the gate of the switching transistor T and be connected to the signal transmission line 108.

[0182] Assuming that the signal transmission line 108 provides an on signal to the gate of the switching transistor T, the first and second electrodes of the switching transistor T are turned on, and the signal from the second electrode of the switching transistor T can be transmitted to the first electrode of the switching transistor T, and then transmitted to the bonding interface 103. Assuming that the signal transmission line 108 provides an off signal to the gate of the switching transistor T, the signal between the first and second electrodes of the switching transistor T is disconnected, and the signal from the second electrode of the switching transistor T cannot be transmitted to the first electrode of the switching transistor T, nor can it be transmitted to the bonding interface 103.

[0183] During the testing phase, the test equipment needs to provide a detection signal to the bonding interface 103 through the test interface, test circuit, and connection line 104, so the signal needs to be turned on. In this case, the signal transmission line 108 can provide an on signal to the gate of the switching transistor T, so that the switching transistor T is in the on state, thereby allowing the detection signal to be transmitted to the bonding interface 103 through the switching transistor T.

[0184] After the test phase, cutting equipment is required to cut along the cutting path. The connecting traces 104 will produce carbonized substances due to the high temperature during cutting, which may cause adjacent connecting traces 104 to short-circuit (for example, the second sub-traces 1042 of adjacent connecting traces 104 to short-circuit).

[0185] Therefore, in the display stage, in order to prevent the short-circuit signal from being transmitted to the binding interface 103 , the signal transmission line 108 may provide a turn-off signal to the gate of the switch transistor T, so that the switch transistor T is in the turn-off state.

[0186] Referring to Figure 17 , the connecting trace 104 is located on the gate layer n4 of the display module 100. The gate pattern n41 of the switching transistor T is also located on the gate layer n4 of the display module. Both the first sub-trace 1041 and the second sub-trace 1042 of the connecting trace 104 have a gap with the gate pattern n41 of the switching transistor T. Furthermore, the bonding interface 103 may be located on the second touch layer 1053 , with the first end z1 of the connecting trace 104 connected to the bonding interface 103 via the first connecting portion 106 and the second connecting portion 107 .

[0187] Optionally, because the first source / drain layer n6 has a lower resistance than the gate layer n4 and is more efficient in signal transmission, the signal transmission line 108 can be located in the first source / drain layer n6. The orthographic projection of the signal transmission line 108 on the base substrate 101 overlaps with the orthographic projection of the gate pattern n41 on the base substrate 101, and the gate pattern n41 is connected to the signal transmission line 108 via a third via k3 in the second gate insulating layer n2.

[0188] Furthermore, referring to FIG17 , the width of the gate pattern n41 of the switching transistor T can be equal to the width of the first target portion z2. To ensure the reliability of the connection between the signal transmission line 108 and the gate pattern n41, a certain connection area between the signal transmission line 108 and the gate pattern n41 is required. If the width of the gate pattern n41 is small, the connection area between the gate pattern n41 and the signal transmission line 108 can be increased by designing a larger number of third vias k3.

[0189] Referring to Figure 17, the display module 100 also includes a signal transmission interface 109 and a signal transmission connection line 110. Among them, the signal transmission interface 109 can be located in the same layer as the binding interface 103, such as located in the second touch layer 1053. The signal transmission connection line 110 can be located in the same layer as the connection line 104, such as located in the gate layer n4. The signal transmission interface 109 and the signal transmission connection line 110 can be connected through the first connection part 106 and the second connection part 107. The end of the signal transmission connection line 110 away from the signal transmission interface 109 is also connected to the signal transmission line 108. In addition, since the signal transmission connection line 110 (gate layer n4) and the signal transmission line 108 (first source and drain layer n6) are located in different layers, they can be connected through the fourth via k4 in the interlayer dielectric layer n5.

[0190] Optionally, the width of the signal transmission connection trace 110 can be the same as the width of the connection trace 104. Figure 18 is a cross-sectional view of Figure 16 along the DD' direction. Referring to Figure 18, the width of the active pattern n21 can be equal to the width of the gate pattern n41. In addition, the width of the active pattern n21 can be equal to the width of the first target portion z2. This embodiment of the present application is not limited to this.

[0191] Optionally, the extension direction of the signal transmission connection trace 110 may be parallel to the extension direction of the connection trace 104, and the extension direction of the signal transmission line 108 may be parallel to the arrangement direction of the plurality of connection traces 104. For example, the plurality of connection traces 104 may be arranged along the pixel row direction of the display module, and the extension direction of the signal transmission line 108 may be the pixel row direction.

[0192] It should be noted that the signal transmission line 108 can also be located in the second source-drain layer n8. In this case, the signal transmission line 108 can be connected to the gate pattern n41 of the switching transistor T through vias in the interlayer dielectric layer and the second gate insulation layer n2. Alternatively, the signal transmission line 108 can also be located in the gate layer n4. In this case, the gate patterns n41 of the multiple switching transistors T arranged along the target direction M can be an integrated structure, and this integrated structure is spaced apart from the first sub-routing 1041 and the second sub-routing 1042.

[0193] In summary, an embodiment of the present application provides a display module, which includes a base substrate, a plurality of pixel units and a touch film layer located in the display area of ​​the base substrate, and a plurality of binding interfaces and a plurality of connecting wires located in the binding area of ​​the base substrate. The plurality of binding interfaces are connected to the touch electrodes in the touch film layer, and the first end of the connecting wire is connected to the binding interface. When the connecting wire is cut, even if the connecting wire produces carbonized material due to the high temperature during cutting, causing the second sub-wire close to the cutting path to short-circuit, in the display stage, the switching transistor between the first sub-wire and the second sub-wire included in the first target part of the connecting wire is in an off state. In this way, the short-circuit signal can be prevented from being transmitted to the binding interface, and the short-circuit of different binding interfaces can be avoided, thereby improving the yield of the display panel.

[0194] FIG19 is a flow chart of a method for preparing a display module according to an embodiment of the present application. The method can be applied to prepare the display module provided in the above embodiment. Referring to FIG19 , the method includes:

[0195] Step S101: Acquire an initial display module.

[0196] In an embodiment of the present application, referring to Figure 20, the initial display module 100a includes: an initial base substrate 101c, multiple pixel units 102, a touch film layer (not shown in Figure 20), multiple binding interfaces 103, multiple initial connection lines 104a, multiple test circuits and multiple test interfaces.

[0197] 20 , the initial base substrate 101c has a display area 101a and a peripheral area 101b surrounding the display area 101a. The peripheral area 101b includes a binding area 101b1 located on one side of the display area 101a and a to-be-cut area 101b2 located on a side of the binding area 101b1 away from the display area 101a.

[0198] Multiple pixel units 102 are located in the display area 101a, and the multiple pixel units 102 are used to display images. A touch film layer is located on a side of the multiple pixel units 102 away from the base substrate 101, and the touch film layer includes at least touch electrodes. Multiple binding interfaces 103 are located in the binding area 101b1, and the multiple binding interfaces 103 are connected to the touch electrodes in the multiple touch film layers. The first end z1 of the initial connection trace 104a is connected to the binding interface 103, and the first end z1 of the initial connection trace 104a and the first target portion z2 are located in the binding area 101b1. Multiple test circuits, multiple test interfaces, and the second end z3 of the initial connection trace 104a and the second target portion z4 are located in the area to be cut 101b2. The test circuit is connected to the second end z3 of the initial connection trace 104a and to the test interface.

[0199] In the embodiment of the present application, the initial display module 100a may be the display module 100 before being cut along the cutting line. The cutting line may be located between the first end z1 and the second end z3 of the initial connection line 104a.

[0200] Step S102 : The testing device sequentially provides a detection signal to the touch electrode through the test interface, the test circuit, the initial connection wiring, and the binding interface to test the touch performance of the display module.

[0201] In the embodiment of the present application, for the schemes shown in Figures 21 to 23, the test equipment can directly provide a detection signal to the touch electrode through the test interface, the test circuit, the initial connection line 104a, and the binding interface 103. For the schemes shown in Figures 24 and 25, the signal transmission line 108 can provide a turn-on signal to the gate of the switching transistor T, and the switching transistor T is in the turn-on state under the action of the turn-on signal. In this case, the second electrode and the first electrode of the switching transistor T are turned on. The signal provided by the test equipment can be transmitted from the second electrode of the switching transistor T to the first electrode, thereby providing a detection signal to the touch electrode.

[0202] Step S103: using a cutting device to cut along a cutting path between the first end of the initial connection line and the second end of the initial connection line.

[0203] In the embodiment of the present application, the display module 100 can be obtained by cutting along the cutting lines. After cutting, the to-be-cut area 101b2 of the initial base substrate 101c, the test circuit, the test interface and the portion of the initial connection trace 104a located in the to-be-cut area 101b2 can be removed.

[0204] The portion of the initial connection trace 104a that is not cut away is the connection trace 104 in the display module 100. For example, the cutting path is located between the first target portion z2 and the second target portion. The portion of the initial connection trace 104a that is not cut away includes the first end z1 and the first target portion z2, and the portion that is cut away includes the second end z3 and the second target portion z4.

[0205] Optionally, before cutting, the first target portion z2 and the second target portion z4 are directly connected, and the width of the first target portion z2 is equal to the width of the second target portion z4.

[0206] 21 to 24 , the width of the first target portion z2 and the width of the second target portion z4 may both be smaller than the width of the bonding interface 103 . Alternatively, referring to FIG. 25 , the width of the first target portion z2 and the width of the second target portion z4 may be equal to the width of the bonding interface 103 .

[0207] Optionally, the first central axis z21 of the first target portion z2 and the third central axis of the second target portion z4 are collinear. For example, in the solution shown in FIG21 , both boundaries of the first target portion z2 and the second target portion z4 along their extension direction are indented relative to the ends (first end and second end) of the initial connection line 104a. In the solutions shown in FIG22 and FIG23 , one of the boundaries of the first target portion z2 and the second target portion z4 along their extension direction is indented relative to the ends (first end and second end) of the initial connection line 104a.

[0208] Referring to Figures 20 and 21 to 25, the initial display module 100a also includes: multiple transition traces. The first end of the transition trace is connected to the second end z3 of the initial connection trace 104a, and the second end of the transition trace is connected to the test circuit. The width of the transition trace can be greater than or equal to the width of the second target portion z4 of the initial connection trace 104a. The width of the transition trace can be equal to the width of the binding interface 103 and greater than the width of the second target portion of the initial connection trace 104a. Since the distance between the cutting path and the transition trace is relatively far, the high temperature during cutting has less impact on the transition trace.

[0209] 26 , the transition trace may be located in the first source / drain layer n6 of the initial display module 100a, and the first end of the transition trace may be connected to the second end of the initial connection trace 104a through a fifth via k5 in the second gate insulating layer n2. FIG26 shows two fifth vias k5.

[0210] In summary, the embodiments of the present application provide a method for manufacturing a display module. The display module manufactured by this method includes a base substrate, a plurality of pixel units and a touch film layer located in a display region of the base substrate, and a plurality of binding interfaces and a plurality of connecting wires located in a binding region of the base substrate. The plurality of binding interfaces are connected to touch electrodes in the touch film layer, and the first ends of the connecting wires are connected to the binding interfaces.

[0211] The width of the first target portion of the connecting trace, located at the first end away from the display area, is smaller than the width of the bonding interface, and the distance between adjacent first target portions is smaller than the distance between adjacent bonding interfaces. Therefore, even if carbonized material is generated during cutting of the connecting trace due to the high temperature during cutting, the total amount of carbonized material is insufficient to fill the gaps between the first target portions of adjacent connecting traces, reducing the risk of short circuits between adjacent connecting traces and thereby improving the yield of the display panel.

[0212] Alternatively, when cutting the connecting traces, even if the high temperature during cutting produces carbonized material, causing a short circuit in the second sub-trace of the connecting trace near the cutting path, during the display phase, the switching transistor between the first sub-trace and the second sub-trace included in the first target portion of the connecting trace is in the off state. This prevents the short-circuit signal from being transmitted to the bonding interface, preventing short circuits between different bonding interfaces, and thereby improving the yield of the display panel.

[0213] Figure 27 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. Referring to Figure 27 , the display panel includes a flexible printed circuit (FPC) 200 and a display module 100 as provided in the above-described embodiment. The display module 100 has a display side a and a non-display side b that are opposed to each other. The flexible printed circuit 200 includes multiple signal interfaces 201 located on the display side a. These multiple signal interfaces 201 are connected to corresponding binding interfaces 103 in the display module 100. At least a portion of the flexible printed circuit 200 is located on the non-display side b of the display module 200.

[0214] As shown in Figure 27 , a portion of the flexible circuit board 200 is located on the display side a of the display module 100 for bonding to the display module 100, while the other portion is bent from the side of the display module 100 to the non-display side b of the display module 100. This reduces the size of the display panel's bezel, facilitating the realization of a narrow-bezel product.

[0215] Since the display panel can have substantially the same technical effects as the display module described in the previous embodiment, the technical effects of the display panel will not be repeatedly described here for the purpose of brevity.

[0216] The terms used in the embodiments of this application are only used to explain the embodiments of this application and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this application should have the common meanings understood by people with ordinary skills in the field to which this application belongs.

[0217] The terms used in the embodiments of this application are intended solely to illustrate the embodiments of this application and are not intended to limit this application. Unless otherwise defined, technical or scientific terms used in the embodiments of this application should have the same ordinary meaning as those understood by persons of ordinary skill in the art to which this application belongs. The terms "first," "second," "third," and similar terms used in this patent specification and claims do not denote any order, quantity, or importance, but are simply used to distinguish between different components. Similarly, terms such as "a" or "an" do not denote a limitation of quantity, but rather denote the presence of at least one. Terms such as "include" or "comprising" and similar terms mean that the elements or objects listed before "include" or "comprising" include the elements or objects listed after "include" or "comprising," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used solely to indicate relative positions. When the absolute position of the described objects changes, the relative positions may also change accordingly.

[0218] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display module, characterized in that: The display module includes: a base substrate, the base substrate having a display area and a peripheral area surrounding the display area, the peripheral area including a binding area located on one side of the display area; a plurality of pixel units, wherein the plurality of pixel units are located in the display area; A touch film layer, the touch film layer is located on a side of the plurality of pixel units away from the base substrate, and the touch film layer at least includes a touch electrode; a plurality of binding interfaces, the plurality of binding interfaces being located in the binding area and connected to the touch electrodes; and a plurality of connecting traces, wherein first ends of the connecting traces are connected to the binding interface, a width of a first target portion of the connecting traces is smaller than a width of the binding interface, and a distance between adjacent first target portions of the connecting traces is greater than a distance between adjacent binding interfaces; The first target portion is located at a side of the first end of the connecting wire away from the display area, and the end of the first target portion away from the display area is obtained by cutting.

2. The display module according to claim 1, wherein: The width of the first target portion of the connecting trace is greater than or equal to 1.8 microns.

3. The display module according to claim 1, wherein: The width of the first end of the connecting trace is greater than the width of the first target portion of the connecting trace.

4. The display module according to claim 3, wherein: The first central axis of the first target portion of the connecting line and the second central axis of the first end of the connecting line both extend along an extension direction of the connecting line.

5. The display module according to claim 4, wherein: The first central axis and the second central axis are collinear.

6. The display module according to claim 4, wherein: The first target portion of the connecting trace has a first boundary and a second boundary facing each other, and the first end of the connecting trace has a third boundary and a fourth boundary facing each other; The first boundary and the third boundary are collinear and constitute a common boundary of the connecting trace, and the second boundary is closer to the common boundary than the fourth boundary; The first boundary, the second boundary, the third boundary, and the fourth boundary all extend along the extending direction of the connecting line.

7. The display module according to claim 3, wherein: The connecting trace further includes a transition portion between the first target portion and the first end of the connecting trace; The width of the transition portion close to the first end of the connecting trace is equal to the width of the first end of the connecting trace, the width of the transition portion close to the first target portion is equal to the width of the first target portion, and the width of the transition portion decreases as the distance from the first end increases.

8. The display module according to claim 7, wherein: The transition portion has opposing fifth and sixth boundaries; At least one of the fifth boundary and the sixth boundary intersects with an extension direction of the connecting line.

9. The display module according to claim 8, wherein: The fifth boundary and the sixth boundary are both straight lines, and the boundary among the fifth boundary and the sixth boundary that intersects with the extension direction of the connecting line has an obtuse angle with the extension direction of the connecting line.

10. The display module according to any one of claims 1 to 9, characterized in that: The first target portion of the connecting trace includes a first sub-trace and a second sub-trace spaced apart along an extending direction of the connecting trace; The display module also includes: a switching transistor and a signal transmission line, the first electrode of the switching transistor is connected to the first sub-line, the second electrode of the switching transistor is connected to the second sub-line, and the gate of the switching transistor is connected to the signal transmission line. The switching transistor is used to receive a shutdown signal provided from the signal transmission line during the display stage and is in an off state under the action of the shutdown signal.

11. The display module according to claim 10, wherein: The display module includes an active layer, a gate insulating layer, and a gate layer stacked on the base substrate; the connecting wire is located on the gate layer; The switching transistor includes an active pattern located in the active layer; an orthographic projection of a first end of the active pattern on the base substrate overlaps with an orthographic projection of the first sub-route on the base substrate, and the first end of the active pattern serves as a first electrode of the switching transistor and is connected to the first sub-route through a first via in the gate insulating layer; an orthographic projection of a second end of the active pattern on the base substrate overlaps with an orthographic projection of the second sub-route on the base substrate, and the second end of the active pattern serves as a second electrode of the switching transistor and is connected to the second sub-route through a second via in the gate insulating layer; The switching transistor further includes a gate pattern located in the gate layer, the orthographic projection of the gate pattern on the base substrate overlaps with the orthographic projection of the active pattern on the base substrate, and the gate pattern serves as the gate of the switching transistor and is connected to the signal transmission line.

12. The display module according to claim 11, wherein: The number of the first vias and the number of the second vias are both negatively correlated with the width of the first target portion of the connecting trace.

13. The display module according to claim 11, wherein: The display module further includes an interlayer dielectric layer and a first source-drain layer located on a side of the gate layer away from the base substrate; the signal transmission line is located in the first source-drain layer; An orthographic projection of the signal transmission line on the base substrate overlaps with an orthographic projection of the gate pattern on the base substrate, and the gate pattern is connected to the signal transmission line through a third via hole in the interlayer dielectric layer.

14. The display module according to claim 10, wherein: The switch transistor is further configured to receive a start signal provided by the signal transmission line during a test phase, and be in a turn-on state under the action of the start signal.

15. The display module according to any one of claims 1 to 9, characterized in that: The display module includes an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, a first source and drain electrode layer, a first planar layer, a second source and drain electrode layer, a second planar layer, an anode layer, a pixel defining layer, a light-emitting layer, a cathode layer, and an encapsulation layer stacked on the base substrate; the touch film layer is located on a side of the encapsulation layer away from the base substrate, the touch film layer includes: a first touch layer, a touch insulating layer, and a second touch layer, and the touch electrodes are located on the first touch layer and the second touch layer; Wherein, the anode layer, the light-emitting layer, and the cathode layer are used to constitute the plurality of pixel units; The connecting wire is located on the gate layer, the bonding interface is located on the second touch layer, and a first end of the connecting wire is connected to the bonding interface through a via in an insulating film layer between the gate layer and the second touch layer.

16. The display module according to claim 15, wherein: The display module further includes a first connecting portion located on the first source-drain electrode layer, and a second connecting portion located on the second source-drain electrode layer; The first end of the connecting trace is connected to the first connecting portion through a via in the interlayer dielectric layer, the first connecting portion and the second connecting portion are connected through a via in the first flat layer, and the second connecting portion is connected through a via in the second flat layer, the pixel defining layer, the encapsulation layer and the touch insulating layer.

17. A display module, characterized in that: The display module includes: a base substrate, the base substrate having a display area and a peripheral area surrounding the display area, the peripheral area including a binding area located on one side of the display area; a plurality of pixel units, wherein the plurality of pixel units are located in the display area; A touch film layer, the touch film layer is located on a side of the plurality of pixel units away from the base substrate, and the touch film layer at least includes a touch electrode; a plurality of binding interfaces, the plurality of binding interfaces being located in the binding area and connected to the touch electrodes; and a plurality of connecting traces, wherein a first end of the connecting trace is connected to the binding interface, a first target portion of the connecting trace comprises a first sub-trace and a second sub-trace spaced apart along an extension direction of the connecting trace, the first target portion is located on a side of the first end of the connecting trace away from the display area, and an end of the first target portion away from the display area is obtained by cutting; The display module also includes: a switching transistor and a signal transmission line, the first electrode of the switching transistor is connected to the first sub-line, the second electrode of the switching transistor is connected to the second sub-line, and the gate of the switching transistor is connected to the signal transmission line. The switching transistor is used to receive a shutdown signal provided from the signal transmission line during the display stage and is in an off state under the action of the shutdown signal.

18. A method for preparing a display module, characterized in that: Used to prepare the display module according to any one of claims 1 to 17; The preparation method comprises: Obtain an initial display module, the initial display module comprising: an initial base substrate, the initial base substrate having a display area and a peripheral area surrounding the display area, the peripheral area comprising a binding area located on one side of the display area and an area to be cut located on a side of the binding area away from the display area; a plurality of pixel units, the plurality of pixel units being located in the display area; a touch film layer, the touch film layer being located on a side of the plurality of pixel units away from the base substrate, the touch film layer comprising at least touch electrodes; a plurality of binding interfaces, the plurality of binding interfaces being located in the binding area, the plurality of binding interfaces being connected to the touch electrodes; a plurality of initial connection traces, the first ends and first target portions of the initial connection traces being located in the binding area, the first ends of the initial connection traces being connected to the binding interfaces; a plurality of test circuits and a plurality of test interfaces, the plurality of test circuits, the plurality of test interfaces, and the second target portions and second ends of the initial connection traces being located in the area to be cut, the test circuits being connected to the second ends of the initial connection traces and to the test interfaces; Using a test device to sequentially provide a detection signal to the touch electrode through the test interface, the test circuit, the initial connection line, and the binding interface to test the touch performance of the display module; A cutting device is used to cut along the cutting path between the first end of the initial connecting trace and the second end of the initial connecting trace, and the area to be cut of the initial substrate, the test circuit, the test interface and the portion of the initial connecting trace located in the area to be cut are cut off. The portion of the initial connecting trace that is not cut off is the connecting trace, and the first end of the initial connecting trace is the first end of the connecting trace.

19. The method according to claim 18, characterized in that The first target portion is a portion of the initial connection line that has not been cut off, and the second target portion is a portion of the initial connection line that has been cut off; The first target portion and the second target portion are directly connected, and the width of the first target portion is equal to the width of the second target portion.

20. A display panel, characterized in that: The display panel comprises: a flexible circuit board, and a display module according to any one of claims 1 to 17; The display module has a relative display side and a non-display side, and the flexible circuit board includes a plurality of signal interfaces located on the display side, and the plurality of signal interfaces are correspondingly connected to a plurality of binding interfaces in the display module; at least a portion of the flexible circuit board is located on the non-display side of the display module.

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