Display panel, display control method therefor, and display apparatus

Abstract

A display panel, a display control method therefor, and a display apparatus. Each sub-pixel receives a data signal (Vda) at a first level in a data writing period (tw). In a first period (ta), the data signal (Vda) is at a second level, and in a second period (tb), the data signal (Vda) is at a third level. The absolute value of the difference between a third voltage (V3) corresponding to the third level and a first voltage (V1) corresponding to the first level is less than the absolute value of the difference between a second voltage (V2) corresponding to the second level and the first voltage (V1).

Description

Display panel, display control method thereof, and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel, a display control method thereof, and a display device. Background Art

[0002] Compared with low-resolution display panels of the same size, medium- and high-resolution display panels have smaller spacing between pixels, greater signal interference between pixels, and are prone to crosstalk problems. SUMMARY OF THE INVENTION

[0003] The embodiments of the present application provide a display panel and a display control method thereof, and a display device, which are helpful in improving the display crosstalk problem.

[0004] An embodiment of the present invention provides a display panel comprising a plurality of scan lines, a plurality of data lines, and a plurality of sub-pixels. The plurality of scan lines are configured to transmit a plurality of scan signals, the plurality of data lines are configured to transmit a plurality of data signals, and the plurality of sub-pixels are electrically connected to the plurality of scan lines and the plurality of data lines. Each of the sub-pixels is configured to receive the data signal transmitted by the electrically connected data line according to the corresponding scan signal during the corresponding data writing period. In the data writing period, the data signal has a first level; in a first period before or after the data writing period, the data signal has a second level; in a second period between the first period and the data writing period, the data signal has a third level; the absolute value of the difference between a third voltage corresponding to the third level and a first voltage corresponding to the first level is less than the absolute value of the difference between a second voltage corresponding to the second level and the first voltage.

[0005] An embodiment of the present invention also provides a display control method, comprising: obtaining an initial display grayscale corresponding to a plurality of sub-pixels included in each pixel column in a display panel, and determining a grayscale interval corresponding to the pixel column based on the plurality of initial display grayscales corresponding to each pixel column; obtaining a third voltage when the data signal received by the plurality of sub-pixels in each pixel column is a third level based on the grayscale interval corresponding to each pixel column; in a data writing period corresponding to each sub-pixel, controlling the sub-pixel to receive a data signal transmitted by the electrically connected data line, and controlling the data signal to have a first level during the data writing period; controlling the data signal to have a second level during a first period before or after the data writing period; and controlling the data signal to have the third level during a second period between the first period and the data writing period; wherein the absolute value of the difference between the third voltage corresponding to the third level and the first voltage corresponding to the first level is less than the absolute value of the difference between the second voltage corresponding to the second level and the first voltage.

[0006] An embodiment of the present invention further provides a display device, comprising any of the above-mentioned display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0008] FIG2 is a schematic diagram of the structure of a sub-pixel provided in an embodiment of the present invention;

[0009] FIG3A is a timing diagram of a corresponding pixel driving circuit provided by an embodiment of the present invention;

[0010] FIG3B is another timing diagram of a corresponding pixel driving circuit provided by an embodiment of the present invention;

[0011] FIG3C is another timing diagram of a corresponding pixel driving circuit provided in an embodiment of the present invention;

[0012] FIG3D is another timing diagram of a corresponding pixel driving circuit provided in an embodiment of the present invention;

[0013] FIG3E is another timing diagram of a corresponding pixel driving circuit provided in an embodiment of the present invention;

[0014] FIG3F is another timing diagram of a corresponding pixel driving circuit provided in an embodiment of the present invention;

[0015] FIG3G is another timing diagram of a corresponding pixel driving circuit provided in an embodiment of the present invention;

[0016] FIG3H is another timing diagram of a corresponding pixel driving circuit provided in an embodiment of the present invention;

[0017] FIG4 is a flow chart of a display control method provided by an embodiment of the present invention;

[0018] FIG5 is a schematic structural diagram of a display device provided by an embodiment of the present invention. Modes for Carrying Out the Invention

[0019] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0020] Optionally, in some embodiments, the display panel includes a plurality of pixel columns, and each pixel column includes a plurality of sub-pixels electrically connected to the same data line. Within a frame, the plurality of sub-pixels in the same pixel column correspond to a plurality of initial display grayscales, and a midpoint between a voltage corresponding to a maximum display grayscale among the plurality of initial display grayscales and a voltage corresponding to a minimum display grayscale among the plurality of initial display grayscales is an intermediate voltage; and the absolute value of the difference between the third voltage and the second voltage is less than or equal to the intermediate voltage.

[0021] Optionally, in some embodiments, the absolute value of the difference between the second voltage and the first voltage is greater than or equal to the intermediate voltage, and the third voltage is equal to the intermediate voltage.

[0022] Optionally, in some embodiments, the absolute value of the difference between the second voltage and the first voltage is smaller than the intermediate voltage, and the absolute value of the difference between the third voltage and the second voltage is smaller than the intermediate voltage.

[0023] Optionally, in some embodiments, the third voltage is equal to 0.5 times the absolute value of the difference between the first voltage and the second voltage.

[0024] Optionally, in some embodiments, the duration corresponding to the data writing period is less than or equal to the duration corresponding to the second period.

[0025] Optionally, in some embodiments, each sub-pixel includes a light-emitting device, a driving transistor, a switching transistor, and a first capacitor. The input terminal of the driving transistor is electrically connected to the first power supply terminal, and the output terminal of the driving transistor is electrically connected to the light-emitting device. The control terminal of the switching transistor is electrically connected to the corresponding scan line, the input terminal of the switching transistor is electrically connected to the corresponding data line, and the output terminal of the switching transistor is electrically connected to the control terminal of the driving transistor. The first terminal of the first capacitor is electrically connected to the control terminal of the driving transistor, and the second terminal of the first capacitor is electrically connected to the output terminal of the driving transistor.

[0026] Optionally, in some embodiments, at least one of the sub-pixels further comprises a reset transistor and a compensation transistor. The control terminal of the reset transistor is configured to receive a reset control signal, the input terminal of the reset transistor is configured to receive a reset signal, and the output terminal of the reset transistor is electrically connected to the light-emitting device. The control terminal of the compensation transistor is configured to receive a compensation control signal, the input terminal of the compensation transistor is configured to receive a compensation signal, and the output terminal of the compensation transistor is electrically connected to the control terminal of the driving transistor.

[0027] The present invention provides a display panel, a display control method thereof, and a display device. Each subpixel included in the display panel receives a data signal having a first level according to a corresponding scanning signal during a corresponding data writing period, thereby implementing an operation of writing the corresponding data signal into the subpixel. The data signal is enabled to have a second level during a first period before or after the data writing period; and the data signal is enabled to have a third level during a second period between the first period and the data writing period. Furthermore, the absolute value of the difference between a third voltage corresponding to the third level and a first voltage corresponding to the first level is smaller than the absolute value of the difference between a second voltage corresponding to the second level and the first voltage, so that the coupling effect of the jump voltage difference between the third voltage and the first voltage caused by parasitic capacitance is smaller than the coupling effect of the jump voltage difference between the second voltage and the first voltage caused by parasitic capacitance. This improves the problem that when the data signal directly jumps between the first voltage and the second voltage, the voltage jump voltage difference is large, and the coupling effect is severe after coupling through parasitic capacitance, thereby affecting signal quality and causing display problems such as crosstalk on the display panel.

[0028] Specifically, FIG1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention. The embodiment of the present invention provides a display panel including a plurality of scan lines SL, a plurality of data lines DL, and a plurality of sub-pixels Spi.

[0029] The plurality of scan lines SL are configured to transmit a plurality of scan signals Ga. Optionally, each of the scan lines SL extends along the first direction x, and the plurality of scan lines SL are arranged along the second direction y.

[0030] The plurality of data lines DL are configured to transmit a plurality of data signals Vda. Optionally, each of the data lines DL extends along the second direction y, and the plurality of data lines DL are arranged along the first direction x.

[0031] The plurality of sub-pixels Spi are electrically connected to the plurality of scan lines SL and the plurality of data lines DL, and the plurality of sub-pixels Spi realize display according to the corresponding scan signals Ga and the data signals Vda.

[0032] Optionally, each of the sub-pixels Spi includes a light-emitting device Di and a pixel driving circuit, wherein the pixel driving circuit is electrically connected to the light-emitting device Di, and the pixel driving circuit is configured to drive the corresponding light-emitting device Di to emit light.

[0033] Optionally, each of the sub-pixels Spi includes at least one light-emitting device Di. The light-emitting device Di includes one of an organic light-emitting diode, a sub-millimeter light-emitting diode, a micro light-emitting diode, and the like.

[0034] FIG2 is a schematic structural diagram of a sub-pixel provided by an embodiment of the present invention. The pixel driving circuit of each sub-pixel Spi includes a driving transistor Tdr, a switching transistor Tda, and a first capacitor C1.

[0035] The input terminal of the driving transistor Tdr is electrically connected to the first power supply terminal VDD, the output terminal of the driving transistor Tdr is electrically connected to the light emitting device Di, and the driving transistor Tdr is configured to generate a driving current for driving the light emitting device Di to emit light.

[0036] The control end of the switching transistor Tda is electrically connected to the corresponding scan line SL, the input end of the switching transistor Tda is electrically connected to the corresponding data line DL, the output end of the switching transistor Tda is electrically connected to the control end of the driving transistor Tdr, and the switching transistor Tda is configured to control the signal transmission between the control end of the driving transistor Tdr and the data line DL according to the corresponding scan signal Ga.

[0037] A first end of the first capacitor C1 is electrically connected to the control end of the driving transistor Tdr, and a second end of the first capacitor C1 is electrically connected to the output end of the driving transistor Tdr.

[0038] The anode of the light emitting device Di is electrically connected to the output terminal of the driving transistor Tdr, and the cathode of the light emitting device Di is electrically connected to the second power supply terminal VSS.

[0039] Continuing to refer to FIG. 2 , in some embodiments, at least one of the sub-pixels Spi further includes a reset transistor Ti and a compensation transistor Tc.

[0040] The control end of the reset transistor Ti is configured to receive a reset control signal INI, the input end of the reset transistor Ti is configured to receive a reset signal Vini, the output end of the reset transistor Ti is electrically connected to the light-emitting device Di, and the reset transistor Ti is configured to transmit the reset signal Vini to the anode of the light-emitting device Di according to the reset control signal INI to reset the anode potential of the light-emitting device Di.

[0041] The control end of the compensation transistor Tc is configured to receive a compensation control signal REF, the input end of the compensation transistor Tc is configured to receive a compensation signal Vref, the output end of the compensation transistor Tc is electrically connected to the control end of the driving transistor Tdr, and the compensation transistor Tc is configured to transmit the compensation signal Vref to the control end of the driving transistor Tdr according to the compensation control signal REF.

[0042] Accordingly, referring to FIG1 , the display panel may include a plurality of reset control lines INL and a plurality of compensation control lines REL. The plurality of reset control lines INL are configured to transmit a plurality of reset control signals INI, and the plurality of compensation control lines REL are configured to transmit a plurality of compensation control signals REF. The reset transistor Ti is configured to transmit the reset signal Vini to the anode of the light-emitting device Di according to the corresponding reset control signal INI, and the compensation transistor Tc of the sub-pixel Spi is configured to transmit the compensation signal Vref to the control terminal of the drive transistor Tdr according to the corresponding compensation control signal REF.

[0043] Optionally, the display panel includes a first gate driving unit configured to generate a plurality of the scanning signals Ga for transmission to the plurality of sub-pixels Spi through the plurality of scanning lines SL, wherein the effective pulses of the plurality of scanning signals Ga have the same pulse width.

[0044] Optionally, the display panel includes a second gate driving unit, and the second gate driving unit is configured to generate a plurality of the reset control signals INI to be transmitted to a plurality of the sub-pixels Spi through a plurality of the reset control lines INL.

[0045] Optionally, in some embodiments, the second gate driving unit is further configured to generate a plurality of the compensation control signals REF, so as to transmit the plurality of the sub-pixels Spi through a plurality of the compensation control lines REL.

[0046] Optionally, in some embodiments, the display panel includes a third gate driving unit, and the third gate driving unit is configured to generate a plurality of the compensation control signals REF to be transmitted to a plurality of the sub-pixels Spi through a plurality of the compensation control lines REL.

[0047] It is understandable that the circuit structure of the pixel driving circuit is not limited to the form shown in FIG2 , and may also be configured as 5T1C, 7T1C, 8T2C, etc. Wherein, XTYC indicates that the pixel driving circuit includes X transistors and Y capacitors.

[0048] However, due to the parasitic capacitance between the data line DL and the control end of the driving transistor Tdr of the adjacent sub-pixel Spi, and when the display panel adopts a high-resolution design, the parasitic capacitance is relatively large, resulting in that when the data signal Vda changes, the control end potential of the driving transistor Tdr of the sub-pixels Spi in different rows will be coupled to different degrees, and then the data signal Vda will interfere with the scanning signal Ga, so that some of the sub-pixels Spi cannot accurately receive the required data signal Vda, resulting in display crosstalk and other problems on the display panel.

[0049] Therefore, to improve the display crosstalk problem, the present application adjusts the variation of the data signal Vda. That is, each sub-pixel Spi is configured to receive the data signal Vda transmitted by the electrically connected data line DL according to the corresponding scan signal Ga during the corresponding data writing period tw. During the data writing period tw, the data signal Vda has a first level; in a first period ta before or after the data writing period tw, the data signal Vda has a second level; and in a second period tb between the first period ta and the data writing period tw, the data signal Vda has a third level. Among them, the absolute value of the difference between the third voltage V3 corresponding to the third level and the first voltage V1 corresponding to the first level is smaller than the absolute value of the difference between the second voltage V2 corresponding to the second level and the first voltage V1, so that the coupling effect caused by the parasitic capacitance of the jump voltage difference between the third voltage V3 and the first voltage V1 is smaller than the coupling effect caused by the parasitic capacitance of the jump voltage difference between the second voltage V2 and the first voltage V1, thereby improving the situation that when the data signal Vda directly jumps between the first voltage V1 and the second voltage V2, the voltage jump voltage difference is large, resulting in a more serious coupling effect, affecting the signal quality, and causing display problems such as vertical display crosstalk on the display panel.

[0050] It should be noted that the data writing period tw corresponds to the stage when the scanning signal Ga received by the sub-pixel Spi is at a high level and the data signal Vda is transmitted to the control terminal of the driving transistor Tdr.

[0051] 3A is a timing diagram of a corresponding pixel driving circuit provided in an embodiment of the present invention. Taking the driving transistor Tdr, the switching transistor Tda, the compensation transistor Tc and the reset transistor Ti as N-type transistors, the scanning signal Ga applied to the sub-pixel Spi corresponds to the n-th scanning signal Ga(n) among multiple scanning signals, the reset control signal INI applied to the sub-pixel Spi corresponds to the n-th reset control signal INI(n) among multiple reset control signals, the compensation control signal REF applied to the sub-pixel Spi corresponds to the n-th compensation control signal REF(n) among multiple compensation control signals, and the data signal Vda applied to the sub-pixel Spi corresponds to the n-th data signal Vda(n) among multiple data signals as an example, the working principle of the pixel driving circuit is described.

[0052] Initialization phase t1: The nth compensation control signal REF(n) and the nth reset control signal INI(n) are high, and the nth scanning signal Ga(n) is low. The compensation transistor Tc and the reset transistor Ti are turned on, the reset signal Vini resets the anode potential of the light-emitting device Di, and the compensation signal Vref is transmitted to the control terminal of the driving transistor Tdr.

[0053] Compensation stage t2: the nth compensation control signal REF(n) is at a high level, the nth reset control signal INI(n) and the nth scanning signal Ga(n) are at a low level, the reset transistor Ti is turned off, and the compensation transistor Tc remains on.

[0054] During a data writing period tw, the nth compensation control signal REF(n) and the nth reset control signal INI(n) are at a low level, and the nth scan signal Ga(n) is at a high level. The compensation transistor Tc and the reset transistor Ti are turned off, the switching transistor Tda is turned on, and the data signal Vda is transmitted to the control terminal of the driving transistor Tdr. The driving transistor Tdr generates a driving current according to the corresponding data signal Vda to drive the light-emitting device Di to emit light.

[0055] By controlling the voltage value of the data signal Vda during the data writing period tw, the magnitude of the driving current generated by the driving transistor Tdr can be controlled, thereby controlling the brightness of the light emitting device Di.

[0056] 3A , the first period ta is located before the data writing period tw. Optionally, corresponding to the time axis, the first period ta may partially overlap with the initialization phase t1 and the compensation phase t2.

[0057] FIG3B is another timing diagram of a corresponding pixel driving circuit provided by an embodiment of the present invention, wherein the first period ta is located after the data writing period tw.

[0058] Because each data line DL is electrically connected to the plurality of sub-pixels Spi located in the same column, voltage transitions of the data signal Vda will affect the control terminals of the drive transistors Tdr of the plurality of sub-pixels Spi located in the same column to varying degrees. Therefore, to comprehensively compensate for the coupling effect of the voltage transitions of the data signal Vda on the plurality of sub-pixels Spi located in the same column, the third voltage V3 can be set based on the voltage corresponding to the initial display grayscale of the plurality of sub-pixels Spi electrically connected to the same data line DL.

[0059] Continuing with FIG. 1 , the display panel includes a plurality of pixel columns SPC. Each pixel column SPC includes a plurality of sub-pixels Spi that are electrically connected to the same data line DL. The third voltage V3 can be set based on the voltage corresponding to the initial display grayscale of the plurality of sub-pixels Spi in the same pixel column SPC.

[0060] Because each pixel column SPC displays a different image in each frame, the initial display grayscales corresponding to the multiple sub-pixels Spi in each pixel column SPC are also different. Accordingly, the voltages of the data signal Vda required for the multiple sub-pixels Spi in each pixel column SPC are also different, resulting in different coupling effects. Therefore, to compensate for the coupling effects in different display images, the third voltage V3 can be set based on the voltages corresponding to the maximum and minimum display grayscales among the multiple initial display grayscales corresponding to the pixel column SPC.

[0061] Optionally, in some embodiments, within a frame, the plurality of sub-pixels Spi in the same pixel column SPC correspond to a plurality of initial display grayscales, and a midpoint between a voltage corresponding to a maximum display grayscale among the plurality of initial display grayscales and a voltage corresponding to a minimum display grayscale among the plurality of initial display grayscales is an intermediate voltage Vm. If the voltage corresponding to the maximum display grayscale among the plurality of initial display grayscales is Vmax, and the voltage corresponding to the minimum display grayscale among the plurality of initial display grayscales is Vmin, then the intermediate voltage Vm is Vmin+(Vmax-Vmin) / 2.

[0062] Optionally, in some embodiments, the voltage corresponding to the intermediate display grayscale between the maximum display grayscale and the minimum display grayscale in the plurality of initial display grayscales is the intermediate voltage Vm. For example, if the maximum display grayscale is 200 grayscale and the minimum display grayscale is 20 grayscale, the intermediate display grayscale is 110 grayscale, and the voltage corresponding to 110 grayscale is the intermediate voltage Vm.

[0063] The absolute value of the difference between the third voltage V3 and the second voltage V2 is less than or equal to the middle voltage Vm, so that the coupling effect under different display screens can be compensated.

[0064] For example, within a frame, the maximum display grayscale corresponding to a certain pixel column SPC is 255 grayscale, and the minimum display grayscale is 0 grayscale. Meanwhile, the maximum display grayscale corresponding to another pixel column SPC is 200 grayscale, and the minimum display grayscale is 30 grayscale. Therefore, the intermediate voltage Vm obtained based on the voltages corresponding to 255 grayscale and 0 grayscale is different from the intermediate voltage Vm obtained based on the voltages corresponding to 200 grayscale and 30 grayscale. The value range of the third voltage V3 used by the pixel column SPC corresponding to the maximum display grayscale of 255 grayscale and the minimum display grayscale of 0 grayscale can be different from the value range of the third voltage V3 used by the pixel column SPC corresponding to the maximum display grayscale of 200 grayscale and the minimum display grayscale of 30 grayscale.

[0065] Furthermore, each pixel column SPC displays different images in different frames, and thus may have different maximum and minimum grayscales. Therefore, by setting the third voltage V3 based on the voltages corresponding to the maximum and minimum grayscales of the pixel column SPC, each pixel column SPC can be matched to a corresponding third voltage V3 in different frames, thereby compensating for the coupling effect caused by the actual display content of each pixel column SPC in each frame.

[0066] The larger the voltage difference jump of the data signal Vda, the more significant the coupling effect caused by parasitic capacitance. The smaller the voltage difference jump of the data signal Vda, the smaller the coupling effect caused by parasitic capacitance. If the voltage difference between the third voltage V3 and the second voltage V2 is set to be greater than the voltage difference between the first voltage V1 and the second voltage V2, then the coupling effect caused by the data signal Vda jumping between the third voltage V3 and the second voltage V2 will be greater than the coupling effect caused by the data signal Vda jumping between the second voltage V2 and the first voltage V1, thereby increasing the impact of the coupling effect. To this end, the third voltage V3 can be determined based on the relationship between the absolute value of the difference between the first voltage V1 and the second voltage V2 and the intermediate voltage Vm, so that the data signal Vda has a smaller voltage difference jump.

[0067] Accordingly, in some embodiments, the absolute value of the difference between the second voltage V2 and the first voltage V1 is greater than or equal to the intermediate voltage Vm, and the third voltage V3 is equal to the intermediate voltage Vm, so that the absolute value of the difference between the third voltage V3 and the first voltage V1 is smaller than the absolute value of the difference between the second voltage V2 and the first voltage V1.

[0068] Continuing with FIG. 3A , the first period ta precedes the data writing period tw, and the second voltage V2 corresponds to a voltage of a high display grayscale (e.g., grayscale 240), while the first voltage V1 corresponds to a voltage of a low display grayscale (e.g., grayscale 20). Therefore, when the absolute value of the difference between the second voltage V2 and the first voltage V1 is greater than or equal to the intermediate voltage Vm, the third voltage V3 can be set equal to the intermediate voltage Vm during the second period tb, and the data signal Vda can be set to the first voltage V1 during the data writing period tw. The data signal Vda forms a trapezoidal variation trend during the first period ta, the second period tb, and the data writing period tw.

[0069] Similarly, please continue to refer to Figure 3B. The first time period ta is located after the data writing time period tw, and the second voltage V2 corresponds to a voltage for a low display grayscale, and the first voltage V1 corresponds to a voltage for a high display grayscale. Then, when the absolute value of the difference between the second voltage V2 and the first voltage V1 is greater than or equal to the intermediate voltage Vm, the third voltage V3 can be made equal to the intermediate voltage Vm corresponding to the second time period tb, and the data signal Vda can have the first voltage V1 in the data writing time period tw.

[0070] Similarly, Figure 3C is another timing diagram of the corresponding pixel driving circuit provided in an embodiment of the present invention. The first time period ta is located before the data writing period tw, and the second voltage V2 corresponds to a voltage for a low display grayscale, and the first voltage V1 corresponds to a voltage for a high display grayscale. Then, when the absolute value of the difference between the second voltage V2 and the first voltage V1 is greater than or equal to the intermediate voltage Vm, the third voltage V3 can be made equal to the intermediate voltage Vm corresponding to the second time period tb, and the data signal Vda can have the first voltage V1 in the data writing period tw.

[0071] Similarly, Figure 3D is another timing diagram of the corresponding pixel driving circuit provided in an embodiment of the present invention. The first time period ta is located after the data writing period tw, and the second voltage V2 corresponds to a voltage for a high display grayscale, and the first voltage V1 corresponds to a voltage for a low display grayscale. Then, when the absolute value of the difference between the second voltage V2 and the first voltage V1 is greater than or equal to the intermediate voltage Vm, the third voltage V3 can be made equal to the intermediate voltage Vm corresponding to the second time period tb, and the data signal Vda can have the first voltage V1 in the data writing period tw.

[0072] In some embodiments, the absolute value of the difference between the second voltage V2 and the first voltage V1 is less than the intermediate voltage Vm, and the absolute value of the difference between the third voltage V3 and the second voltage V2 is less than the intermediate voltage Vm, so that the absolute value of the difference between the third voltage V3 and the first voltage V1 is less than the absolute value of the difference between the second voltage V2 and the first voltage V1.

[0073] Optionally, in some embodiments, when the absolute value of the difference between the second voltage V2 and the first voltage V1 is less than the intermediate voltage Vm, the third voltage V3 is equal to 0.5 times the absolute value of the difference between the first voltage V1 and the second voltage V2, so that the third voltage V3 is the intermediate value between the first voltage V1 and the second voltage V2.

[0074] As shown in Figure 3E, there is another timing diagram of the corresponding pixel driving circuit provided by an embodiment of the present invention. The first time period ta is located before the data writing period tw, and the second voltage V2 corresponds to a voltage for displaying a high grayscale, and the first voltage V1 corresponds to a voltage for displaying a low grayscale. Then, when the absolute value of the difference between the second voltage V2 and the first voltage V1 is less than the intermediate voltage Vm, the third voltage V3 can be made equal to 0.5 times the absolute value of the difference between the first voltage V1 and the second voltage V2 corresponding to the second time period tb, and the data signal Vda has the first voltage V1 in the data writing period tw.

[0075] Similarly, Figure 3F is another timing diagram of the corresponding pixel driving circuit provided in an embodiment of the present invention, in which the first time period ta is located before the data writing time period tw, and the second voltage V2 corresponds to a voltage for a low display grayscale, and the first voltage V1 corresponds to a voltage for a high display grayscale. Then, when the absolute value of the difference between the second voltage V2 and the first voltage V1 is less than the intermediate voltage Vm, the third voltage V3 can be made equal to 0.5 times the absolute value of the difference between the first voltage V1 and the second voltage V2 corresponding to the second time period tb, and the data signal Vda has the first voltage V1 during the data writing time period tw.

[0076] Similarly, Figure 3G is another timing diagram of the corresponding pixel driving circuit provided in an embodiment of the present invention. The first time period ta is located after the data writing period tw, and the second voltage V2 corresponds to a voltage for a high display grayscale, and the first voltage V1 corresponds to a voltage for a low display grayscale. Then, when the absolute value of the difference between the second voltage V2 and the first voltage V1 is less than the intermediate voltage Vm, the third voltage V3 can be made equal to 0.5 times the absolute value of the difference between the first voltage V1 and the second voltage V2 corresponding to the second time period tb, and the data signal Vda has the first voltage V1 during the data writing period tw.

[0077] Similarly, Figure 3H is another timing diagram of the corresponding pixel driving circuit provided by an embodiment of the present invention, in which the first time period ta is located after the data writing time period tw, and the second voltage V2 corresponds to a voltage for a low display grayscale, and the first voltage V1 corresponds to a voltage for a high display grayscale. Then, when the absolute value of the difference between the second voltage V2 and the first voltage V1 is less than the intermediate voltage Vm, the third voltage V3 can be made equal to 0.5 times the absolute value of the difference between the first voltage V1 and the second voltage V2 corresponding to the second time period tb, and the data signal Vda has the first voltage V1 during the data writing time period tw.

[0078] To prevent the data signal Vda having the third level from being received by the corresponding sub-pixel Spi, thereby affecting the display effect of the sub-pixel Spi, the duration of the data writing period tw can be adjusted. For example, the duration of the data writing period tw can be adjusted from 1H to less than 1H. Here, H represents a unit duration, which is set by the control device.

[0079] Optionally, the duration of the data writing period tw can be shortened by controlling the pulse width of the effective pulse of the scanning signal Ga received by the sub-pixel Spi. That is, the pulse width of the effective pulse of the scanning signal Ga is reduced, and the duration of the data writing period tw is shortened.

[0080] Correspondingly, when the data signal Vda corresponding to the sub-pixel Spi has a third level, the scanning signal Ga corresponding to the sub-pixel Spi has an invalid level. When the data signal Vda corresponding to the sub-pixel Spi has a first level, the scanning signal Ga corresponding to the sub-pixel Spi has an effective level, so that the pulse width of the effective pulse of the scanning signal Ga can be reduced. For example, when the data signal Vda corresponding to the sub-pixel Spi has a third level, the scanning signal Ga corresponding to the sub-pixel Spi has a low level. When the data signal Vda corresponding to the sub-pixel Spi has a first level, the scanning signal Ga corresponding to the sub-pixel Spi has a high level.

[0081] Optionally, in some embodiments, the duration corresponding to the data writing period tw is less than or equal to the duration corresponding to the second period tb, so that the data signal Vda required by the sub-pixel Spii is normally written into the corresponding sub-pixel Spi, while the coupling effect caused by the voltage jump of the data signal Vda is compensated.

[0082] Optionally, in some embodiments, the pulse width corresponding to the data writing period tw is 0.3H~0.5H, so that the data signal Vda required by the sub-pixel Spi is written normally, ensuring that the sub-pixel Spi has a better charging rate while compensating for the coupling effect caused by the voltage jump of the data signal Vda.

[0083] It can be understood that, since there is a phase difference between the effective pulses output by the plurality of scanning signals Ga, each sub-pixel Spi is matched with a corresponding first period ta, second period tb and data writing period tw.

[0084] Optionally, in some embodiments, the plurality of sub-pixels Spi include a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel being adjacent to each other along the second direction y and electrically connected to the same data line DL, wherein the data writing period tw corresponding to the first sub-pixel precedes the data writing period tw corresponding to the second sub-pixel.

[0085] When the first time period ta corresponding to each sub-pixel Spi is before the corresponding data writing time period tw, the second voltage V2 of the data signal Vda received by the second sub-pixel in the corresponding first time period ta may be equal to the first voltage V1 of the data signal Vda received by the first sub-pixel in the corresponding data writing time period tw.

[0086] When the first time period ta corresponding to each sub-pixel Spi is located after the corresponding data writing time period tw, the second voltage V2 of the data signal Vda received by the first sub-pixel in the corresponding first time period ta may be equal to the first voltage V1 of the data signal Vda received by the second sub-pixel in the corresponding data writing time period tw.

[0087] In some embodiments, the data signal Vda is restored to a reference voltage during the blanking interval, and the second voltage V2 of the data signal Vda during the first period ta may be equal to the reference voltage.

[0088] When the second voltage V2 is equal to the reference voltage, the third voltage V3 can still be determined based on the absolute value of the difference between the first voltage V1 and the second voltage V2. That is, when the absolute value of the difference between the second voltage V2 and the first voltage V1 is greater than or equal to the intermediate voltage Vm, the third voltage V3 can still be set equal to the intermediate voltage Vm. When the absolute value of the difference between the second voltage V2 and the first voltage V1 is less than the intermediate voltage Vm, the third voltage V3 can still be set equal to 0.5 times the absolute value of the difference between the first voltage V1 and the second voltage V2.

[0089] Optionally, the blanking interval period includes at least one of a horizontal blanking interval period and a vertical blanking interval period.

[0090] Optionally, in some embodiments, after the intermediate voltage Vm corresponding to each of the pixel columns SPC is determined, the third voltage V3 corresponding to the pixel column SPC can be directly set to the intermediate voltage Vm, so that the third voltages V3 corresponding to multiple sub-pixels Spi in the pixel column SPC are the same, thereby reducing the control difficulty and power consumption while compensating to a certain extent for the coupling effect caused by the voltage jump of the data signal Vda.

[0091] The present application controls the voltage change of the data signal Vda, thereby reducing the coupling effect of the sub-pixel Spii receiving the data signal Vda on the control end of the driving transistor Tdr of the adjacent row sub-pixel Spi, so that the coupling effect of all sub-pixels Spi in the display panel on the control end of the driving transistor Tdr of the adjacent row sub-pixel Spi is reduced, thereby improving the vertical crosstalk problem.

[0092] Optionally, the third voltage V3 corresponding to different display requirements can be pre-stored in the storage module, so that when the data signal Vda required by the corresponding pixel column SPC needs to be level controlled, the required third voltage V3 can be directly called by the control device, thereby saving display control time.

[0093] Optionally, in some embodiments, the grayscale interval corresponding to the pixel column SPC may be determined by a plurality of the initial display grayscales corresponding to the pixel column SPC, and then the middle voltage Vm and the third voltage V3 may be determined.

[0094] FIG4 is a flow chart of a display control method provided by an embodiment of the present invention. An embodiment of the present invention further provides a display control method, including:

[0095] Acquire initial display grayscales corresponding to a plurality of sub-pixels Spi included in each pixel column SPC in the display panel, and determine a grayscale interval corresponding to the pixel column SPC according to the plurality of initial display grayscales corresponding to each pixel column SPC;

[0096] According to the grayscale interval corresponding to each pixel column SPC, a third voltage V3 is obtained when the data signal Vda received by the plurality of sub-pixels Spi in each pixel column SPC is at a third level;

[0097] During a data writing period tw corresponding to each sub-pixel Spi, the sub-pixel Spi is controlled to receive a data signal Vda transmitted by the electrically connected data line DL, and during the data writing period tw, the data signal Vda is controlled to have a first level; during a first period ta before or after the data writing period tw, the data signal Vda is controlled to have a second level; and during a second period tb between the first period ta and the data writing period tw, the data signal Vda is controlled to have a third level. The absolute value of the difference between a third voltage V3 corresponding to the third level and a first voltage V1 corresponding to the first level is smaller than the absolute value of the difference between a second voltage V2 corresponding to the second level and the first voltage V1.

[0098] Optionally, the step of determining the grayscale interval corresponding to the pixel column SPC based on the multiple initial display grayscales corresponding to each pixel column SPC includes: determining the grayscale interval corresponding to the pixel column SPC based on the maximum display grayscale and the minimum display grayscale among the multiple initial display grayscales corresponding to each pixel column SPC.

[0099] Because each pixel column SPC may have different maximum and minimum display grayscales corresponding to different display images, each grayscale interval corresponds to a different grayscale range. For example, the grayscale interval may correspond to grayscale 0 to grayscale 255, grayscale 1 to grayscale 255, grayscale 2 to grayscale 255, and so on. Optionally, the grayscale interval corresponding to each pixel column SPC corresponds to a grayscale range of grayscale X to grayscale Y, where X is the minimum display grayscale corresponding to the pixel column SPC, and Y is the maximum display grayscale corresponding to the pixel column SPC.

[0100] Optionally, the grayscale range corresponding to each grayscale interval can be set during the debugging phase.

[0101] Optionally, during the debugging phase, the grayscale interval can be set to grayscale 0 to grayscale 255, grayscale 32 to grayscale 255, etc. Based on the brightness data of each pixel column SPC in the display panel corresponding to different grayscale intervals, a crosstalk test method is used to measure the data, and the brightness difference when the crosstalk problem exists is counted. Afterwards, the corresponding intermediate voltage Vm is set for each of the different grayscale intervals, and the corresponding third voltage V3 is obtained, and the set intermediate voltage Vm and the third voltage V3 are verified and optimized. Until the intermediate voltage Vm and the third voltage V3 corresponding to the different grayscale intervals are applied to realize display in conjunction with the sub-pixel Spi, they meet the crosstalk test standard, and the intermediate voltage Vm and the third voltage V3 that meet the crosstalk test standard are stored in the storage module, so that in actual use, the control device can call the required data when executing the steps of the display control method.

[0102] During the optimization and adjustment process of the intermediate voltage Vm and the third voltage V3, fluctuations in the intermediate voltage Vm and the third voltage V3 can cause fluctuations in display brightness. Therefore, to ensure that the display brightness is consistent with the target brightness after the fluctuations in the intermediate voltage Vm and the third voltage V3, the voltages corresponding to the initial display grayscales of the plurality of sub-pixels Spi can be controlled to also fluctuate when the intermediate voltage Vm and the third voltage V3 fluctuate. Accordingly, in actual use, the first voltage V1 and the second voltage V2 of the data signal Vda can be voltages obtained by compensating the voltages corresponding to the initial display grayscales of the sub-pixels Spi (i.e., the fluctuations in the voltages corresponding to the initial display grayscales made during the debugging phase that meet test requirements are recorded so that, in actual use, the desired first voltage V1 and second voltage V2 can be obtained based on the fluctuations corresponding to the initial display grayscale).

[0103] Optionally, during the process of optimizing and adjusting the intermediate voltage Vm and the third voltage V3, the pulse widths of the second period tb and the data writing period tw may be controlled to increase or decrease from 0.5H.

[0104] Optionally, after the intermediate voltage Vm and the third voltage V3 corresponding to one grayscale interval are adjusted, the intermediate voltage Vm and the third voltage V3 corresponding to another grayscale interval may be adjusted.

[0105] Optionally, the middle voltage Vm and the third voltage V3 corresponding to a plurality of the grayscale intervals may be different.

[0106] FIG5 is a schematic structural diagram of a display device provided by an embodiment of the present invention. An embodiment of the present invention further provides a display device comprising any of the above-mentioned display panels.

[0107] Optionally, the display device further includes a control module CU and a storage module, the control module CU and the storage module are electrically connected to the display panel, the control module CU is configured to control the display panel to achieve display, and the storage module is configured to store the intermediate voltage Vm and the third voltage V3 corresponding to different grayscale intervals.

[0108] Optionally, the control module CU includes a timing controller, a microprocessor, a central processing unit, etc. The storage module includes a volatile memory and a non-volatile memory.

[0109] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A display panel, wherein: include: a plurality of scan lines configured to transmit a plurality of scan signals; a plurality of data lines configured to transmit a plurality of data signals; as well as a plurality of sub-pixels electrically connected to the plurality of scan lines and the plurality of data lines; each of the sub-pixels being configured to receive the data signal transmitted by the electrically connected data line according to the corresponding scan signal during a corresponding data writing period; In which, during the data writing period, the data signal has a first level; in a first period before or after the data writing period, the data signal has a second level; in a second period between the first period and the data writing period, the data signal has a third level; the absolute value of the difference between a third voltage corresponding to the third level and a first voltage corresponding to the first level is less than the absolute value of the difference between a second voltage corresponding to the second level and the first voltage.

2. The display panel according to claim 1, wherein The display panel includes a plurality of pixel columns, and each pixel column includes a plurality of sub-pixels electrically connected to the same data line; Among them, within one frame, multiple sub-pixels of the same pixel column correspond to multiple initial display grayscales, and the intermediate value of the voltage corresponding to the maximum display grayscale among the multiple initial display grayscales and the voltage corresponding to the minimum display grayscale among the multiple initial display grayscales is the intermediate voltage; the absolute value of the difference between the third voltage and the second voltage is less than or equal to the intermediate voltage.

3. The display panel according to claim 2, wherein: An absolute value of a difference between the second voltage and the first voltage is greater than or equal to the middle voltage, and the third voltage is equal to the middle voltage.

4. The display panel according to claim 2, wherein: An absolute value of a difference between the second voltage and the first voltage is smaller than the middle voltage, and an absolute value of a difference between the third voltage and the second voltage is smaller than the middle voltage.

5. The display panel according to claim 4, wherein: The third voltage is equal to 0.5 times the absolute value of the difference between the first voltage and the second voltage. The display panel according to claim 1 , wherein: The duration corresponding to the data writing period is less than or equal to the duration corresponding to the second period.

7. The display panel according to claim 1, wherein: Each of the sub-pixels includes: Light-emitting devices; a driving transistor, wherein an input terminal of the driving transistor is electrically connected to the first power supply terminal, and an output terminal of the driving transistor is electrically connected to the light-emitting device; a switching transistor, wherein a control terminal of the switching transistor is electrically connected to the corresponding scan line, an input terminal of the switching transistor is electrically connected to the corresponding data line, and an output terminal of the switching transistor is electrically connected to the control terminal of the driving transistor; and A first capacitor, wherein a first end of the first capacitor is electrically connected to the control end of the driving transistor, and a second end of the first capacitor is electrically connected to the output end of the driving transistor.

8. The display panel according to claim 7, wherein: At least one of the sub-pixels further comprises: a reset transistor, wherein a control terminal of the reset transistor is configured to receive a reset control signal, an input terminal of the reset transistor is configured to receive a reset signal, and an output terminal of the reset transistor is electrically connected to the light-emitting device; and A compensation transistor, wherein the control terminal of the compensation transistor is configured to receive a compensation control signal, the input terminal of the compensation transistor is configured to receive a compensation signal, and the output terminal of the compensation transistor is electrically connected to the control terminal of the driving transistor.

9. A display control method, wherein: include: Acquire initial display grayscales corresponding to a plurality of sub-pixels included in each pixel column in the display panel, and determine a grayscale interval corresponding to each pixel column based on the plurality of initial display grayscales corresponding to the pixel column; acquiring, according to the grayscale interval corresponding to each pixel column, a third voltage when the data signal received by the plurality of sub-pixels in each pixel column is at a third level; During a data writing period corresponding to each of the sub-pixels, the sub-pixels are controlled to receive a data signal transmitted by the electrically connected data line, and during the data writing period, the data signal is controlled to have a first level; during a first period before or after the data writing period, the data signal is controlled to have a second level; and during a second period between the first period and the data writing period, the data signal is controlled to have a third level; wherein the absolute value of the difference between the third voltage corresponding to the third level and the first voltage corresponding to the first level is less than the absolute value of the difference between the second voltage corresponding to the second level and the first voltage.

10. A display device, wherein: It includes a display panel and a control module electrically connected to the display panel, wherein the control module is configured to control the display panel to realize display; The display panel includes a plurality of scan lines, a plurality of data lines, and a plurality of sub-pixels. The plurality of scan lines are configured to transmit a plurality of scan signals, and the plurality of data lines are configured to transmit a plurality of data signals. The plurality of sub-pixels are electrically connected to the plurality of scan lines and the plurality of data lines. Each of the sub-pixels is configured to receive the data signal transmitted by the electrically connected data line according to the corresponding scan signal during a corresponding data writing period. In which, during the data writing period, the data signal has a first level; in a first period before or after the data writing period, the data signal has a second level; in a second period between the first period and the data writing period, the data signal has a third level; the absolute value of the difference between a third voltage corresponding to the third level and a first voltage corresponding to the first level is less than the absolute value of the difference between a second voltage corresponding to the second level and the first voltage.

11. The display device according to claim 10, wherein: The display panel includes a plurality of pixel columns, and each pixel column includes a plurality of sub-pixels electrically connected to the same data line; Among them, within one frame, multiple sub-pixels of the same pixel column correspond to multiple initial display grayscales, and the intermediate value of the voltage corresponding to the maximum display grayscale among the multiple initial display grayscales and the voltage corresponding to the minimum display grayscale among the multiple initial display grayscales is the intermediate voltage; the absolute value of the difference between the third voltage and the second voltage is less than or equal to the intermediate voltage.

12. The display device according to claim 11, wherein An absolute value of a difference between the second voltage and the first voltage is greater than or equal to the middle voltage, and the third voltage is equal to the middle voltage.

13. The display device according to claim 11, wherein An absolute value of a difference between the second voltage and the first voltage is smaller than the middle voltage, and an absolute value of a difference between the third voltage and the second voltage is smaller than the middle voltage.

14. The display device according to claim 13, wherein: The third voltage is equal to 0.5 times the absolute value of the difference between the first voltage and the second voltage.

15. The display device according to claim 11, wherein The display device includes a storage module electrically connected to the display panel, and the storage module is configured to store the intermediate voltage and the third voltage corresponding to different grayscale intervals.

16. The display device according to claim 10, wherein The duration corresponding to the data writing period is less than or equal to the duration corresponding to the second period.

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