Receiving device, laser radar, imaging system, and related method

Abstract

Embodiments of the present application provide a receiving device, a laser radar, an imaging system, and a related method. The receiving device is connected to a receiving array, the receiving array comprises N receiving units, and each receiving unit is used for detecting a photon signal and outputting a pulse signal; and the receiving device comprises a combiner and a speed limiter. The combiner is connected to the receiving array and is used for performing signal combination processing on N received pulse signals respectively output by the N receiving units, and outputting a first combined pulse signal, the first combined pulse signal comprising K pulse signals among the N pulse signals. The speed limiter is used for performing pulse deletion processing on the received first combined pulse signal on the basis of a signal processing rate or a preset time interval, and outputting a second combined pulse signal, wherein the second combined pulse signal comprises M pulse signals among the K pulse signals. By implementing the embodiments of the present application, the hardware volume can be reduced and the resource consumption can be reduced without limiting the photon event processing scale.

Description

A receiving device, lidar, imaging system, and related methods TECHNICAL FIELD

[0001] The present application relates to the technical field of radar, and in particular to a receiving device, lidar, imaging system, and related methods. BACKGROUND

[0002] In the prior art, a lidar or imaging system can often first send a light signal to an object, and receive the light signal reflected by the object after a period of time. The lidar or imaging system can perform imaging and / or ranging processing on the object based on the reflected light signal. As is known, the amount of received photon signals is much larger than the transmission speed and processing speed of the signal stream in the processor. Therefore, the receiving end often receives a large number of photon events to be processed in a very short period of time. In the subsequent processor processing process, when the photon events received at the previous moment are processed, a large number of photon events at the current moment are likely to be lost, thereby causing the lidar or imaging system to be unable to obtain high-quality imaging and / or ranging information. In order to ensure the collection of photon static information, a memory is often provided at the receiving end of the lidar or imaging system in the prior art. Each receiving unit of the receiving end that receives a photon can correspond to one or more storage bits in the memory, and the memory can be used to store the photon information received by the corresponding receiving unit, so as to ensure the collection of photon static information.

[0003] However, the size of the memory in this scheme is often determined according to the scale of the receiving unit of the receiving end, which can cause a large area of memory devices to appear on the chip. Moreover, the photon information received by each receiving unit needs to be first stored in the memory and then read out for processing, and the size of the memory can further limit the processing scale of the photon events. In addition, additional resources are needed to drive the memory to write, read, or reset, etc.

[0004] Therefore, how to reduce the hardware volume and save resource consumption without limiting the processing scale of the photon events is a technical problem to be solved.

[0005] SUMMARY

[0006] The embodiments of the present application provide a receiving device, lidar, imaging system, and related methods to reduce the hardware volume and save resource consumption without limiting the processing scale of the photon events.

[0007] In a first aspect, an embodiment of the present application provides a receiving device connected with a receiving array, wherein the receiving array comprises N receiving units, each of which is configured to detect a photon signal and output a pulse signal, and N is a positive integer greater than or equal to 2; the receiving device comprises a combiner and a rate limiter; the combiner is connected with the receiving array and configured to: receive the pulse signals output by the N receiving units respectively, perform a combining signal processing on the received N pulse signals, and output a first combined pulse signal, wherein the first combined pulse signal comprises K pulse signals in the N pulse signals, and K is a positive integer less than or equal to N; and the rate limiter is configured to: receive the first combined pulse signal, perform a pulse pruning processing on the first combined pulse signal based on a signal processing rate or a preset time interval, and output a second combined pulse signal; wherein the second combined pulse signal comprises M pulse signals in the K pulse signals, and M is a positive integer less than or equal to K.

[0008] In the prior art, in order to avoid missing large-scale photon events, a memory is usually added at the receiving end to store photon events that have not been completely processed. However, this can cause a large area of memory devices on the chip or receiving end, and the size of the memory can also limit the scale of subsequent processing of photon events. In addition, the chip or receiving end also needs additional resources to drive the memory to write, read or reset, etc. To this end, the embodiments of the present application can efficiently process a large number of photon events without setting a memory, avoid missing large-scale photon events, and thus reduce resource consumption while reducing hardware area and improve the processing efficiency of photon events. For example, the embodiments of the present application provide a receiving device that can be applied to the receiving end of a laser radar or imaging system. The receiving device is connected with a receiving array that outputs a plurality of pulse signals. The receiving device includes a combiner and a rate limiter. The combiner is connected with the receiving array and can be used for signal processing of N pulse signals output by the receiving array, outputting a first combined pulse signal, and the first combined pulse signal includes K pulse signals in the N pulse signals. The combiner combines the plurality of pulse signals from parallel transmission into serial transmission, which is conducive to the orderly processing of the back-end processing system. Compared with the prior art scheme of directly imaging or ranging processing the first combined pulse signal, the first combined pulse signal output by the combiner in the embodiments of the present application still needs to be processed by the pulse pruning of the rate limiter, and then the second combined pulse signal obtained after the pulse pruning is processed is imaged or ranged. Since the rate limiter performs pulse pruning on the first combined pulse signal based on the size of the signal processing rate or the preset time interval, the number and time interval of the pulse signals in the output second combined pulse signal can meet the needs of the subsequent signal processing rate or the preset time interval. Therefore, in the embodiments of the present application, large-scale memory devices can be avoided without missing large-scale photon events. Moreover, the area of the rate limiter is greatly reduced compared with the area of the memory, which greatly reduces the overall area of the receiving device. Moreover, the rate limiter does not need many additional resources to drive the write, read or reset operations, which greatly reduces the resource consumption. Most importantly, since the second combined pulse signal obtained after the pulse pruning meets the needs of the size of the signal processing rate, the rate limiter does not limit the scale of subsequent processing of photon events, which greatly improves the processing efficiency of photon events.

[0009] In a possible implementation, the speed limiter is specifically used for: performing pulse pruning processing on the first combined pulse signal based on driving of the K pulse signals in the first combined pulse signal and a size of the signal processing rate or a preset time interval, and outputting the second combined pulse signal; a time interval between any two adjacent pulse signals in the M pulse signals in the second combined pulse signal is greater than or equal to a first preset time length, and the first preset time length is determined by the signal processing rate.

[0010] Compared with a global clock used by a memory, the speed limiter in the embodiment of the application is an asynchronous speed limiter, which does not need driving of a global clock, and can perform pulse pruning processing on the first combined pulse signal based on driving of the pulse signals in the first combined pulse signal, thereby greatly reducing device cost. Moreover, a pulse signal that does not meet the size of the signal processing rate or the preset time interval under driving of the pulse signal, that is, a pulse signal with a time interval between two adjacent pulse signals being less than the first preset time length, will be pruned, so that a subsequent processing system can normally and orderly process all pulse signals in the second combined pulse signal.

[0011] In a possible implementation, the speed limiter includes: a latch, an integrator, and a comparator; an input end of the latch and a driving end of the comparator are connected to an output end of the combiner, a reset end of the latch is connected to an output end of the comparator, an output end of the latch is connected to a first input end of the comparator through the integrator, and a second input end of the comparator is connected to a reference voltage; the latch is configured to receive the K pulse signals in the first combined pulse signal, and output the M pulse signals in the second combined pulse signal based on a reset signal fed back by the comparator; the integrator is configured to receive the M pulse signals output by the latch, perform integration processing on the M pulse signals, and output a corresponding integration voltage; and the comparator is configured to, when receiving driving of the K pulse signals in the first combined pulse signal, compare the integration voltage output by the integration circuit and the reference voltage, and output the reset signal to the latch based on a comparison result.

[0012] In the embodiment of the present application, the state of the input end of the latch is saved to the output end only when a valid reset signal is input to the reset end, until the next valid reset signal is input to the reset end. In this regard, the integrator performs integration processing on the M pulse signals and outputs corresponding integration voltages, and the comparator can compare the integration voltages output by the integration circuit with the reference voltage and output the reset signal to the latch based on the comparison result, so as to output different reset signals according to different comparison results, so as to filter the pulse signals. This filtering method is simple and efficient, and does not require the driving of a global clock, which helps to further reduce the device size of the receiving device and improve the processing efficiency of the photon event.

[0013] In a possible implementation, the integrator includes a current source, a first switch tube, a second switch tube, and a capacitor. One end of the current source is connected to a power supply voltage. One end of the current source is connected to one end of the first switch tube. The other end of the first switch tube and one end of the second switch tube are connected to one end of the capacitor. The other end of the second switch tube is connected to the other end of the capacitor. The control end of the first switch tube and the control end of the second switch tube serve as the input end of the integrator and are connected to the output of the latch, for receiving the second combined pulse signal.

[0014] In the embodiment of the present application, a simple and efficient circuit structure of an integrator is provided. The current source and the capacitor value in the integrator can determine the speed of the integration processing of the integrator. Therefore, the speed of the integration processing of the integrator can be controlled by adjusting the size of the current source and the capacitor value in the integrator, so as to adapt to the signal processing rate of the second combined pulse signal. The smaller the capacitor value of the capacitor is, the larger the current value of the current source in the integrator is, and the faster the integration speed of the integrator is.

[0015] In a possible implementation, the smaller the capacitor value of the capacitor in the integrator is, the shorter the first preset time length is. The larger the current value of the current source in the integrator is, the shorter the first preset time length is. The smaller the reference voltage in the comparator is, the shorter the first preset time length is.

[0016] In the embodiment of the present application, the length of the minimum time interval (i.e., the first preset time length) between any two adjacent pulse signals in the second combined pulse signal can be adjusted according to the size of the current source and the capacitor value in the integrator and the size of the reference voltage received by the comparator. For example, when the signal processing rate is slow, the minimum time interval between the two adjacent pulse signals can be lengthened, in which case the capacitor value can be increased, the current source can be reduced, or the reference voltage can be increased, and the like.

[0017] In a possible implementation, the N pulse signals include a first pulse signal and a second pulse signal; and the time at which the combiner receives the first pulse signal is earlier than the time at which the combiner receives the second pulse signal; and the combiner is specifically configured to: in a case where a time interval between the time at which the first pulse signal is received and the time at which the second pulse signal is received is greater than a second preset time length, the K pulse signals include the first pulse signal and the second pulse signal; in a case where the time interval between the time at which the first pulse signal is received and the time at which the second pulse signal is received is less than or equal to the second preset time length and greater than a third preset time length, the K pulse signals include the first pulse signal and do not include the second pulse signal; and in a case where the time interval between the time at which the first pulse signal is received and the time at which the second pulse signal is received is less than or equal to the third preset time length, the K pulse signals do not include the first pulse signal and the second pulse signal.

[0018] In the embodiment of the application, if the combiner receives two non-coincident pulse signals (for example, the time interval is greater than the second preset time length), the combiner can directly combine the two pulse signals for signal processing. If the combiner receives two coincident pulse signals, but the time interval between the two coincident pulse signals is greater than the dead time (for example, the third preset time length) of the address processing module or other hardware circuit, the combiner retains only the first received pulse signal and discards the later received pulse signal. If the time interval between the two coincident pulse signals is very small and is insufficient to be distinguished by the address processing module or other hardware circuit, the combiner directly discards the two coincident pulse signals, thereby avoiding the phenomenon of signal error.

[0019] In a possible implementation, the apparatus further includes an address processing module, and the address processing module is configured to determine address information of each pulse signal in the second combined pulse signal corresponding to a receiving unit in the receiving array.

[0020] In the embodiment of the application, the receiving apparatus further includes an address processing module configured to determine address information of each pulse signal in the second combined pulse signal, so as to facilitate subsequent imaging or ranging processing.

[0021] In a possible implementation manner, the address processing module includes an address encoder and an address decoder; the address encoder is configured to, in the case that the combiner outputs the first combined pulse signal, output, to the address decoder, encoded address information corresponding to each pulse signal in the first combined pulse signal; and the address decoder is configured to, in the case that the rate limiter outputs the second combined pulse signal, output, based on the encoded address information corresponding to each pulse signal in the first combined pulse signal, decoded address information corresponding to each pulse signal in the second combined pulse signal, the decoded address information including address information of a receiving unit corresponding to each pulse signal in the second combined pulse signal in the receiving array.

[0022] In the embodiment of the present application, the address information of each pulse signal is input to a processing system at the rear end for imaging or ranging processing. Accordingly, the address processing module includes an address encoder and an address decoder to encode and decode the address information, and to avoid errors or omissions of the address information of the pulse signal.

[0023] In a possible implementation manner, each receiving unit detects a photon signal by using one or more avalanche diodes and outputs the pulse signal; and the receiving device further includes an avalanche quenching and resetting module; the avalanche resetting module is configured to quench and reset one or more avalanche diodes of the corresponding receiving unit after the receiving unit outputs the pulse signal.

[0024] In the embodiment of the present application, the receiving device can be applied to the field of single-photon imaging or ranging, and the avalanche diode is used to collect photon events, thereby greatly improving the quality of imaging or ranging. In order to enable the normal use of the avalanche diode in each time window, the receiving device further includes an avalanche resetting module to quench and reset one or more avalanche diodes of the corresponding receiving unit in time after the receiving unit outputs the pulse signal.

[0025] In a second aspect, the embodiment of the present application provides a laser radar, and the laser radar includes: a receiving array and the receiving device provided by the first aspect or any possible implementation manner of the first aspect, the receiving device being connected to the receiving array, and the receiving array including a plurality of receiving units, each receiving unit being configured to detect a photon signal and output a pulse signal.

[0026] In a third aspect, the embodiment of the present application provides an imaging system, and the imaging system includes: a receiving array and the receiving device provided by the first aspect or any possible implementation manner of the first aspect, the receiving device being connected to the receiving array, and the receiving array including a plurality of receiving units, each receiving unit being configured to detect a photon signal and output a pulse signal.

[0027] In a fourth aspect, an embodiment of the present application provides a receiving method, characterized in application to a receiving device, wherein the receiving device is connected with a receiving array, the receiving array comprises N receiving units, each of the receiving units is configured to receive an optical signal and output a pulse signal, N is a positive integer greater than or equal to 2; the receiving device comprises a combiner and a rate limiter, and the method comprises: receiving, by the combiner, the pulse signals output by the N receiving units respectively, performing combined signal processing on the received N pulse signals to obtain a first combined pulse signal, the first combined pulse signal comprises K pulse signals in the N pulse signals, K is a positive integer less than or equal to N; performing, by the rate limiter, pulse pruning processing on the first combined pulse signal based on a size of a signal processing rate or a preset time interval to obtain a second combined pulse signal; wherein the second combined pulse signal comprises M pulse signals in the K pulse signals, M is a positive integer less than or equal to K.

[0028] In a possible implementation, the pulse pruning processing on the first combined pulse signal based on the size of the signal processing rate or the preset time interval to obtain the second combined pulse signal comprises: performing, under driving of the K pulse signals in the first combined pulse signal, pulse pruning processing on the first combined pulse signal based on the size of the signal processing rate or the preset time interval to output the second combined pulse signal; a time interval between any two adjacent pulse signals in the M pulse signals in the second combined pulse signal is greater than or equal to a first preset time length, and the first preset time length is determined by the signal processing rate.

[0029] In a possible implementation, the speed limiter includes a latch, an integrator, and a comparator; an input end of the latch and a driving end of the comparator are connected to an output end of the combiner; a reset end of the latch is connected to an output end of the comparator; an output end of the latch is connected to a first input end of the comparator through the integrator; and a second input end of the comparator is connected to a reference voltage; the pulse pruning processing of the first combined pulse signal based on the size of the signal processing rate or the preset time interval by the speed limiter to obtain the second combined pulse signal includes: receiving the K pulse signals in the first combined pulse signal by the latch, and outputting the M pulse signals in the second combined pulse signal based on the reset signal fed back by the comparator; and the method further includes: receiving the M pulse signals output by the latch by the integrator, performing integral processing on the M pulse signals, and outputting corresponding integral voltages; and when the driving of the K pulse signals in the first combined pulse is received, comparing the integral voltages output by the integral circuit and the reference voltage by the comparator, and outputting the reset signal to the latch based on the comparison result.

[0030] In a possible implementation, the integrator includes a current source, a first switch tube, a second switch tube, and a capacitor; one end of the current source is connected to a power supply voltage, one end of the current source is connected to one end of the first switch tube, the other end of the first switch tube and one end of the second switch tube are connected to one end of the capacitor, and the other end of the second switch tube is connected to the other end of the capacitor; the control end of the first switch tube and the control end of the second switch tube serve as the input end of the integrator and are connected to the output of the latch, and are used to receive the second combined pulse signal.

[0031] In a possible implementation, the smaller the capacitance value of the capacitor in the integrator is, the shorter the first preset time length is; the greater the current value of the current source in the integrator is, the shorter the first preset time length is; and the smaller the reference voltage in the comparator is, the shorter the first preset time length is.

[0032] In a possible implementation, the N pulse signals include a first pulse signal and a second pulse signal; the combiner receives the first pulse signal earlier than the second pulse signal; when a time interval between the time of receiving the first pulse signal and the time of receiving the second pulse signal is greater than a second preset time length, the K pulse signals include the first pulse signal and the second pulse signal; when the time interval between the time of receiving the first pulse signal and the time of receiving the second pulse signal is less than or equal to the second preset time length and greater than a third preset time length, the K pulse signals include the first pulse signal and do not include the second pulse signal; and when the time interval between the time of receiving the first pulse signal and the time of receiving the second pulse signal is less than or equal to the third preset time length, the K pulse signals do not include the first pulse signal and the second pulse signal.

[0033] In a possible implementation, the device further includes an address processing module; and the method further includes determining, by the address processing module, address information of each pulse signal in the second combined pulse signal corresponding to a receiving unit in the receiving array.

[0034] In a possible implementation, the address processing module includes an address encoder and an address decoder; and the determining, by the address processing module, address information of each pulse signal in the second combined pulse signal corresponding to a receiving unit in the receiving array includes: in a case where the combiner outputs the first combined pulse signal, outputting, by the address encoder, encoded address information corresponding to each pulse signal in the first combined pulse signal to the address decoder; and in a case where the rate limiter outputs the second combined pulse signal, outputting, by the address decoder, decoded address information corresponding to each pulse signal in the second combined pulse signal based on the encoded address information corresponding to each pulse signal in the first combined pulse signal, the decoded address information including address information of each pulse signal in the second combined pulse signal corresponding to a receiving unit in the receiving array.

[0035] In a possible implementation, each receiving unit detects a photon signal by using one or more avalanche diodes and outputs the pulse signal; the receiving device further includes an avalanche quenching and resetting module; and the method further includes quenching and resetting, by the avalanche resetting module, one or more avalanche diodes of a corresponding receiving unit after the receiving unit outputs the pulse signal.

[0036] It should be understood that the laser radar provided by the second aspect of the present application, the imaging system provided by the third aspect of the present application, and the receiving method provided by the fourth aspect of the present application are consistent with the technical solutions of the first aspect of the present application, and the specific contents and beneficial effects can be referred to the receiving device provided in the first aspect of the present application, which will not be described here in detail. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments or background of the present application, the drawings needed to be used in the embodiments or background of the present application will be described below.

[0038] FIG. 1 is a structural schematic diagram of a receiving end in the prior art provided by an embodiment of the present application.

[0039] FIG. 2 is a structural schematic diagram of a receiving device provided by an embodiment of the present application.

[0040] FIG. 3A is a schematic diagram of a combined pulse signal provided by an embodiment of the present application.

[0041] FIG. 3B is a schematic diagram of another combined pulse signal provided by an embodiment of the present application.

[0042] FIG. 4 is a schematic diagram of a pruned pulse signal provided by an embodiment of the present application.

[0043] FIG. 5 is a structural schematic diagram of another receiving device provided by an embodiment of the present application.

[0044] FIG. 6 is a schematic diagram of the working principle of a speed limiter provided by an embodiment of the present application.

[0045] FIGS. 7 and 8 are comparative schematic diagrams of second combined pulse signals corresponding to a group of different integration speeds provided by an embodiment of the present application.

[0046] FIG. 9 is a schematic diagram of the circuit structure of a speed limiter provided by an embodiment of the present application.

[0047] FIG. 10 is a comparative schematic diagram of second combined pulse signals corresponding to different reference voltages provided by an embodiment of the present application.

[0048] FIG. 11 is a structural schematic diagram of still another receiving device provided by an embodiment of the present application.

[0049] FIG. 12 is a flow schematic diagram of a receiving method provided by an embodiment of the present application. DETAILED DESCRIPTION

[0050] The embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0051] The terms "first", "second", "third", and "fourth" and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. Moreover, the terms "include", "have", and the like when used in this specification and in the following claims are intended to mean the inclusion of a non-exclusive "including" such that the method, system, product, apparatus or device that is described includes, but is not limited to, the elements and / or steps that are listed. Furthermore, the term "comprise" and variations of the term, such as "comprising", "comprises" and "comprised of", are not intended to exclude the presence of elements other than the ones stated in a claim.

[0052] It should be understood that, in this application, "at least one" means one or more, "multiple" means two or more. "And / or", used to describe the relationship between associated objects, means that there can be three relationships, for example, "A and / or B" can mean: only A, only B, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c, can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0053] For the convenience of description, the embodiments of the present application can use spatial relationship words such as "under", "below", "lower than", "under", "above", "upper" and the like to describe the relationship of one element or feature shown in the drawings with other elements or features. It will be understood that these spatial relationship words are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. For example, if the device in the drawing is turned over, the direction of the element described as "below" or "under" or "under" the other element or feature will be changed to "above" the other element or feature. Therefore, the example words "below" and "under" can include both the upper and lower directions. The device can also have other orientations (rotated 90 degrees or in other directions), so the spatial relationship description words used herein should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.

[0054] Reference to“an embodiment” herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase“in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all referring to a common embodiment, or an embodiment that is independent of other embodiments. One of ordinary skill in the art will recognize that an implementation including“an embodiment” encompasses one or more recitations of claims.

[0055] As used in this description, the terms“component,”“module,”“system,” and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and / or thread of execution and a component can be localized, co-resident, and / or distributed amongst one or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. The components can communicate by way of local and / or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and / or across a network such as the Internet with other systems via the signal).

[0056] First, in order to facilitate the understanding of the embodiments of the present application, the technical problems to be solved by the embodiments of the present application are specifically analyzed as follows.

[0057] In the prior art, the laser radar or imaging system can first send a light signal to an object, receive the light signal reflected by the object after a period of time, and perform imaging and / or ranging processing on the object based on the reflected light signal.

[0058] As known, the amount of received photon signals is much larger than the transmission speed and processing speed of the signal stream in the processor, and therefore, the receiving end often receives a large number of photon events to be processed in a very short time. In the subsequent processor processing process, when the photon events received at the previous moment are processed, a large number of photon events at the current moment are likely to be lost, and thus the laser radar or imaging system cannot obtain high-quality imaging and / or ranging information.

[0059] In order to ensure the collection of the static information of the photons, refer to Fig. 1, which is a structural schematic diagram of a receiving end in the prior art according to an embodiment of the present application. As shown in Fig. 1, a memory is usually arranged in the receiving end in the prior art, and each receiving unit of the receiving end can correspond to one or more storage bits in the memory, so that the memory can be used to store the information of the photons received by the corresponding receiving unit, so as to ensure the collection of the static information of the photons. For example, when the receiving array receives the information of the photons, the receiving end inputs the event pulse signal corresponding to the information of the photons into the event sampler after the event pulse signal is combined by the combiner. At this time, since the combiner outputs a large number of event pulse signals of the photons, the event sampler cannot process completely in time, at this time, the receiving end pre-stores the photon events in the memory, and then reads out the corresponding photon events in sequence following the counting of the event sampler, so as to be processed by the back end.

[0060] However, the size of the memory in the scheme is usually determined according to the scale of the receiving unit of the receiving end. For example, if Y storage bits are arranged for each receiving unit to store the corresponding photon events, M*N receiving units need a memory with a size of M*N*Y storage bits at least. This will cause a large area of memory devices on the chip. Moreover, the size of the memory will also limit the processing scale of the photon events. For example, if the memory has only the storage bits corresponding to M*N receiving units, it is difficult to store more photon events corresponding to the receiving units after the memory is full. In addition, after the information of the photon events is stored in the memory, the above-mentioned photon events need to be read out in sequence in the subsequent processing process, and the memory is reset after all the photon events are read out, so as to receive the photon events of the next receiving window. Therefore, the receiving end needs additional resources to drive the memory to write, read or reset, etc., and the processing efficiency of the photon events is greatly prolonged.

[0061] In this regard, this application can efficiently process a large number of photon events without setting up a memory or limiting the scale of photon event processing, thereby reducing hardware area, reducing resource consumption, and improving photon event processing efficiency. For example, embodiments of this application provide a receiving device that can be applied to the receiving end of a lidar or imaging system for imaging or ranging processing of received photon events. The receiving device is connected to a receiving array, which includes multiple receiving units. The receiving device includes a combiner and a speed limiter. The combiner is connected to the receiving array and can receive pulse signals output from the N receiving units, perform merging signal processing on the received N pulse signals, and output a first combined pulse signal. The first combined pulse signal includes K pulse signals from the N pulse signals, where K is a positive integer less than or equal to N. The speed limiter is used to: receive the first combined pulse signal; and perform pulse reduction processing on the first combined pulse signal based on the signal processing rate or a preset time interval, outputting a second combined pulse signal. The second combined pulse signal includes M pulse signals from the K pulse signals, where M is a positive integer less than or equal to K. The specific structure and related description of the receiving device are provided in the following embodiments, which are not described in this application.

[0062] Secondly, based on the technical problems mentioned above, and in order to facilitate understanding of the embodiments of this application, the hardware architecture on which the embodiments of this application are based will be described below.

[0063] The receiving device in this embodiment is connected to a receiving array, and the receiving device includes a combiner and a speed limiter. The receiving array is used to detect photon signals and output pulse signals. It is understood that the receiving array includes N receiving units arranged in an array, i.e., multiple receiving units. These multiple receiving units can detect photon signals in each of multiple time windows and output the corresponding pulse signal for that time window, so that the back-end processing system can perform imaging or ranging processing based on the pulse signals output in multiple time windows. The following related embodiments use the photon signal detected in one time window as an example for illustrative explanation.

[0064] The combiner in the receiving device is connected with the receiving array, wherein the receiving array comprises N receiving units, each of which is configured to detect a photon signal and output a pulse signal, and N is a positive integer greater than or equal to 2. The combiner can be configured to: receive the event pulse signals output by the N receiving units respectively, perform a combined signal processing on the N pulse signals, and output a first combined pulse signal, wherein the first combined pulse signal comprises K pulse signals in the N pulse signals, and K is a positive integer less than or equal to N; and the rate limiter in the receiving device can be configured to: receive the first combined pulse signal sent by the combiner, perform a pulse pruning processing on the first combined pulse signal based on the size of the signal processing rate or a preset time interval, and output a second combined pulse signal; wherein the second combined pulse signal comprises M pulse signals in the K pulse signals, and M is a positive integer less than or equal to K.

[0065] Please refer to FIG. 2, which is a structural schematic diagram of a receiving device provided in the embodiments of the present application.

[0066] As shown in FIG. 2, the receiving device in the embodiments of the present application comprises a combiner and a rate limiter. Compared with setting a memory in the receiving end, the cooperation of the combiner and the rate limiter in the embodiments of the present application can adjust the number of pulse signals output by the receiving device based on the signal processing rate of the back end or a preset time interval. For example, the rate limiter in the receiving device can filter out pulse signals with a relatively short time interval, so that the back end processing system can have sufficient time to process multiple pulse signals in a pipeline manner. Alternatively, the rate limiter in the receiving device can determine a preset time interval corresponding to the signal processing pulse signal requirement of a specific algorithm in the back end processing system, and filter out pulse signals that do not meet the preset time interval requirement. The receiving device in the embodiments of the present application can avoid missing large-scale photon events without setting a large-scale memory device. Moreover, the area of the rate limiter is greatly reduced compared with the area of the memory, which greatly reduces the overall area of the receiving device. In addition, the rate limiter does not need many additional resources to drive write, read or reset operations, which greatly reduces resource consumption. Most importantly, the second combined pulse signal obtained after the pulse pruning processing meets the size requirement of the signal processing rate and the algorithm requirement of the back end processing system, so the rate limiter does not limit the scale of subsequent processing of photon events, which greatly improves the processing efficiency of photon events. The rate limiter can also control the signal flow transmission function and signal-to-noise ratio and other key signal processing indicators by controlling the interval of the second combined pulse signal, so as to match various application scenarios.

[0067] Exemplarily, as shown in FIG. 2, the combiner combines the N pulse signals output by the N receiving units respectively, and outputs a first combined pulse signal. Each receiving unit can output a pulse signal corresponding to a photon event, and the pulse corresponding to the pulse signal can include a single pulse or multiple pulses, which is not limited in the embodiments of the present application.

[0068] The first combined pulse signal can include part or all of the N pulse signals. It can be understood that the first combined pulse signal output by the combiner is a signal processing result of combining multiple pulse signals (i.e., the N pulse signals mentioned above) in the time domain, that is, combining multiple pulse signals sent in parallel into multiple pulse signals sent in series one after another. In order to avoid the conflict of pulse signals sent by different receiving units in the time domain in the signal processing, when the pulse signals sent by any two receiving units do not overlap in the time domain, the combiner can retain all the pulse signals for output; when the pulse signals sent by any two receiving units overlap in the time domain, the combiner can preferentially retain the first received pulse signal in the time domain. Therefore, the first combined pulse signal output by the combiner can include part or all of the N pulse signals, that is, K pulse signals, K being a positive integer less than or equal to N.

[0069] Exemplarily, please refer to FIG. 3A, which is a schematic diagram of combining pulse signals provided by the embodiments of the present application. As shown in FIG. 3A, taking the receiving array including 5 receiving units as an example, the 5 receiving units output 5 pulse signals respectively, and the combiner can combine the 5 pulse signals in the time domain to obtain one combined pulse signal (i.e., the first combined pulse signal), which includes 4 pulse signals (1, 2, 4 and 5).

[0070] In some embodiments, the N pulse signals include a first pulse signal and a second pulse signal; and the time at which the combiner receives the first pulse signal is earlier than the time at which the combiner receives the second pulse signal; and the combiner is specifically configured to: in a case where a time interval between the time at which the combiner receives the first pulse signal and the time at which the combiner receives the second pulse signal is greater than a second preset time length, the K pulse signals include the first pulse signal and the second pulse signal; in a case where the time interval between the time at which the combiner receives the first pulse signal and the time at which the combiner receives the second pulse signal is less than or equal to the second preset time length and greater than a third preset time length, the K pulse signals include the first pulse signal and do not include the second pulse signal; and in a case where the time interval between the time at which the combiner receives the first pulse signal and the time at which the combiner receives the second pulse signal is less than or equal to the third preset time length, the K pulse signals do not include the first pulse signal and the second pulse signal.

[0071] It can be understood that, when the combiner performs the signal processing on the multiple pulse signals, if the combiner receives two non-coincident pulse signals (for example, the time interval is greater than the second preset time length), the combiner can directly perform the signal processing on the two pulse signals. As shown in FIG. 3A, the five receiving units output five pulse signals, and the combiner can perform the signal processing on the five pulse signals to obtain one combined pulse signal (i.e., a first combined pulse signal), which includes four pulse signals (1, 2, 4 and 5) of the five pulse signals (1, 2, 3, 4 and 5). Since the shortest time interval between the pulse signal 2, the pulse signal 4 and the pulse signal 5 is greater than the second preset time length, the combiner can directly perform the signal processing on the pulse signal 2, the pulse signal 4 and the pulse signal 5.

[0072] If two coincident pulse signals are received, but the time interval between the two coincident pulse signals is greater than the dead time of the address processing module or the dead time of other related hardware circuits (for example, the third preset time length), the combiner only retains the first received pulse signal and discards the later received pulse signal. As shown in FIG. 3A, the shortest time interval between the pulse signal 1 and the pulse signal 3 is less than or equal to the second preset time length but greater than or equal to the third preset time length, and thus the first combined pulse signal output by the combiner only includes the pulse signal 1 and does not include the pulse signal 3. That is, according to the priority principle, the third pulse signal (the pulse signal 3) is discarded or filtered out in the first combined pulse signal because the third pulse signal coincides with the first pulse signal (the pulse signal 1) in the time domain.

[0073] If the interval between the two coinciding pulse signals is small, for example, the two pulse signals completely coincide, and the interval between any two pulse signals is less than the third preset time length, the combiner can discard the two coinciding pulse signals to avoid the phenomenon that the address of the pulse signal cannot be resolved. Please refer to FIG. 3B, which is another schematic diagram of merging pulse signals provided by the embodiment of the present application. As shown in FIG. 3B, five receiving units output five pulse signals respectively. The combiner can perform signal processing on the five pulse signals in the time domain. The interval between the pulse signal 1 and the pulse signal 3 is less than or equal to the third preset time length, that is, the interval between the pulse signal 1 and the pulse signal 3 is very small, and the address processing module or other hardware circuit cannot distinguish the two pulse signals. Therefore, the combiner directly discards or filters the pulse signal 1 and the pulse signal 3 in the first combined pulse signal, and only includes the pulse signal 2, the pulse signal 4 and the pulse signal 5.

[0074] It should be noted that the second preset time length mentioned in the embodiment of the present application can be a time length for judging whether there is photon coincidence. The third preset time length can be a time length set in advance based on the dead time of the address processing module or other related hardware circuit mentioned in the following embodiment, and generally, the second preset time length is greater than the third preset time length. In this regard, the embodiment of the present application does not specifically limit the specific size of the second preset time length and the third preset time length.

[0075] In other embodiments, in some application scenarios that do not require to retain the address information corresponding to the pulse signal, the combiner can choose to retain the coinciding pulse signal. For example, in the case where the time interval between the time of receiving the first pulse signal and the time of receiving the second pulse signal is less than or equal to the third preset time length, the above-mentioned K pulse signals include the above-mentioned first pulse signal and the above-mentioned second pulse signal. In this regard, the embodiment of the present application does not make specific limitation.

[0076] After the combiner combines the multiple pulse signals to obtain a first combined pulse signal, the first combined pulse signal includes most of the photon events received by the receiving array within a time window, i.e., the amount of received photon signals is much larger than the transmission speed and processing speed of the signal stream in the processor, so the back-end processing system cannot process all the pulse signals (i.e., the first combined pulse signal) in time within the time window. In order to avoid the loss of a large amount of photon information, the speed limiter in the embodiments of the present application can perform pulse pruning processing on part of the pulse signals in the first combined pulse signal based on the size of the signal processing rate of the back-end processing system or a preset time interval, so that the pruned pulse signals (second combined pulse signals) can be processed completely by the back-end processing system (such as the event sampler shown in FIG. 2) in time. For example, the speed limiter can receive the first combined pulse signal output by the combiner, perform pulse pruning processing on the first combined pulse signal based on the size of the signal processing rate, and output the second combined pulse signal; wherein the second combined pulse signal includes M pulse signals in the K pulse signals. For example, if the processing time of each pulse signal of the back-end processing system is at least X nanoseconds, the speed limiter can prune the pulse signals that are too close in time (for example, the time interval is less than X nanoseconds) in the first combined pulse signal, to ensure that each pulse signal in the output second combined pulse signal can be processed by the back-end processing system in time.

[0077] In some embodiments, the speed limiter is specifically configured to: perform pulse pruning processing on the first combined pulse signal based on the driving of the K pulse signals in the first combined pulse signal and the signal processing period, and output the second combined pulse signal; and the time interval between any two adjacent pulse signals in the M pulse signals in the second combined pulse signal is greater than or equal to a first preset time length, and the first preset time length is determined by the signal processing rate.

[0078] Please refer to FIG. 4, which is a schematic diagram of pruned pulse signals provided by the embodiments of the present application. As shown in FIG. 4, the first combined pulse signal output by the combiner includes pulse signal 1, pulse signal 2, pulse signal 4, and pulse signal 5. Since the time interval between pulse signal 4 and pulse signal 5 is too short, i.e., the highest processing speed of the processor in the back-end processing system or the highest sampling speed of the event sampler is not enough to process pulse signal 4 completely when pulse signal 5 is received, the speed limiter can filter out pulse signal 5 to ensure efficient and smooth subsequent processing. For example, as shown in FIG. 4, the second combined pulse signal includes pulse signal 1, pulse signal 2, and pulse signal 4, and pulse signal 5 is deleted. This way of not needing to store the unprocessed pulse signals in the memory can reduce the size of the hardware while greatly improving the processing efficiency of the entire process.

[0079] It can be understood that the signal processing rate mentioned in the above embodiments can be the highest processing rate of the event sampler or event timer for the pulse signal in the subsequent processing process, or the fastest reading rate of the histogram memory, and the embodiments of the present application do not make specific limitations. For example, the event sampler shown in FIG. 2 can be used for sampling processing of the received second combined pulse signal, and the highest processing rate of the event sampler can be simply understood as the signal processing rate of the back-end processing system.

[0080] It should be noted that the preset time interval can be the pulse signal time interval required by the algorithm in the back-end processing system. For example, in different application scenarios, different algorithms have different specific requirements for photon pulses (for example: signal-to-noise ratio, relationship between light wavelength and photon pulse interval, etc.), that is, different algorithms have different time interval requirements for adjacent two pulse signals in the second combined pulse signal. The rate limiter can also perform pulse reduction processing on the first combined pulse signal based on different preset time intervals to output the second combined pulse signal. For example, in two different application scenarios of laser radar ranging and photon imaging, when the maximum signal processing rate of the back-end processing system is consistent, the rate limiter in the different scenarios can perform pulse reduction processing on the first combined pulse signal based on different preset time intervals to output different second combined pulse signals. The size of the preset time interval can be specifically controlled by the back-end processing system, and the embodiments of the present application do not make specific limitations.

[0081] It can also be understood that the pulse signals in the first combined pulse signal can drive the rate limiter to perform reduction processing on the first combined pulse signal, wherein the rate limiter does not perform reduction processing on the first combined pulse signal based on the number of pulse signals, but performs reduction processing based on the length of the time interval between the pulse signals in the time domain. The time interval between any adjacent two pulse signals in the obtained second combined pulse signal is greater than or equal to the first preset time length.

[0082] For example, as shown in FIG. 4, the time interval between any adjacent two pulse signals in the pulse signal 1, the pulse signal 2 and the pulse signal 4 is greater than or equal to the first preset time length, the time interval between the pulse signal 4 and the pulse signal 5 is less than the first preset time length, therefore, the second combined pulse signal includes the pulse signal 1, the pulse signal 2 and the pulse signal 4, and the pulse signal 5 is deleted.

[0083] Correspondingly, the first preset time length can be understood as the minimum time interval between any two adjacent pulse signals in the second combined pulse signal. The first preset time length can be pre-set or adaptively adjusted according to a back-end signal processing rate or a preset time interval. The embodiments of the present application do not make specific limitations in this regard. For example, when the signal processing rate is slow, the size of the first preset time length is increased, and when the signal processing rate is fast, the size of the first preset time length is decreased. The embodiments of the present application do not make specific limitations in this regard.

[0084] In addition, it should be noted that the first preset time length needs to be greater than the circuit time delay of the speed limiter, otherwise the speed limiter cannot correctly output the second combined pulse signal with a time interval less than the circuit time delay.

[0085] It can also be understood that, compared with the global clock used by the memory, the speed limiter in the embodiments of the present application is an asynchronous speed limiter that does not need to be driven by a global clock. The pulse pruning processing of the first combined pulse signal can be realized based on the driving of the pulse signal in the first combined pulse signal, which greatly reduces the cost of the device.

[0086] It should be noted that the asynchronous combiner and the asynchronous speed limiter are used in the embodiments of the present application, that is, the combined signal processing or pruning processing of the pulse signal is asynchronous processing, which does not need a synchronous global clock signal. For example, when K pulse signals in the first combined pulse signal are input, the speed limiter performs pulse pruning processing on the first combined pulse signal. When the first combined pulse signal is not received, the speed limiter cannot work normally due to the absence of a driving signal.

[0087] In some embodiments, the speed limiter comprises a latch, an integrator and a comparator. The input end of the latch and the driving end of the comparator are connected with the output end of the combiner, the reset end of the latch is connected with the output end of the comparator, the output end of the latch is connected with the first input end of the comparator through the integrator, and the second input end of the comparator is connected with a reference voltage. The latch is configured to receive the K pulse signals in the first combined pulse signal and output the M pulse signals in the second combined pulse signal based on the reset signal fed back by the comparator. The integrator is configured to receive the M pulse signals output by the latch, perform integration processing on the M pulse signals and output a corresponding integration voltage. The comparator is configured to compare the integration voltage output by the integration circuit with the reference voltage when the K pulse signals in the first combined pulse signal are received, and output the reset signal to the latch based on the comparison result.

[0088] Please refer to FIG. 5 and FIG. 6, FIG. 5 is a structural schematic diagram of another receiving device provided by the embodiment of the present application, and FIG. 6 is a working principle schematic diagram of a speed limiter provided by the embodiment of the present application. As shown in FIG. 5, the speed limiter comprises a latch, an integrator and a comparator. The latch comprises an input end S, a reset end R and an output end Q. The input end S of the latch is connected with the output end of the combiner and the driving end of the comparator. The reset end R of the latch is connected with the output end of the comparator. The output end Q of the latch is connected with the first input end of the comparator through the integrator. For example, the input end of the integrator is connected with the output end Q of the latch, and the output end is connected with the first input end of the comparator. In addition, the second input end of the comparator is connected with a reference voltage VREF.

[0089] It can be understood that, for the latch, only when the valid reset signal is input to the reset end, the state of the input end of the latch is saved to the output end (i.e., the output at this time changes with the change of the input), and when there is no valid reset signal input to the reset end, the latch will be in the latching state until the next valid reset signal is input to the reset end. For example, as shown in FIG. 6, taking the low-level valid reset signal as an example, i.e., when S=1 and R=0, only the pulse signal 1 and the pulse signal 3 in the first combined pulse signal input to the input end of the latch can pass through, and when R=1, the state of the latch is locked, and the output at this time will not change with the change of the input, so the pulse signal 2 of the first combined pulse signal input to the latch cannot pass through. Therefore, the latch of the receiving device can control the output of the M pulse signals (i.e., the second combined pulse signal) in the K pulse signals (i.e., the first combined pulse signal) based on the reset signal fed back by the comparator, i.e., M is a positive integer less than or equal to K.

[0090] For the comparator, the comparator in the rate limiter is a dynamic comparator, which can maintain the output high level without the driving of the pulse signal, that is, the reset end maintains R = 1 at this time. When the comparator receives the driving of the K pulse signals in the first combined pulse signal, for example, when the comparator receives the rising edge of the pulse signal, the comparator starts to compare the integrated voltage output by the integrator and the reference voltage, and outputs the reset signal to the latch based on the comparison result, for example, when the integrated voltage is greater than the reference voltage, the low level is pulled down, so that R = 0, at this time the latch outputs the corresponding pulse signal. This follows the driving of the pulse signal and the integration processing of the integrator on the pulse signal under the driving of the pulse signal. The comparator can obtain different comparison results in the process of integrating the integrated voltage output by the integrator, and can output different reset signals in different time periods. Correspondingly, the rate limiter can control the time of maintaining the high level or the low level in the reset signal (as shown in the above FIG. 6), and finally control the time interval of adjacent pulse signals in the output second combined pulse signal. This pulse pruning method is simple and efficient, and does not need the driving of the global clock, which is helpful to further reduce the device volume of the receiving device and improve the processing efficiency of the photon event.

[0091] For the integrator, the integrator can receive the M pulse signals output by the latch, integrate the M pulse signals and output the corresponding integrated voltage. It should be noted that the integrated voltage of the integrator will be quickly reset to the power supply voltage (VDD) without the driving of the pulse signal or after the integration processing of the previous pulse signal is completed.

[0092] Please refer to FIG. 7 and FIG. 8, which are a group of second combined pulse signals corresponding to different integration speeds provided by the embodiments of the present application.

[0093] As shown in FIG. 7, without input of the pulse signal, the integrated voltage Vramp of the integrator maintains or approaches the power supply voltage VDD, at this time the reset signal Vout output by the comparator maintains the high level state.

[0094] When the pulse signal 1 in the first combined pulse signal inputs the latch and drives the comparator, the integrator has not received the input of the pulse signal 1 at this time, and the corresponding integrated voltage Vramp still maintains or approaches the power supply voltage VDD; the driving end of the comparator directly receives the driving of the pulse signal 1, and then can compare the integrated voltage Vramp and the reference voltage VREF, at this time, since the integrated voltage Vramp is greater than the reference voltage VREF, the comparator pulls down the output reset signal Vout, that is, the reset signal Vout changes from high level to low level state; after receiving the pulled-down reset signal Vout, the latch can output the first pulse signal in the second combined pulse signal, that is, the pulse signal 1.

[0095] In addition, after receiving the falling edge of the first pulse signal, the comparator pulls up the reset signal Vout, i.e., the reset signal Vout changes from low level to high level.

[0096] At this time, since the latch also outputs the pulse signal 1 to the integrator, the pulse signal 1 can be input to the integrator to start the integration process, i.e., the integration voltage Vramp output by the integrator starts to rise. During the integration process of the integrator, if the comparator receives the rising edge of the second pulse signal (i.e., pulse signal 2) in the first combined pulse signal again, the comparison between the integration voltage Vramp and the reference voltage VREF can be started again.

[0097] As shown in FIG. 7, the comparator receives the rising edge of the second pulse signal (i.e., pulse signal 2) in the first combined pulse signal again, and starts to compare the integration voltage Vramp and the reference voltage VREF. Since the integration speed of the integrator is relatively fast, the integration voltage Vramp is greater than the reference voltage VREF at this time, the comparator pulls down the output reset signal Vout again, i.e., the reset signal Vout changes from high level to low level. After receiving the reset signal Vout pulled down again, the latch outputs the second pulse signal in the second combined pulse signal, i.e., the pulse signal 2. After completing the integration process for the pulse signal 1, the integrator will perform the integration process for the pulse signal 2 again.

[0098] As shown in FIG. 8, the comparator receives the rising edge of the second pulse signal (i.e., pulse signal 2) in the first combined pulse signal again, and starts to compare the integration voltage Vramp and the reference voltage VREF. Since the integration speed of the integrator is relatively slow, the integration voltage Vramp is less than the reference voltage VREF at this time, the comparator keeps the reset signal Vout at high level, i.e., the reset signal Vout maintains high level, and the latch cannot output the pulse signal 2. The integrator will continue to complete the integration process for the pulse signal 1.

[0099] After receiving the falling edge of the pulse signal 2, the comparator keeps the reset signal Vout at high level, and starts to compare the integration voltage Vramp and the reference voltage VREF after receiving the rising edge of the pulse signal 3, i.e., the integration voltage Vramp is greater than the reference voltage VREF at this time, the comparator can pull down the output reset signal Vout, and the latch receives the reset signal Vout pulled down to output the second pulse signal in the second combined pulse signal, i.e., the pulse signal 3.

[0100] As can be seen from the comparison diagrams of the second combined pulse signal shown in FIG. 7 and FIG. 8, the integrator can control the time interval of the output of the second combined pulse signal according to the different integration speed of the pulse signal. When the integration speed is fast enough, i.e. the integration voltage Vramp output by the integrator can be greater than the reference voltage VREF in a short enough time, such as before the rising edge of the next pulse signal (for example, within a time period less than t0), the latch can receive the reset signal to output the next pulse signal. As shown in FIG. 7, the second combined pulse signal includes pulse signal 1 and pulse signal 2. Correspondingly, when the integration speed is slow, the integrator output integration voltage Vramp cannot be greater than the reference voltage VREF before the rising edge of the next pulse signal, and the latch cannot output the next pulse signal. As shown in FIG. 8, the second combined pulse signal does not include pulse signal 2.

[0101] It can be understood that the first preset time length mentioned in the above embodiment can be understood as the time length when the size of the integration voltage reaches or exceeds the size of the reference voltage after the integrator starts to integrate. When the time interval of the adjacent two pulse signals in the first combined pulse signal is less than the first preset time length, the second combined pulse signal will perform the pruning processing on the latter one of the two pulse signals.

[0102] In some embodiments, the integrator includes a current source, a first switch tube, a second switch tube and a capacitor; one end of the current source is connected to a power supply voltage, one end of the current source is connected to one end of the first switch tube, the other end of the first switch tube and one end of the second switch tube are connected to one end of the capacitor, the other end of the second switch tube and the other end of the capacitor are grounded; the control end of the first switch tube and the control end of the second switch tube are used as the input end of the integrator and are connected to the output of the latch for receiving the second combined pulse signal.

[0103] Please refer to FIG. 9, which is a circuit structure diagram of a speed limiter according to an embodiment of the present application. As shown in FIG. 9, the speed limiter comprises a latch, an integrator and a comparator. The integrator comprises a current source, a first switch tube T1, a second switch tube T2 and a capacitor C. One end of the current source is connected to a power supply voltage VDD, one end of the current source is connected to one end of the first switch tube T1, the other end of the first switch tube T1 and one end of the second switch tube T2 are connected to one end of the capacitor C, the other end of the second switch tube T2 and the other end of the capacitor C are connected to ground. The control ends of the first switch tube T1 and the second switch tube T2 are connected to the input end of the integrator and the output of the latch, and are used to receive the second combined pulse signal. It can be understood that the pulse signal can control the first switch tube T1 and the second switch tube T2 to be turned on to integrate the pulse signal. In this regard, the present application provides a simple and efficient circuit structure of the integrator. The current source and the capacitor value in the integrator can determine the integration speed of the integrator. Therefore, the integration speed of the integrator can be controlled by adjusting the size of the current source and the capacitor value in the integrator, so as to adapt to the subsequent signal processing rate of the second combined pulse signal.

[0104] In some embodiments, the smaller the capacitance value of the capacitor, the shorter the first preset time length; the greater the current value of the current source, the shorter the first preset time length; the smaller the reference voltage, the shorter the first preset time length.

[0105] It can be understood that according to the circuit structure of the integrator and the above-mentioned FIG. 7 and FIG. 8, the smaller the capacitance value of the capacitor, the faster the integration speed, and the integration voltage can reach the size of the reference voltage faster, and the shorter the first preset time length. When the current value of the current source is greater, the faster the integration speed, and the integration voltage can reach the size of the reference voltage faster, and the shorter the first preset time length. Therefore, the present application can control the integration speed by adjusting the size of the capacitor and the current source of the integrator, and then control the length of the first preset time length, so as to control the pulse rate of the second combined pulse signal. For example, when the signal processing rate is slow, the minimum time interval (i.e. the first preset time length) between adjacent two pulse signals can be extended, and in this case, the capacitor value can be increased, and the current source can be reduced, etc.

[0106] It can also be understood that when the preset reference voltage is constant, the faster the integration speed of the integrator to the pulse signal, the shorter the first preset time length, and the shorter the effective waiting time length corresponding to the pulse signal. Correspondingly, when the integration speed of the integrator to the pulse signal is constant, the smaller the reference voltage, the shorter the first preset time length, and the shorter the effective waiting time length corresponding to the pulse signal.

[0107] Please refer to FIG. 10, which is a comparison diagram of second combined pulse signals corresponding to different reference voltages according to an embodiment of the present application. As shown in FIG. 10, when the integration processing speed of the integrator is the same, the effective waiting time corresponding to the pulse signal can be controlled by changing the reference voltage. When the integrator outputs the integrated voltage, the comparator compares the integrated voltage with the reference voltage. The smaller the reference voltage VREF is, the earlier the reset signal Vout2 outputs a low signal, and the shorter the first preset time is. The larger the reference voltage VREF is, the later the reset signal Vout1 outputs a low signal, and the longer the first preset time is. For example, as shown in FIG. 10, because the reference voltage VREF1 is larger than the reference voltage VREF2, the time interval corresponding to the second combined pulse signal 1 is larger than the time interval corresponding to the second combined pulse signal 2. The second combined pulse signal 1 only includes the pulse signal 1, and the second combined pulse signal 2 includes the pulse signal 1 and the pulse signal 2.

[0108] In some embodiments, the apparatus further includes an address processing module, which is configured to determine the address information of each pulse signal in the second combined pulse signal corresponding to the receiving unit in the receiving array.

[0109] Please refer to FIG. 11, which is a structural diagram of another receiving apparatus according to an embodiment of the present application. As shown in FIG. 11, the receiving apparatus further includes an address processing module configured to determine the address information of each pulse signal in the second combined pulse signal, so as to perform imaging or ranging processing subsequently. It can be understood that when the second combined pulse signal is processed for imaging or ranging, the address information of each pulse signal in the second combined pulse signal corresponding to the receiving unit in the receiving array needs to be determined. The address processing module can determine the address information of the remaining pulse signal when the multiple pulse signals are processed for combined signal processing or pulse pruning, so as to determine the address information of each pulse signal in the second combined pulse signal when the second combined pulse signal is output.

[0110] In some embodiments, the address processing module includes an address encoder and an address decoder. The address encoder is configured to output the encoded address information of each pulse signal in the first combined pulse signal to the address decoder when the combiner outputs the first combined pulse signal. The address decoder is configured to output the decoded address information of each pulse signal in the second combined pulse signal based on the encoded address information of each pulse signal in the first combined pulse signal when the rate limiter outputs the second combined pulse signal. The decoded address information includes the address information of each pulse signal in the second combined pulse signal corresponding to the receiving unit in the receiving array.

[0111] It can be understood that the address information of each pulse signal is input to the processing system at the rear end for imaging or ranging processing in synchronization with the pulse signal. Correspondingly, the address processing module includes an address encoder and an address decoder to encode and decode the address information, and also to avoid errors or omissions of the address information of the pulse signal. For example, the address encoder can output the encoded address information corresponding to each pulse signal in the first combined pulse signal to the address decoder when the combiner outputs the first combined pulse signal. Illustratively, the address decoder can decode the address coding information of the M pulse signals based on the encoded address information corresponding to each pulse signal in the first combined pulse signal to obtain the address information of the M pulse signals in the receiving array of the receiving unit corresponding to the M pulse signals when the limiter outputs the second combined pulse signal, i.e., after determining the M pulse signals output by the second combined pulse signal. It can be understood that the encoding and decoding methods of the address information are not specifically limited in the embodiments of the present application.

[0112] In some embodiments, each of the receiving units detects the photon signal through one or more avalanche diodes and outputs the pulse signal; the receiving device further includes an avalanche quenching and reset module; the avalanche reset module is configured to quench and reset one or more avalanche diodes of the corresponding receiving unit after the receiving unit outputs the pulse signal.

[0113] The receiving device can be applied to the field of single-photon imaging or ranging, for example, the photon events can be collected by using avalanche diodes, which can greatly improve the quality of imaging or ranging. In order to enable the normal use of the avalanche diode in each time window, as shown in FIG. 11, the receiving device further includes an avalanche reset module, which can quench and reset one or more avalanche diodes of the corresponding receiving unit after the receiving unit outputs the pulse signal, so as to detect the photon signal again and output the corresponding pulse signal after the receiving unit outputs the pulse signal.

[0114] In the prior art, in order to avoid missing large-scale photon events, a memory is usually added at the receiving end to store photon events that have not been completely processed. However, this will cause a large area of memory device on the chip or receiving end, and the size of the memory will also limit the scale of subsequent processing of photon events. In addition, the chip or receiving end also needs additional resources to drive the memory to write, read or reset, etc. which wastes resources. In this regard, the embodiments of the present application can efficiently process a large number of photon events without setting a memory, avoid missing large-scale photon events, and thus reduce resource consumption while reducing hardware area and improve the processing efficiency of photon events. For example, the embodiments of the present application provide a receiving device that can be applied to the receiving end of a laser radar or imaging system. The receiving device is connected with a receiving array that outputs a plurality of pulse signals. The receiving device includes a combiner and a rate limiter. The combiner is connected with the receiving array and can be used for signal processing of merging N pulse signals output by the receiving array to output a first combined pulse signal. The first combined pulse signal includes K pulse signals in the N pulse signals. The combiner combines the plurality of pulse signals from parallel transmission into serial transmission, which is conducive to the orderly processing of the back-end processing system. Compared with the prior art scheme of directly imaging or ranging processing the first combined pulse signal, the first combined pulse signal output after the combiner combines in the embodiments of the present application still needs to be processed by the pulse pruning of the rate limiter, and then the second combined pulse signal obtained after the pulse pruning is processed is imaged or ranged. Since the rate limiter performs pulse pruning on the first combined pulse signal based on the size of the signal processing rate or the preset time interval, the number and time interval of the pulse signals in the output second combined pulse signal can meet the demand of the subsequent signal processing rate or the preset time interval. Therefore, in the embodiments of the present application, large-scale memory devices can be avoided without missing large-scale photon events. Moreover, the area of the rate limiter is greatly reduced compared with the area of the memory, which greatly reduces the overall area of the receiving device. Moreover, the rate limiter does not need many additional resources to drive the write, read or reset operations, which greatly reduces the resource consumption. Most importantly, since the second combined pulse signal obtained after the pulse pruning meets the demand of the size of the signal processing rate, the rate limiter does not limit the scale of subsequent processing of photon events, which greatly improves the processing efficiency of photon events.

[0115] In addition, based on the hardware structure of the receiving device mentioned above, the technical problems proposed in the present application are further analyzed and solved by combining the receiving method provided in the present application.

[0116] Please refer to FIG. 12, which is a flowchart of a receiving method provided by the embodiments of the present application.

[0117] The receiving method can be applied to the receiving device involved in the embodiments shown in FIGS. 2-11, and the receiving device is connected with a receiving array, wherein the receiving array includes N receiving units, each of which is configured to receive an optical signal and output a pulse signal, and N is a positive integer greater than or equal to 2; and the receiving device includes a combiner and a rate limiter. The specific related description of each step of the method is as follows:

[0118] Step S101: receiving, by the combiner, the pulse signals output by the N receiving units respectively, and performing combined signal processing on the received N pulse signals to obtain a first combined pulse signal.

[0119] Specifically, the receiving device can receive, by the combiner, the pulse signals output by the N receiving units respectively, and perform combined signal processing on the received N pulse signals to obtain a first combined pulse signal. The first combined pulse signal includes K pulse signals in the N pulse signals, and K is a positive integer less than or equal to N.

[0120] In some embodiments, the N pulse signals include a first pulse signal and a second pulse signal; the combiner receives the first pulse signal at an earlier time than the second pulse signal; in the case where the time interval between the time of receiving the first pulse signal and the time of receiving the second pulse signal is greater than a second preset time length, the K pulse signals include the first pulse signal and the second pulse signal; in the case where the time interval between the time of receiving the first pulse signal and the time of receiving the second pulse signal is less than or equal to the second preset time length and greater than a third preset time length, the K pulse signals include the first pulse signal and do not include the second pulse signal; and in the case where the time interval between the time of receiving the first pulse signal and the time of receiving the second pulse signal is less than or equal to the third preset time length, the K pulse signals do not include the first pulse signal and the second pulse signal.

[0121] Step S102: performing, by the rate limiter, pulse pruning processing on the first combined pulse signal based on the size of the signal processing rate or a preset time interval to obtain a second combined pulse signal.

[0122] Specifically, the receiving device can perform, by the rate limiter, pulse pruning processing on the first combined pulse signal based on the size of the signal processing rate or a preset time interval to obtain a second combined pulse signal. The second combined pulse signal includes M pulse signals in the K pulse signals, and M is a positive integer less than or equal to K.

[0123] In some embodiments, the pulse deletion processing of the first combined pulse signal based on the signal processing rate or the preset time interval by the speed limiter to obtain the second combined pulse signal comprises: under the driving of the K pulse signals in the first combined pulse signal, the pulse deletion processing of the first combined pulse signal based on the signal processing rate or the preset time interval is performed to output the second combined pulse signal; the time interval between any two adjacent pulse signals in the M pulse signals in the second combined pulse signal is greater than or equal to a first preset time length, and the first preset time length is determined by the signal processing rate.

[0124] In some embodiments, the speed limiter comprises a latch, an integrator and a comparator; the input end of the latch and the driving end of the comparator are connected with the output end of the combiner, the reset end of the latch is connected with the output end of the comparator, the output end of the latch is connected with the first input end of the comparator through the integrator, and the second input end of the comparator is connected with a reference voltage; the pulse deletion processing of the first combined pulse signal based on the signal processing rate or the preset time interval by the speed limiter to obtain the second combined pulse signal comprises: the K pulse signals in the first combined pulse signal are received by the latch, and the M pulse signals in the second combined pulse signal are output based on the reset signal fed back by the comparator; the method further comprises: the M pulse signals output by the latch are received by the integrator, the M pulse signals are integrated and processed to output corresponding integral voltages; when the K pulse signals in the first combined pulse are received, the integral voltages output by the integral circuit are compared with the reference voltage by the comparator, and the reset signal is output to the latch based on the comparison result.

[0125] In some embodiments, the integrator comprises a current source, a first switch tube, a second switch tube and a capacitor; one end of the current source is connected with a power supply voltage, one end of the current source is connected with one end of the first switch tube, the other end of the first switch tube and one end of the second switch tube are connected with one end of the capacitor, and the other end of the second switch tube is connected with the other end of the capacitor; the control end of the first switch tube and the control end of the second switch tube are used as the input end of the integrator and are connected with the output of the latch for receiving the second combined pulse signal.

[0126] In some embodiments, the smaller the capacitance value of the capacitor in the integrator is, the shorter the first preset time length is; the greater the current value of the current source in the integrator is, the shorter the first preset time length is; the smaller the reference voltage in the comparator is, the shorter the first preset time length is.

[0127] In some embodiments, the apparatus further comprises an address processing module; and the method further comprises: determining, by the address processing module, address information of each pulse signal in the second combined pulse signal corresponding to a receiving unit in the receiving array.

[0128] In some embodiments, the address processing module comprises an address encoder and an address decoder; and the determining, by the address processing module, address information of each pulse signal in the second combined pulse signal corresponding to a receiving unit in the receiving array comprises: in a case that the combiner outputs the first combined pulse signal, outputting, by the address encoder, encoded address information corresponding to each pulse signal in the first combined pulse signal to the address decoder; and in a case that the rate limiter outputs the second combined pulse signal based on the encoded address information corresponding to each pulse signal in the first combined pulse signal, outputting, by the address decoder, decoded address information corresponding to each pulse signal in the second combined pulse signal, the decoded address information comprising the address information of each pulse signal in the second combined pulse signal corresponding to a receiving unit in the receiving array.

[0129] In some embodiments, each receiving unit detects a photon signal by one or more avalanche diodes and outputs the pulse signal; the receiving apparatus further comprises an avalanche quenching and resetting module; and the method further comprises: quenching and resetting, by the avalanche resetting module, one or more avalanche diodes of a corresponding receiving unit after the receiving unit outputs the pulse signal.

[0130] Embodiments of the present application also provide a laser radar, which comprises a receiving array and a receiving device as described in the related embodiments of FIGS. 2-11, the receiving device being connected to the receiving array, the receiving array comprising a plurality of receiving units, each receiving unit being configured to detect a photon signal and output a pulse signal.

[0131] Embodiments of the present application also provide an imaging system, which comprises a receiving array and a receiving device as described in the related embodiments of FIGS. 2-11. The receiving device is connected to the receiving array, the receiving array comprising a plurality of receiving units, each receiving unit being configured to detect a photon signal and output a pulse signal.

[0132] It should be understood that the receiving method, laser radar or imaging system provided by the embodiments of the present application are consistent with the receiving device as described in the related embodiments of FIGS. 2-11, and the specific content and beneficial effects thereof can be referred to the receiving device as described in the related embodiments of FIGS. 2-11, which will not be described here in detail.

[0133] In the above embodiments, the description of each embodiment is focused on, and the part not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0134] It should be noted that, for the foregoing method embodiments, in order to simply describe, they are all described as a series of action combinations, but those skilled in the art should know that the present application is not limited to the order of the actions described, because according to the present application, some steps can be performed in other order or at the same time. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0135] In several embodiments provided by the present application, it should be understood that the disclosed device can be implemented by other means. For example, the device embodiments described above are only illustrative, for example, the division of the above units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical or other forms.

[0136] The units described as separate components above can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. According to actual needs, part or all of the units can be selected to achieve the purpose of the embodiment scheme.

[0137] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of software functional unit.

[0138] The integrated unit described above, if realized in the form of a software function unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the present application essentially or say the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server or a network device, etc., specifically a processor in the computer device) to execute all or part of the steps of the above-mentioned method of each embodiment of the present application. Among them, the aforementioned storage medium can include: a U disk, a mobile hard disk, a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, abbreviated as: ROM) or a random access memory (Random Access Memory, abbreviated as: RAM) and various program code storage media.

[0139] The above-described embodiments are only used to illustrate the technical solutions of the present application, not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A receiving device, characterized by The device is connected with a receiving array, wherein the receiving array comprises N receiving units, each of which is used for detecting a photon signal and outputting a pulse signal, and N is a positive integer greater than or equal to 2; the receiving device comprises a combiner and a speed limiter; The combiner is connected with the receiving array and is used for receiving the pulse signals output by the N receiving units respectively, performing combined signal processing on the received N pulse signals, and outputting a first combined pulse signal, wherein the first combined pulse signal comprises K pulse signals in the N pulse signals, and K is a positive integer less than or equal to N; The speed limiter is used for receiving the first combined pulse signal, performing pulse pruning processing on the first combined pulse signal based on the size of a signal processing rate or a preset time interval, and outputting a second combined pulse signal; wherein the second combined pulse signal comprises M pulse signals in the K pulse signals, and M is a positive integer less than or equal to K.

2. The apparatus of claim 1, wherein The speed limiter is specifically used for performing pulse pruning processing on the first combined pulse signal based on the size of the signal processing rate or the preset time interval under the driving of the K pulse signals in the first combined pulse signal, and outputting the second combined pulse signal. The time interval between any two adjacent pulse signals in the M pulse signals in the second combined pulse signal is greater than or equal to a first preset time length, and the first preset time length is determined by the signal processing rate or the preset time interval.

3. The apparatus of claim 2, wherein, The speed limiter comprises a latch, an integrator and a comparator; The input end of the latch and the driving end of the comparator are connected with the output end of the combiner, the reset end of the latch is connected with the output end of the comparator, the output end of the latch is connected with the first input end of the comparator through the integrator, and the second input end of the comparator is connected with a reference voltage; The latch is used for receiving the K pulse signals in the first combined pulse signal and outputting the M pulse signals in the second combined pulse signal based on the reset signal fed back by the comparator. The integrator is used for receiving the M pulse signals output by the latch, performing integration processing on the M pulse signals and outputting a corresponding integration voltage. The comparator is used for comparing the integration voltage output by the integration circuit and the reference voltage when receiving the driving of the K pulse signals in the first combined pulse, and outputting the reset signal to the latch based on the comparison result.

4. The apparatus of claim 3, wherein The integrator comprises a current source, a first switch tube, a second switch tube and a capacitor; One end of the current source is connected with a power supply voltage, one end of the current source is connected with one end of the first switch tube, the other end of the first switch tube and one end of the second switch tube are connected with one end of the capacitor, and the other end of the second switch tube is connected with the other end of the capacitor. The control end of the first switch tube and the control end of the second switch tube serve as the input end of the integrator and are connected with the output of the latch, and are used for receiving the second combined pulse signal.

5. The apparatus of claim 4, wherein The smaller the capacitance value of the capacitor in the integrator, the shorter the first preset time length; the greater the current value of the current source in the integrator, the shorter the first preset time length; the smaller the reference voltage in the comparator, the shorter the first preset time length.

6. The apparatus of any one of claims 1-5, wherein, The N pulse signals include a first pulse signal and a second pulse signal; and the time at which the combiner receives the first pulse signal is earlier than the time at which the combiner receives the second pulse signal. The combiner is specifically configured to: in a case where a time interval between the time at which the first pulse signal is received and the time at which the second pulse signal is received is greater than a second preset time length, the K pulse signals include the first pulse signal and the second pulse signal. In a case where the time interval between the time at which the first pulse signal is received and the time at which the second pulse signal is received is less than or equal to the second preset time length and greater than a third preset time length, the K pulse signals include the first pulse signal and do not include the second pulse signal. In a case where the time interval between the time at which the first pulse signal is received and the time at which the second pulse signal is received is less than or equal to the third preset time length, the K pulse signals do not include the first pulse signal and the second pulse signal.

7. The device of any one of claims 1-6, wherein, The device further includes an address processing module; the address processing module is configured to determine address information of each pulse signal in the second combined pulse signal corresponding to a receiving unit in the receiving array.

8. The apparatus of claim 7, wherein, The address processing module includes an address encoder and an address decoder. The address encoder is configured to, in a case where the combiner outputs the first combined pulse signal, output, to the address decoder, encoded address information corresponding to each pulse signal in the first combined pulse signal. The address decoder is configured to, in a case where the rate limiter outputs the second combined pulse signal based on the encoded address information corresponding to each pulse signal in the first combined pulse signal, output, to the rate limiter, decoded address information corresponding to each pulse signal in the second combined pulse signal, the decoded address information including address information of each pulse signal in the second combined pulse signal corresponding to a receiving unit in the receiving array.

9. The apparatus of any of claims 1-8, wherein, Each receiving unit detects a photon signal through one or more avalanche diodes and outputs the pulse signal; the receiving device further includes an avalanche quenching and resetting module. The avalanche resetting module is configured to quench and reset one or more avalanche diodes of a corresponding receiving unit after the receiving unit outputs the pulse signal.

10. A lidar, comprising: The laser radar includes a receiving array and the receiving device according to any one of claims 1-9, the receiving device being connected to the receiving array, the receiving array including a plurality of receiving units, each receiving unit being configured to detect a photon signal and output a pulse signal.

11. An imaging system characterized by, The imaging system includes a receiving array and the receiving device according to any one of claims 1-9, the receiving device being connected to the receiving array, the receiving array including a plurality of receiving units, each receiving unit being configured to detect a photon signal and output a pulse signal.

12. A receiving method, characterized by, The application is applied to a receiving device connected with a receiving array, wherein the receiving array comprises N receiving units, each of which is used for receiving an optical signal and outputting a pulse signal, and N is a positive integer greater than or equal to 2; the receiving device comprises a combiner and a rate limiter, and the method comprises the following steps: receiving, by the combiner, the pulse signals output by the N receiving units respectively, performing combined signal processing on the received N pulse signals, and obtaining a first combined pulse signal, wherein the first combined pulse signal comprises K pulse signals in the N pulse signals, and K is a positive integer less than or equal to N; performing, by the rate limiter, pulse pruning processing on the first combined pulse signal based on the size of the signal processing rate or a preset time interval, and obtaining a second combined pulse signal; wherein the second combined pulse signal comprises M pulse signals in the K pulse signals, and M is a positive integer less than or equal to K.

Images