Capacitor structure, preparation method therefor, and radio frequency device

Abstract

A capacitor structure, comprising a substrate, a first electrode, a dielectric layer, and a second electrode. The first electrode, the dielectric layer and the second electrode are sequentially stacked on one side of the substrate, and orthographic projections of the first electrode, the dielectric layer, and the second electrode onto the substrate at least partially overlap. The second electrode comprises a first sub-layer, a second sub-layer and a third sub-layer, the first sub-layer, the second sub-layer and the third sub-layer being stacked in sequence away from the substrate, and an orthographic projection of the second sub-layer onto the substrate being located within orthographic projection areas of the first sub-layer and the third sub-layer onto the substrate.

Description

Capacitor structure and preparation method thereof and radio frequency device Technical Field

[0001] The embodiments of the present disclosure belong to the technical field of capacitor structures, and specifically relate to a capacitor structure, a preparation method thereof, and a radio frequency device. Background Art

[0002] With the continuous advancement of electronic technology, the integration level of active electronic components has increased significantly, and the demand for passive devices to complement these active components has also increased. As electronic products continue to move towards miniaturization and micro-scaling, reducing the cost and space required for passive components while improving their performance has become a pressing issue. Integrated Passive Device (IPD) technology (functional devices that integrate resistors, capacitors, and inductors using semiconductor processing techniques and are essentially a passive device integration technology based on silicon or glass) utilizes semiconductor precision processing technology to integrate passive components such as capacitors and inductors onto glass substrates, enabling highly integrated, high-performance devices that achieve specific functions. IPD technology is considered an effective path to achieving System in a Package (SiP), a system-level package where RF passive components such as filters, couplers, and antennas, composed of resistors and capacitors, are integrated onto a substrate using thin film lamination or other methods to form a packaged component with system functionality.

[0003] Metal-Insulator-Metal (MIM) capacitors are a typical passive component with advantages such as low parasitic capacitance and low electrode resistivity. With their unique performance advantages, they are widely suitable for fields such as radio frequency microwaves and optical communications, and have broad application space in the future.

[0004] Summary of the Invention

[0005] In a first aspect, an embodiment of the present disclosure provides a capacitor structure, comprising a substrate, a first electrode, a dielectric layer, and a second electrode.

[0006] The first electrode, the dielectric layer, and the second electrode are sequentially stacked on one side of the substrate, and the orthographic projections of the first electrode, the dielectric layer, and the second electrode on the substrate at least partially overlap;

[0007] The second electrode includes a first sublayer, a second sublayer and the third sublayer,

[0008] The first sublayer, the second sublayer and the third sublayer are stacked in sequence away from the substrate,

[0009] The orthographic projection of the second sub-layer on the substrate is located within the orthographic projection region of the first sub-layer and the third sub-layer on the substrate.

[0010] In some embodiments, a distance between any side edge of the orthographic projection of the first sublayer and the third sublayer on the substrate and a corresponding side edge of the orthographic projection of the second sublayer on the substrate is in a range of 7 to 15 μm.

[0011] In some embodiments, an angle between an edge surface of the second sub-layer and a surface of the second sub-layer close to the substrate is in a range of 20° to 45°.

[0012] In some embodiments, the present invention further includes a first flat layer located on a side of the second electrode facing away from the substrate.

[0013] A first opening is formed in the first flat layer, and an orthographic projection of the first opening on the substrate is located within an orthographic projection area of ​​the second electrode on the substrate.

[0014] An included angle between a sidewall of the first opening and a surface of the second electrode facing away from the substrate is in a range of 70° to 90°.

[0015] In some embodiments, the depth of the first opening ranges from 2 μm to 10 μm.

[0016] In some embodiments, a minimum radial dimension of the first opening is greater than 10 μm.

[0017] In some embodiments, the invention further includes a connecting structure located on a side of the first planar layer facing away from the substrate.

[0018] The connecting structure extends into the first opening and contacts and is electrically connected to the second electrode.

[0019] In some embodiments, a distance between a surface of the connection structure facing away from the substrate and the substrate is greater than a distance between a surface of the first planar layer facing away from the substrate and the substrate.

[0020] In some embodiments, the material of the area where the surface of the second electrode facing away from the substrate overlaps with the orthographic projection of the first opening on the substrate is a metal material.

[0021] The material of the area of ​​the surface of the second electrode on the side facing away from the substrate that does not overlap with the orthographic projection of the first opening on the substrate is a metal oxide material.

[0022] In some embodiments, a second flat layer is further included, located between the first flat layer and the substrate.

[0023] A second opening is formed in the second flat layer, the first electrode is located in the second opening, and the orthographic projections of the first electrode and the second opening on the substrate coincide with each other;

[0024] A distance between a surface of the second planar layer facing away from the substrate and the substrate is smaller than a distance between a surface of the first electrode facing away from the substrate and the substrate.

[0025] In some embodiments, the orthographic projection of the second electrode on the substrate is located within the orthographic projection area of ​​the dielectric layer on the substrate.

[0026] The orthographic projection of the dielectric layer on the substrate is located within the orthographic projection region of the first electrode on the substrate.

[0027] In some embodiments, the second electrode, the dielectric layer, and the first electrode have the same orthographic projection shape on the substrate.

[0028] The orthographic projection centers of the second electrode, the dielectric layer, and the first electrode on the substrate coincide with each other;

[0029] The orthographic projection shape of the second electrode on the substrate includes a rectangle or a rounded rectangle.

[0030] In a second aspect, an embodiment of the present disclosure further provides a radio frequency device, which includes the above-mentioned capacitor structure.

[0031] In a third aspect, the present disclosure also provides a method for preparing a capacitor structure, which includes: sequentially preparing a first electrode, a dielectric layer, and a second electrode on a substrate;

[0032] The orthographic projections of the first electrode, the dielectric layer, and the second electrode on the substrate at least partially overlap;

[0033] Preparing the second electrode includes preparing a first sublayer, a second sublayer and a third sublayer,

[0034] The orthographic projection of the second sub-layer on the substrate is located within the orthographic projection region of the first sub-layer and the third sub-layer on the substrate.

[0035] In some embodiments, the preparing the first sublayer, the second sublayer, and the third sublayer comprises:

[0036] forming a first sub-layer film and a second sub-layer film in sequence on the substrate on which the first electrode and the dielectric layer are formed by physical vapor deposition;

[0037] forming a pattern of the second sub-layer through a first exposure process;

[0038] forming a third sub-layer film by physical vapor deposition; wherein the third sub-layer film and the first sub-layer film wrap the pattern of the second sub-layer;

[0039] The patterns of the third sub-layer and the first sub-layer are simultaneously formed through a second exposure process.

[0040] In some embodiments, the method further includes: preparing a first flat layer on a side of the second electrode facing away from the substrate, and opening a first opening in the first flat layer.

[0041] The preparing the first flat layer and opening the first opening in the first flat layer comprises:

[0042] forming a first planarization layer film by coating on the substrate on which the second electrode is formed;

[0043] forming a mask layer including a third opening pattern on a side of the first planar layer facing away from the substrate;

[0044] The first planar layer film is dry-etched through the third opening pattern in the mask layer to form the first opening.

[0045] In some embodiments, the method further includes dry etching the surface layer of the second electrode exposed at the first opening through the third opening pattern in the mask layer to remove the metal oxide surface layer of the second electrode exposed at the first opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed exemplary embodiments with reference to the accompanying drawings, in which:

[0047] FIG1 is a schematic cross-sectional view of the structure of a MIM capacitor in the related art.

[0048] 2a-2g are schematic diagrams of a preparation process of a MIM capacitor in related art.

[0049] FIG3 a is a schematic cross-sectional view of a capacitor structure according to an embodiment of the present disclosure.

[0050] FIG3 b is a scanning electron microscope image of the second electrode in an embodiment of the present disclosure.

[0051] FIG3 c is a schematic top view of a capacitor structure in an embodiment of the present disclosure.

[0052] FIG3 d is a schematic top view of another structure of the capacitor structure in an embodiment of the present disclosure.

[0053] 4a-4c are schematic diagrams of a process for preparing a second electrode of a capacitor structure according to an embodiment of the present disclosure.

[0054] 4d-4e are schematic diagrams of a process for preparing a first flat layer and a first opening therein in an embodiment of the present disclosure.

[0055] FIG4 f is a schematic diagram of a connection structure for preparing a capacitor structure in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] To enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, a capacitor structure, a preparation method thereof, and a radio frequency device provided by the embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0057] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully enable those skilled in the art to understand the scope of this disclosure.

[0058] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate specific shapes of the regions, but are not intended to be limiting.

[0059] In the related art, refer to Figure 1, which is a schematic cross-sectional view of the structure of a MIM capacitor in the related art, which is a miniaturized glass-based MIM (Metal Insulator Metal) capacitor used in the field of radio frequency devices. The glass-based MIM capacitor includes a glass substrate 1, and a lower electrode 9, an intermediate dielectric layer 10, and an upper electrode 11 formed in sequence on one side of the glass substrate 1. A first flat layer 12 is also formed on the side of the glass substrate 1 where the MIM capacitor is formed. An opening is provided in the first flat layer 12, and the lower electrode is located in the opening of the first flat layer 12; a second flat layer 13 is provided on the side of the upper electrode 11 facing away from the glass substrate 1, and a metal lead 14 is also formed on the side of the second flat layer 13 facing away from the glass substrate 1. The upper electrode 11 is electrically connected to the metal lead 14 through a via 130 provided in the second flat layer 13 to achieve signal conduction between the upper electrode 11 and the metal lead 14.

[0060] The accuracy of MIM capacitors is mainly related to the fluctuation of the area S between the upper and lower electrodes of the capacitor and the thickness d of the intermediate dielectric layer, as shown in the following formula:

[0061] Where S is the area of ​​the upper and lower electrodes of the capacitor, ε0 is the dielectric constant of vacuum, and ε r is the dielectric constant of the intermediate dielectric layer; C is the capacitance of the MIM capacitor.

[0062] The dielectric constant of the intermediate dielectric layer is typically determined by the desired capacitance of the product and is primarily determined by the material used. Fluctuations are relatively small. However, the facing area S between the upper and lower electrodes and the thickness d of the intermediate dielectric layer are often affected by the equipment, process, and capacitor structure design, leading to fluctuations that can affect the processing accuracy of the capacitor. Therefore, controlling the facing area between the upper and lower electrodes and the thickness of the intermediate dielectric layer is crucial.

[0063] With the continuous development of radio frequency microwave and optical communication devices, the size of capacitors continues to shrink, and the area of ​​the electrodes on the capacitors continues to decrease. However, higher requirements are placed on the capacitor's capacitance consistency, operating frequency band, loss and other performance. This leads to challenges in the size consistency of the capacitor's electrodes and the formation of vias electrically connecting the upper electrodes in the second flat layer.

[0064] 2a-2g are schematic diagrams of a preparation process of a MIM capacitor in related art; the preparation of the MIM capacitor in related art mainly includes the following steps: Step S1: Referring to FIG. 2a, the first flat layer 12 on one side of the glass substrate 1 is patterned.

[0065] In this step, a first planar layer is coated on one side of the glass substrate 1, and then a photolithography process is performed to form the pattern of the first planar layer 12 and the pattern of the opening 120 therein. The thickness of the first planar layer 12 after curing is generally 2-10 μm.

[0066] Step S2: Referring to FIG. 2 b , the lower electrode 9 is patterned.

[0067] In this step, a Ti (titanium) seed layer and a Cu (copper) seed layer are sequentially prepared on the side of the first flat layer 12 facing away from the glass substrate 1; wherein the thickness of the Ti seed layer is 20 to 200 nm, and the thickness of the Cu seed layer is 100 to 1000 nm; then, the thickness of the copper layer is thickened by electroplating; the thickness of the copper layer needs to be greater than the thickness of the first flat layer 12, generally 4 to 12 μm; then, by chemical mechanical polishing (CMP), the first flat layer 12 is used as a stop layer for chemical mechanical polishing (i.e., the copper layer is CMP-treated). The copper layer and titanium seed layer on the side of the first flattening layer 12 facing away from the glass substrate 1 are removed. A titanium layer is then deposited using a PVD (physical vapor deposition) process; the thickness of this titanium layer is between 20 and 200 nm. Finally, a single-step photolithography and etching process forms the pattern of the top titanium layer (i.e., the titanium layer on the side of the copper layer facing away from the glass substrate). This top titanium layer only covers the surface of the copper layer, ultimately forming the Ti / Cu / Ti stacked capacitor bottom electrode 9. The primary function of the top titanium layer is to enhance adhesion to the intermediate dielectric layer 10 (e.g., SiNx material) and to prevent copper in the copper layer from diffusing into the intermediate dielectric layer 10.

[0068] Step S3: Referring to FIG. 2 c , an intermediate dielectric layer film 101 is deposited.

[0069] In this step, an intermediate dielectric layer 101 is formed on the side of the lower electrode 9 facing away from the glass substrate 1 by a coating process. The material of the intermediate dielectric layer 101 can be SiNx, SiO2, Al2O3, etc., with a thickness of 0.1μm to 0.2μm.

[0070] Step S4: Referring to FIG. 2 d , the upper electrode 11 is patterned.

[0071] In this step, a Ti / Cu / Ti (titanium / copper / titanium) metal stack is sequentially deposited on the side of the intermediate dielectric layer film 101 facing away from the glass substrate 1 through a PVD (physical vapor deposition) process, and then a pattern of the capacitor upper electrode 11 is formed through a single photolithography, development and wet etching process.

[0072] Step S5: Referring to FIG. 2 e , the intermediate dielectric layer 10 is patterned.

[0073] In this step, the intermediate dielectric layer 10 is patterned by photolithography and dry etching processes.

[0074] Step S6: Referring to FIG. 2 f , the second planar layer 13 is patterned.

[0075] In this step, a second planar layer is formed on the side of the top electrode 11 facing away from the glass substrate 1 by spin coating. The portion of the second planar layer directly above the surface of the top electrode 11 facing away from the glass substrate 1 (i.e., the portion of the second planar layer that overlaps with the orthographic projection of the top electrode 11 on the glass substrate 1) has a thickness of 2 to 10 μm. Then, a photolithography and development process is used to form the pattern of the second planar layer 13 and the pattern of the via hole 130 therein. The diameter of the via hole 130 is generally 15 to 100 μm. For example, the opening diameter of the via hole 130 near the top electrode 11 is 15 μm, while the opening diameter of the via hole 130 away from the top electrode 11 is 100 μm.

[0076] Step S7 : Referring to FIG. 2 g , the metal lead 14 is patterned.

[0077] In this step, a Ti (titanium) seed layer and a Cu (copper) seed layer are sequentially deposited on the side of the second planar layer 13 facing away from the glass substrate 1 using a PVD (physical vapor deposition) process. The copper layer is then thickened using electroplating. Finally, photolithography, development, and wet etching processes are used to form the pattern of the metal leads 14. The metal leads 14 connect to the top electrode 11 through vias 130 in the second planar layer 13, enabling signal conduction between the top electrode 11 and the metal leads 14.

[0078] On the one hand, the upper electrode 11 of the MIM capacitor in the above technical solution is a Ti / Cu / Ti laminated metal, and the upper electrode 11 is usually patterned by a wet etching scheme. However, the Ti / Cu / Ti laminated metal needs to be etched in three steps during the patterning process. The bottom Ti metal is thinner than the Cu metal, and the etching speed is difficult to accurately control. Bottom side etching is very likely to occur, resulting in abnormal size and morphology of the capacitor upper electrode 11 and poor capacitance consistency.

[0079] On the other hand, in the above technical solution, the via 130 for electrically connecting the upper electrode 11 and the metal lead 14 is usually prepared by photolithography and development technology. The slope angle θ1 of the formed via 130 is too gentle (less than 50°), the diameter of the bottom of the via 130 becomes smaller, and the contact area between the upper electrode 11 and the metal lead 14 at the bottom of the via 130 is small, resulting in the minimum size of the capacitor being limited by the process capability of the opening limit of the via 130.

[0080] On the other hand, the top metal Ti of the laminated metal of the upper electrode 11 in the above technical solution is easily oxidized to form titanium oxide (TiO2) during the process. The titanium oxide material has a large resistivity and poor conductivity, which increases the contact resistance between the upper electrode 11 and the metal lead 14 at the bottom of the via 130, ultimately leading to a large loss in capacitor performance. At the same time, the oxidation of the metal Ti at the bottom of the via 130 will also cause the overlap adhesion between the upper electrode 11 and the metal lead 14 to deteriorate, resulting in poor connection reliability of the capacitor.

[0081] In order to solve the above-mentioned problems in the related art, on the first aspect, an embodiment of the present disclosure provides a capacitor structure. Referring to Figure 3a, it is a structural cross-sectional schematic diagram of a capacitor structure in an embodiment of the present disclosure, wherein the capacitor structure includes a substrate 1, a first electrode 2, a dielectric layer 3 and a second electrode 4, and the first electrode 2, the dielectric layer 3 and the second electrode 4 are stacked in sequence on one side of the substrate 1, and the orthographic projections of the first electrode 2, the dielectric layer 3 and the second electrode 4 on the substrate 1 at least partially overlap; the second electrode 4 includes a first sublayer 41, a second sublayer 42 and a third sublayer 43, and the first sublayer 41, the second sublayer 42 and the third sublayer 43 are stacked in sequence away from the substrate 1, and the orthographic projection of the second sublayer 42 on the substrate 1 is located in the orthographic projection area of ​​the first sublayer 41 and the third sublayer 43 on the substrate 1.

[0082] When the orthographic projection area of ​​the third sublayer 43 on the substrate 1 is larger than the orthographic projection area of ​​the second sublayer 42 on the substrate 1, the third sublayer 43 wraps around the surface of the second sublayer 42 away from the substrate 1 and its surrounding edge side surfaces; the first sublayer 41 and the third sublayer 43 completely wrap around the second sublayer. When the orthographic projection areas of the first sublayer 41 and the third sublayer 43 on the substrate 1 are both larger than the orthographic projection areas of the second sublayer 42 on the substrate 1, the first sublayer 41 and the third sublayer 43 also completely wrap around the second sublayer.

[0083] In this embodiment, by making the orthographic projection of the second sublayer 42 on the substrate 1 located within the orthographic projection area of ​​the first sublayer 41 and the third sublayer 43 on the substrate 1, the first sublayer 41 can cover the side surface of the second sublayer 42 close to the substrate 1, and the third sublayer 43 can cover the surrounding edge sides and the side surface away from the substrate 1 of the second sublayer 42, thereby achieving complete wrapping of the second sublayer 42 by the first sublayer 41 and the third sublayer 43, thereby avoiding the side corrosion problem of the first sublayer 41 of the second electrode 4 close to the substrate 1 during the preparation process, optimizing the morphology of the stacked structure of the second electrode 4 of the capacitor structure, and thus ensuring the dimensional consistency of the first sublayer 41 and the third sublayer 43 of the second electrode 4 of the capacitor structure after preparation, thereby improving the consistency of the capacitance of the capacitor structure; the capacitor structure has the advantages of low insertion loss (referring to inserting the capacitor structure into the radio frequency circuit), high integration, high reliability, etc., can achieve better electrical performance, and match the development trend of radio frequency products.

[0084] In some embodiments, referring to FIG. 3 a , the orthographic projections of the first sublayer 41 and the third sublayer 43 on substrate 1 overlap, and the orthographic projections of the first sublayer 41 and the third sublayer 43 on substrate 1 are larger than the orthographic projections of the second sublayer 42 on substrate 1. This ensures that the first sublayer 41 and the third sublayer 43 completely encapsulate the second sublayer 42, preventing undercutting of the first sublayer 41 during fabrication. This ensures dimensional consistency between the first sublayer 41 and the third sublayer 43 after fabrication, improving the capacitance consistency of the capacitor structure.

[0085] In some embodiments, distances between any side edge of the orthographic projection of the first sublayer 41 and the third sublayer 43 on the substrate 1 and corresponding side edges of the orthographic projection of the second sublayer 42 on the substrate 1 are equal.

[0086] In some embodiments, the distance L between any side edge of the orthographic projection of the first sublayer 41 and the third sublayer 43 on the substrate 1 and the corresponding side edge of the orthographic projection of the second sublayer 42 on the substrate 1 is in a range of 7 to 15 μm. For example, the distance L between any side edge of the orthographic projection of the first sublayer 41 and the third sublayer 43 on the substrate 1 and the corresponding side edge of the orthographic projection of the second sublayer 42 on the substrate 1 is 10 μm.

[0087] In some embodiments, referring to FIG3b , which is a scanning electron microscope image of the second electrode in the disclosed embodiment, the angle θ between the edge end face of the second sub-layer 42 and the surface of the second sub-layer 42 on the side close to the substrate 1 ranges from 20° to 45°. For example, the angle θ between the edge end face of the second sub-layer 42 and the surface of the second sub-layer 42 on the side close to the substrate 1 is 20°. The angle θ between the edge end face of the second sub-layer 42 and the surface of the second sub-layer 42 on the side close to the substrate 1 can effectively ensure the subsequent slope coverage of the third sub-layer 43, effectively solving the process defect of discontinuous slope of the third sub-layer 43.

[0088] In some embodiments, the capacitor structure further includes a first flat layer 5, which is located on the side of the second electrode 4 facing away from the substrate 1. A first opening 50 is provided in the first flat layer 5. The orthographic projection of the first opening 50 on the substrate 1 is located within the orthographic projection area of ​​the second electrode 4 on the substrate 1. The angle α between the side wall of the first opening 50 and the surface of the second electrode 4 facing away from the substrate 1 is in the range of 70° to 90°.

[0089] With such a configuration, compared with the case where the slope angle of the via in the second flat layer in the related art is too gentle, the angle α between the side wall of the first opening 50 and the surface of the second electrode 4 facing away from the substrate 1 is increased, which can effectively solve the problem of the smaller bottom diameter of the via in the related art, increase the bottom diameter size of the first opening 50 in contact with the second electrode 4, and thus increase the area of ​​the second electrode 4 exposed at the first opening 50.

[0090] In some embodiments, the capacitor structure further includes a connecting structure 6 located on a side of the first planar layer 5 facing away from the substrate 1 . The connecting structure 6 extends into the first opening 50 and contacts and is electrically connected to the second electrode 4 .

[0091] Among them, the angle α between the side wall of the first opening 50 and the side surface of the second electrode 4 facing away from the substrate 1 increases, which can increase the contact area between the connecting structure 6 and the second electrode 4, thereby reducing the contact resistance between the connecting structure 6 and the second electrode 4, thereby effectively improving the performance of the capacitor structure.

[0092] In some embodiments, the surface of the connection structure 6 facing away from the substrate 1 is flush, and the distance h1 between the surface of the connection structure 6 facing away from the substrate 1 and the substrate 1 is greater than the distance h2 between the surface of the first flat layer 5 facing away from the substrate 1 and the substrate 1.

[0093] In some embodiments, the connection structure 6 is formed by stacking a titanium layer and a copper layer in sequence. The titanium layer can enhance the adhesion between the upper copper layer and the second electrode 4 and the first flat layer 5, thereby improving product reliability.

[0094] In some embodiments, the connection structure 6 may be a signal lead of a capacitor structure.

[0095] In some embodiments, the material of the area of ​​the surface of the second electrode 4 facing away from the substrate 1 that overlaps with the orthographic projection of the first opening 50 on the substrate 1 is a metal material, and the material of the area of ​​the surface of the second electrode 4 facing away from the substrate 1 that does not overlap with the orthographic projection of the first opening 50 on the substrate 1 is a metal oxide material.

[0096] Such a configuration can reduce the contact resistance between the second electrode 4 at the bottom of the first opening 50 and the connection structure 6, increase the adhesion between the second electrode 4 at the bottom of the first opening 50 and the connection structure 6, and effectively improve the performance and reliability of the capacitor structure.

[0097] In some embodiments, the material of the surface layer of the second electrode 4 on the side facing away from the substrate 1 in the area overlapping with the orthographic projection of the first opening 50 on the substrate 1 is titanium metal, and the material of the surface layer of the second electrode 4 on the side facing away from the substrate 1 in the area not overlapping with the orthographic projection of the first opening 50 on the substrate 1 is titanium oxide material.

[0098] In some embodiments, the thickness range of the first sublayer 41 and the third sublayer 43 is 20 to 200 nm respectively; the thickness range of the second sublayer 42 is 200 nm to 1 μm; the thickness range of the surface layer of the metal oxide material of the second electrode 4 facing away from the substrate 1 is 10 to 30 nm.

[0099] In some embodiments, the depth s of the first opening 50 ranges from 2 to 10 μm, and the radial dimension of the first opening 50 at different depths varies by less than 2 μm. This arrangement, on the one hand, enables reliable electrical connection between the second electrode 4 and the connection structure 6, and on the other hand, allows the radial dimensions of the first opening 50 at different depths to be approximately equal, thereby ensuring that the angle α between the sidewall of the first opening 50 and the surface of the second electrode 4 facing away from the substrate 1 is within a range of 70° to 90°. This effectively addresses the issue of reduced bottom diameter of the via in related art, increases the bottom diameter of the first opening 50 where it contacts the second electrode 4, and thereby increases the area of ​​the second electrode 4 exposed at the first opening 50.

[0100] In this embodiment, the first opening 50 penetrates the thickness of the first flat layer 5 directly above the second electrode 4. That is, the thickness of the portion of the first flat layer 5 directly above the second electrode 4 and having the first opening 50 is in the range of 2 to 10 μm. The radial dimensions of the first opening 50 at different depths are approximately equal.

[0101] In some embodiments, the minimum radial dimension of the first opening 50 is greater than 10 μm. If limited by the manufacturing process of the first opening 50 , the radial dimension of the first opening 50 near the second electrode 4 is the smallest, and the minimum radial dimension of the first opening 50 may be 10 μm.

[0102] In some embodiments, the capacitor structure further includes a second flat layer 7, which is located between the first flat layer 5 and the substrate 1. A second opening 70 is defined in the second flat layer 7. The first electrode 2 is located in the second opening 70, and the orthographic projections of the first electrode 2 and the second opening 70 on the substrate 1 coincide with each other. The distance m1 between the surface of the second flat layer 7 facing away from the substrate 1 and the substrate 1 is less than the distance m2 between the surface of the first electrode 2 facing away from the substrate 1 and the substrate 1.

[0103] In some embodiments, the orthographic projection of the second electrode 4 on the substrate 1 is located within the orthographic projection area of ​​the dielectric layer 3 on the substrate 1 , and the orthographic projection of the dielectric layer 3 on the substrate 1 is located within the orthographic projection area of ​​the first electrode 2 on the substrate 1 .

[0104] In some embodiments, referring to Figure 3c, which is a schematic top view of a capacitor structure in an embodiment of the present disclosure, and Figure 3d is a schematic top view of another capacitor structure in an embodiment of the present disclosure, the orthographic projection area of ​​the second electrode 4 on the substrate 1 is smaller than the orthographic projection area of ​​the dielectric layer 3 on the substrate 1, and the orthographic projection area of ​​the dielectric layer 3 on the substrate 1 is smaller than the orthographic projection area of ​​the first electrode 2 on the substrate 1.

[0105] In this embodiment, the effective area of ​​the capacitor structure is determined by the facing area of ​​the second electrode 4, the dielectric layer 3, and the first electrode 2. However, during the process, the orthographic projections of the three on the substrate 1 cannot completely overlap. In order to ensure the consistency of the area of ​​the manufactured capacitor structure and reduce the difficulty of alignment between the second electrode 4, the dielectric layer 3, and the first electrode 2 during the process, the first electrode 2, the dielectric layer 3, and the second electrode 4 are stacked in a stepped manner in this solution. This can leave a certain process margin for the alignment between the three during the preparation of the capacitor structure, and ultimately make the size of the second electrode 4 of the capacitor structure determine the effective area of ​​the capacitor structure, so that the process is more stable and the capacitor structure has better consistency.

[0106] In some embodiments, the orthographic projection shapes of the second electrode 4, the dielectric layer 3, and the first electrode 2 on the substrate 1 are the same, and the orthographic projection centers of the second electrode 4, the dielectric layer 3, and the first electrode 2 on the substrate 1 coincide with each other; the orthographic projection shape of the second electrode 4 on the substrate 1 includes a rectangle or a rounded rectangle.

[0107] In some embodiments, the distance n1 between the corresponding side edges of the orthographic projections of the second electrode 4 and the dielectric layer 3 on the substrate 1 is greater than 3 μm, and the distance n2 between the corresponding side edges of the orthographic projections of the dielectric layer 3 and the first electrode 2 on the substrate 1 is greater than 3 μm.

[0108] In some embodiments, the first sublayer 41 of the second electrode 4 is made of titanium, the second sublayer 42 is made of copper, and the third sublayer 43 is made of titanium. The thickness of the second sublayer 42 is greater than the thickness of the first sublayer 41, and the thickness of the second sublayer 42 is greater than the thickness of the third sublayer 43.

[0109] In some embodiments, the first electrode 2 adopts a stacked structure in which titanium, copper, and titanium are stacked in sequence, and the thickness of the copper layer is greater than the thickness of the upper and lower titanium layers.

[0110] In some embodiments, the material of the dielectric layer 3 may be SiNx, SiO2, Al2O3 or the like, and the thickness of the dielectric layer 3 is 0.1 μm to 0.2 μm.

[0111] In some embodiments, the substrate 1 may be made of glass or silicon. The first flat layer 5 and the second flat layer 7 may be made of high molecular weight organic polymer materials, such as polyimide. The thickness of the second flat layer 7 is generally 2 to 10 μm.

[0112] Based on the above structure of the capacitor structure, an embodiment of the present disclosure also provides a method for preparing the capacitor structure, which includes: preparing a first electrode, a dielectric layer, and a second electrode in sequence on a substrate, and the orthographic projections of the first electrode, the dielectric layer, and the second electrode on the substrate at least partially overlap; preparing the second electrode includes preparing a first sublayer, a second sublayer, and a third sublayer, and the orthographic projection of the second sublayer on the substrate is located within the orthographic projection area of ​​the first sublayer and the third sublayer on the substrate.

[0113] In some embodiments, referring to Figures 4a-4c, there are schematic diagrams of the process of preparing the second electrode of the capacitor structure in the embodiments of the present disclosure, wherein the first sublayer 41, the second sublayer 42 and the third sublayer 43 are prepared, including: step 4-1, forming the first sublayer film 410 and the second sublayer film in sequence by physical vapor deposition on the substrate 1 on which the first electrode 2 and the dielectric layer 3 are formed.

[0114] Step 4-2: forming a pattern of the second sub-layer 42 through a first exposure process.

[0115] In this step, the first exposure process can process the second sub-layer film to form the pattern of the second sub-layer 42. The first exposure process includes the steps of photoresist coating, exposure, development, and etching. The etching can be wet etching.

[0116] Step 4 - 3 , forming a third sub-layer film 430 by physical vapor deposition; the third sub-layer film 430 and the first sub-layer film 410 wrap the pattern of the second sub-layer 42 .

[0117] Step 4-4: The patterns of the third sub-layer 43 and the first sub-layer 41 are simultaneously formed through a second exposure process.

[0118] In this step, the second exposure process can process the third sub-layer film 430 and the first sub-layer film 410 together to form the patterns of the third sub-layer 43 and the first sub-layer 41. The second exposure process includes the steps of photoresist coating, exposure, development, and etching. The etching can be wet etching.

[0119] In this step, the surface layer 44 of the second electrode 4 is oxidized to form metal oxide during the process.

[0120] In this embodiment, compared with the preparation method of the upper electrode of the capacitor structure in the related art, the second electrode 4 of the capacitor structure no longer adopts a graphic scheme of one-time photolithography, development, and wet etching, but adopts a graphic scheme of two exposure processes (including exposure, development, and etching steps) in the above steps 4-1 to 4-4. The graphic scheme of the two-exposure process can enable the first sublayer 41 and the third sublayer 43 to wrap the middle second sublayer 42, thereby effectively solving the problem of side etching of the first sublayer 41 of the second electrode 4 close to the substrate 1 during the preparation process, and further effectively ensuring the size consistency of the first sublayer 41 and the third sublayer 43 of the second electrode 4 of the capacitor structure after preparation, thereby improving the consistency of the capacitance value of the capacitor structure.

[0121] In some embodiments, referring to Figures 4d-4e, schematic diagrams of the process of preparing a first planar layer and a first opening therein are shown in embodiments of the present disclosure. The method for preparing a capacitor structure further includes: preparing a first planar layer 5 on a side of the second electrode 4 facing away from the substrate 1 and defining a first opening 50 in the first planar layer 5. Preparing the first planar layer 5 and defining the first opening 50 in the first planar layer 5 include: Steps 4-5, forming a first planar layer film 51 by coating on the substrate 1 on which the second electrode 4 is formed.

[0122] In step 4-6, a mask layer 8 including a third opening pattern 80 is formed on the side of the first planar layer 51 facing away from the substrate 1 .

[0123] The thickness of the mask layer ranges from 500 to 1000 nm.

[0124] Step 4-7: dry-etching the first planarization layer 51 through the third opening pattern 80 in the mask layer 8 to form a first opening 50.

[0125] In this step, the pattern of the first planar layer 5 is formed simultaneously.

[0126] The angle α between the side wall of the first opening 50 prepared through steps 4-5 to 4-7 and the surface of the second electrode 4 on the side facing away from the substrate 1 is in the range of 70° to 90°. Compared with the case where the slope angle of the via in the second flat layer in the related art is too gentle, the angle α between the side wall of the first opening 50 and the surface of the second electrode 4 on the side facing away from the substrate 1 is increased, which can effectively solve the problem of the smaller bottom diameter of the via in the related art, increase the bottom diameter size of the first opening 50 in contact with the second electrode 4, and thus increase the area of ​​the second electrode 4 exposed at the first opening 50.

[0127] In some embodiments, referring to Figures 4d-4e, in steps 4-6, a mask layer 8 including a third opening pattern 80 is formed on the side of the first planar layer film 51 facing away from the substrate 1, including: forming a metal mask layer by metal organic vapor deposition, physical vapor deposition or atomic layer deposition; and forming a third opening pattern 80 in the metal mask layer by an exposure process.

[0128] The exposure process includes the steps of photoresist coating, exposure, development, and etching. A third opening pattern 80 is formed on the metal mask layer by wet etching. The sidewalls of the third opening pattern 80 are approximately perpendicular to the first planar layer 51, and the third opening pattern 80 can form the first opening 50 with steep sidewalls.

[0129] In some embodiments, the material of the metal mask layer includes a metal material or a metal nitride material; the metal material includes any one of aluminum, titanium and gold; the metal nitride material includes titanium nitride or tantalum nitride.

[0130] In some embodiments, referring to Figures 4d-4e, in step 4-6, a mask layer 8 including a third opening pattern 80 is formed on the side of the first planar layer 51 facing away from the substrate 1, including: forming a photoresist mask layer by spin coating; and forming the third opening pattern 80 in the photoresist mask layer by a photolithography process.

[0131] The photoresist mask layer is made of a PR photoresist material with high etching resistance (a material whose solubility changes after exposure to light). The photolithography process includes exposure and development steps. The sidewalls of the third opening pattern 80 are approximately perpendicular to the first planar layer 51, and the third opening pattern 80 can form the first opening 50 with steep sidewalls.

[0132] In some embodiments, referring to FIG. 4e , the method for fabricating a capacitor structure further includes: step 4-8, dry etching the surface layer of the second electrode 4 exposed at the first opening 50 through the third opening pattern 80 in the mask layer 8 to remove the metal oxide surface layer of the second electrode 4 exposed at the first opening 50. This reduces the contact resistance of the surface layer of the second electrode 4 exposed at the first opening 50.

[0133] In some embodiments, referring to Figure 4e, the mask layer 8 is used as a barrier layer, and the surface of the second electrode 4 exposed at the first opening 50 is plasma bombarded through the third opening pattern 80 in the mask layer 8, so that the metal oxide layer (such as a titanium oxide layer) on the surface of the second electrode 4 can be dry-etched. The etching gas can be hydrogen or argon, thereby removing the metal oxide layer on the surface of the second electrode 4 exposed at the first opening 50 and reducing the contact resistance of the surface of the second electrode 4.

[0134] In some embodiments, referring to Figure 4f, which is a schematic diagram of a connection structure for preparing a capacitor structure in an embodiment of the present disclosure, the method for preparing the capacitor structure also includes: steps 4-9, removing the mask layer; forming a connection structure 6 on the side of the first flat layer 5 away from the substrate 1 through a composition process; the connection structure 6 extends into the first opening 50, and contacts and is electrically connected to the second electrode 4.

[0135] In some embodiments, the metal mask layer may be removed by a wet etching process, and the photoresist mask layer may be removed by a stripping solution.

[0136] In some embodiments, the connection structure 6 includes a titanium layer and a copper layer, which are stacked in a direction away from the substrate 1; the thickness of the titanium layer is less than that of the copper layer. The connection structure 6 can be prepared by first forming a titanium seed layer and a copper seed layer through a physical vapor deposition process; then increasing the thickness of the copper layer through additive electroplating; and finally, forming the pattern of the connection structure 6 through photolithography, development, and wet etching. The patterning process is a relatively mature traditional process and will not be described in detail here.

[0137] In this embodiment, the above steps 4-8 remove the metal oxide surface layer of the second electrode 4 exposed at the first opening 50, which can reduce the contact resistance between the second electrode 4 at the bottom of the first opening 50 and the connecting structure 6, increase the adhesion between the second electrode 4 at the bottom of the first opening 50 and the connecting structure 6, and effectively improve the performance and reliability of the capacitor structure.

[0138] In this embodiment, the preparation process of the first electrode 2 and the dielectric layer 3 is the same as that in the related art, and will not be described again here.

[0139] The capacitor structure provided in the embodiment of the present disclosure achieves complete wrapping of the second sublayer 42 by the first sublayer 41 and the third sublayer 43 by making the orthographic projection of the second sublayer 42 on the substrate 1 located within the orthographic projection area of ​​the first sublayer 41 and the third sublayer 43 on the substrate 1, thereby avoiding the problem of side corrosion of the first sublayer 41 of the second electrode 4 close to the substrate 1 during the preparation process, optimizing the morphology of the stacked structure of the second electrode 4 of the capacitor structure, and thus ensuring the dimensional consistency of the first sublayer 41 and the third sublayer 43 of the second electrode 4 of the capacitor structure after preparation, thereby improving the consistency of the capacitance value of the capacitor structure; the capacitor structure has the advantages of low insertion loss, high integration, high reliability, etc., can achieve better electrical performance, and match the development trend of radio frequency products.

[0140] In a second aspect, an embodiment of the present disclosure further provides a radio frequency device, comprising the capacitor structure in the above embodiment.

[0141] By adopting the capacitor structure in the above embodiment, the performance of the radio frequency device can be improved.

[0142] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A capacitor structure, wherein: comprising a substrate, a first electrode, a dielectric layer and a second electrode, The first electrode, the dielectric layer, and the second electrode are sequentially stacked on one side of the substrate, and the orthographic projections of the first electrode, the dielectric layer, and the second electrode on the substrate at least partially overlap; The second electrode includes a first sublayer, a second sublayer and the third sublayer, The first sublayer, the second sublayer and the third sublayer are stacked in sequence away from the substrate, The orthographic projection of the second sub-layer on the substrate is located within the orthographic projection region of the first sub-layer and the third sub-layer on the substrate.

2. The capacitor structure according to claim 1, wherein: The distance between any side edge of the orthographic projection of the first sublayer and the third sublayer on the substrate and the corresponding side edge of the orthographic projection of the second sublayer on the substrate is in the range of 7 to 15 μm.

3. The capacitor structure according to any one of claims 1 to 2, wherein: An included angle between an edge surface of the second sub-layer and a surface of the second sub-layer close to the substrate is in a range of 20° to 45°.

4. The capacitor structure according to any one of claims 1 to 2, wherein: The device further comprises a first flat layer located on a side of the second electrode facing away from the substrate. A first opening is formed in the first flat layer, and an orthographic projection of the first opening on the substrate is located within an orthographic projection area of ​​the second electrode on the substrate. An included angle between a sidewall of the first opening and a surface of the second electrode facing away from the substrate is in a range of 70° to 90°.

5. The capacitor structure according to claim 4, wherein: The depth of the first opening is in the range of 2 to 10 μm.

6. The capacitor structure according to claim 5, wherein: The minimum radial dimension of the first opening is greater than 10 μm.

7. The capacitor structure according to claim 4, wherein: It also includes a connecting structure located on a side of the first flat layer facing away from the substrate. The connecting structure extends into the first opening and contacts and is electrically connected to the second electrode.

8. The capacitor structure according to claim 7, wherein: A distance between a surface of the connection structure facing away from the substrate and the substrate is greater than a distance between a surface of the first planar layer facing away from the substrate and the substrate.

9. The capacitor structure according to claim 7, wherein: The material of the area where the surface of the second electrode on the side facing away from the substrate overlaps with the orthographic projection of the first opening on the substrate is a metal material. The material of the area of ​​the surface of the second electrode on the side facing away from the substrate that does not overlap with the orthographic projection of the first opening on the substrate is a metal oxide material.

10. The capacitor structure according to claim 4, wherein: Also included is a second flat layer located between the first flat layer and the substrate, A second opening is formed in the second flat layer, the first electrode is located in the second opening, and the orthographic projections of the first electrode and the second opening on the substrate coincide with each other; A distance between a surface of the second planar layer facing away from the substrate and the substrate is smaller than a distance between a surface of the first electrode facing away from the substrate and the substrate.

11. The capacitor structure according to claim 1, wherein: The orthographic projection of the second electrode on the substrate is located within the orthographic projection area of ​​the dielectric layer on the substrate. The orthographic projection of the dielectric layer on the substrate is located within the orthographic projection region of the first electrode on the substrate.

12. The capacitor structure according to claim 10 or 11, wherein: The orthographic projection shapes of the second electrode, the dielectric layer and the first electrode on the substrate are the same, The orthographic projection centers of the second electrode, the dielectric layer, and the first electrode on the substrate coincide with each other; The orthographic projection shape of the second electrode on the substrate includes a rectangle or a rounded rectangle.

13. A radio frequency device, wherein: The capacitor structure comprises the capacitor structure described in any one of claims 1-12.

14. A method for preparing a capacitor structure, wherein: include: A first electrode, a dielectric layer, and a second electrode are sequentially prepared on the substrate. The orthographic projections of the first electrode, the dielectric layer, and the second electrode on the substrate at least partially overlap; Preparing the second electrode includes preparing a first sublayer, a second sublayer and a third sublayer, The orthographic projection of the second sub-layer on the substrate is located within the orthographic projection region of the first sub-layer and the third sub-layer on the substrate.

15. The method for preparing a capacitor structure according to claim 14, wherein: The preparation of the first sublayer, the second sublayer and the third sublayer comprises: forming a first sub-layer film and a second sub-layer film in sequence on the substrate on which the first electrode and the dielectric layer are formed by physical vapor deposition; forming a pattern of the second sub-layer through a first exposure process; forming a third sub-layer film by physical vapor deposition; wherein the third sub-layer film and the first sub-layer film wrap the pattern of the second sub-layer; The patterns of the third sub-layer and the first sub-layer are simultaneously formed through a second exposure process.

16. The method for preparing a capacitor structure according to claim 15, wherein: Also includes: A first flat layer is prepared on a side of the second electrode facing away from the substrate, and a first opening is opened in the first flat layer. The preparing the first flat layer and opening the first opening in the first flat layer comprises: forming a first planarization layer film by coating on the substrate on which the second electrode is formed; forming a mask layer including a third opening pattern on a side of the first planar layer facing away from the substrate; The first planar layer film is dry-etched through the third opening pattern in the mask layer to form the first opening.

17. The method for preparing a capacitor structure according to claim 16, wherein: Also includes: The surface layer of the second electrode exposed at the first opening is dry-etched through the third opening pattern in the mask layer to remove the metal oxide surface layer of the second electrode exposed at the first opening.

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