Display panel, display apparatus and driving method

Abstract

Disclosed are a display panel, a display apparatus and a driving method. The display panel comprises: a substrate, having a first display area (AA1) and a second display area (AA2); a plurality of first sub-pixels (P1) located in the first display area (AA1); and a plurality of second sub-pixels (P2) located in the second display area (AA2). At least one second sub-pixel (P2) of the plurality of second sub-pixels (P2) comprises a first pixel portion (P21) and a second pixel portion (P22), the light-emitting area of the first pixel portion (P21) being less than the light-emitting area of the second pixel portion (P22).

Description

Display panel, display device, and driving method Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a display panel, a display device, and a driving method. Background Art

[0002] With the continuous advancement of display technology, people's demands for display methods are becoming increasingly diverse. In some display applications, users like to share information with others. In other application scenarios, users need to protect their privacy and require display products with anti-peeping features. For example, when users enter personal information on their mobile phones or handle confidential company information, display sharing and privacy switching are gradually becoming functional trends in display products.

[0003] Summary of the Invention

[0004] The present disclosure provides a display panel, a display device, and a driving method. The display panel includes:

[0005] A substrate having a first display area and a second display area;

[0006] a plurality of first sub-pixels, located in the first display area;

[0007] A plurality of second sub-pixels are located in the second display area; at least one second sub-pixel among the plurality of second sub-pixels includes: a first pixel portion and a second pixel portion; wherein the light-emitting area of ​​the first pixel portion is smaller than the light-emitting area of ​​the second pixel portion.

[0008] In a possible implementation, at least one first sub-pixel among the plurality of first sub-pixels includes a third pixel portion and a fourth pixel portion; a light-emitting area of ​​the third pixel portion is equal to a light-emitting area of ​​the fourth pixel portion.

[0009] In a possible implementation, at least one first sub-pixel among the plurality of first sub-pixels includes: a third pixel portion and a fourth pixel portion; and a light-emitting area of ​​the third pixel portion is smaller than a light-emitting area of ​​the fourth pixel portion.

[0010] In a possible implementation manner, a light-emitting area of ​​the fourth pixel portion is equal to a light-emitting area of ​​the second pixel portion.

[0011] In a possible implementation, at least one first sub-pixel among the plurality of first sub-pixels is an integrally connected structure.

[0012] In a possible implementation, the light-emitting area of ​​the first sub-pixel is greater than or equal to the sum of the light-emitting areas of the first sub-pixel portion and the second sub-pixel portion.

[0013] In one possible embodiment, the display panel includes: a first blocking layer; the first blocking layer includes: a first opening and a second opening; an orthographic projection of the first opening on the substrate overlaps with an orthographic projection of the first pixel portion on the substrate; and an orthographic projection of the second opening on the substrate overlaps with an orthographic projection of the second pixel portion on the substrate.

[0014] An orthographic projection area of ​​the first opening on the substrate is smaller than an orthographic projection area of ​​the second opening on the substrate.

[0015] In a possible implementation, at least one first sub-pixel among the plurality of first sub-pixels includes: a third pixel portion and a fourth pixel portion; the first shielding layer further includes: a third opening and a fourth opening; an orthographic projection of the third opening on the substrate overlaps with an orthographic projection of the third pixel portion on the substrate; and an orthographic projection of the fourth opening on the substrate overlaps with an orthographic projection of the fourth pixel portion on the substrate.

[0016] The orthographic projection area of ​​the fourth opening on the substrate is equal to the orthographic projection area of ​​the second opening on the substrate.

[0017] In a possible implementation manner, an orthographic projection area of ​​the third opening on the substrate is equal to an orthographic projection area of ​​the fourth opening on the substrate.

[0018] In a possible implementation manner, an orthographic projection area of ​​the third opening on the substrate is smaller than an orthographic projection area of ​​the fourth opening on the substrate.

[0019] In a possible embodiment, at least one first sub-pixel among the multiple first sub-pixels is an integrated connection structure; the first blocking layer also includes: a fifth opening; the orthographic projection of the fifth opening on the substrate has an overlapping area with the orthographic projection of the first sub-pixel on the substrate.

[0020] In a possible implementation manner, an orthographic projection area of ​​the fifth opening on the substrate is greater than or equal to the sum of the orthographic projection areas of the first opening and the second opening on the substrate.

[0021] In a possible implementation manner, the first opening includes: a plurality of first sub-openings; and the plurality of first sub-openings of the first opening are distributed in an array.

[0022] In a possible implementation manner, the orthographic projection shape of the first sub-opening on the substrate is rectangular, hexagonal, octagonal, circular, or elliptical.

[0023] In a possible implementation manner, the first pixel portion includes: a first anode portion; the second pixel portion includes: a second anode portion;

[0024] The orthographic projection area of ​​the first anode portion on the substrate is smaller than the orthographic projection area of ​​the second anode portion on the substrate.

[0025] In a possible implementation, at least one first sub-pixel among the plurality of first sub-pixels includes: a third pixel portion and a fourth pixel portion; the third pixel portion has a third anode portion, and the fourth pixel portion has a fourth anode portion;

[0026] The orthographic projection area of ​​the third anode portion on the substrate is equal to the orthographic projection area of ​​the fourth anode portion on the substrate, and both are equal to the orthographic projection area of ​​the second anode portion on the substrate.

[0027] In a possible implementation, at least one first sub-pixel among the plurality of first sub-pixels is an integrally connected structure; the first sub-pixel portion includes: a fifth anode portion;

[0028] An orthographic projection area of ​​the fifth anode portion on the substrate is greater than or equal to the sum of the orthographic projection areas of the first anode portion and the second anode portion on the substrate.

[0029] In a possible implementation, the display panel further includes: a second light-shielding layer located on a side of the first light-shielding layer facing the substrate;

[0030] The second light-shielding layer includes: a first light outlet and a second light outlet; the orthographic projection of the first light outlet on the substrate has an overlapping area with the orthographic projection of the first opening on the substrate; the orthographic projection of the second light outlet on the substrate has an overlapping area with the orthographic projection of the second opening on the substrate.

[0031] In a possible implementation, the display panel further includes: a lens layer located on a side of the first light-shielding layer facing away from the substrate;

[0032] The lens layer includes: a first lens and a second lens; the first lens covers the orthographic projection of the first opening on the substrate; the orthographic projection of the second lens on the substrate covers the orthographic projection of the second opening on the substrate.

[0033] In a possible implementation, the display panel further includes: an encapsulation layer, and a touch layer located on a side of the encapsulation layer facing away from the substrate; and the first light shielding layer is located on a side of the encapsulation layer facing away from the substrate.

[0034] In one possible implementation, among the first sub-pixel and the second sub-pixel, at least the second sub-pixel includes: a plurality of light-emitting bodies stacked in a direction perpendicular to the substrate; the light-emitting bodies include one or a combination of the following stacked film layers:

[0035] hole transport layer;

[0036] a luminescent layer;

[0037] Electron transport layer.

[0038] In a possible implementation, the second sub-pixel includes: a second pixel circuit;

[0039] The first anode portion and the second anode portion are both electrically connected to the second pixel circuit.

[0040] In a possible implementation, the second pixel circuit includes at least: a first light emitting control subcircuit and a second light emitting control subcircuit; the display panel further includes: a first light emitting control line and a second light emitting control line;

[0041] The first light emitting control subcircuit is electrically connected to the first light emitting control line and the first anode portion, and is configured to drive the first pixel portion to emit light under the control of the first light emitting control line;

[0042] The second light emitting control sub-circuit is electrically connected to the second light emitting control line and the second anode portion, and is configured to drive the second pixel portion to emit light under the control of the second light emitting control line.

[0043] In a possible implementation, the second sub-pixel includes: a first sub-pixel circuit and a second sub-pixel circuit;

[0044] The first anode portion is electrically connected to the first sub-pixel circuit; and the second anode portion is electrically connected to the second sub-pixel circuit.

[0045] In one possible implementation, the plurality of second sub-pixels include: a first pixel row and a second pixel row; the first pixel row and the second pixel row extend along a first direction and are alternately arranged along a second direction; the first pixel row includes: a plurality of first pixel portions; the second pixel row includes: a plurality of second pixel portions;

[0046] The display panel also includes: a first pixel row control line, and a second pixel row control line; the first pixel row control line is electrically connected to the first pixel portion of the first pixel row, and the second pixel row control line is electrically connected to the second pixel portion of the second pixel row; the first pixel row control line is configured to provide a signal to the first pixel portion of the first pixel row, and the second pixel control line is configured to provide a signal to the second pixel portion of the second pixel row.

[0047] An embodiment of the present disclosure provides a display device, which includes the display panel provided by the embodiment of the present disclosure.

[0048] The present disclosure further provides a method for driving the display panel provided in the embodiment of the present disclosure, which includes:

[0049] When determining to perform the normal display mode, controlling at least part of the first sub-pixels in the first display area and at least part of the second pixel portion in the second display area to emit light;

[0050] When it is determined to perform the partial anti-peeping display mode, at least a portion of the first sub-pixels in the first display area and part of the first sub-pixels in the second display area are controlled to emit light.

[0051] In a possible implementation, when determining to perform the normal display mode, controlling the first sub-pixel of the first display area and at least the second pixel portion of the second display area to emit light includes: when determining to perform the normal display mode, controlling the fourth pixel portion of the first display area and the second pixel portion of the second display area to emit light;

[0052] When determining to perform the partial anti-peeping display mode, controlling at least a portion of the first sub-pixels in the first display area and the first sub-pixel portion in the second display area to emit light includes: controlling the third pixel portion in the first display area and the first sub-pixel portion in the second display area to emit light.

[0053] In a possible implementation, when determining to perform the normal display mode, controlling the first sub-pixel in the first display area and at least the second pixel portion in the second display area to emit light includes: when determining to perform the normal display mode, controlling all of the first sub-pixels in the first display area and all of the second sub-pixels in the second display area to emit light;

[0054] When determining to perform the partial anti-peeping display mode, controlling at least a portion of the first sub-pixels in the first display area and the first sub-pixel portion of the second display area to emit light includes: controlling all of the first sub-pixels in the first display area and the first sub-pixel portion of the second display area to emit light.

[0055] In a possible implementation, when determining to perform the normal display mode, controlling the first sub-pixel in the first display area and at least the second pixel portion in the second display area to emit light includes: when determining to perform the normal display mode, controlling all of the first sub-pixels in the first display area and the second pixel portion in the second display area to emit light;

[0056] When determining to perform the partial anti-peeping display mode, controlling at least a portion of the first sub-pixels in the first display area and the first sub-pixel portion of the second display area to emit light includes: controlling all of the first sub-pixels in the first display area and the first pixel portion of the second display area to emit light.

[0057] In a possible implementation, the driving method further includes: in normal display mode, when determining that there is a brightness difference between the first display area and the second display area, calling a stored relationship table to adjust the brightness of the first display area and the second display area to be consistent. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] FIG1A is a schematic diagram of a display panel according to an embodiment of the present disclosure;

[0059] FIG1B is a schematic diagram of FIG1A in an anti-peeping display mode;

[0060] FIG1C is a schematic diagram of FIG1A in a normal display mode;

[0061] FIG1D is a schematic diagram of dividing an anode into a first anode portion and a second anode portion according to an embodiment of the present disclosure;

[0062] FIG2A is a schematic cross-sectional view of FIG1A taken along the dotted line A1A2;

[0063] FIG2B is a schematic cross-sectional view of FIG1A taken along the dotted line A3A4;

[0064] FIG2C is another schematic cross-sectional view of FIG1A taken along the dotted line A1A2;

[0065] FIG2D is a schematic diagram of the first opening at the first pixel portion P21 in FIG2C ;

[0066] FIG3 is a pixel circuit diagram of the second display area corresponding to FIG1A ;

[0067] FIG4A is a schematic diagram of wiring connections in the second display area corresponding to FIG1A ;

[0068] FIG4B is a schematic diagram of wiring connections in the first display area corresponding to FIG1A ;

[0069] FIG5A is a second schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0070] FIG5B is a schematic diagram of FIG5A in an anti-peeping display mode;

[0071] FIG5C is a schematic diagram of FIG5A in a normal display mode;

[0072] FIG6A is a schematic cross-sectional view of FIG5A taken along the dotted line A1A2;

[0073] FIG6B is a schematic cross-sectional view of FIG5A taken along the dotted line A3A4;

[0074] FIG7 is a pixel circuit diagram of the second display area corresponding to FIG5A;

[0075] FIG8 is a schematic diagram of wiring connections between the first display area and the second display area corresponding to FIG5A;

[0076] FIG9A is a third schematic diagram of a display panel provided in an embodiment of the present disclosure;

[0077] FIG9B is a schematic diagram of FIG9A in an anti-peeping display mode;

[0078] FIG9C is a schematic diagram of FIG9A in a normal display mode;

[0079] FIG10A is a schematic cross-sectional view of FIG9A taken along the dotted line A1A2;

[0080] FIG10B is a schematic cross-sectional view of FIG9A taken along the dotted line A3A4;

[0081] FIG11 is a pixel circuit diagram of the second display area corresponding to FIG9A ;

[0082] FIG12A is a fourth schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0083] FIG12B is a fifth schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0084] FIG13A is a sixth schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0085] FIG13B is a seventh schematic diagram of a display panel provided in an embodiment of the present disclosure;

[0086] FIG14 is a schematic diagram of a stacked layer of a first pixel portion provided by an embodiment of the present disclosure;

[0087] FIG15 is a schematic diagram of a plurality of first display areas and a second display area provided by an embodiment of the present disclosure;

[0088] FIG16 is a schematic diagram of an application scenario of a display panel provided by an embodiment of the present disclosure;

[0089] FIG17 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0090] FIG18 is a flow chart of a display panel driving method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0091] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0092] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0093] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0094] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0095] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0096] Anti-peeping display has new requirements in new scenarios, as shown in Figure 16. For example, the display screen only needs to have an anti-peeping function in local areas, and other areas need to display normally. The application scenario is such as in-vehicle display. The vehicle display can be a large horizontal screen. The main driver and the co-driver can share a screen. The area facing the main driver can be a normal screen, while the co-driver area needs to be an active anti-peeping screen (when the vehicle is driving, the co-driver can choose to turn on active anti-peeping when watching audio and video to prevent the co-driver display from affecting the main driver's driving, thereby improving safe driving).

[0097] In view of this, an embodiment of the present disclosure provides a display panel, as shown in FIG1A , FIG5A , or FIG9A . In FIG1A , FIG5A , and FIG9A , the lower left figure is an enlarged schematic diagram of the upper left dotted box, and the lower right figure is an enlarged schematic diagram of the upper right dotted box. The display panel includes:

[0098] The substrate has a first display area AA1 and a second display area AA2; specifically, the first display area AA1 can be used as a normal display area, and the second display area AA2 can be used as an anti-peeping display area;

[0099] A plurality of first sub-pixels P1 are located in the first display area AA1; specifically, the first sub-pixels P1 may include red sub-pixels R, green sub-pixels G, or blue sub-pixels B;

[0100] Multiple second sub-pixels P2 are located in the second display area AA2; specifically, the second sub-pixel P2 may include a red sub-pixel R, a green sub-pixel G, or a blue sub-pixel B; at least one second sub-pixel P2 among the multiple second sub-pixels P2 includes: a first pixel portion P21, and a second pixel portion P22; wherein the light-emitting area of ​​the first pixel portion P21 is smaller than the light-emitting area of ​​the second pixel portion P22.

[0101] In a possible embodiment, referring to FIG2A , FIG2A is a schematic cross-sectional view along the dotted line A1A2 in FIG1A , and the light-emitting area of ​​the first pixel portion P21 and the light-emitting area of ​​the second pixel portion P22 can be controlled by the size of the opening area of ​​the shading layer (such as the first shading layer 106 in FIG2A ). For example, in FIG2A , the display panel includes: a first blocking layer 106; the first blocking layer 106 includes: a first opening K1, and a second opening K2; the orthographic projection of the first opening on the K1 substrate 101 has an overlapping area with the orthographic projection of the first pixel portion P21 on the substrate 101; the orthographic projection of the second opening K2 on the substrate 101 has an overlapping area with the orthographic projection of the second pixel portion P22 on the substrate 101; the orthographic projection area of ​​the first opening K1 on the substrate 101 is smaller than the orthographic projection area of ​​the second opening K2. The positive projection area of ​​the opening K2 on the substrate 101 can thereby make the light-emitting area of ​​the first pixel portion P21 smaller than the light-emitting area of ​​the second pixel portion P22; as shown in FIG2A , when the first opening K1 is smaller than the second opening K2, at the area where the first pixel portion P21 is located, since the first opening K1 is smaller, the light at the front angle can be emitted, while the light at the side angle will be blocked (wherein, the dotted arrows represent the light that is blocked by the shading layer and cannot be emitted, and the solid arrows represent the normally emitted light); as for the light emitted at the area where the second pixel portion P22 is located, since the second opening K2 is larger, the light at the front angle can be emitted, and the light at the side angle can also be emitted, that is, by controlling the size of the openings of the shading layer at different positions, the emission angle of the emitted light can be controlled, thereby achieving anti-peeping or normal display control.

[0102] In the embodiment of the present disclosure, the display panel has a first display area AA1 and a second display area AA2, wherein the second sub-pixel P2 of the second display area AA2 includes: a first pixel portion P21, and a second pixel portion P22. The light-emitting area of ​​the first pixel portion P21 is smaller than the light-emitting area of ​​the second pixel portion P22, so that the front-viewing angle light of the first pixel portion P21 can be emitted, and the side-viewing angle light is blocked, and the front-viewing angle light and the side-viewing angle light of the second pixel portion P22 can be emitted. Therefore, when it is necessary to make the second display area AA2 anti-peep display, by only making the first pixel portion P21 display, it is possible to make only the viewer facing the second display area AA2 watch the content displayed in the second display area AA2, while viewers at other positions cannot watch the content displayed in the second display area AA2. content, realizing anti-peeping display of the second display area AA2; and when the second display area AA2 needs to be displayed normally, by at least displaying the second pixel portion P22, the viewer facing the second display area AA2 can watch the content of the second display area AA2, and the viewers at other positions can also watch the content displayed in the second display area AA2, realizing normal display of the second display area AA2, and then the second display area AA2 can realize partial anti-peeping display, and then for application scenarios where partial anti-peeping is required in a display panel, for example, on a car display, the main driver and the co-driver share a screen. When the vehicle is driving, the co-driver can choose to turn on active anti-peeping when watching audio and video, so as to avoid the co-driver's display screen affecting the main driver's driving, thereby improving driving safety.

[0103] In one possible embodiment, the light-emitting area of ​​the first sub-pixel portion P21 is smaller than the light-emitting area of ​​the second sub-pixel P22. This can be achieved by reducing the light-emitting area of ​​the first sub-pixel portion P21 simultaneously in the sub-pixel row direction and the sub-pixel column direction. Specifically, this can be achieved by making the first opening K1 smaller than the size of the second opening K2 in both the sub-pixel row direction and the sub-pixel column direction.

[0104] In some exemplary embodiments, the second display area AA2 of the display panel may include an active anti-peeping display mode and a normal display mode. The active anti-peeping display mode can meet the display needs of the co-pilot who needs to watch the car alone, and the normal display mode can meet the display needs of users in information sharing scenarios. In some examples, the display panel may be provided with a switch button, and the user switches the display mode of the second display area AA2 by switching the switch button. However, this embodiment is not limited to this. In other examples, voice control, induction, or other triggering methods can be used to initiate the display mode switching of the second display area AA2.

[0105] In a possible embodiment, referring to Figures 1A and 2B, wherein Figure 2B is a cross-sectional schematic diagram along the dotted line A3A4 in Figure 1A, at least one first sub-pixel P1 among the multiple first sub-pixels P1 includes: a third pixel portion P11, and a fourth pixel portion P12; the light-emitting area of ​​the third pixel portion P11 is equal to the light-emitting area of ​​the fourth pixel portion P12.

[0106] In one possible embodiment, the luminous area of ​​P11 of the third pixel portion and the luminous area of ​​the fourth pixel portion P12 can be controlled by the opening area size of the shading layer (such as the first shading layer 106 in Figure 2B). For example, referring to Figure 1A and Figure 2B, the first shading layer 106 also includes: a third opening K3 and a fourth opening K4; the orthographic projection of the third opening K3 on the substrate 101 has an overlapping area with the orthographic projection of the third pixel portion P21 on the substrate 101; the orthographic projection of the fourth opening K4 on the substrate 101 has an overlapping area with the orthographic projection of the fourth pixel portion P22 on the substrate 101; the orthographic projection area of ​​the third opening K3 on the substrate 101 is equal to the orthographic projection area of ​​the fourth opening K4 on the substrate 101, thereby making the luminous area of ​​P11 of the third pixel portion equal to the luminous area of ​​the fourth pixel portion P12.

[0107] Specifically, with reference to FIG. 1B and FIG. 1C , FIG. 1B is a schematic diagram of the display panel shown in FIG. 1A during anti-peeping display, and FIG. 1C is a schematic diagram of the display panel shown in FIG. 1A during normal display. When performing anti-peeping display, as shown in FIG. 1B , by making the third pixel portion P11 of the first display area AA1 display and the fourth pixel portion P12 non-display, and making the first pixel portion P21 of the second display area AA2 display and the second pixel portion P22 non-display, the first display area AA1 can display normally, while the second display area AA2 can perform anti-peeping display. During normal display, as shown in FIG1C , by making the third pixel portion P11 of the first display area AA1 non-displaying and the fourth pixel portion P12 displaying, and making the first pixel portion P21 of the second display area AA2 non-displaying and the second pixel portion P22 displaying, both the first display area AA1 and the second display area AA2 can be displayed normally. Moreover, during normal display, only the fourth pixel portion P12 of the first display area AA1 is displayed and the second pixel portion P22 of the second display area AA2 is displayed, so that the visual difference between the first display area AA1 and the second display area AA2 can be reduced.

[0108] In one possible embodiment, during normal display, the third pixel portion P11 of the first display area AA1 can be displayed, and the fourth pixel portion P12 can be non-displayed, and the first pixel portion P21 of the second display area AA2 can be non-displayed, and the second pixel portion P22 can be displayed, so that both the first display area AA1 and the second display area AA2 can be displayed normally.

[0109] In one possible implementation, the light-emitting areas of the third pixel portion P11 and the fourth pixel portion P12 can be made equal to the light-emitting area of ​​the second pixel portion P22. Specifically, the orthographic projection area of ​​the fourth opening K4 on the substrate 101 can be made equal to the orthographic projection area of ​​the second opening K2 on the substrate 101. In this way, during normal display, by only displaying the fourth pixel portion P12 of the first display area AA1 and the second pixel portion P22 of the second display area AA2, the visual difference between the first display area AA1 and the second display area AA2 can be minimized.

[0110] In a possible embodiment, after the second sub-pixel P2 of the second display area AA2 is divided as shown in FIG1A , the first pixel portion P21 and the second pixel portion P22 of the sub-pixel P2 can be driven separately by different pixel circuits. For example, the circuit shown in FIG7 can be used for driving.

[0111] In another possible embodiment, after the second subpixel P2 of the second display area AA2 is divided as shown in FIG1A , the first pixel portion P21 and the second pixel portion P22 of the same subpixel P2 can be driven to emit light by the same pixel circuit. Specifically, as shown in FIG3 , the second subpixel P2 includes: a second pixel circuit; and a first anode portion 205a and a second anode portion 205b electrically connected to the second pixel circuit. Driving the first pixel portion P21 and the second pixel portion P22 of the same subpixel P2 to emit light by the same pixel driver circuit can save circuit wiring space of the display panel and reduce the cost of the display panel.

[0112] In a possible embodiment, referring to Figures 3, 4A and 4B, wherein Figure 4A is a wiring connection diagram corresponding to the second display area AA2, and Figure 4B is a wiring connection diagram corresponding to the first display area AA1, the second pixel circuit at least includes: a first light-emitting control sub-circuit S1, and a second light-emitting control sub-circuit S2; the display panel also includes: a first light-emitting control line EM2, a second light-emitting control line EM3; the first light-emitting control sub-circuit S1 is electrically connected to the first light-emitting control line EM2, and the first pixel portion P21 (specifically, it can be the first anode portion 205a in the first pixel portion P21), and is configured to drive the first pixel portion P21 to emit light under the control of the first light-emitting control line EM2; the second light-emitting control sub-circuit S2 is electrically connected to the second light-emitting control line, and the second pixel portion P22 (specifically, it can be the second anode portion 205b in the second pixel portion P22), and is configured to drive the second pixel portion P22 to emit light under the control of the second light-emitting control line EM3.

[0113] Specifically, in combination with FIG4A or FIG4B, the display panel further includes: a gate driving circuit, which may specifically include: a first sub-circuit (EM1-1...EM1-n), a second sub-circuit (EM2-1...EM2-n), a third sub-circuit (EM3-1...EM3-n), a fourth sub-circuit (Re1...Ren), and a fifth sub-circuit (GT1...GT n); wherein the second sub-circuit (EM2-1...EM2-n) may provide a first light-emitting control signal for a sub-pixel row, and transmit the signal to the sub-pixel row through a first light-emitting control line EM2, the third sub-circuit (EM3-1...EM3-n) may provide a second light-emitting control signal for a sub-pixel row, and transmit the signal to the sub-pixel row through a second light-emitting control line EM3, the first sub-circuit (EM1-1...EM1-n) may provide a third light-emitting control signal for a sub-pixel row, and transmit the signal to the sub-pixel row through a third light-emitting control line EM1, the fourth sub-circuit (Re1...Ren) may provide a reset signal for a sub-pixel row, and transmit the signal to the sub-pixel row through a reset signal line Re, and the fifth sub-circuit (GT1...GT n ... second light-emitting control signal for a sub n) can provide scan signals for sub-pixel rows and transmit them to the sub-pixel rows via scan signal lines GT. Specifically, the first sub-circuit (EM1-1 ... EM1-n) can include transistors and / or capacitors, the second sub-circuit (EM2-1 ... EM2-n) can include transistors and / or capacitors, the third sub-circuit (EM3-1 ... EM3-n) can include transistors and / or capacitors, the fourth sub-circuit (Re1 ... Ren) can include transistors and / or capacitors, and the fifth sub-circuit (GT1 ... GT n) can include transistors and / or capacitors.

[0114] In some examples, the first pixel portion P21 may include a stacked first anode portion 205a, a first organic light-emitting layer, and a first cathode. The second pixel portion P22 may include a stacked second anode portion 205b, a second organic light-emitting layer, and a second cathode. The first cathode of the first pixel portion P21 may be electrically connected to the second power supply line VSS. The second cathode of the second pixel portion P22 may be electrically connected to the second power supply line VSS. In some examples, as shown in FIG1D , the first anode portion 205a of the first pixel portion P21 and the second anode portion 205b of the second pixel portion P22 may be obtained by dividing the anode of the second sub-pixel P2 (e.g., dividing along the dotted line in FIG1D ).

[0115] In some examples, the first power line VDD can be configured to continuously provide a first voltage signal of high potential, and the second power line VSS can be configured to continuously provide a second voltage signal of low potential. The first voltage signal is greater than the second voltage signal.

[0116] In some examples, a plurality of transistors of a pixel circuit may adopt low-temperature polysilicon thin-film transistors, or may adopt oxide thin-film transistors, or may adopt low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor adopts low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor adopts oxide (Oxide). Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current. In some examples, low-temperature polysilicon thin-film transistors and oxide thin-film transistors can be integrated on a display panel to form a low-temperature polycrystalline oxide display panel, which can take advantage of the advantages of both, achieve high resolution (PPI, Pixel Per Inch), low-frequency drive, reduce power consumption, and improve display quality. However, this embodiment is not limited to this.

[0117] Figure 3 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. In some examples, as shown in Figure 3, the pixel circuit can be a 9T1C structure. The pixel circuit can include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a storage capacitor Cst. The first light-emitting control subcircuit S1 can include: an eighth transistor T8; and the second light-emitting control subcircuit S2 can include: a ninth transistor T9. In the circuit structure shown in Figure 3, the first transistor T1 can be a reset transistor, the second transistor T2 can be a threshold compensation transistor, the third transistor T3 can be a driving transistor, the fourth transistor T4 can be a data writing transistor, the fifth transistor T5 can be a light-emitting control transistor, the sixth transistor T6 can be a light-emitting control transistor, the seventh transistor T7 can be a reset transistor, the eighth transistor T8 can be a light-emitting control transistor, and the ninth transistor T9 can be a light-emitting control transistor.

[0118] In some examples, as shown in FIG3 , the gate of the first transistor T1 is electrically connected to the first reset control line Re1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line Vint1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The gate of the second transistor T2 is electrically connected to the scan line GT, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3. The gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the scan line GT, the first electrode of the fourth transistor T4 is electrically connected to the data line Vdata, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The gate of the fifth transistor T5 is electrically connected to the third emission control line EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the third emission control line EM1, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the seventh transistor T7 is electrically connected to the second reset control line Re2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line Vint2, and the second electrode of the seventh transistor T7 is electrically connected to the fifth node N5 (i.e., the first anode portion 205a of the first pixel portion P21). The gate of the eighth transistor T8 is electrically connected to the first emission control line EM2, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first anode portion 205a of the first pixel portion P21. The gate of the ninth transistor T9 is electrically connected to the second emission control line EM3, the first electrode of the ninth transistor T9 is electrically connected to the fourth node N4, and the second electrode of the ninth transistor T9 is electrically connected to the second anode portion 205b of the second pixel portion P22. A first electrode of the storage capacitor Cst is electrically connected to the first node N1 , and a second electrode of the storage capacitor Cst is electrically connected to the first power line VDD.

[0119] In some examples, the first node N1 is a connection point between the first transistor T1, the second transistor T2, the third transistor T3, and the storage capacitor Cst. The second node N2 is a connection point between the third transistor T3, the fourth transistor T4, and the fifth transistor T5. The third node N3 is a connection point between the third transistor T3, the second transistor T2, and the sixth transistor T6. The fourth node N4 is a connection point between the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9. The fifth node N5 is a connection point between the seventh transistor T7, the eighth transistor T8, and the first anode portion 205a of the first pixel portion P21.

[0120] In some examples, the nine transistors of the pixel circuit are all P-type transistors. The second reset control line Re2 can be connected to the scan line GT to be input with a scan signal. In the local anti-peeping mode, the first light-emitting control line EM2 can continuously provide a low-level signal, so that the third control transistor T8 is turned on, and the first pixel portion P21 is in a light-emitting state; the second light-emitting control line EM3 can continuously provide a high-level signal, so that the fourth control transistor T9 is turned off, and the second pixel portion P22 is in a non-light-emitting state. In the shared (normal) display mode, the first light-emitting control line EM2 can continuously provide a high-level signal, so that the third control transistor T8 is turned off, and the first pixel portion P21 is in a non-light-emitting state; the second light-emitting control line EM3 can continuously provide a low-level signal, so that the fourth control transistor T9 is turned on, and the second pixel portion P22 is in a light-emitting state.

[0121] The above pixel circuit is only an example, and the present embodiment does not limit the structure of the pixel circuit.

[0122] After the first subpixel P1 of the first display area AA1 is divided as shown in FIG1A , the third pixel portion P11 and the fourth pixel portion P12 of the same first subpixel P1 can be driven to emit light by the same pixel circuit. The first subpixel P1 includes: a first pixel circuit; a third anode portion 205c and a fourth anode portion 205d electrically connected to the first pixel circuit. The structure of the first pixel circuit can be consistent with the circuit structure shown in FIG3 , and the driving process is similar, so it will not be repeated here.

[0123] In a possible embodiment, referring to Figures 5A, 6A and 6B, wherein Figure 6A may be a cross-sectional schematic diagram along the dotted line A1A2 in Figure 5A, and Figure 6B may be a cross-sectional schematic diagram along the dotted line A3A4 in Figure 5A, at least one first sub-pixel P1 among the multiple first sub-pixels P1 includes: a third pixel portion P11, and a fourth pixel portion P12; the light-emitting area of ​​the third pixel portion P11 is smaller than the light-emitting area of ​​the fourth pixel portion P12.

[0124] In a possible embodiment, referring to Figures 5A, 6A and 6B, at least one first sub-pixel P1 among the multiple first sub-pixels P1 includes: a third pixel portion P21, and a fourth pixel portion P22; the first blocking layer 106 also includes: a third opening K3, and a fourth opening K4; the orthographic projection of the third opening K3 on the substrate 101 has an overlapping area with the orthographic projection of the third pixel portion P21 on the substrate 101; the orthographic projection of the fourth opening K4 on the substrate 101 has an overlapping area with the orthographic projection of the fourth pixel portion P22 on the substrate 101, and the orthographic projection area of ​​the third opening K3 on the substrate 101 is smaller than the orthographic projection area of ​​the fourth opening K4 on the substrate 101. In this way, the luminous area of ​​the third pixel portion P11 is smaller than the luminous area of ​​the fourth pixel portion P12.

[0125] In the embodiment of the present disclosure, for the first display area AA1 that needs to display normally, the first sub-pixel P1 can also be divided, for example, into a third pixel portion P11 and a fourth pixel portion P12, and the light-emitting area of ​​the third pixel portion P11 is made smaller than the light-emitting area of ​​the fourth pixel portion P12, which can reduce the visual difference (such as brightness) between the first display area AA1 and the second display area AA2 during normal display.

[0126] Specifically, in combination with FIG5B and FIG5C, FIG5B is a schematic diagram of the display panel shown in FIG5A when performing anti-peeping display, and FIG5C is a schematic diagram of the display panel shown in FIG5A when performing normal display. When performing anti-peeping display, as shown in FIG5B, by making the third pixel portion P11 of the first display area AA1 display and the fourth pixel portion P12 also display, the first pixel portion P21 of the second display area AA2 is displayed and the second pixel portion P22 is not displayed, thereby enabling the first display area AA1 to display normally and the second display area AA2 to perform anti-peeping display; when performing normal display, as shown in FIG5C, by making the third pixel portion P11 of the first display area AA1 display and the fourth pixel portion P12 display, the second display area AA2 is not displayed. The first pixel portion P21 of area AA2 is displayed, and the second pixel portion P22 is also displayed, so that the first display area AA1 and the second display area AA2 can both be displayed normally. Moreover, during anti-peeping display, the third pixel portion P11 and the fourth pixel portion P12 of the first display area AA1 are both displayed, which can avoid the problem of a small light-emitting area and limited brightness of each first sub-pixel P1 in the first display area AA1 when only the third pixel portion P11 is displayed. During normal display, by displaying the third pixel portion P11 and the fourth pixel portion P12 of the first display area AA1 and displaying the first pixel portion P21 and the second pixel portion P22 of the second display area AA2, the visual difference between the first display area AA1 and the second display area AA2 can be reduced.

[0127] In one possible embodiment, when performing anti-peeping display, the third pixel portion P11 of the first display area AA1 is displayed, and the fourth pixel portion P12 is not displayed, and the first pixel portion P21 of the second display area AA2 is displayed, and the second pixel portion P22 is not displayed, so that the first display area AA1 can display normally, while the second display area AA2 performs anti-peeping display.

[0128] In one possible embodiment, for the display panel shown in Figure 5A, after the second sub-pixel P2 of the second display area AA2 is divided, the first pixel portion P21 and the second pixel portion P22 of the same sub-pixel P2 can be driven to emit light by the same pixel circuit. For example, the first pixel portion P21 and the second pixel portion P22 can be driven to emit light by the circuit shown in Figure 3.

[0129] In one possible embodiment, for the display panel shown in Figure 5A, after the second sub-pixel P2 of the second display area AA2 is divided, the first pixel portion P21 and the second pixel portion P22 of the same sub-pixel P2 can be driven to emit light through different pixel circuits. The first pixel portion P21 is driven by one pixel circuit, and the second pixel portion P22 is driven by another pixel circuit. That is, specifically, the second sub-pixel includes: a first sub-pixel circuit, and a second sub-pixel circuit; the first anode portion 205a is electrically connected to the first sub-pixel circuit P21; and the second anode portion 205b is electrically connected to the second sub-pixel circuit P22.

[0130] In a possible embodiment, the structures of the first sub-pixel circuit and the second sub-pixel circuit can be as shown in Figure 7, including: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9 and a first capacitor C1; wherein the gate of the first transistor T1 is electrically connected to the scan line GT, the first electrode of the first transistor T1 is electrically connected to the data line Vdata, and the second electrode of the first transistor T1 is electrically connected to the second node N2; the gate of the second transistor T2 is electrically connected to the scan line GT, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the gate of the third transistor T3 is electrically connected to the first node, and the third transistor T3 is electrically connected to the data line Vdata. The second electrode of the third transistor T3 is electrically connected to the third stage N3; the gate of the fourth transistor T4 is electrically connected to the reset signal line Re, the first electrode of the fourth transistor T4 is electrically connected to the first initial signal line Vint, and the second electrode of the fourth transistor T4 is electrically connected to the first node N1; the gate of the fifth transistor T5 is electrically connected to the reset signal line Re, the first electrode of the fifth transistor T5 is electrically connected to the reference signal line Vref, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the gate of the sixth transistor T6 is electrically connected to the first pixel row control line EMO (or the second pixel row control line EME, if the sub-pixel portion is located in the first pixel row P100, it is electrically connected to the first pixel row control line EMO, if the sub-pixel portion is located in the second pixel row P200, it is electrically connected to the second pixel row control line EME The first electrode of the sixth transistor T6 is electrically connected to the reference signal line Vref, and the second electrode of the sixth transistor T6 is electrically connected to the second node N2; the gate of the seventh transistor T7 is electrically connected to the first pixel row control line EMO (or the second pixel row control line EME, if the sub-pixel portion is located in the first pixel row P100, it is electrically connected to the first pixel row control line EMO, if the sub-pixel portion is located in the second pixel row P200, it is electrically connected to the second pixel row control line EME), the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the reset signal line Re, the first electrode of the eighth transistor T8 is electrically connected to the second initial signal line Vint2, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the gate of the ninth transistor T9 is electrically connected to the first pixel row control line EMO (or the second pixel row control line EME, if the sub-pixel portion is located in the first pixel row P100, it is electrically connected to the first pixel row control line EMO, if the sub-pixel portion is located in the second pixel row P200, it is electrically connected to the second pixel row control line EME), and the first and second electrodes of the ninth transistor T9 are electrically connected to the first node N1;A first end of the first capacitor C1 is electrically connected to the first node N1, a second end of the first capacitor C1 is electrically connected to the second node N2, the first anode portion 205a of the first pixel portion P21 (or the second anode portion 205b of the second pixel portion P22, or the third anode portion 205c of the third pixel portion P11, or the fourth anode portion 205d of the fourth pixel portion P12) is electrically connected to the fourth node N4, and the cathode of the first pixel portion P21 (or the cathode of the second pixel portion P22, or the cathode of the third pixel portion P11, or the cathode of the fourth pixel portion P12) is electrically connected to the second power signal line VSS.

[0131] In some examples, the first node N1 is a connection point between the first capacitor C1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the ninth transistor T9. The second node N2 is a connection point between the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the first capacitor C1. The third node N3 is a connection point between the third transistor T3, the second transistor T2, and the seventh transistor T7. The fourth node N4 is a connection point between the seventh transistor T7, the eighth transistor T8, and the first anode portion 205a of the first pixel portion P21 (or the second anode portion 205b of the second pixel portion P22, or the third anode portion 205c of the third pixel portion P11, or the fourth anode portion 205d of the fourth pixel portion P12).

[0132] The driving and emitting process of the 9T1C pixel circuit shown in FIG7 may be similar to the driving and emitting process of a conventional 9T1C pixel circuit, and will not be further described in detail in the embodiment of the present disclosure.

[0133] In one possible embodiment, as shown in FIG8 , the plurality of second sub-pixels P2 include: a first pixel row P100 (for example, an odd-numbered pixel row may be used as the first pixel row) and a second pixel row P200 (for example, an even-numbered pixel row may be used as the second pixel row); the first pixel row P100 and the second pixel row P200 extend along a first direction X and are alternately arranged along a second direction Y; the first pixel row P100 includes: a plurality of first pixel portions P21; the second pixel row P200 includes: a plurality of second pixel portions P22;

[0134] The display panel also includes: a first pixel row control line EMO, and a second pixel row control line EME; the first pixel row control line EMO is electrically connected to the first pixel portion P21 of the first pixel row P100, and the second pixel row control line EME is electrically connected to the second pixel portion P22 of the second pixel row P200; the first pixel row control line EMO is configured to provide a signal to the first pixel portion P21 of the first pixel row P100, and the second pixel control line EME is configured to provide a signal to the second pixel portion P22 of the second pixel row P200.

[0135] In one possible embodiment, the first direction X may be a row direction of sub-pixels, and the second direction Y may be a column direction of sub-pixels; in one possible embodiment, the first direction X may be a direction from the first display area AA1 to the second display area AA2, and the second direction Y may be a direction perpendicular to the first direction X.

[0136] In a possible embodiment, the first pixel row P100 may further include a plurality of third pixel portions P11 of the first sub-pixel P1, and the second pixel row P200 may further include a plurality of fourth pixel portions P12 of the first sub-pixel P1, that is, the third pixel portion P11 of the first display area AA1 and the first pixel P21 of the second display area AA2 are located in odd rows, and signals are provided by the first pixel row control line EMO, and the fourth pixel portion P12 of the first display area AA1 and the second pixel P22 of the second display area AA2 are located in even rows, and signals are provided by the second pixel row control line EME.

[0137] In one possible embodiment, referring to Figures 9A, 10A, and 10B, at least one first sub-pixel P1 among the plurality of first sub-pixels P1 is an integrally connected structure. That is, the first sub-pixel P1 of the first display area AA1 may be an undivided sub-pixel, similar to the sub-pixels of a conventional display panel. Specifically, referring to Figures 9A, 10A, and 10B, the first shielding layer 106 further includes: a fifth opening K5; the orthographic projection of the fifth opening K5 on the substrate 101 has an overlapping area with the orthographic projection of the first sub-pixel P1 on the substrate 101. That is, the fifth opening K5 may be the undivided first sub-pixel P1 corresponding to the first display area AA1.

[0138] In the embodiment of the present disclosure, for the first display area AA1 that needs to display normally, the first sub-pixel P1 does not need to be divided. That is, the first sub-pixel P1 is an integrated connection structure, and only the second sub-pixel of the second display area AA2 can be divided, thereby reducing the difficulty of manufacturing the display panel.

[0139] In one possible embodiment, for the display panel shown in Figure 9A, after the second sub-pixel P2 of the second display area AA2 is divided, in one possible embodiment, the first pixel portion P21 and the second pixel portion P22 can be driven by the same pixel circuit, and the specific pixel circuit can be as shown in Figure 3; in another possible embodiment, the first pixel portion P21 and the second pixel portion P22 can be driven by different pixel circuits, and each pixel circuit can be as shown in Figure 7; for the first sub-pixel P1 of the first display area AA1 is not divided, in one possible embodiment, the pixel circuit driving of the first sub-pixel P1 can be specifically shown in Figure 7.

[0140] In one possible embodiment, for the display panel shown in Figure 9A, the first sub-pixel P1 of the first display area AA1 is not divided, and the second sub-pixel P2 of the second display area AA2 is divided. For the second display AA2, the connection relationship of the signal lines within the display panel can be as shown in Figure 4A; and for the first display area AA1, the connection relationship of the signal lines within the display panel can be as shown in Figure 11. The difference from Figure 4A is that in a row of sub-pixels, there is only the first sub-pixel P1, rather than the divided first pixel portion P21 and second pixel portion P22.

[0141] In one possible embodiment, as shown in Figures 9A, 10A, and 10B, the light-emitting area of ​​the first subpixel P1 is greater than or equal to the sum of the light-emitting areas of the first subpixel portion P21 and the second subpixel portion P22. Specifically, the orthographic projection area of ​​the fifth opening K5 on the substrate 101 is greater than or equal to the sum of the orthographic projection areas of the first opening K1 and the second opening K2 on the substrate 101. This allows the first display area AA1, which is performing normal display, to have higher brightness and better display quality.

[0142] Specifically, in combination with Figures 9B and 9C, Figure 9B is a schematic diagram of the display panel shown in Figure 9A when performing anti-peeping display, and Figure 9C is a schematic diagram of the display panel shown in Figure 9A when performing normal display. When performing anti-peeping display, as shown in Figure 9B, by making the first sub-pixel P1 of the first display area AA1 displayed, the first pixel portion P21 of the second display area AA2 is displayed, and the second pixel portion P22 is not displayed, the first display area AA1 can be displayed normally, while the second display area AA2 performs anti-peeping display; when performing normal display, as shown in Figure 9C, by making the first sub-pixel P1 of the first display area AA1 displayed, the first pixel portion P21 of the second display area AA2 is not displayed, and the second pixel portion P22 is displayed, so that both the first display area AA1 and the second display area AA2 can be displayed normally.

[0143] In one possible embodiment, referring to Figures 2C and 2D , Figure 2D is a schematic diagram illustrating the distribution of multiple first sub-openings K10 at the first opening K1 in Figure 2C . The first opening K1 includes multiple first sub-openings K10 distributed in an array. This can limit the emission angle of the first opening K1, facilitating a privacy protection effect.

[0144] In a possible implementation, the orthographic projection shape of the first sub-opening K10 on the substrate 101 is at least one of a rectangle, a hexagon, an octagon, a circle, or an ellipse.

[0145] In one possible embodiment, the orthographic projection pattern of the first opening K1 on the substrate 101 may be at least one of a rectangle, a hexagon, an octagon, a circle or an ellipse; in one possible embodiment, the orthographic projection pattern of the second opening K2 on the substrate 101 may be at least one of a rectangle, a hexagon, an octagon, a circle or an ellipse; in one possible embodiment, the orthographic projection pattern of the first light outlet Q1 on the substrate 101 may be at least one of a rectangle, a hexagon, an octagon, a circle or an ellipse; in one possible embodiment, the orthographic projection pattern of the second light outlet Q2 on the substrate 101 may be at least one of a rectangle, a hexagon, an octagon, a circle or an ellipse.

[0146] In one possible implementation, as shown in FIG2A , the first pixel portion P21 includes a first anode portion 205a, and the second pixel portion includes a second anode portion 205b. The orthographic projection area of ​​the first anode portion 205a on the substrate 101 is smaller than the orthographic projection area of ​​the second anode portion 205b on the substrate 101. In this manner, the light-emitting area of ​​the first pixel portion P21 is smaller than the light-emitting area of ​​the second pixel portion P22.

[0147] In a possible embodiment, in combination with what is shown in FIG2B , at least one first sub-pixel P1 among the plurality of first sub-pixels P1 includes: a third pixel portion P11, and a fourth pixel portion P12; the third pixel portion P11 has a third anode portion 205c, and the fourth pixel portion P12 has a fourth anode portion 205d; an orthographic projection area of ​​the third anode portion 205c on the substrate 101 is equal to an orthographic projection area of ​​the fourth anode portion 205d on the substrate 101, and both are equal to an orthographic projection area of ​​the second anode portion 205b on the substrate 101.

[0148] In a possible embodiment, as shown in Figure 10B, at least one first sub-pixel P1 among the multiple first sub-pixels P1 is an integrated connection structure; the first sub-pixel portion P1 includes: a fifth anode portion 205e; the positive projection area of ​​the fifth anode portion 205e on the substrate 101 is greater than or equal to the sum of the positive projection areas of the first anode portion 205a and the second anode portion 205b on the substrate 101.

[0149] In a possible embodiment, in combination with Figure 2A, the display panel also includes: a second light-shielding layer 107 located on the side of the first light-shielding layer 106 facing the substrate 101; the second light-shielding layer 107 includes: a first light outlet Q1, and a second light outlet Q2; the orthographic projection of the first light outlet Q1 on the substrate 101 has an overlapping area with the orthographic projection of the first opening K1 on the substrate 101; the orthographic projection of the second light outlet Q2 on the substrate 101 has an overlapping area with the orthographic projection of the second opening K2 on the substrate 101. In the embodiment of the present disclosure, by setting two shading layers (i.e., the first shading layer 106 and the second shading layer 107), the emission angle of the first sub-pixel portion P21 (or the second sub-pixel portion P22, or the third sub-pixel portion P11, or the fourth sub-pixel portion P22) can be limited (for example, the anti-peeping viewing angle limited by the first shading layer 106 alone may be only 60o, and after adding the second shading layer 107, the anti-peeping viewing angle can be reduced to 30o), which is conducive to achieving an anti-peeping effect.

[0150] In one possible embodiment, the orthographic projection area of ​​the first light outlet Q1 on the substrate 101 may be smaller than the orthographic projection area of ​​the first opening K1 on the substrate 101; the orthographic projection area of ​​the second light outlet Q2 on the substrate 101 may be smaller than the orthographic projection area of ​​the second opening K2 on the substrate 101, so as to limit the emission angle of the first sub-pixel portion P21 (or the second sub-pixel portion P22, or the third sub-pixel portion P11, or the fourth sub-pixel portion P22), thereby facilitating the realization of an anti-peeping effect.

[0151] In one possible embodiment, the orthographic projection area of ​​the first light outlet Q1 on the substrate 101 may be smaller than the orthographic projection area of ​​the second light outlet Q2 on the substrate 101, so that the second sub-pixel portion P22 of the second display area AA2 can achieve viewing angle limitation in other directions (for example, the second display area AA2 corresponding to the co-pixel can be emitted at an angle in the direction of the windshield).

[0152] In a possible implementation manner, the orthographic projection area of ​​the first light outlet Q1 on the substrate 101 may be equal to the orthographic projection area of ​​the second light outlet Q2 on the substrate 101 .

[0153] This embodiment does not limit the number of light shielding layers. In other examples, the number of light shielding layers can be greater than or equal to three, and a protective layer can be provided between adjacent light shielding layers.

[0154] Figure 2A is an example diagram of a partial cross-section along the A1A2 direction in Figure 1A. Figure 2A illustrates a partial cross-sectional structure of a second sub-pixel P2. In some examples, as shown in Figure 2A, in a direction perpendicular to the display panel, the display panel may include: a base substrate 101, a display structure layer sequentially arranged on the base substrate 101, an encapsulation structure layer 104, a second shielding layer 107, a first protective layer 105, and a first shielding layer 106. The display structure layer may include: a circuit structure layer 102 and a light-emitting structure layer 103 sequentially arranged on the base substrate 101. In some possible implementations, the display panel may include other film layers, such as spacers, etc., which are not limited in this disclosure. Among them, the circuit structure layer 102 may include: a buffer layer 210, a semiconductor layer 201, a first insulating layer 211, a first gate metal layer 204, a second insulating layer 212, a first source and drain metal layer 202, and a third insulating layer 213 sequentially arranged on the base substrate 101.

[0155] In one possible embodiment, referring to FIG. 12A or FIG. 13A , the display panel further includes: a lens layer located on the side of the first light-shielding layer 106 facing away from the substrate 101; the lens layer may include: a first lens 108a and a second lens 108b; the first lens 108a covers the orthographic projection of the first opening K1 on the substrate 101; the orthographic projection of the second lens 108b on the substrate 101 covers the orthographic projection of the second opening K2 on the substrate 101. In the embodiment of the present disclosure, the display panel further includes: a first lens 108a and a second lens 108b; the orthographic projection of the first lens 108a on the substrate 101 covers the orthographic projection of the first opening K1 on the substrate 101; the orthographic projection of the second lens 108b on the substrate 101 covers the orthographic projection of the second opening K2 on the substrate 101. The first lens 108a and the second lens 108b can be used to converge light from corresponding light outlets, thereby improving the brightness of the light output of the display panel.

[0156] In a possible embodiment, referring to FIG. 12A or FIG. 13A , the display panel further includes: an encapsulation layer 104 , and a touch layer 109 located on a side of the encapsulation layer 104 facing away from the substrate; and a first light shielding layer 106 located on a side of the encapsulation layer 104 facing away from the substrate 101 .

[0157] In one possible embodiment, referring to FIG12A or FIG13B , the touch layer 109 may be located on the side of the first light-shielding layer 106 facing the substrate 101; specifically, as shown in FIG12A , the touch layer 109 may be located on the side of the second light-shielding layer 107 facing the substrate 101; specifically, the touch layer 109 may be a film layer in contact with the second light-shielding layer 107; specifically, as shown in FIG13B , the touch layer 109 may also be a film layer in contact with the first light-shielding layer 106.

[0158] In another possible embodiment, as shown in FIG13A , the touch layer 109 can be located on the side of the first light-shielding layer 106 facing away from the substrate 101. Specifically, a first protective layer 105 can be disposed between the touch layer 109 and the first light-shielding layer 106. Specifically, the touch layer 109 can be a film layer in contact with the lens layer. Specifically, when the touch layer 109 is located on the side of the lens layer facing the substrate 101, the touch layer 109 can replace a light-shielding layer. For example, as shown in FIG12A and FIG13A , the touch layer 109 can replace the second light-shielding layer 107.

[0159] In a possible implementation, as shown in FIG12A , a second protective layer 110 , an optical adhesive layer 111 , a polarizer 112 , and a cover plate 113 may be sequentially provided on the side of the lens layer facing away from the substrate 101 .

[0160] In one possible embodiment, in the embodiment of the present disclosure, the display panel may be provided with a color filter layer on the encapsulation layer 104, that is, it may be COE (CF On TFE). For example, as shown in Figure 2A, Figure 12B or Figure 13B, the color filter layer may include a first color resist CR (for example, red color resist) located at the first opening K1 and the second opening K2, and the color filter layer may also include a second color resist (for example, green color resist, not shown in Figure 2A) and a third color resist (for example, blue color resist, not shown in Figure 2A); in one possible embodiment, in the embodiment of the present disclosure, the display panel may also be a non-COE structure. For example, in combination with Figure 12A or Figure 13A, the display panel may be provided with a polarizer 112.

[0161] In a possible implementation, the first light-shielding layer 106 and the second light-shielding layer 107 may be black matrix layers.

[0162] In one possible implementation, as shown in FIG14 , among the first sub-pixel P1 and the second sub-pixel P2, at least the second sub-pixel P2 includes: a plurality of light-emitting bodies F stacked in a direction perpendicular to the substrate 101; the light-emitting bodies F include one or a combination of the following stacked film layers:

[0163] hole transport layer 207;

[0164] light-emitting layer 206;

[0165] Electron transport layer 208 .

[0166] In the embodiment of the present disclosure, at least the second sub-pixel P2 includes: a plurality of light-emitting bodies F stacked in a direction perpendicular to the substrate 101, that is, the second sub-pixel P2 is set to a stacked structure, which can improve the brightness of the second sub-pixel P2 and solve the problem of low brightness and / or life of the second sub-pixel P2 in the anti-peep display area after being divided.

[0167] In a possible implementation, as shown in FIG14 , a charge transfer layer CGL may be further provided between two adjacent light-emitting bodies F.

[0168] In some exemplary embodiments, the display panel may be an organic light emitting diode (OLED) display panel, or a quantum dot light emitting diode (QLED) display panel, or a plasma display device (PDP) display panel, or an electrophoretic display (EPD) display panel. This embodiment is not limited thereto.

[0169] In one possible embodiment, the display panel may have only one first display area AA1 and one second display area AA2, and the first display area AA1 is located on one side of the second display area AA2, as shown in FIG1A ; in another possible embodiment, the display panel may also have more first display areas AA1 and more second display areas AA2. For example, as shown in FIG15 , the display panel may have two first display areas AA1 and one second display area AA2, wherein the second display area AA2 is located between the two first display areas AA1.

[0170] In one possible embodiment, for the first display area AA1, the viewing angle of the first sub-pixel P1 in a direction perpendicular to the sub-pixel row can also be reduced. For example, the width of the first light-shielding layer 106 in the sub-pixel column direction can be reduced. Furthermore, when the display panel is used in an automotive application, the width of the first sub-pixel P1 in the sub-pixel column direction (i.e., perpendicular to the sub-pixel row direction) can be reduced when the sub-pixel row direction is the direction from the first display area AA1 to the second display area AA2. This can reduce the viewing angle of the first sub-pixel P1 in the direction of light emitted to the windshield, thereby preventing the image displayed in the first display area AA1 from being reflected on the windshield and affecting the driver's normal line of sight. For example, an anti-peeping function can be provided at the driver's seat; for example, a function of anti-peeping up and down but not anti-peeping left and right can be provided.

[0171] FIG17 is a schematic diagram of the structure of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in FIG17 , the display panel may include: a timing controller 20, a data driver 40, a gate drive circuit, and a sub-pixel array 10. The gate drive circuit may include at least one driver, such as a scan driver 30. The timing controller 20, the data driver 40, and the gate drive circuit may be located in a peripheral area outside the display area of ​​the display panel. The sub-pixel array 10 located in the display area may include a plurality of sub-pixels PX arranged in a regular pattern. The scan driver 30 may be configured to provide a scan signal to the sub-pixel PX along a scan line; the data driver 40 may be configured to provide a data signal to the sub-pixel PX along a data line; and the timing controller 20 may be configured to control the scan driver 30 and the data driver 40.

[0172] In some examples, the timing controller 20 may provide grayscale values ​​and control signals suitable for the specifications of the data driver 40 to the data driver 40. The timing controller 20 may also provide clock signals, initial signals, and other signals suitable for the specifications of the scan driver 30 to the scan driver 30. The data driver 40 may use the grayscale values ​​and control signals received from the timing controller 20 to generate data voltages to be supplied to the data lines D1 to Dn. For example, the data driver 40 may use the clock signal to sample the grayscale values ​​and apply data signals corresponding to the grayscale values ​​to the data lines D1 to Dn on a sub-pixel row basis. The scan driver 30 may use the clock signal, initial signals, and other signals received from the timing controller 20 to generate scan signals to be supplied to the scan lines G1 to Gm. For example, the scan driver 30 may sequentially supply scan signals having on-level pulses to the scan lines. In some examples, the scan driver 30 may include a shift register that sequentially transmits scan initial signals provided in the form of on-level pulses to the next stage of circuitry under the control of the clock signal to generate the scan signals. Where n and m are both natural numbers.

[0173] In some examples, the gate driver circuit can be directly provided on the base substrate. For example, the gate driver can be provided in the peripheral areas on the left and right sides of the display area. In some examples, the gate driver can be formed together with the sub-pixel in the process of forming the sub-pixel. However, this embodiment does not limit the location or formation method of the gate driver. In some examples, the gate driver can be provided on a separate chip or printed circuit board to connect to the pads or pads formed on the base substrate.

[0174] In some examples, the data driver 40 can be provided on a separate chip or printed circuit board, and connected to the sub-pixels PX via signal access pins provided on the substrate. For example, the data driver 40 can be provided using a chip on glass, a chip on plastic, a chip on film, etc., and connected to the signal access pins on the substrate. The timing controller 20 can be provided separately from the data driver 40 or integrated with the data driver 40. However, this embodiment is not limited to this.

[0175] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0176] Based on the same inventive concept, the embodiment of the present disclosure further provides a method for driving a display panel provided by the embodiment of the present disclosure, as shown in FIG18 , which includes:

[0177] Step S100: When it is determined that the normal display mode is to be used, at least part of the first sub-pixels in the first display area and at least part of the second sub-pixels in the second display area are controlled to emit light;

[0178] Step S200: When it is determined to be in the partial anti-peeping display mode, at least a portion of the first sub-pixels in the first display area and a portion of the first pixel in the second display area are controlled to emit light.

[0179] In one possible embodiment, with respect to the display panel corresponding to FIG1A , that is, when the second sub-pixel P2 of the second display area AA2 is divided into a first pixel portion P21 for privacy protection and a second pixel portion P22 for normal display, and when the first sub-pixel P1 of the first display area AA1 is divided into two third pixel portions P11 and a fourth pixel portion P12 for normal display, in different display modes, with respect to step S100, when determining to perform the normal display mode, controlling the first sub-pixel of the first display area and at least the second pixel portion of the second display area to emit light includes: when determining to perform the normal display mode, controlling the fourth pixel portion P12 of the first display area AA1 and the second pixel portion P22 of the second display area AA2 to emit light, as shown in FIG1C ;

[0180] Regarding step 2100, when determining to perform the partial anti-peeping display mode, controlling at least a portion of the first sub-pixels in the first display area and the first sub-pixel portion in the second display area to emit light includes: controlling the third pixel portion P11 of the first display area AA1 and the first pixel portion P21 of the second display area AA2 to emit light, as shown in Figure 1B.

[0181] In one possible embodiment, with respect to the display panel corresponding to FIG5A , that is, when the second sub-pixel P2 of the second display area AA2 is divided into a first pixel portion P21 for privacy protection and a second pixel portion P22 for normal display, and when the first sub-pixel P1 of the first display area AA1 is divided into a third pixel portion P11 for privacy protection and a fourth pixel portion P12 for normal display, in different display modes, with respect to step S100, when determining to perform the normal display mode, controlling the first sub-pixel of the first display area and at least the second pixel portion of the second display area to emit light includes: when determining to perform the normal display mode, controlling all first sub-pixels P1 of the first display area AA1 and all second sub-pixels P2 of the second display area AA2 to emit light, as shown in FIG5C ;

[0182] Regarding step S200, when determining to perform the partial anti-peeping display mode, controlling at least a portion of the first sub-pixels in the first display area and a portion of the first sub-pixels in the second display area to emit light includes: controlling all the first sub-pixels P1 in the first display area AA1 and a portion of the first pixel P21 in the second display area AA2 to emit light, as shown in FIG5B .

[0183] In one possible embodiment, regarding the display panel corresponding to FIG9A , that is, when the second sub-pixel P2 of the second display area AA2 is divided into a privacy-preventing first pixel portion P21 and a normal display second pixel portion P22, and the first sub-pixel P1 of the first display area AA1 is not divided, in different display modes, regarding step S100, when determining to use the normal display mode, controlling the first sub-pixel of the first display area and at least the second pixel portion of the second display area to emit light, includes: when determining to use the normal display mode, controlling all the first sub-pixels P1 of the first display area AA1 and the second pixel portion P22 of the second display area AA2 to emit light, as shown in FIG9C ;

[0184] Regarding step S200, when determining to perform the partial anti-peeping display mode, controlling at least a portion of the first sub-pixels in the first display area and a portion of the first sub-pixels in the second display area to emit light includes: controlling all the first sub-pixels P1 in the first display area AA1 and a portion of the first pixel P21 in the second display area AA2 to emit light, as shown in FIG9B .

[0185] In a possible implementation, in an embodiment of the present disclosure, the driving method further includes: step S300, when determining that there is a difference in brightness between the first display area and the second display area during normal display mode, calling a stored relationship table to adjust the brightness of the first display area to be consistent with that of the second display area, wherein the relationship table includes: a gamma correction relationship table (Gama Look-Up Table, Gama LUT), and / or a moiré correction relationship table (Demura LUT), and / or a brightness attenuation relationship table (De Burn-in LUT).

[0186] Specifically, for the display panel structure corresponding to FIG1A , that is, when the second sub-pixel P2 of the second display area AA2 is divided into the first pixel portion P21 for anti-peeping and the second pixel portion P22 for normal display, and the first sub-pixel P1 of the first display area AA1 is divided into two third pixel portions P11 and fourth pixel portions P12 for normal display, a first Gama LUT, a second Gama LUT, and a third Gama LUT can be correspondingly stored in the display device, wherein the first Gama LUT corresponds to the first display area AA1 and is used for correcting the brightness of the first display area AA1 in the anti-peeping display mode; the second Gama LUT corresponds to the second display area AA2 and is used for correcting the brightness of the second display area AA2 in the anti-peeping mode; the third Gama LUT corresponds to the first display area AA1 and the second display area AA2 and is used for correcting the brightness of the first display area AA1 and the second display area AA2 in the normal display (i.e., shared display) mode; in addition, the display device may further store a first Demura LUT and a second Demura LUT, wherein the first Demura The LUT corresponds to the first display area AA1 and the second display area AA2, and is used to correct the brightness of the first display area AA1 and the second display area AA2 during anti-peeping display; the second Demura LUT corresponds to the first display area AA1 and the second display area AA2, and is used to correct the brightness of the first display area AA1 and the second display area AA2 during shared display; in addition, the display device may further store a first De Burn-in LUT, a second De Burn-in LUT, and a third De Burn-in LUT, wherein the first De Burn-in LUT corresponds to the first display area AA1, and is used to correct the brightness of the first display area AA1 in the anti-peeping display mode; the second De Burn-in LUT corresponds to the second display area AA2, and is used to correct the brightness of the second display area AA2 in the anti-peeping display mode; the third De Burn-in LUT corresponds to the first display area AA1 and the second display area AA2, and is used to correct the brightness of the first display area AA1 and the second display area AA2 in the shared display mode.

[0187] Specifically, for the display panel structure corresponding to FIG1A , that is, when the second sub-pixel P2 of the second display area AA2 is divided into the first pixel portion P21 for anti-peeping and the second pixel portion P22 for normal display, and the first sub-pixel P1 of the first display area AA1 is divided into two third pixel portions P11 and fourth pixel portions P12 for normal display, the display device may store a first Gama LUT and a second Gama LUT; wherein the first Gama LUT corresponds to the second display area AA2 and is used to correct the brightness of the second display area AA2 during anti-peeping display; the second Gama LUT corresponds to the first display area AA1 and the second display area AA2 and is used to correct the brightness of the first display area AA1 during anti-peeping display, and is used to correct the brightness of the first display area AA1 and the second display area AA2 during shared display; in addition, the display device may store a first Demura LUT and a second Demura LUT; wherein the first Demura The LUT corresponds to the first display area AA1 and the second display area AA2, and is used to correct the brightness of the first display area AA1 and the second display area AA2 during anti-peeping display; the second Demura LUT corresponds to the first display area AA1 and the second display area AA2, and is used to correct the brightness of the first display area AA1 and the second display area AA2 during shared display; in addition, the display device may store a first De Burn-in LUT, a second De Burn-in LUT, and a third De Burn-in LUT; wherein the first De Burn-in LUT corresponds to the first display area AA1, and is used to correct the brightness of the first display area AA1 during anti-peeping display; the second De Burn-in LUT corresponds to the second display area AA2, and is used to correct the brightness of the second display area AA2 during anti-peeping display and shared display; the third De Burn-in LUT corresponds to the second display area AA2, and is used to correct the brightness of the second display area AA2 during shared display;

[0188] Specifically, for the display panel structure corresponding to FIG9A , that is, the second sub-pixel P2 of the second display area AA2 is divided into the first pixel portion P21 for anti-peeping and the second pixel portion P22 for normal display, and the first sub-pixel P1 of the first display area AA1 is not divided, a first Gama LUT, a second Gama LUT, and a third Gama LUT can be correspondingly stored in the display device, wherein the first Gama LUT corresponds to the first display area AA1, and is used for correcting the brightness of the first display area AA1 in the anti-peeping display mode and the shared display mode; the second Gama LUT corresponds to the second display area AA2, and is used for correcting the brightness of the second display area AA2 in the anti-peeping mode; the third Gama LUT corresponds to the second display area AA2, and is used for correcting the brightness of the second display area AA2 in the shared display mode; in addition, the display device may further store a first Demura LUT and a second Demura LUT, wherein the first Demura The LUT corresponds to the first display area AA1 and the second display area AA2, and is used to correct the brightness of the first display area AA1 and the second display area AA2 during anti-peeping display; the second Demura LUT corresponds to the first display area AA1 and the second display area AA2, and is used to correct the brightness of the first display area AA1 and the second display area AA2 during shared display; in addition, the display device may further store a first De Burn-in LUT, a second De Burn-in LUT, and a third De Burn-in LUT, wherein the first De Burn-in LUT corresponds to the first display area AA1, and is used to correct the brightness of the first display area AA1 in the anti-peeping display mode and the shared display mode; the second De Burn-in LUT corresponds to the second display area AA2, and is used to correct the brightness of the second display area AA2 in the anti-peeping display mode; the third De Burn-in LUT corresponds to the second display area AA2, and is used to correct the brightness of the second display area AA2 in the shared display mode.

[0189] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0190] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A display panel, wherein: include: A substrate having a first display area and a second display area; a plurality of first sub-pixels, located in the first display area; a plurality of second sub-pixels, located in the second display area; At least one second sub-pixel among the plurality of second sub-pixels includes a first pixel portion and a second pixel portion; wherein a light emitting area of ​​the first pixel portion is smaller than a light emitting area of ​​the second pixel portion.

2. The display panel according to claim 1, wherein: At least one first sub-pixel among the plurality of first sub-pixels includes a third pixel portion and a fourth pixel portion; a light emitting area of ​​the third pixel portion is equal to a light emitting area of ​​the fourth pixel portion.

3. The display panel according to claim 1, wherein: At least one first sub-pixel among the plurality of first sub-pixels includes a third pixel portion and a fourth pixel portion; a light-emitting area of ​​the third pixel portion is smaller than a light-emitting area of ​​the fourth pixel portion.

4. The display panel according to claim 2 or 3, wherein: The light emitting area of ​​the fourth pixel portion is equal to the light emitting area of ​​the second pixel portion.

5. The display panel according to claim 1, wherein: At least one first sub-pixel among the plurality of first sub-pixels is an integrally connected structure.

6. The display panel according to claim 5, wherein: A light-emitting area of ​​the first sub-pixel is greater than or equal to the sum of light-emitting areas of the first pixel portion and the second pixel portion.

7. The display panel according to any one of claims 1 to 6, wherein: The display panel includes: a first shielding layer; the first shielding layer includes: a first opening and a second opening; an orthographic projection of the first opening on the substrate overlaps with an orthographic projection of the first pixel portion on the substrate; an orthographic projection of the second opening on the substrate overlaps with an orthographic projection of the second pixel portion on the substrate; An orthographic projection area of ​​the first opening on the substrate is smaller than an orthographic projection area of ​​the second opening on the substrate.

8. The display panel according to claim 7, wherein: At least one first sub-pixel among the plurality of first sub-pixels includes: a third pixel portion and a fourth pixel portion; the first shielding layer further includes: a third opening and a fourth opening; an orthographic projection of the third opening on the substrate overlaps with an orthographic projection of the third pixel portion on the substrate; an orthographic projection of the fourth opening on the substrate overlaps with an orthographic projection of the fourth pixel portion on the substrate; The orthographic projection area of ​​the fourth opening on the substrate is equal to the orthographic projection area of ​​the second opening on the substrate.

9. The display panel according to claim 8, wherein: The orthographic projection area of ​​the third opening on the substrate is equal to the orthographic projection area of ​​the fourth opening on the substrate.

10. The display panel according to claim 8, wherein: An orthographic projection area of ​​the third opening on the substrate is smaller than an orthographic projection area of ​​the fourth opening on the substrate.

11. The display panel according to claim 7, wherein: At least one first sub-pixel among the plurality of first sub-pixels is an integrally connected structure; the first shielding layer further includes: a fifth opening; the orthographic projection of the fifth opening on the substrate has an overlapping area with the orthographic projection of the first sub-pixel on the substrate.

12. The display panel according to claim 11, wherein: The orthographic projection area of ​​the fifth opening on the substrate is greater than or equal to the sum of the orthographic projection areas of the first opening and the second opening on the substrate.

13. The display panel according to any one of claims 7 to 12, wherein: The first opening includes: a plurality of first sub-openings; the plurality of first sub-openings of the first opening are distributed in an array.

14. The display panel according to claim 13, wherein: The orthographic projection shape of the first sub-opening on the substrate is rectangular, hexagonal, octagonal, circular or elliptical.

15. The display panel according to any one of claims 1 to 14, wherein: The first pixel portion includes: a first anode portion; the second pixel portion includes: a second anode portion; The orthographic projection area of ​​the first anode portion on the substrate is smaller than the orthographic projection area of ​​the second anode portion on the substrate.

16. The display panel according to claim 15, wherein: At least one first sub-pixel among the plurality of first sub-pixels includes: a third pixel portion and a fourth pixel portion; the third pixel portion has a third anode portion, and the fourth pixel portion has a fourth anode portion; An orthographic projection area of ​​the third anode portion on the substrate is equal to an orthographic projection area of ​​the fourth anode portion on the substrate.

17. The display panel according to claim 16, wherein: At least one first sub-pixel among the plurality of first sub-pixels is an integrally connected structure; the first sub-pixel portion includes: a fifth anode portion; An orthographic projection area of ​​the fifth anode portion on the substrate is greater than or equal to the sum of the orthographic projection areas of the first anode portion and the second anode portion on the substrate.

18. The display panel according to any one of claims 7 to 17, wherein: The display panel further includes: a second light shielding layer located on a side of the first light shielding layer facing the substrate; The second light-shielding layer includes: a first light outlet and a second light outlet; the orthographic projection of the first light outlet on the substrate has an overlapping area with the orthographic projection of the first opening on the substrate; the orthographic projection of the second light outlet on the substrate has an overlapping area with the orthographic projection of the second opening on the substrate.

19. The display panel according to any one of claims 7 to 18, wherein: The display panel further includes: a lens layer located on a side of the first light shielding layer facing away from the substrate; The lens layer includes: a first lens and a second lens; the orthographic projection of the first lens on the substrate covers the orthographic projection of the first opening on the substrate; the orthographic projection of the second lens on the substrate covers the orthographic projection of the second opening on the substrate.

20. The display panel according to any one of claims 7 to 19, wherein: The display panel further includes: an encapsulation layer, and a touch layer located on a side of the encapsulation layer facing away from the substrate; the first light shielding layer is located on a side of the encapsulation layer facing away from the substrate.

21. The display panel according to any one of claims 1 to 20, wherein: Of the first sub-pixel and the second sub-pixel, at least the second sub-pixel includes: a plurality of light-emitting bodies stacked in a direction perpendicular to the substrate; the light-emitting bodies include one or a combination of the following film layers stacked: hole transport layer; a luminescent layer; Electron transport layer.

22. The display panel according to any one of claims 15 to 21, wherein: The second sub-pixel includes: a second pixel circuit; The first anode portion and the second anode portion are both electrically connected to the second pixel circuit.

23. The display panel according to claim 22, wherein: The second pixel circuit at least includes: a first light emitting control subcircuit and a second light emitting control subcircuit; the display panel further includes: a first light emitting control line and a second light emitting control line; The first light emitting control subcircuit is electrically connected to the first light emitting control line and the first anode portion, and is configured to drive the first pixel portion to emit light under the control of the first light emitting control line; The second light emitting control sub-circuit is electrically connected to the second light emitting control line and the second anode portion, and is configured to drive the second pixel portion to emit light under the control of the second light emitting control line.

24. The display panel according to any one of claims 15 to 21, wherein: The second sub-pixel includes: a first sub-pixel circuit and a second sub-pixel circuit; The first anode portion is electrically connected to the first sub-pixel circuit; and the second anode portion is electrically connected to the second sub-pixel circuit.

25. The display panel according to claim 24, wherein: The plurality of second sub-pixels include: a first pixel row and a second pixel row; the first pixel row and the second pixel row extend along a first direction and are alternately arranged along a second direction; the first pixel row includes: a plurality of first pixel portions; the second pixel row includes: a plurality of second pixel portions; The display panel also includes: a first pixel row control line, and a second pixel row control line; the first pixel row control line is electrically connected to the first pixel portion of the first pixel row, and the second pixel row control line is electrically connected to the second pixel portion of the second pixel row; the first pixel row control line is configured to provide a signal to the first pixel portion of the first pixel row, and the second pixel control line is configured to provide a signal to the second pixel portion of the second pixel row.

26. A display device, wherein: Comprising the display panel according to any one of claims 1-25.

27. A method for driving a display panel according to any one of claims 1 to 25, wherein: include: When determining to perform the normal display mode, controlling at least part of the first sub-pixels in the first display area and at least part of the second pixel portion in the second display area to emit light; When it is determined to perform the partial anti-peeping display mode, at least a portion of the first sub-pixels in the first display area and the first pixel portion in the second display area are controlled to emit light.

28. The driving method according to claim 27, wherein: When determining to perform the normal display mode, controlling the first sub-pixel of the first display area and at least the second pixel portion of the second display area to emit light includes: when determining to perform the normal display mode, controlling the fourth pixel portion of the first display area and the second pixel portion of the second display area to emit light; When determining to perform the partial anti-peeping display mode, controlling at least a portion of the first sub-pixels in the first display area and the first sub-pixel portion in the second display area to emit light includes: controlling the third pixel portion in the first display area and the first pixel portion in the second display area to emit light.

29. The driving method according to claim 27, wherein: When determining to perform the normal display mode, controlling the first sub-pixel in the first display area and at least the second pixel portion in the second display area to emit light includes: when determining to perform the normal display mode, controlling all of the first sub-pixels in the first display area and all of the second sub-pixels in the second display area to emit light; When determining to perform the partial anti-peeping display mode, controlling at least a portion of the first sub-pixels in the first display area and the first sub-pixel portion of the second display area to emit light includes: controlling all of the first sub-pixels in the first display area and the first pixel portion of the second display area to emit light.

30. The driving method according to claim 29, wherein: When determining to perform the normal display mode, controlling the first sub-pixel of the first display area and at least the second pixel portion of the second display area to emit light includes: when determining to perform the normal display mode, controlling all the first sub-pixels of the first display area and the second pixel portion of the second display area to emit light; When determining to perform the partial anti-peeping display mode, controlling at least a portion of the first sub-pixels in the first display area and the first pixel portion in the second display area to emit light includes: controlling all of the first sub-pixels in the first display area and the first pixel portion in the second display area to emit light.

31. The driving method according to any one of claims 27 to 30, wherein: The driving method further includes: in a normal display mode, when it is determined that there is a brightness difference between the first display area and the second display area, calling a stored relationship table to adjust the brightness of the first display area and the second display area.

Images