Display panel and display apparatus

Abstract

Provided in the present application are a display panel and a display apparatus. A first capacitor and a second capacitor are connected to a second power line that is connected to a second output transistor, such that the overall capacitance on the second power line is increased, the voltage drop on the second power line is reduced, and the stability of output signals of a gate driving circuit is improved, so as to alleviate the problem of certain fluctuations generated by a high level that is output by existing GOA circuits, affecting the stability of output signals.

Description

Display panel and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] As demand for display panels continues to rise, GOA (Gate Driver On Array) circuits are undergoing gradual refinement. The output signal of the gate driver circuit directly impacts the display quality, making optimizing the output signal stability extremely important. However, existing GOA circuits are subject to significant disturbances when outputting signals in-plane, causing fluctuations in the output high level and compromising the stability of the output signal. SUMMARY OF THE INVENTION

[0003] The present application provides a display panel and a display device to alleviate the technical problem that the high level output by the existing GOA circuit will produce certain fluctuations, affecting the stability of the output signal.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] In a first aspect, embodiments of the present application provide a display panel comprising a first power line and a second power line extending along a first direction and spaced apart along a second direction, the first direction and the second direction being different; the display panel further comprising a multi-stage cascaded gate drive circuit, the gate drive circuit being configured to generate a plurality of gate control signals for output to a plurality of sub-pixels of the display panel; each gate drive circuit comprising:

[0006] a start transistor, wherein a gate of the start transistor is configured to receive a corresponding clock signal, and a source of the start transistor is configured to receive a start signal;

[0007] a first output transistor, wherein the gate of the first output transistor is electrically connected to the drain of the start-up transistor, the source of the first output transistor is connected to a first power line, and the drain of the first output transistor is connected to a first output trace of the gate drive circuit of this stage;

[0008] a first capacitor, wherein a first plate of the first capacitor is connected to the gate of the first output transistor;

[0009] a second output transistor, wherein a gate of the second output transistor is electrically connected to the gate of the first output transistor, a source of the second output transistor is connected to a second power line, and a drain of the second output transistor is connected to a second output trace of the gate drive circuit of the current stage;

[0010] a second capacitor, wherein a first plate of the second capacitor is connected to the gate of the second output transistor and is electrically connected to the first plate of the first capacitor, a second plate of the second capacitor is connected to the second plate of the first capacitor, and is connected to the source of the second output transistor, and is connected to the second power line through the source of the second output transistor.

[0011] In a second aspect, embodiments of the present application further provide a display device, comprising a display panel, the display panel comprising a first power line and a second power line extending along a first direction and spaced apart along a second direction, the first direction and the second direction being different; the display panel further comprising a multi-stage cascaded gate drive circuit, the gate drive circuit being configured to generate a plurality of gate control signals for output to a plurality of sub-pixels of the display panel; each gate drive circuit comprising:

[0012] a start transistor, wherein a gate of the start transistor is configured to receive a corresponding clock signal, and a source of the start transistor is configured to receive a start signal;

[0013] a first output transistor, wherein the gate of the first output transistor is electrically connected to the drain of the start-up transistor, the source of the first output transistor is connected to a first power line, and the drain of the first output transistor is connected to a first output trace of the gate drive circuit of this stage;

[0014] a first capacitor, wherein a first plate of the first capacitor is connected to the gate of the first output transistor;

[0015] a second output transistor, wherein a gate of the second output transistor is electrically connected to the gate of the first output transistor, a source of the second output transistor is connected to a second power line, and a drain of the second output transistor is connected to a second output trace of the gate drive circuit of the current stage;

[0016] a second capacitor, wherein a first plate of the second capacitor is connected to the gate of the second output transistor and is electrically connected to the first plate of the first capacitor, a second plate of the second capacitor is connected to the second plate of the first capacitor, and is connected to the source of the second output transistor, and is connected to the second power line through the source of the second output transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] FIG1 is a schematic plan view of a display panel provided in an embodiment of the present application.

[0019] FIG2 is a circuit diagram of a gate drive circuit provided in an embodiment of the present application.

[0020] FIG3 is a planar schematic diagram of a gate driver provided in an embodiment of the present application.

[0021] FIG. 4 a is a schematic plan view of the active layer of each transistor in FIG. 3 .

[0022] FIG4 b is a schematic diagram of the planar structure of the first metal layer in FIG3 .

[0023] FIG. 4 c is a schematic diagram of a stack of the active layer in FIG. 4 a and the first metal layer in FIG. 4 b .

[0024] FIG. 5 a is a schematic plan view of the light shielding layer in FIG. 3 .

[0025] FIG. 5 b is a schematic diagram of the stacking of the light shielding layer in FIG. 3 and the layer in FIG. 4 c .

[0026] FIG. 6 a is a schematic plan view of the second metal layer in FIG. 3 .

[0027] FIG6 b is a schematic diagram of a stack of the second metal layer in FIG6 a and the first metal layer in FIG4 b .

[0028] FIG. 7 a is a schematic plan view of an opening in the interlayer dielectric layer in FIG. 3 .

[0029] FIG. 7 b is a schematic diagram of the stacking of FIG. 7 a and FIG. 6 b .

[0030] FIG8 a is a schematic plan view of the third metal layer in FIG3 .

[0031] FIG8b is a schematic diagram of the stacking of FIG8a and FIG6b.

[0032] FIG. 9 a is a schematic plan view of a hole opened on the planarization layer in FIG. 3 .

[0033] FIG9 b is a schematic diagram of the stacking of FIG9 a and FIG8 b .

[0034] FIG. 10 a is a schematic plan view of the fourth metal layer in FIG. 3 .

[0035] FIG10 b is a schematic diagram of the stacking of FIG10 a and FIG9 b .

[0036] FIG. 11 a is a schematic diagram showing waveforms of output signals of various stages of a gate driving circuit in the prior art.

[0037] FIG11 b is a schematic diagram of waveforms of output signals of each stage of the gate driving circuit provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0038] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in this application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and areas is exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0039] In response to the problem that the high level output of the existing GOA circuit will produce certain fluctuations, affecting the stability of the output signal, the inventors of this application found in their research that this is mainly because when the GOA circuit outputs a high level, the output transistor is turned on, and when the high-level power line is output, a large instantaneous current will pass through the output transistor, causing the high-level power line to have a certain voltage drop. This will cause the output high level to produce certain fluctuations, thereby affecting the stability of the output signal.

[0040] To this end, the present application provides a display panel and a display device to improve the above-mentioned problems.

[0041] In one embodiment, the present application provides a display panel comprising a first power line and a second power line extending along a first direction and spaced apart along a second direction, wherein the first direction and the second direction are different; the display panel further comprises a multi-stage cascaded gate drive circuit, wherein the gate drive circuit is configured to generate a plurality of gate control signals for output to a plurality of sub-pixels of the display panel; each gate drive circuit comprises:

[0042] a start transistor, wherein a gate of the start transistor is configured to receive a corresponding clock signal, and a source of the start transistor is configured to receive a start signal;

[0043] a first output transistor, wherein the gate of the first output transistor is electrically connected to the drain of the start-up transistor, the source of the first output transistor is connected to a first power line, and the drain of the first output transistor is connected to a first output trace of the gate drive circuit of this stage;

[0044] a first capacitor, wherein a first plate of the first capacitor is connected to the gate of the first output transistor;

[0045] a second output transistor, wherein the gate of the second output transistor is electrically connected to the gate of the first output transistor, the source of the second output transistor is connected to the second power line, and the drain of the second output transistor is connected to the second output trace of the gate drive circuit of this stage; and

[0046] a second capacitor, wherein a first plate of the second capacitor is connected to the gate of the second output transistor and is electrically connected to the first plate of the first capacitor, a second plate of the second capacitor is connected to the second plate of the first capacitor, and is connected to the source of the second output transistor, and is connected to the second power line through the source of the second output transistor.

[0047] In one embodiment, each of the gate driving circuits further includes a third capacitor, and a second plate of the third capacitor is connected to the second plate of the second capacitor.

[0048] In one embodiment, each of the gate drive circuits further includes a first frequency-dividing transistor, the gate of the first frequency-dividing transistor is connected to the first plate of the third capacitor, the source of the first frequency-dividing transistor is connected to the first plate of the first capacitor, and the drain of the first frequency-dividing transistor is connected to the first plate of the second capacitor.

[0049] In one embodiment, the first plate of the first capacitor, the first plate of the second capacitor, and the first plate of the third capacitor are integrally provided and located between the first power line and the second power line.

[0050] In one embodiment, the gate of the second output transistor includes a plurality of first sub-routes extending along the second direction, a first gap is defined between two adjacent first sub-routes, each of the first sub-routes is connected to the first plate of the second capacitor, and the first plate of the second capacitor is located on the same side of the plurality of first sub-routes and extends along the first direction;

[0051] The source of the second output transistor includes a plurality of second sub-routes extending along the second direction and a third sub-routes connecting the plurality of second sub-routes, the third sub-routes extending along the first direction and arranged corresponding to the second plate of the second capacitor and connected to the second plate of the second capacitor, and the second sub-routes are connected to the second power line;

[0052] The drain of the second output transistor includes a plurality of fourth sub-routes extending along the second direction and a fifth sub-routes connecting the plurality of fourth sub-routes, the fifth sub-routes extending along the first direction and being located on a side of the fourth sub-routes away from the third sub-routes, and the fifth sub-routes being connected to the second output route;

[0053] The second sub-route and the fourth sub-route are both arranged corresponding to the first gap and are located on opposite sides of the first sub-route.

[0054] In one embodiment, the second power line includes a first sub-power line and a second sub-power line arranged at intervals, the second output transistors in a portion of the gate drive circuit are connected to the first sub-power line, and the second output transistors in another portion of the gate drive circuit are connected to the second sub-power line.

[0055] In one embodiment, in any two adjacent levels of the gate drive circuit, the second output transistor in one level of the gate drive circuit is connected to the first sub-power line, and the second output transistor in the other level of the gate drive circuit is connected to the second sub-power line.

[0056] In one embodiment, the display panel further includes:

[0057] substrate;

[0058] a first metal layer, disposed on the substrate, the first metal layer including a gate of the first output transistor, a gate of the second output transistor, a first plate of the first capacitor, a first plate of the second capacitor, a first plate of the third capacitor, and a second output trace;

[0059] a second metal layer, disposed on a side of the first metal layer away from the substrate, the second metal layer comprising a second plate of the first capacitor, a second plate of the second capacitor, and a second plate of the third capacitor;

[0060] a third metal layer, disposed on a side of the second metal layer away from the first metal layer, the third metal layer including a source of the first output transistor, a drain of the first output transistor, a source of the second output transistor, a drain of the second output transistor, and the first output trace;

[0061] The fourth metal layer is disposed on a side of the third metal layer away from the second metal layer, and the fourth metal layer includes the first power line and the second power line.

[0062] In one embodiment, the display panel further includes a third power line extending along the first direction, and the third power line is located on a side of the second power line away from the first power line;

[0063] Each of the gate drive circuits further includes a third output transistor and a fourth output transistor, the gate of the third output transistor being connected to the gate of the fourth output transistor, the source of the third output transistor being connected to the source of the fourth output transistor, the drain of the third output transistor being connected to the first output trace, the source of the fourth output transistor being connected to the third power line, and the drain of the fourth output transistor being connected to the second output trace.

[0064] In one embodiment, in the second direction, the width of the third power line is greater than the width of the second power line and the width of the first power line.

[0065] In one embodiment, the present application further provides a display device, which includes the display panel of one of the aforementioned embodiments.

[0066] In the display panel and display device provided in the present application, the first capacitor and the second capacitor are connected to the second power line connected to the second output transistor to increase the overall capacitance on the second power line, reduce the voltage drop on the second power line, and improve the stability of the output signal of the gate drive circuit, so as to alleviate the problem that the high level output of the existing GOA circuit will produce certain fluctuations and affect the stability of the output signal.

[0067] The display panel and display device of the present application will be further described below with reference to the accompanying drawings and through specific implementations.

[0068] Please refer to Figures 1 to 3. Figure 1 is a planar schematic diagram of a display panel provided in an embodiment of the present application, Figure 2 is a circuit schematic diagram of a gate drive circuit provided in an embodiment of the present application, and Figure 3 is a planar schematic diagram of a gate drive provided in an embodiment of the present application. Referring to Figure 1, a display panel 100 includes a substrate 10 and a plurality of sub-pixels SP arranged in an array on the substrate 10. Optionally, the plurality of sub-pixels SP include red sub-pixels, green sub-pixels, and blue sub-pixels, wherein the red sub-pixels emit red light, the green sub-pixels emit green light, and the blue sub-pixels emit blue light, to achieve color display of the display panel 100.

[0069] The display panel 100 further includes a multi-stage cascade of gate drive circuits GDC. The gate drive circuits GDC are configured to generate a plurality of gate control signals for output to a plurality of sub-pixels SP of the display panel 100. For example, each gate control signal generated by the gate drive circuit GDC may control one or two rows of sub-pixels SP. Optionally, the display panel 100 further includes a display area AA and a non-display area NA located to one side of the display area AA. The sub-pixels SP are located within the display area AA, and the gate drive circuits GDC are located within the non-display area NA.

[0070] 1 and 2 , each gate drive circuit GDC includes at least a start transistor T3 and a first output transistor T10. The gate of the start transistor T3 is configured to receive a corresponding clock signal (e.g., a first clock signal line XCK), the source of the start transistor T3 is configured to receive a start signal (e.g., a start signal Nscan_in), and the drain of the start transistor T3 is electrically connected to the gate of the first output transistor T10.

[0071] Among them, the multi-stage gate driving circuit GDC cascaded after the first-stage gate driving circuit GDC can receive the first control signal (such as the first control signal N_OUT) output by the previous-stage gate driving circuit GDC from the first output transistor T10 as the said start signal, and the first-stage gate driving circuit GDC of the multi-stage gate driving circuit GDC can receive the control signal generated by the timing controller and other devices as the said start signal.

[0072] Optionally, the n-th stage gate driver circuit GDC(n) receives the first control signal outputted from the first output transistor T10 of the nA-th stage gate driver circuit GDC(nA) as the startup signal, where A ≥ 1. If the multi-stage gate driver circuit GDC adopts a row-by-row cascade design, the n-th stage gate driver circuit GDC(n) receives the control signal outputted from the first output transistor T10 of the n-1-th stage gate driver circuit GDC(n-1) as the startup signal.

[0073] 2 and 3 , the display panel 100 further includes a first power line VGH1 and a second power line VGH2 extending along a first direction X and spaced apart along a second direction Y. The first direction X and the second direction Y are different. For example, the first direction X is a column direction, the second direction Y is a row direction, and the first direction X is perpendicular to the second direction Y. The source of the first output transistor T10 is connected to the first power line VGH1, and the drain of the first output transistor T10 is connected to a first output trace of the gate drive circuit GDC at this stage. The first output trace is used to output a first control signal N_OUT output by the first output transistor T10.

[0074] Each gate drive circuit GDC further includes a first capacitor C3, a second output transistor T22, and a second capacitor C4. A first plate of the first capacitor C3 is connected to the gate of the first output transistor T10, a gate of the second output transistor T22 is electrically connected to the gate of the first output transistor T10, a source of the second output transistor T22 is connected to a second power supply line VGH2, and a drain of the second output transistor T22 is connected to a second output trace of the gate drive circuit GDC at this stage. The second output trace is configured to output a gate control signal N_out_AA output by the second output transistor T22. The gate control signal N_out_AA is output from the gate drive circuit GDC to a sub-pixel SP within the display area AA of the display panel 100 to control the on / off state of the sub-pixel SP. The first plate of the second capacitor C4 is connected to the gate of the second output transistor T22 and electrically connected to the first plate of the first capacitor C3. The second plate of the second capacitor C4 is connected to the second plate of the first capacitor C3 and to the source of the second output transistor T22, and is connected to the second power line VGH2 through the source of the second output transistor T22. It should be noted that in this application, "connection" refers to direct contact between two structures or direct connection achieved through a wire, etc., while "electrical connection" refers to electrical connection between two structures achieved through a switching device, etc.

[0075] In this embodiment, the first capacitor C3 and the second capacitor C4 are connected to the second power line VGH2 connected to the second output transistor T22 to increase the overall capacitance on the second power line VGH2, reduce the voltage drop on the second power line VGH2, and improve the stability of the output signal of the gate drive circuit GDC. This improves the technical problem that the high level output of the existing GOA circuit will produce certain fluctuations, affecting the stability of the output signal.

[0076] In one embodiment, each of the gate drive circuits GDC further includes a third capacitor C5, wherein the second plate of the third capacitor C5 is connected to the second plate of the second capacitor C4. Each of the gate drive circuits GDC further includes a first frequency-dividing transistor T18, wherein the gate of the first frequency-dividing transistor T18 is connected to the first plate of the third capacitor C5, the source of the first frequency-dividing transistor T18 is connected to the first plate of the first capacitor C3, and the drain of the first frequency-dividing transistor T18 is connected to the first plate of the second capacitor C4. Optionally, the first plate of the first capacitor C3, the first plate of the second capacitor C4, and the first plate of the third capacitor C5 are integrally arranged and located between the first power line VGH1 and the second power line VGH2.

[0077] The display panel 100 further includes a third power line VGL1 and a fourth power line VGL2 extending along the first direction X. The third power line VGL1 is located on a side of the second power line VGH2 away from the first power line VGH1, and the fourth power line VGL2 is located on a side of the first power line VGH1 away from the second power line VGH2. In the second direction Y, the width of the third power line VGL1 is greater than the width of the second power line VGH2 and the width of the first power line VGH1. The third power line VGL1 and the fourth power line VGL2 are low-level power lines, while the first power line VGH1 and the second power line VGH2 are high-level signal lines. The voltages on the first power line VGH1 and the second power line VGH2 are both greater than the voltages on the third power line VGL1 and the fourth power line VGL2.

[0078] Each gate drive circuit GDC further includes a third output transistor T9 and a fourth output transistor T21, wherein the gate of the third output transistor T9 is connected to the gate of the fourth output transistor T21, the source of the third output transistor T9 is connected to the source of the fourth output transistor T21, the drain of the third output transistor T9 is connected to the first output trace, the source of the fourth output transistor is connected to the third power line VGL1, and the drain of the fourth output transistor T21 is connected to the second output trace.

[0079] The display panel 100 further includes a first clock signal line XCK, a second clock signal line CK, a power-on reset control line Con, a first frequency-dividing control signal line Con2, and a second frequency-dividing control signal line Con1 extending along the first direction X.

[0080] The gate driving circuit GDC further includes a first transistor T4, a second transistor T5, a third transistor T6, a fourth transistor T7, a fifth transistor T8, a sixth transistor T1, a seventh transistor T2, a fourth capacitor C2, and a fifth capacitor C1.

[0081] The gate of the first transistor T4 is connected to the gate of the start transistor T3, the gate of the start transistor T3 is connected to the first clock signal line XCK, the first clock signal line XCK is used to provide a clock signal to the start transistor T3, and the source of the first transistor T4 is connected to the fourth power line VGL2.

[0082] The gate of the second transistor T5 is connected to the drain of the start transistor T3 , the source of the second transistor T5 is connected to the first clock signal line XCK, and the drain of the second transistor T5 is connected to the drain of the first transistor T4 .

[0083] A gate of the third transistor T6 is electrically connected to the drain of the first transistor T4 , and a source of the third transistor T6 is connected to the second clock signal line CK.

[0084] A gate of the fourth transistor T7 is connected to the second clock signal line CK, and a source of the fourth transistor T7 is connected to a drain of the third transistor T6.

[0085] The gate of the fifth transistor T8 is connected to the gate of the second transistor T5, the gate of the second transistor T5 is electrically connected to the drain of the start transistor T3, the source of the fifth transistor T8 is connected to the first power line VGH1, the drain of the fifth transistor T8 is electrically connected to the drain of the fourth transistor T7, and the drain of the fifth transistor T8 is connected to the first plate of the first capacitor C3.

[0086] A gate of the sixth transistor T1 is electrically connected to a drain of the first transistor T4 , and a source of the sixth transistor T1 is electrically connected to the first power line VGH1 .

[0087] A source of the seventh transistor T2 is connected to the second clock signal line CK, and a drain of the seventh transistor T2 is connected to the drain of the sixth transistor T1 .

[0088] The gate of the first output transistor T10 is electrically connected to the drain of the fourth transistor T7 , the source of the first output transistor T10 is connected to the first power line VGH1 , and the drain of the first output transistor T10 is electrically connected to the drain of the third output transistor T9 .

[0089] A first plate of the fourth capacitor C2 is connected to the gate of the third transistor T6 , and a second plate of the fourth capacitor C2 is electrically connected to the drain of the third transistor T6 .

[0090] A first plate of the fifth capacitor C1 is electrically connected to the gate of the seventh transistor T2 , and a second plate of the fifth capacitor C1 is electrically connected to the drain of the seventh transistor T2 .

[0091] Optionally, the gate of the start transistor T3 of one gate drive circuit GDC in the two adjacent gate drive circuits GDC is configured to receive the first clock signal XCK, and the gate of the fourth transistor T7 is configured to receive the second clock signal CK; the gate of the start transistor T3 of the other gate drive circuit GDC in the two adjacent gate drive circuits GDC is configured to receive the second clock signal CK, and the gate of the fourth transistor T7 is configured to receive the first clock signal XCK.

[0092] Optionally, the gate of the start transistor T3 of the odd-level gate drive circuit GDC is configured to receive the first clock signal XCK, and the gate of the start transistor T3 of the even-level gate drive circuit GDC is configured to receive the second clock signal CK; the gate of the fourth transistor T7 of the odd-level gate drive circuit GDC is configured to receive the second clock signal CK, and the gate of the fourth transistor T7 of the even-level gate drive circuit GDC is configured to receive the first clock signal XCK.

[0093] Optionally, the gate driving circuit GDC further includes a first shielding transistor T11 and a second shielding transistor T12.

[0094] The source of the first shielding transistor T11 is connected to the drain of the first transistor T4 and to the gate of the sixth transistor T1 . The drain of the first shielding transistor T11 is connected to the gate of the third transistor T6 . The gate of the first shielding transistor T11 is connected to the fourth power line VGL2 .

[0095] The source of the second shielding transistor T12 is connected to the gate of the fifth transistor T8 and the gate of the second transistor T5 , the drain of the second shielding transistor T12 is electrically connected to the gate of the third output transistor T9 , and the gate of the second shielding transistor T12 is connected to the fourth power line VGL2 .

[0096] Optionally, the first shielding transistor T11 and the second shielding transistor T12 are P-type transistors, the gate of the first shielding transistor T11 is electrically connected to the fourth power line VGL2, and the gate of the second shielding transistor T12 is electrically connected to the fourth power line VGL2. The first shielding transistor T11 and the second shielding transistor T12 are N-type transistors, the gate of the first shielding transistor T11 and the gate of the second shielding transistor T12 are electrically connected to the first power line VGH1.

[0097] Optionally, the gate driving circuit GDC further includes an eighth transistor T16 and a ninth transistor T14.

[0098] The gate of the eighth transistor T16 and the source of the eighth transistor T16 are connected to the gate of the seventh transistor T2 , and the drain of the eighth transistor T16 is connected to the gate of the third output transistor T9 and to the drain of the second shielding transistor T12 .

[0099] The gate of the ninth transistor T14 is connected to the gate of the start transistor T3 , the source of the ninth transistor T14 is connected to the source of the start transistor T3 , and the drain of the ninth transistor T14 is electrically connected to the gate of the seventh transistor T2 .

[0100] Optionally, the gate drive circuit GDC further includes a third shielding transistor T15. The source of the third shielding transistor T15 is connected to the drain of the ninth transistor T14, and the drain of the third shielding transistor T15 is connected to the first plate of the fifth capacitor C1. Optionally, the third shielding transistor T15 is a P-type transistor, and the gate of the third shielding transistor T15 is electrically connected to the fourth power line VGL2. The third shielding transistor T15 is an N-type transistor, and the gate of the third shielding transistor T15 is electrically connected to the first power line VGH1.

[0101] Optionally, the gate drive circuit GDC further includes a tenth transistor T13, a gate of the tenth transistor T13 connected to the power-on reset control line Con, a source of the tenth transistor T13 connected to the first power line VGH1, and a drain of the tenth transistor T13 connected to the source of the second shielding transistor T12.

[0102] Optionally, the gate drive circuit GDC further includes a second frequency-dividing transistor T17, the gate of the second frequency-dividing transistor T17 is connected to the first frequency-dividing control signal line Con2, the source of the second frequency-dividing transistor T17 is connected to the drain of the fourth transistor T7, and the drain of the second frequency-dividing transistor T17 is connected to the drain of the fifth transistor T8.

[0103] Optionally, the gate driving circuit GDC further includes a third frequency-dividing transistor T20 and a fourth frequency-dividing transistor T19.

[0104] The gate of the third frequency-dividing transistor T20 is connected to the gate of the fourth frequency-dividing transistor T19 and the gate of the fifth transistor T8. The source of the third frequency-dividing transistor T20 is connected to the second frequency-dividing control signal line Con1. The gate of the first frequency-dividing transistor T18 is connected to the drain of the third frequency-dividing transistor T20.

[0105] A source of the fourth frequency dividing transistor T19 is connected to the first power line VGH1 , and a drain of the fourth frequency dividing transistor T19 is connected to the gate of the second output transistor T22 .

[0106] The structures of the first capacitor C3, the second capacitor C4, the third capacitor C5 and the second output transistor T22 are described in detail below:

[0107] Referring to Figures 1 to 10b, Figures 4a to 10b are schematic diagrams of the stacking of some of the film layers in Figure 3, and Figures 11a and 11b are schematic diagrams of simulation data provided by the embodiments of the present application. Figure 4a is a planar schematic diagram of the active layer of each transistor in Figure 3, Figure 4b is a planar structural schematic diagram of the first metal layer in Figure 3, Figure 4c is a schematic diagram of the stacking of the active layer in Figure 4a and the first metal layer in Figure 4b, Figure 5a is a planar schematic diagram of the light shielding layer in Figure 3, Figure 5b is a schematic diagram of the stacking of the light shielding layer in Figure 3 and Figure 4c, Figure 6a is a planar schematic diagram of the second metal layer in Figure 3, and Figure 6b is a schematic diagram of the stacking of the second metal layer in Figure 6a and the first metal layer in Figure 4b. 7a is a planar schematic diagram of an opening on the interlayer dielectric layer in FIG3 , FIG7b is a schematic diagram of the stacking of FIG7a and FIG6b , FIG8a is a planar schematic diagram of the third metal layer in FIG3 , FIG8b is a schematic diagram of the stacking of FIG8a and FIG6b , FIG9a is a planar schematic diagram of an opening on the planarization layer in FIG3 , FIG9b is a schematic diagram of the stacking of FIG9a and FIG8b , FIG10a is a planar schematic diagram of the fourth metal layer in FIG3 , and FIG10b is a schematic diagram of the stacking of FIG10a and FIG9b .

[0108] Specifically, the display panel 100 further includes a substrate 10 and a light shielding layer, an active layer, a first metal layer, a second metal layer, an interlayer insulating layer, a third metal layer, a planarization layer and a fourth metal layer sequentially stacked on the substrate 10 .

[0109] 4a to 4c , the active layer is disposed on the substrate 10, and the first metal layer is disposed on a side of the active layer away from the substrate 10. The first metal layer includes the gate GE1 of the first output transistor T10, the gate GE2 of the second output transistor T22, the gate GE3 of the third output transistor T9, the gate GE4 of the fourth output transistor T21, the gate GE5 of the first frequency-dividing transistor T18, the first plate C11 of the first capacitor C3, the first plate C21 of the second capacitor C4, the first plate C31 of the third capacitor C5, the first plate C41 of the fourth capacitor C2, and the first plate C51 of the fifth capacitor C1. Of course, the first metal layer also includes the gates of other transistors, such as the gates of the first transistor T4, the second transistor T5, and other transistors.

[0110] The gate GE1 of the first output transistor T10 is set above the active layer AS1 of the first output transistor T10, the gate GE2 of the second output transistor T22 is set above the active layer AS2 of the second output transistor T22, the gate GE3 of the third output transistor T9 is set above the active layer AS3 of the third output transistor T9, the gate GE4 of the fourth output transistor T21 is set above the active layer AS4 of the fourth output transistor T21, and the gate GE5 of the first frequency-dividing transistor T18 is set above the active layer AS5 of the first frequency-dividing transistor T18.

[0111] The gate GE2 of the second output transistor T22 includes multiple first sub-routes SG1 extending along the second direction Y, with a first gap between two adjacent first sub-routes SG1. Each first sub-routes SG1 is connected to the first plate C21 of the second capacitor C4. The first plate C21 of the second capacitor C4 is located on the same side of the multiple first sub-routes SG1 and extends along the first direction X.

[0112] The gate GE4 of the fourth output transistor T21 includes a plurality of tenth sub-routes SG2 extending along the second direction Y, with a second gap between two adjacent tenth sub-routes SG2, and each tenth sub-routes SG2 is connected to the gate GE3 of the third output transistor T9.

[0113] 5a and 5b , the light-shielding layer is disposed on one side of the substrate 10, the active layer is disposed on a side of the light-shielding layer away from the substrate 10, and the first metal layer is disposed on a side of the active layer away from the light-shielding layer. The light-shielding layer can shield some transistors from light and overlap the second gates of these transistors. For example, the light-shielding layer can shield the third output transistor T9, the second shielding transistor T12, the third shielding transistor T15, and the eighth transistor T16 from light, and serve as the second gate GE9 of the third output transistor T9, the second gate GE12 of the second shielding transistor T12, the second gate GE15 of the third shielding transistor T15, and the second gate GE16 of the eighth transistor T16.

[0114] 6a and 6b, the second metal layer is arranged on a side of the first metal layer away from the substrate 10. Of course, a gate insulating layer is also provided between the second metal layer and the first metal layer to electrically isolate the first metal layer from the second metal layer. The second metal layer includes the second plate C12 of the first capacitor C3, the second plate C22 of the second capacitor C4, the second plate C32 of the third capacitor C5, the second plate C42 of the fourth capacitor C2, and the second plate C52 of the fifth capacitor C1. The second plate C12 of the first capacitor C3, the second plate C22 of the second capacitor C4, and the second plate C32 of the third capacitor C5 are arranged in an integrated manner. For example, the second plate C22 of the second capacitor C4 is connected between the second plate C12 of the first capacitor C3 and the second plate C32 of the third capacitor C5.

[0115] 7a and 7b , the interlayer insulating layer is disposed on a side of the second metal layer away from the first metal layer. A plurality of first openings HL1 are disposed on the interlayer insulating layer. For example, the interlayer insulating layer is provided with a first opening HL1 at a position corresponding to the second electrode plate C22 of the second capacitor C4. The first opening HL1 exposes a portion of the second electrode plate C22 of the second capacitor C4.

[0116] Referring to Figures 8a and 8b, a third metal layer is disposed on a side of the second metal layer away from the first metal layer, with the interlayer insulating layer located between the third metal layer and the second metal layer. The third metal layer includes the source S1 of the first output transistor T10, the drain D1 of the first output transistor T10, the source S2 of the second output transistor T22, the drain D2 of the second output transistor T22, the source S3 of the third output transistor T9, the drain D1 of the third output transistor T9, the source S4 of the fourth output transistor T21, the drain D4 of the second output transistor T21, and the first output trace OL1. The drain D1 of the first output transistor T10 and the drain D1 of the third output transistor T9 are both connected to the first output trace OL1. The source S3 of the third output transistor T9 is connected to the source S4 of the fourth output transistor T21.

[0117] The source S2 of the second output transistor T22 includes a plurality of second sub-routes S21 extending along the second direction Y and a third sub-routes S22 connecting the plurality of second sub-routes S21. The third sub-routes S22 extend along the first direction X, and the third sub-routes S22 are arranged corresponding to the second plate C22 of the second capacitor C4, and are connected to the second plate C22 of the second capacitor C4 through the first via HL1 of the interlayer insulating layer.

[0118] The drain D2 of the second output transistor T22 includes a plurality of fourth sub-routes D21 extending along the second direction Y, and a fifth sub-routes D22 connecting the plurality of fourth sub-routes D21. The fifth sub-routes D22 extend along the first direction X and are located on a side of the fourth sub-routes D21 away from the third sub-routes S22. The fifth sub-routes D22 are connected to the second output route. The second sub-routes S21 and the fourth sub-routes D21 are both arranged corresponding to the first gap and located on opposite sides of the first sub-routes SG1.

[0119] The source S4 of the fourth output transistor T21 includes multiple sixth sub-routes S41 extending along the second direction Y and a seventh sub-routes S42 connecting the multiple sixth sub-routes S41. The seventh sub-routes S42 extend along the first direction X. The drain D4 of the fourth output transistor T21 includes multiple eighth sub-routes D41 extending along the second direction Y and a ninth sub-routes D42 connecting the multiple eighth sub-routes D41. The ninth sub-routes D42 extend along the first direction X and are located on a side of the eighth sub-routes D41 away from the seventh sub-routes S42. The ninth sub-routes D42 are connected to the second output route. The sixth sub-routes S41 and the eighth sub-routes D41 are both arranged corresponding to the second gap and located on opposite sides of the tenth sub-routes SG2.

[0120] Referring to Figures 9a and 9b, the planarization layer is disposed on a side of the third metal layer away from the interlayer insulating layer. A plurality of second vias HL2 are provided on the planarization layer. For example, the planarization layer includes a second opening HL2 at a location corresponding to the second sub-route S21, which exposes a portion of the second sub-route S21. The second opening HL2 is located on a side of the second sub-route S21 near the third sub-route S22. The planarization layer also includes a second opening HL2 at a location corresponding to the sixth sub-route S41, which exposes a portion of the sixth sub-route S41.

[0121] Referring to Figures 10a and 10b, the fourth metal layer is disposed on a side of the third metal layer away from the second metal layer, and the planarization layer is located between the fourth metal layer and the third metal layer. The fourth metal layer includes the first power line VGH1, the second power line VGH2, the third power line VGL1, the fourth power line VGL2, a first clock signal line XCK, a second clock signal line CK, a power-on reset control line Con, a first frequency division control signal line Con2, and a second frequency division control signal line Con1, extending along the first direction X. The second power line VGH2 is connected to the second sub-route S21 through the second via HL2 in the planarization layer, and the third power line VGL1 is connected to the sixth sub-route S41 through the second via HL2 in the planarization layer.

[0122] The second power line VGH2 includes a first sub-power line VGH21 and a second sub-power line VGH22 arranged at intervals. The second output transistors T22 in a part of the gate drive circuit GDC are connected to the first sub-power line VGH21, and the second output transistors T22 in another part of the gate drive circuit GDC are connected to the second sub-power line VGH22.

[0123] In any two adjacent gate drive circuits GDC, the second output transistor T22 in one gate drive circuit GDC is connected to the first sub-power line VGH21, and the second output transistor T22 in the other gate drive circuit GDC is connected to the second sub-power line VGH22.

[0124] Referring to Figures 11a and 11b, Figure 11a is a schematic diagram of the waveforms of the output signals of each stage of the gate drive circuit in the prior art, and Figure 11b is a schematic diagram of the waveforms of the output signals of each stage of the gate drive circuit provided by an embodiment of the present application. When the load on the second power line VGH2 is small, there will be a fluctuation of approximately 1V, causing the high pulse signal corresponding to the gate control signal N_out_AA of the gate drive circuit to also have similar fluctuations, as shown in Figure 11a. When the load on the second power line VGH2 is large, the fluctuation is reduced to 0.4V, and the fluctuation of the high pulse signal corresponding to the gate control signal N_out_AA of the gate drive circuit is also reduced to 0.4V. In other words, when the overall output of the second power line VGH2 is small, the gate control signal N_out_AA of each row of the gate drive circuit will be subject to significant disturbances when it is output. However, by increasing the overall capacitance on the second power line VGH2, the gate control signal N_out_AA of the gate drive circuit is more stable.

[0125] Based on the same inventive concept, an embodiment of the present application further provides a display device, comprising a display panel as described in one of the aforementioned embodiments. The display device may include, but is not limited to, a wearable device such as a smart bracelet, a smart watch, VR (Virtual Reality), a mobile phone, a television, or a personal laptop.

[0126] According to the above embodiments, it can be seen that:

[0127] In the display panel and display device provided by the present application, the first capacitor and the second capacitor are connected to the second power line connected to the second output transistor to increase the overall capacitance on the second power line, reduce the voltage drop on the second power line, and improve the stability of the output signal of the gate drive circuit, thereby improving the technical problem that the high level output of the existing GOA circuit will produce certain fluctuations and affect the stability of the output signal.

[0128] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0129] The above is a detailed introduction to the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel comprising a first power line and a second power line extending in a first direction and spaced apart in a second direction, the first direction and the second direction being different; the display panel further comprising a multi-stage cascaded gate driver circuit configured to generate a plurality of gate control signals for output to a plurality of sub-pixels of the display panel; Each of the gate drive circuits comprises: a start transistor, wherein a gate of the start transistor is configured to receive a corresponding clock signal, and a source of the start transistor is configured to receive a start signal; a first output transistor, wherein the gate of the first output transistor is electrically connected to the drain of the start-up transistor, the source of the first output transistor is connected to a first power line, and the drain of the first output transistor is connected to a first output trace of the gate drive circuit of this stage; a first capacitor, wherein a first plate of the first capacitor is connected to the gate of the first output transistor; a second output transistor, wherein the gate of the second output transistor is electrically connected to the gate of the first output transistor, the source of the second output transistor is connected to the second power line, and the drain of the second output transistor is connected to the second output trace of the gate drive circuit of this stage; and a second capacitor, wherein a first plate of the second capacitor is connected to the gate of the second output transistor and is electrically connected to the first plate of the first capacitor, a second plate of the second capacitor is connected to the second plate of the first capacitor, and is connected to the source of the second output transistor, and is connected to the second power line through the source of the second output transistor.

2. The display panel according to claim 1, wherein Each of the gate driving circuits further includes a third capacitor, and a second plate of the third capacitor is connected to the second plate of the second capacitor.

3. The display panel according to claim 2, wherein: Each of the gate drive circuits further includes a first frequency dividing transistor, the gate of the first frequency dividing transistor is connected to the first plate of the third capacitor, the source of the first frequency dividing transistor is connected to the first plate of the first capacitor, and the drain of the first frequency dividing transistor is connected to the first plate of the second capacitor.

4. The display panel according to claim 2, wherein: The first plate of the first capacitor, the first plate of the second capacitor, and the first plate of the third capacitor are integrally provided and located between the first power line and the second power line.

5. The display panel according to claim 2, wherein: The gate of the second output transistor includes a plurality of first sub-routes extending along the second direction, a first gap being defined between two adjacent first sub-routes, each of the first sub-routes being connected to the first plate of the second capacitor, and the first plate of the second capacitor being located on the same side of the plurality of first sub-routes and extending along the first direction; The source of the second output transistor includes a plurality of second sub-routes extending along the second direction and a third sub-routes connecting the plurality of second sub-routes, the third sub-routes extending along the first direction and arranged corresponding to the second plate of the second capacitor and connected to the second plate of the second capacitor, and the second sub-routes are connected to the second power line; The drain of the second output transistor includes a plurality of fourth sub-routes extending along the second direction and a fifth sub-routes connecting the plurality of fourth sub-routes, the fifth sub-routes extending along the first direction and being located on a side of the fourth sub-routes away from the third sub-routes, and the fifth sub-routes being connected to the second output route; The second sub-route and the fourth sub-route are both arranged corresponding to the first gap and are located on opposite sides of the first sub-route. The display panel according to claim 5 , wherein: The second power line includes a first sub-power line and a second sub-power line arranged at intervals, the second output transistors in a part of the gate drive circuit are connected to the first sub-power line, and the second output transistors in another part of the gate drive circuit are connected to the second sub-power line.

7. The display panel according to claim 6, wherein: In any two adjacent gate drive circuits, the second output transistor in one gate drive circuit is connected to the first sub-power line, and the second output transistor in the other gate drive circuit is connected to the second sub-power line.

8. The display panel according to claim 5, wherein: The display panel further includes: substrate; a first metal layer, disposed on the substrate, the first metal layer including a gate of the first output transistor, a gate of the second output transistor, a first plate of the first capacitor, a first plate of the second capacitor, a first plate of the third capacitor, and a second output trace; a second metal layer, disposed on a side of the first metal layer away from the substrate, the second metal layer comprising a second plate of the first capacitor, a second plate of the second capacitor, and a second plate of the third capacitor; a third metal layer, disposed on a side of the second metal layer away from the first metal layer, the third metal layer including a source of the first output transistor, a drain of the first output transistor, a source of the second output transistor, a drain of the second output transistor, and the first output trace; The fourth metal layer is disposed on a side of the third metal layer away from the second metal layer, and the fourth metal layer includes the first power line and the second power line.

9. The display panel according to claim 1, wherein: The display panel further includes a third power line extending along the first direction, wherein the third power line is located on a side of the second power line away from the first power line; Each of the gate drive circuits further includes a third output transistor and a fourth output transistor, the gate of the third output transistor being connected to the gate of the fourth output transistor, the source of the third output transistor being connected to the source of the fourth output transistor, the drain of the third output transistor being connected to the first output trace, the source of the fourth output transistor being connected to the third power line, and the drain of the fourth output transistor being connected to the second output trace.

10. The display panel according to claim 9, wherein: In the second direction, the width of the third power line is greater than the width of the second power line and the width of the first power line.

11. A display device comprising a display panel, the display panel comprising a first power line and a second power line extending in a first direction and spaced apart in a second direction, the first direction and the second direction being different; the display panel further comprising a multi-stage cascaded gate driving circuit, the gate driving circuit configured to generate a plurality of gate control signals for output to a plurality of sub-pixels of the display panel; Each of the gate drive circuits comprises: a start transistor, wherein a gate of the start transistor is configured to receive a corresponding clock signal, and a source of the start transistor is configured to receive a start signal; a first output transistor, wherein the gate of the first output transistor is electrically connected to the drain of the start-up transistor, the source of the first output transistor is connected to a first power line, and the drain of the first output transistor is connected to a first output trace of the gate drive circuit of this stage; a first capacitor, wherein a first plate of the first capacitor is connected to the gate of the first output transistor; a second output transistor, wherein the gate of the second output transistor is electrically connected to the gate of the first output transistor, the source of the second output transistor is connected to the second power line, and the drain of the second output transistor is connected to the second output trace of the gate drive circuit of this stage; and a second capacitor, wherein a first plate of the second capacitor is connected to the gate of the second output transistor and is electrically connected to the first plate of the first capacitor, a second plate of the second capacitor is connected to the second plate of the first capacitor, and is connected to the source of the second output transistor, and is connected to the second power line through the source of the second output transistor.

12. The display device according to claim 11, wherein Each of the gate driving circuits further includes a third capacitor, and a second plate of the third capacitor is connected to the second plate of the second capacitor.

13. The display device according to claim 12, wherein: Each of the gate drive circuits further includes a first frequency dividing transistor, the gate of the first frequency dividing transistor is connected to the first plate of the third capacitor, the source of the first frequency dividing transistor is connected to the first plate of the first capacitor, and the drain of the first frequency dividing transistor is connected to the first plate of the second capacitor.

14. The display device according to claim 12, wherein: The first plate of the first capacitor, the first plate of the second capacitor, and the first plate of the third capacitor are integrally provided and located between the first power line and the second power line.

15. The display device according to claim 12, wherein: The gate of the second output transistor includes a plurality of first sub-routes extending along the second direction, a first gap being defined between two adjacent first sub-routes, each of the first sub-routes being connected to the first plate of the second capacitor, and the first plate of the second capacitor being located on the same side of the plurality of first sub-routes and extending along the first direction; The source of the second output transistor includes a plurality of second sub-routes extending along the second direction and a third sub-routes connecting the plurality of second sub-routes, the third sub-routes extending along the first direction and arranged corresponding to the second plate of the second capacitor and connected to the second plate of the second capacitor, and the second sub-routes are connected to the second power line; The drain of the second output transistor includes a plurality of fourth sub-routes extending along the second direction and a fifth sub-routes connecting the plurality of fourth sub-routes, the fifth sub-routes extending along the first direction and being located on a side of the fourth sub-routes away from the third sub-routes, and the fifth sub-routes being connected to the second output route; The second sub-route and the fourth sub-route are both arranged corresponding to the first gap and are located on opposite sides of the first sub-route.

16. The display device according to claim 15, wherein The second power line includes a first sub-power line and a second sub-power line arranged at intervals, the second output transistors in a part of the gate drive circuit are connected to the first sub-power line, and the second output transistors in another part of the gate drive circuit are connected to the second sub-power line.

17. The display device according to claim 16, wherein: In any two adjacent gate drive circuits, the second output transistor in one gate drive circuit is connected to the first sub-power line, and the second output transistor in the other gate drive circuit is connected to the second sub-power line.

18. The display device according to claim 15, wherein The display panel further includes: substrate; a first metal layer, disposed on the substrate, the first metal layer including a gate of the first output transistor, a gate of the second output transistor, a first plate of the first capacitor, a first plate of the second capacitor, a first plate of the third capacitor, and a second output trace; a second metal layer, disposed on a side of the first metal layer away from the substrate, the second metal layer comprising a second plate of the first capacitor, a second plate of the second capacitor, and a second plate of the third capacitor; a third metal layer, disposed on a side of the second metal layer away from the first metal layer, the third metal layer including a source of the first output transistor, a drain of the first output transistor, a source of the second output transistor, a drain of the second output transistor, and the first output trace; The fourth metal layer is disposed on a side of the third metal layer away from the second metal layer, and the fourth metal layer includes the first power line and the second power line.

19. The display device according to claim 11, wherein The display panel further includes a third power line extending along the first direction, wherein the third power line is located on a side of the second power line away from the first power line; Each of the gate drive circuits further includes a third output transistor and a fourth output transistor, the gate of the third output transistor being connected to the gate of the fourth output transistor, the source of the third output transistor being connected to the source of the fourth output transistor, the drain of the third output transistor being connected to the first output trace, the source of the fourth output transistor being connected to the third power line, and the drain of the fourth output transistor being connected to the second output trace.

20. The display device according to claim 19, wherein In the second direction, the width of the third power line is greater than the width of the second power line and the width of the first power line.

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