Control substrate and spatial light modulator

Abstract

Provided in the embodiments of the present application are a control substrate and a spatial light modulator. The control substrate comprises a driving layer, a metasurface layer and a first filling layer, wherein the first filling layer is located between the driving layer and the metasurface layer and configured to support the metasurface layer; the driving layer comprises a plurality of first driving structures, and a first gap is provided between every two adjacent first driving structures; the metasurface layer comprises a plurality of microstructures; the first filling layer comprises a first portion and a second portion, wherein the first portion is located in an area where the first driving structure is located, and the second portion is located in an area where the first gap is located; the surface of the first portion that faces away from the driving layer is a first surface, and the surface of the second portion that faces away from the driving layer is a second surface; and in a direction perpendicular to the plane where the control substrate is located, the maximum distance between the first surface and the second surface is D1, where D1 > 0. When the control substrate provided in the embodiments of the present application is prepared, the surface of the first filling layer that faces the metasurface layer is not planarized or polished, such that the preparation difficulty of the control substrate is low.

Description

A control substrate and spatial light modulator

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on March 29, 2024, with application number 202410383682.2 and application name “A control substrate and spatial light modulator”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of semiconductor devices, and in particular to a control substrate and a spatial light modulator. Background Art

[0003] Metasurfaces are layered materials with micro-nanoscale dimensions. Because they can manipulate the phase, amplitude, and polarization of electromagnetic waves at subwavelength scales, metasurfaces are considered promising optical structural materials for widespread application in next-generation optical devices. Metasurfaces have enormous potential for spatial light modulation, for example, enabling holographic displays, holographic projections, beam shaping, and light field manipulation. However, metasurfaces have yet to be widely adopted in optical devices. Summary of the Invention

[0004] In view of this, the present application provides a control substrate and a spatial light modulator to solve the problems in the prior art.

[0005] In the first aspect, an embodiment of the present application provides a control substrate, comprising a drive layer, a super-surface layer, and a first filling layer, wherein the first filling layer is located between the drive layer and the super-surface layer and is used to support the super-surface layer; the drive layer comprises a plurality of first drive structures and a first gap is included between adjacent first drive structures; the super-surface layer comprises a plurality of microstructures; wherein the first filling layer comprises a first portion and a second portion, the first portion being located in the region where the first drive structure is located, and the second portion being located in the region where the first gap is located; the surface of the first portion facing away from the drive layer is the first surface, and the surface of the second portion facing away from the drive layer is the second surface; along a direction perpendicular to the surface where the control substrate is located, the maximum distance between the first surface and the second surface is D1, and D1>0. Since D1>0, the depth of the first concave structure caused by the presence of the first gap is greater than 0. When preparing the control substrate provided by the embodiment of the present application, the surface of the first filling layer facing the super-surface layer is not filled or polished. Therefore, the preparation difficulty of the control substrate provided by the present application is low.

[0006] In one implementation of the first aspect, a height of the first slit in a direction perpendicular to the surface of the control substrate is D2; D1 ≤ D2 / 5. D1 ≤ D2 / 5 balances the manufacturing difficulty and cost of the control substrate with the optical performance of the spatial light modulator on which the control substrate is located.

[0007] In an implementation of the first aspect, the periphery of at least a portion of the first gap includes no less than three first driving structures.

[0008] In an implementation manner of the first aspect, 20 nm ≤ D1 ≤ 80 nm.

[0009] In one implementation of the first aspect, a surface of the second portion facing away from the drive layer includes a first recessed structure; an orthographic projection of the first slit surrounds an orthographic projection of the first recessed structure in a direction perpendicular to the surface of the control substrate; a first slit corresponding to the first recessed structure has a width W1 along the first direction, and a width W2 along the first direction, where W2 ≤ W1 / 5. When W2 ≤ W1 / 5, a certain distance in the first direction is ensured between the region where the first recessed structure resides and the region where the pixels reside, thereby reducing the probability of stray light generated by the microstructure above the first slit entering the region where the pixels reside, thereby improving the stability of the light field control effect of the spatial light modulator where the control substrate resides.

[0010] In an implementation of the first aspect, 0<W2≤30nm.

[0011] In an implementation of the first aspect, the surface of the second portion facing away from the drive layer includes a plurality of first recessed structures; along a direction perpendicular to the surface where the control substrate is located, the orthographic projection of the first gap surrounds the orthographic projection of the first recessed structure; wherein, among any two first recessed structures, the depth of the one with a larger depth is D11, and the depth of the one with a smaller depth is D12, wherein D11 and D12 satisfy: D12 ≥ D11*80%.

[0012] In an implementation of the first aspect, the first filling layer includes a plurality of stacked first sub-filling layers. By stacking the plurality of first sub-filling layers to form the first filling layer 1000, a first recessed structure with a smaller width and depth can be obtained.

[0013] In one implementation of the first aspect, the refractive index of the microstructure is n1, the refractive index of the first filling layer is n2, and n1>n2. Because the refractive index of the first filling layer is less than that of the microstructure, the propagation of light can be easily controlled according to the designed refractive index difference when it is refracted.

[0014] In an implementation manner of the first aspect, n1-n2>1.

[0015] In an implementation of the first aspect, the control substrate also includes a second filling layer located on the side of the super surface layer away from the first filling layer; wherein the second filling layer includes a third part and a fourth part, the third part is located in the area where the first part is located, and the fourth part is located in the area where the second part is located; the surface of the third part away from the driving layer is the third surface, and the surface of the fourth part away from the driving layer is the fourth surface; along the direction perpendicular to the surface where the control substrate is located, the maximum distance between the third surface and the fourth surface is D3, D3<D1.

[0016] In an implementation of the first aspect, the driving layer includes a driving circuit and a first pixel electrode, the first pixel electrode is located on a side of the driving circuit close to the super-surface layer, and the first driving structure is the first pixel electrode.

[0017] In a second aspect, an embodiment of the present application provides a spatial light modulator, comprising a control substrate as provided in the first aspect.

[0018] In an implementation manner of the first aspect, the spatial light modulator further includes an opposing substrate disposed opposite to the control substrate and a liquid crystal layer located between the control substrate and the opposing substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] FIG1 is a simplified diagram of a process for preparing a silicon-based circuit board according to an embodiment of the present application;

[0021] FIG2 is a schematic diagram of a spatial light modulator provided in an embodiment of the present application;

[0022] FIG3 is a cross-sectional schematic diagram of a control substrate provided in an embodiment of the present application;

[0023] FIG4 is a plan view of a control substrate provided in an embodiment of the present application;

[0024] FIG5 is a plan view of a control substrate provided in an embodiment of the present application;

[0025] FIG6 is a schematic cross-sectional view of a partial structure of a control substrate provided in an embodiment of the present application;

[0026] FIG7 is a cross-sectional schematic diagram of a partial structure of a control substrate provided in an embodiment of the present application;

[0027] FIG8 is a cross-sectional schematic diagram of a control substrate provided in an embodiment of the present application;

[0028] FIG9 is a cross-sectional schematic diagram of a control substrate provided in an embodiment of the present application;

[0029] FIG10 is a schematic cross-sectional view of a partial structure of a control substrate provided in an embodiment of the present application;

[0030] FIG11 is a cross-sectional schematic diagram of a control substrate provided in an embodiment of the present application;

[0031] FIG12 is a schematic cross-sectional view of a control substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0033] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0034] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0035] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. Furthermore, the character " / " in this document generally indicates an "or" relationship between the associated objects.

[0036] Existing spatial light modulators include liquid crystal on silicon (LCOS) spatial light modulators, which include silicon-based circuit boards and liquid crystal materials. The light waves emitted by each pixel in the LCOS spatial light modulator can be individually controlled. To achieve this effect, the silicon-based circuit board includes pixel electrodes corresponding to the pixels one by one. Typically, the pixel electrodes on the silicon-based circuit board are arranged in an array. The silicon-based circuit board with an integrated metasurface layer can increase the ability of the LCOS spatial light modulator to control the light field, and is conducive to simplifying the volume of integrated LCOS products and reducing the cost of integrated LCOS products.

[0037] FIG1 is a simple schematic diagram of a preparation process of a silicon-based circuit board related to an embodiment of the present application.

[0038] As shown in Figure 1, a method for preparing a silicon-based circuit board includes: first, separately preparing a wafer Si1 for setting a driving circuit DR and a pixel electrode PE and a wafer Si2 for setting a super surface layer 10, and then bonding the two wafers to obtain a silicon-based circuit board. This preparation method requires bonding the two wafers. In order to ensure the reliability of the bonding structure, high requirements are placed on the flatness and neatness of the surface of the wafer during the preparation process. In addition, higher pressure and temperature can make the bonding quality of the two wafers better. Therefore, if the bonding quality of the two wafers is to be good, more stringent bonding conditions are required. In addition, the alignment accuracy of existing bonding technologies is usually at the micron level, which is significantly inferior to the nanometer-level accuracy that can be provided by photolithography.

[0039] The microstructures of metasurfaces are typically nanometer-sized, making semiconductor processing an excellent choice for producing high-precision metasurfaces. Furthermore, semiconductor processing has proven successful in producing high-performance metasurfaces. Consequently, the fabrication process for optical metasurfaces is compatible with that for circuits. This means that semiconductor processing can be used to create circuit boards with integrated metasurfaces, eliminating the need for assembling (e.g., bonding) the separately fabricated metasurfaces to the circuit boards.

[0040] Currently, metasurfaces have not been widely used in optical device products. The main reason is that the technology for integrating metasurfaces into circuit boards is still immature, and the performance of existing optical devices incorporating metasurfaces cannot yet match that of traditional geometric optical devices (such as imaging lens modules). Based on this, the present application provides a control substrate and a spatial light modulator.

[0041] FIG2 is a schematic diagram of a spatial light modulator provided in an embodiment of the present application.

[0042] According to the different light output methods, spatial light modulators can be divided into reflective spatial light modulators and transmissive spatial light modulators. As shown in Figure 2, the embodiment of the present application takes the reflective LCOS spatial light modulator 001 as an example to illustrate the spatial light modulator provided. The reflective spatial light modulator can be used as an optical element for products in the communication field, for example, as a core component of a wavelength selective switch. It should be noted that the spatial light modulator to be protected by this application can also be a spatial light modulator based on the inventive concept of this application and having other structures other than the reflective LCOS spatial light modulator 001.

[0043] The spatial light modulator shown in Figure 2 includes a control substrate 01 and an opposing substrate 02, which are arranged relative to each other, and a liquid crystal layer 03 located between the control substrate 01 and the opposing substrate 02. The control substrate 01 includes a drive circuit DR, a pixel electrode PE, and a supersurface layer 10. The drive circuit DR can provide a voltage to the pixel electrode PE. The supersurface layer 10 is located on the side of the pixel electrode PE close to the liquid crystal layer 03. The film layer containing the drive circuit DR can be located on the side of the pixel electrode PE away from the supersurface layer 10. In addition, the control substrate 01 also includes a first alignment layer 13 for aligning the liquid crystal molecules in the liquid crystal layer 03. The opposing substrate 02 includes a common electrode 20 and also includes a second alignment layer 21 for aligning the liquid crystal molecules in the liquid crystal layer 03.

[0044] The control substrate 01 includes multiple pixel electrodes PE arranged in an array and electrically insulated from each other. When a voltage is applied to the pixel electrodes PE and the common electrode 20, an electric field can be generated between them. When no electric field is generated between the pixel electrodes PE and the common electrode 20, the liquid crystal molecules in the liquid crystal layer 03 are constrained by the first alignment layer 13 and the second alignment layer 21 and remain in their initial state. When an electric field is generated between the pixel electrodes PE and the common electrode 20, the liquid crystal molecules in the liquid crystal layer 03 are controlled by the electric field and begin to deflect. For example, when no electric field is generated between the pixel electrodes PE and the common electrode 20, the long axes of the liquid crystal molecules in the liquid crystal layer 03 are parallel or substantially parallel to each other. When an electric field is generated between the pixel electrodes PE and the common electrode 20, an angle forms between the long axes of the liquid crystal molecules in the liquid crystal layer 03.

[0045] Furthermore, the pixel electrode PE can be made of a metal with a reflective effect (e.g., aluminum), and the common electrode 20 can be made of a transparent conductive material such as indium tin oxide. Incident light enters the spatial light modulator's opposing substrate 02, passes through the liquid crystal layer 03, and reaches the control substrate 01. The light entering the control substrate 01 is modulated by the metasurface layer 10 before entering the pixel electrode PE. The light entering the pixel electrode PE and modulated by the metasurface layer 10 is reflected by the pixel electrode PE, passes through the metasurface layer 10 and the liquid crystal layer 03, and exits from the opposing substrate 02.

[0046] FIG3 is a schematic cross-sectional view of a control substrate provided in an embodiment of the present application.

[0047] As shown in Figure 3, the control substrate 01 provided in the embodiment of the present application includes a drive layer 100 and a metasurface layer 10. Thus, the control substrate 01 can be a circuit board that integrates a metasurface with a circuit structure. Specifically, the control substrate 01 can be a silicon-based circuit board integrated with a metasurface and can be applied to a spatial light modulator.

[0048] Referring to FIG3 , the metasurface layer 10 includes a plurality of microstructures 11, and the microstructures 11 are structures in the metasurface layer 10 for implementing light field manipulation. Specifically, the size of the microstructures 11 is at the nanometer level. Optionally, the shape of the microstructures 11 is cylindrical, elliptical, prism, rugby ball, etc., with a major axis size of 100 nm to 800 nm and a minor axis size of 100 nm to 700 nm.

[0049] The multiple microstructures 11 included in the supersurface layer 10 can be arranged in an array, and the center spacing between two adjacent microstructures 11 can be 200nm to 1000nm, for example, 500nm or 700nm. Among them, these microstructures 11 arranged in an array can be specifically arranged in a periodic manner, and the sizes of the multiple microstructures 11 in the same period are gradually changed, and / or the rotation angles of the multiple microstructures 11 in the same period are gradually changed, for example, the rotation angles of the multiple microstructures 11 in the same period are gradually changed within -45° to 45°.

[0050] The material of the microstructure 11 in the supersurface layer 10 can be at least one of amorphous silicon, polycrystalline silicon, silicon nitride, aluminum oxide, titanium oxide, gold, silver, aluminum, etc.

[0051] Referring to Figure 3 , the driving layer 100 includes multiple first driving structures 101, which are used to implement pixel-level control functions. The first driving structures 101 can substantially define the location of the pixels, i.e., the pixels are substantially confined within the region where the first driving structures 101 are located. The first driving structures 101 can be pixel electrodes PE electrically connected to the driving circuit DR.

[0052] For example, when the first driving structure 101 is applied to an LCOS spatial light modulator, the first driving structure 101 can drive the deflection state of the liquid crystal molecules on the pixels it defines, thereby controlling the emission angle of the light received by the pixels after being modulated by the metasurface layer 10. Specifically, when the first driving structure 101 receives a corresponding driving voltage, an electric field can be formed between the first driving structure 101 and the common electrode 20 on the opposing substrate 02. This electric field can control the corresponding deflection of the liquid crystal molecules, thereby controlling the emission angle of the light passing through the metasurface layer 10.

[0053] The planar shape of the first driving structure 101 may be a rectangle or a square, the side length of the first driving structure 101 may be 1 um to 20 um, and the distance between two adjacent first driving structures 101 may be between 100 nm and 500 nm.

[0054] FIG4 is a schematic plan view of a control substrate provided in an embodiment of the present application, and FIG5 is a schematic plan view of a control substrate provided in an embodiment of the present application.

[0055] Combined with FIGS. 3, 4, and 5, there is a first gap 102 between adjacent first driving structures 101, and the width of the first gap 102 can be between 100 nm and 500 nm. For example, the width of the first gap 102 is 200 nm.

[0056] Optionally, as shown in FIG. 4, the gaps between adjacent first driving structures 101 are all first gaps 102.

[0057] Optionally, as shown in FIG. 5, the region between at least three adjacent first driving structures 101 is a first gap 102. For example, four adjacent first driving structures 101 are arranged in a "field" shape, and the gap between these four adjacent first driving structures 101 is a first gap 102, and the planar shape of the first gap 102 is basically close to a circle or an ellipse.

[0058] In addition, the control substrate 01 further includes a first filling layer 1000. The first filling layer 1000 is located between the driving layer 100 and the metasurface layer 10 and is used to carry the metasurface layer 10. The first filling layer 1000 includes a first part 1001 and a second part 1002. The first part 1001 is located in the region where the first driving structure 101 is located, and the second part 1002 is located in the region where the first gap 102 is located. After the driving layer 100 is prepared, the first filling layer 1000 includes the first part 1001 above the first driving structure 101 and the second part 1002 above the first gap 102.

[0059] The surface of the first part 1001 facing away from the driving layer 100 is the first surface, and the surface of the second part 1002 facing away from the driving layer 100 is the second surface. The surface of the first filling layer 1000 for carrying the metasurface layer 10 is at least divided into the first surface and the second surface, and the first surface is basically located in the pixel region, and the second surface is basically located in at least part of the region between adjacent pixels.

[0060] FIG. 6 is a schematic cross-sectional view of a partial structure of a control substrate provided by an embodiment of the present application.

[0061] As shown in FIG6 , along the direction Z perpendicular to the surface where the control substrate 01 is located, the maximum distance between the first surface and the second surface is D1, D1>0. This means that the surface of the first filling layer 1000 facing away from the drive layer 100 is the surface that supports the supersurface layer 10, and the surface of the first filling layer 1000 supporting the supersurface layer 10 includes a recessed structure, which is referred to as the first recessed structure H1. Then, along the direction Z perpendicular to the surface where the control substrate 01 is located, the orthographic projection of the first slit 102 surrounds the orthographic projection of the first recessed structure H1. Therefore, the surface of the second portion 1002 of the first filling layer 1000 facing the supersurface is recessed in a direction away from the supersurface relative to the surface of the first portion 1001 facing the supersurface.

[0062] In the embodiment of the present application, the super surface layer 10 is prepared on the first filling layer 1000 of the control substrate 01, and the integration of the super surface layer 10 and the control substrate 01 is achieved without a bonding process. The first filling layer 1000 covers the drive layer 100, and also covers the gaps between the multiple spaced first drive structures 101 and the adjacent first drive structures 101. Then, a first filling layer 1000 for carrying the super surface layer 10 is provided between the super surface layer 10 and the drive layer 100, and also provides the super surface layer 10 with a bearing layer that is flatter relative to the drive layer 100. In addition, the depression depth of the first concave structure H1 that appears due to the presence of the first gap 102 is greater than 0. When preparing the control substrate 01 provided in the embodiment of the present application, the surface of the first filling layer 1000 facing the super surface layer 10 is not fully filled or polished, and the preparation difficulty of the control substrate 01 provided in the present application is low.

[0063] In one embodiment of the present application, the driving layer 100 includes a driving circuit DR and a pixel electrode PE. The pixel electrode PE can be located on the side of the driving circuit DR close to the super-surface layer 10, and the driving circuit DR provides a driving voltage for the pixel electrode PE, wherein the first driving structure 101 can be the pixel electrode PE.

[0064] Optionally, the driving layer 100 includes multiple driving circuits DR and these driving circuits DR can be pixel driving circuits DR, that is, the pixel electrodes PE included in different pixels are electrically connected to different driving circuits DR. In this case, the first driving structure 101 can be electrically connected to the pixel driving circuits DR one by one.

[0065] Optionally, the driving circuit DR included in the driving layer 100 may be an IC driving circuit, that is, different pixel electrodes PE may all be electrically connected to the IC driving circuit. In this case, the first driving circuit DR may all be electrically connected to the IC driving circuit.

[0066] In addition, an insulating dielectric layer is included between the film layer where the pixel electrode PE is located and the film layer where the driving circuit DR is located. The insulating dielectric layer can be made of materials such as silicon oxide, silicon nitride, quartz, and glass, and the refractive index of the insulating dielectric layer can be smaller than the refractive index of the microstructure, and the difference can be greater than 1.

[0067] Since the first filling layer 1000 supports the supersurface layer 10, the flatness of the surface of the first filling layer 1000 near the supersurface layer 10 affects the arrangement of the microstructures 11 in the supersurface layer 10. Different arrangements of the microstructures 11 in the supersurface layer 10 lead to different results in controlling the light field. Therefore, the flatness of the surface of the first filling layer 1000 near the supersurface layer 10 affects the optical performance of the supersurface layer 10.

[0068] Since the first filling layer 1000 is prepared after the driving layer 100, the presence of the first gap 102 will affect the flatness of the surface of the first filling layer 1000 near the super surface layer 10, which leads to the presence of the first recessed structure H1. When the first recessed structure H1 reaches a certain depth, the microstructure 11 located above and around the first recessed structure H1 will appear to sink significantly, thereby causing the optical performance of the super surface layer 10 to deteriorate significantly. Therefore, it is necessary to control the depth of the first recessed structure H1 to ensure the optical performance of the super surface layer 10.

[0069] In one embodiment of the present application, as shown in FIG6 , the height of the first slit 102 along a direction Z perpendicular to the surface of the control substrate 01 is D2, which can be understood as the depth of the first slit 102 being D2. Where D1 ≤ D2 / 5, that is, the depth of the first recessed structure H1 is less than or equal to one-fifth of the depth of the first slit 102.

[0070] Through simulations, the inventors discovered that when the depth of the first recessed structure H1 is greater than 0 and less than or equal to one-fifth of the depth of the first gap 102, the preparation difficulty of the first filling layer 1000 is low and the process cost is low. Furthermore, when D1 ≤ D2 / 5, the optical performance of the metasurface layer 10 can meet conventional requirements. In other words, even if the first recessed structure H1 exists near the surface of the metasurface layer 10 in the first filling layer 1000, the depth of the first recessed structure H1 is less than or equal to one-fifth of the depth of the first gap 102, ensuring that the degradation of the optical performance of the metasurface layer 10 is within a controllable range. Therefore, D1 ≤ D2 / 5 can balance process difficulty, process cost, and optical performance.

[0071] In one embodiment of the present application, 20nm≤D1≤80nm, that is, the maximum distance between the first surface and the second surface in the direction Z perpendicular to the surface where the control substrate 01 is located is greater than or equal to 20nm and less than or equal to 80nm. This embodiment limits the depth of the first recessed structure H1 to be between 20nm and 80nm. When the depth of the first recessed structure H1 is between 20nm and 80nm, based on the conventional size of the microstructure 11 in the supersurface layer 10, if the microstructure 11 in the supersurface layer 10 sinks at the location of the first recessed structure H1 and its vicinity, the sinking depth will not significantly affect the regulation of the light field by the microstructure 11.

[0072] As described above, the location of the first driving structure 101 can basically define the location of the pixel, so the area between adjacent first driving structures 101 corresponds to the area outside the pixel. It can be understood that the area where the first slit 102 is located corresponds to the area outside the pixel. However, when the arrangement of the microstructure 11 above the first slit 102 in the super surface layer 10 sinks due to the recessed structure of the first filling layer 1000 toward the super surface layer 10, it will still affect the light emitted from the pixel area. This is because the microstructure 11 above the first slit 102 will refract and reflect the received light, and since the shape or arrangement of these microstructures 11 and the microstructure 11 above the first driving structure 101 has changed, the light refracted and reflected by the microstructure 11 above the first slit 102 is regarded as stray light and some stray light can enter the pixel area. The stray light entering the pixel area increases the crosstalk between pixels and changes the light output of the pixels. Therefore, the concave structure of the first filling layer 1000 toward the super-surface layer 10 will cause the spatial modulator where the control substrate 01 is located to have unstable control effect on the light field.

[0073] To address the above-mentioned issues, in one embodiment of the present application, as shown in FIG6 , the width of the first slit 102 along the first direction is W1, and the width of the first recessed structure H1 along the first direction is W2, where W2 ≤ W1 / 5. That is, the width of the first recessed structure H1 along the first direction is less than or equal to one-fifth of the width of the first slit 102 below it along the first direction. In this embodiment of the present application, by limiting W2 ≤ W1 / 5, the width of the first recessed structure H1 along the first direction is less than or equal to one-fifth of the width of the slit between adjacent pixels arranged along the first direction. This creates a certain distance in the first direction between the region where the first recessed structure H1 resides and the region where the pixels reside. This reduces the probability of stray light generated by the microstructure 11 above the first slit 102 entering the region where the pixels reside, thereby improving the stability of the light field control effect of the spatial light modulator where the control substrate 01 resides.

[0074] Among them, the first direction can be any direction parallel to the plane where the control substrate 01 is located, so there can be a certain distance between the area where the first recessed structure H1 is located and the area where the pixel is located in any direction, effectively improving the stability of the control effect of the spatial modulator where the control substrate 01 is located on the light field.

[0075] In one implementation, 0 < W2 ≤ 30nm, meaning the width of the first recessed structure H1 along the first direction is 30nm or less. The first direction can be any direction parallel to the plane where the control substrate 01 resides, and the width of the first recessed structure H1 in any direction can be 30nm or less. When the width of the first recessed structure H1 is 30nm or less, based on the precision of existing semiconductor processes, a distance can be substantially maintained between the region where the first recessed structure H1 resides and the region where the pixels reside, thereby improving the stability of the light field control effect of the spatial modulator where the control substrate 01 resides.

[0076] When the gap width between two adjacent first driving structures 101 is larger, the depression of the portion of the upper surface of the first filling layer 1000 located above the gap is deeper, which makes the microstructure 11 in the super surface layer 10 sink more obviously. Among them, the width of the gap surrounded by at least three adjacent first driving structures 101 is wider. For example, in combination with Figures 5 and 6, when the periphery of the first gap 102 includes four first driving structures 101, the projection shape of the first gap 102 along the direction Z perpendicular to the surface where the control substrate 01 is located is close to a circle with a diameter of 20nm-400nm, and the cross-section of the first gap 102 along the direction Z perpendicular to the surface where the control substrate 01 is located is close to a semicircle with a radius of 10nm-50nm.

[0077] Therefore, when considering the flatness of the first filling layer 1000 supporting the metasurface layer 10, the second portion 1002 of the first filling layer 1000 that overlaps with the gap surrounded by at least three adjacent first drive structures 101 is the portion that requires special attention. Therefore, in the control substrate 01 provided in the embodiment of the present application, at least a portion of the periphery of the first gap 102 includes no less than three first drive structures 101, that is, at least a portion of the second portion 1002 of the first filling layer 1000 is located above the first gap 102 surrounded by at least three first drive structures 101.

[0078] Optionally, in the embodiment of the present application, the depth of the first recessed structure H1 above the first slit 102 surrounded by at least three adjacent first driving structures 101 is less than or equal to one-fifth of the depth of the first slit 102. For example, the depth of the first recessed structure H1 above the first slit 102 surrounded by four adjacent first driving structures 101 is less than or equal to one-fifth of the depth of the first slit 102.

[0079] Optionally, in the embodiment of the present application, the depth of the first recessed structure H1 above the first slit 102 surrounded by at least three adjacent first driving structures 101 is between 20 nm and 80 nm. For example, the depth of the first recessed structure H1 above the first slit 102 surrounded by four adjacent first driving structures 101 is between 20 nm and 80 nm.

[0080] Optionally, in the embodiment of the present application, the width of the first recessed structure H1 above the first slit 102 surrounded by at least three adjacent first driving structures 101 along the first direction is W2, and W2 is less than or equal to one-fifth of the width W1 of the first slit 102 below the first recessed structure H1 along the first direction. For example, the width of the first recessed structure H1 above the first slit 102 surrounded by four adjacent first driving structures 101 along the first direction is W2, and W2 is less than or equal to one-fifth of the width W1 of the first slit 102 along the first direction.

[0081] Optionally, in the embodiment of the present application, the width of the first recessed structure H1 above the first gap 102 surrounded by at least three adjacent first driving structures 101 along the first direction is between 20 nm and 80 nm.

[0082] FIG7 is a schematic cross-sectional view of a partial structure of a control substrate provided in an embodiment of the present application.

[0083] In the embodiment of the present application, as shown in FIG7 , of any two first recessed structures H1, the one with the greater depth has a depth D11, and the one with the smaller depth has a depth D12, where D11 and D12 satisfy the following relationship: D12 ≥ D11 * 80%. Thus, the depth difference between different first recessed structures H1 in the first filling layer 1000 is less than 20% of the maximum depth. When the depth difference between different first recessed structures H1 in the first filling layer 1000 is less than 20% of the maximum depth, the surface uniformity of the metasurface layer 10 supported by the first filling layer 1000 is good. Even if the microstructures 11 in the metasurface layer 10 sink due to the presence of the first recessed structures H1, the depth of the sinking is substantially consistent, which facilitates achieving uniform light field control effects of the spatial light modulator on which the control substrate 01 is located.

[0084] In one embodiment of the present application, the first filling layer 1000 is a single film layer, that is, the film layer between the driving layer 100 and the super-surface layer 10 only includes one film layer, namely, the first filling layer 1000 .

[0085] FIG8 is a schematic cross-sectional view of a control substrate provided in an embodiment of the present application.

[0086] In one embodiment of the present application, as shown in Figure 8, the first filling layer 1000 includes a plurality of stacked first sub-filling layers 100a, that is, a plurality of film layers are included between the driving layer 100 and the super surface, and the plurality of film layers are the first sub-filling layers 100a. The materials of the plurality of first sub-filling layers 100a can be the same, or the materials of some of the first sub-filling layers 100a in the plurality of first sub-filling layers 100a are different. When the first sub-filling layer 100a is prepared multiple times on the driving layer 100, the portion of the first sub-filling layer 100a located above the first gap 102 includes a recessed structure. When the stacked plurality of first sub-filling layers 100a are prepared in sequence, the width and depth of the recessed structure of the first sub-filling layer 100a prepared later are smaller, and the recessed structure of the first sub-filling layer 100a prepared last is the first recessed structure H1 and its width and depth are reduced. Therefore, by stacking multiple first sub-filling layers 100a to form the first filling layer 1000, a first recessed structure H1 with a smaller width and depth can be obtained.

[0087] In one embodiment of the present application, the refractive index of the microstructure 11 in the metasurface layer 10 is n1, and the refractive index of the first filling layer 1000 is n2, where n1>n2, i.e., the refractive index of the first filling layer 1000 is less than the refractive index of the microstructure 11. Regardless of whether it is a transmissive spatial light modulator or a reflective spatial light modulator, the light entering the metasurface layer 10 and being regulated and emitted is incident on the metasurface layer 10 through the first filling layer 1000. For example, the light to be regulated by the reflective spatial light modulator is incident on the side of the opposing substrate 02 away from the control substrate 01 and reaches the reflective structure of the control substrate 01 (e.g., the first driving structure 101). After being reflected by the reflective structure, it first passes through the first filling layer 1000 and then passes through the metasurface layer 10.

[0088] In this embodiment, since the refractive index of the first filling layer 1000 is smaller than that of the microstructure 11 , light will be deflected at a larger angle when incident from the first filling layer 1000 to the super-surface layer 10 , thereby achieving the purpose of controlling light deflection.

[0089] In one implementation of this embodiment, n1-n2>1.

[0090] FIG9 is a schematic cross-sectional view of a control substrate provided in an embodiment of the present application.

[0091] As shown in Figures 3 and 9, the control substrate 01 provided in the embodiment of the present application may also include a second filling layer 10000, and the second filling layer 10000 is located on the side of the super surface layer 10 away from the first filling layer 1000, then the second filling layer 10000 can be used to protect the super surface layer 10.

[0092] The second filling layer 10000 includes a third portion and a fourth portion, with the third portion located in the region of the first portion 1001 and the fourth portion located in the region of the second portion 1002. Thus, the orthographic projection of the third portion along a direction perpendicular to the surface of the control substrate 01 overlaps with the orthographic projection of the first portion 1001 along a direction perpendicular to the surface of the control substrate 01, and the orthographic projection of the fourth portion along a direction perpendicular to the surface of the control substrate 01 overlaps with the orthographic projection of the second portion 1002 along a direction perpendicular to the surface of the control substrate 01. Optionally, the orthographic projection of the first portion 1001 along a direction perpendicular to the surface of the control substrate 01 overlaps the orthographic projection of the third portion along a direction perpendicular to the surface of the control substrate 01; and the orthographic projection of the second portion 1002 along a direction perpendicular to the surface of the control substrate 01 overlaps the orthographic projection of the fourth portion along a direction perpendicular to the surface of the control substrate 01.

[0093] The surface of the third portion facing away from the driving layer 100 is the third surface, and the surface of the fourth portion facing away from the driving layer 100 is the fourth surface; along the direction Z perpendicular to the surface where the control substrate 01 is located, the maximum distance between the third surface and the fourth surface is D3, D3<D1.

[0094] FIG10 is a schematic cross-sectional view of a partial structure of a control substrate provided in an embodiment of the present application.

[0095] The structure of the second filling layer 10000 may be similar to that of the first filling layer 1000. For example, as shown in FIG10 , the second filling layer 10000 includes a plurality of stacked second sub-filling layers 10000a, which will not be described in detail here.

[0096] In one technical solution, as shown in FIG3 , the fourth surface does not have a recess relative to the third surface, that is, D3=0, and the surface of the second filling layer 10000 away from the super-surface layer 10 does not include a recessed structure.

[0097] In one technical solution, as shown in FIG9 , the fourth surface is recessed relative to the third surface, i.e., D3>0. Then, the surface of the second filling layer 10000 away from the supersurface layer 10 includes a second recessed structure H2, and the orthographic projection of the second recessed structure H2 along a direction Z perpendicular to the surface of the control substrate 01 overlaps with the orthographic projection of the first recessed structure H1 along a direction Z perpendicular to the surface of the control substrate 01. In this technical solution, 0<D3<D1, and the recessed depth of the second recessed structure H2 is less than the recessed depth of the first recessed structure H1.

[0098] FIG11 is a schematic cross-sectional view of a control substrate provided in an embodiment of the present application.

[0099] As shown in FIG3 and FIG11 , the angle between the side surface of the microstructure 11 and the plane where the control substrate is located is α.

[0100] In some embodiments, as shown in FIG. 11 , 0°<α<90°, for example, α=85°.

[0101] In some embodiments, as shown in FIG. 3 , α=90°.

[0102] FIG12 is a schematic cross-sectional view of a control substrate provided in an embodiment of the present application.

[0103] In one embodiment of the present application, as shown in FIG12 , along a direction Z perpendicular to the surface of the control substrate, the orthographic projection of the microstructure in the metasurface layer 10 does not overlap with the first recessed structure H1. Therefore, the microstructure 11 is not disposed above the first recessed structure H1 to prevent the sinking and tilting of the microstructure 11 from emitting stray light toward the pixel area.

[0104] In one embodiment of the present application, as shown in Figures 3 and 11, along a direction Z perpendicular to the surface of the control substrate, the orthographic projection of the microstructure in the super-surface layer 10 overlaps with the first recessed structure H1. This allows the microstructure 11 to be uniformly fabricated across the entire surface, reducing the process complexity.

[0105] The present application also provides a method for preparing the control substrate provided in any of the above embodiments, the method comprising:

[0106] S1: A drive layer 100 is formed on a silicon substrate. The drive layer 100 includes a plurality of first drive structures 101. The silicon substrate may include a plurality of pixel drive circuits DR. The first drive structures 101 formed on the silicon substrate may be electrically connected to the pixel drive circuits DR. The silicon substrate may have a size of 12 mm by 8 mm. The first drive structures 101 may be square in shape and have a size of 4 μm by 4 μm. The gap width between adjacent first drive electrodes may be 200 nm. The plurality of first drive structures 101 formed on the silicon substrate may be arranged in a 2400 by 1200 array.

[0107] The step of forming the driving layer 100 on the silicon substrate may specifically include:

[0108] S11: depositing a first electrode layer on the silicon substrate; the material of the first electrode layer may be aluminum, and the thickness of the first electrode layer may be 300 nm.

[0109] S12: patterning the first electrode layer to form a driving layer 100 including a plurality of first driving structures 101; wherein, the method of patterning the first electrode layer can be wet etching or dry etching combined with a mask.

[0110] If the driving layer 100 further includes a driving circuit DR, the driving layer 100 is formed on a silicon substrate, and specifically may further include:

[0111] S10: doping the silicon substrate and depositing a conductive layer to form a plurality of transistors and other electronic components constituting the driving circuit DR. The first driving structure 101 is electrically connected to the driving circuit DR.

[0112] S2: forming a first filling layer 1000 on the driving layer 100. The first filling layer 1000 covers the previously prepared driving layer 100. The material of the first filling layer 1000 can be silicon dioxide, silicon nitride, etc.

[0113] The first filling layer 1000 is formed on the driving layer 100, and at least includes:

[0114] S21: using a high-density plasma chemical vapor deposition (HDPCVD) or atomic layer deposition (ALD) process to deposit an initial filling layer on a side of the first electrode layer away from the silicon substrate.

[0115] This article uses the HDPCVD process to deposit an initial fill layer made of silicon dioxide as an example. The reaction gases used for deposition can be SiH₄ and O₂, and the auxiliary gas can be N₂. The deposition process parameters are: a chamber temperature of 50°C and a pressure of 1 Torr. When the initial fill layer has a thickness of 250nm, the deposition time is approximately 30 seconds.

[0116] When the first filling layer 1000 includes a plurality of stacked first sub-filling layers 100 a , step S21 may be repeated to obtain a plurality of stacked initial filling layers, which are the plurality of stacked first sub-filling layers 100 a included in the first filling layer 1000 .

[0117] In addition, forming a first filling layer 1000 on a side of the driving layer 100 away from the silicon substrate may further include:

[0118] S22: Polishing the surface of the initial filling layer away from the driving layer 100 to obtain the first filling layer 1000. The specific polishing method may be chemical mechanical polishing, and the process parameters during polishing may be: rotation speed 50 rpm, polishing liquid flow rate 90 ml / min, pressure 300 gf / cm2, and polishing time 60 s.

[0119] It should be noted that when the first filling layer 1000 includes multiple stacked first sub-filling layers 100a, that is, when step S21 needs to be repeated to prepare multiple stacked initial filling layers, the surface away from the driving layer 100 in each deposited initial filling layer can be polished, or only the surface away from the driving layer 100 in the last prepared initial filling layer can be polished.

[0120] In addition, when preparing multiple stacked initial filling layers using step S21, HDPCVD / ALD technology and / or plasma enhanced chemical vapor deposition (PECVD) technology can be used respectively. For example, HDPCVD technology or ALD technology is used when preparing at least one initial filling layer, and PECVD technology is used when preparing at least one initial filling layer. For example, first, HDPCVD technology or ALD technology is used to prepare one initial filling layer, and then PECVD technology is used to prepare at least one initial filling layer; for example, HDPCVD / ALD technology and PECVD technology are used alternately to prepare the initial filling layer. In addition, multiple rounds of HDPCVD technology can be used to prepare multiple initial filling layers, or multiple rounds of ALD technology can be used to prepare multiple initial filling layers.

[0121] Optionally, an initial filling layer may be first prepared using HDPCVD technology or ALD technology, and then an initial filling layer may be prepared using PECVD technology and the initial filling layer prepared using PECVD technology may be polished to complete one round of preparation, and the above process may be repeated to complete at least one new round of preparation.

[0122] The method of forming the first filling layer 1000 on the driving layer 100 may further include: performing a secondary polishing on the initial filling layer by using an ion beam correction method after chemical mechanical polishing is performed on the surface of the initial filling layer away from the driving layer 100 .

[0123] In the embodiment of the present application, at least one of the HDPCVD technology, the ALD technology, and the PECVD technology can be replaced by a spin coating technology such as spin on glass (SOG) and spin on dielectric (SOD).

[0124] In the present application, the first filling layer 1000 includes a first recessed structure H1, that is, even if the surface of the initial filling layer away from the driving layer 100 is polished, the recessed structure caused by the presence of the first gap 102 is not completely smoothed. The present application appropriately reduces the degree of polishing to avoid the use of a polishing stop layer. Since the refractive index of the polishing stop layer is usually different from the refractive index of the initial filling layer and the microstructure, the introduction of a polishing stop layer will lead to increased light loss and reduce the efficiency of the microstructure in regulating the light field. Therefore, in the present application, the first filling 1000 includes the first recessed structure H1, and the polishing stop layer may not be used, thereby ensuring the consistency of the refractive index of the first filling layer 1000, effectively alleviating or even avoiding the above problems.

[0125] S3: preparing a supersurface layer 10 on the first filling layer 1000 .

[0126] The process of preparing the super surface layer 10 on the first filling layer 1000 may specifically include:

[0127] S31: Depositing an initial metasurface on the first filling layer 1000. PECVD technology can be used to deposit an initial metasurface with a thickness of approximately 500 nm. The material of the initial metasurface can be amorphous silicon. The reaction gas for depositing the initial metasurface using the PECVD process can be SiH4, and the auxiliary gas can be Ar. The process parameters during deposition can be: a temperature in the reaction chamber of 300°C, a pressure of 350 MPa, a power of 250 W, a SiH4 flow rate of 100 sccm, an Ar flow rate of 600 sccm, and a deposition time of 300 s.

[0128] S32: Patterning the initial metasurface to form a microstructure 11, obtaining a metasurface layer 10. The initial metasurface can be patterned by dry etching. Specifically, a photoresist is first coated on the initial metasurface, exposed, and developed. Then, the portion of the initial metasurface exposed by the photoresist is etched in a chamber containing Cl2 and SF6. The etching parameters include a chamber temperature of 80°C, a pressure of 12 mT, a Cl2 flow rate of 20 sccm, an SF6 flow rate of 6 sccm, and an etching time of 240 s.

[0129] If the control substrate further includes a second filling layer 1000, the preparation method further includes:

[0130] S4: forming a second filling layer 10001 on the super surface layer 10. The second filling layer 10000 covers the previously prepared super surface layer 10. The material of the second filling layer 10000 can be silicon dioxide, silicon nitride, etc.

[0131] The second filling layer 10001 is formed on the super surface layer 10, which at least includes:

[0132] S41: using a high-density plasma chemical vapor deposition (HDPCVD) or atomic layer deposition (ALD) process to deposit an initial filling layer on a side of the super surface layer 10 away from the silicon substrate.

[0133] This article uses the HDPCVD process to deposit an initial fill layer made of silicon dioxide as an example. The reaction gases used for deposition can be SiH₄ and O₂, and the auxiliary gas can be N₂. The deposition process parameters are: a chamber temperature of 50°C and a pressure of 1 Torr. When the initial fill layer is 600nm thick, the deposition time is approximately 72 seconds.

[0134] When the second filling layer 10000 includes multiple stacked second sub-filling layers 10000a, step S41 can be repeated to obtain multiple stacked initial filling layers, which are the multiple stacked second sub-filling layers 10000a included in the second filling layer 10000.

[0135] S22: Polishing the surface of the initial filling layer away from the super surface layer to obtain a second filling layer 10000.

[0136] In addition, the techniques and methods used to prepare the multiple initial filling layers of the second filling layer and polish the initial filling layers may be substantially similar to the techniques and methods used to prepare the multiple initial filling layers of the first filling layer, and are not described in detail herein.

[0137] In this specification, reference can be made to the same or similar parts between the various embodiments. In particular, for the device embodiment and the terminal embodiment, since they are basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiment.

Claims

1. A control substrate, characterized in that: include: A driving layer comprising a plurality of first driving structures, wherein first gaps are formed between adjacent first driving structures; a metasurface layer comprising multiple microstructures; a first filling layer, located between the driving layer and the supersurface layer and used to support the supersurface layer; The first filling layer includes a first portion and a second portion, the first portion is located in the area where the first driving structure is located, and the second portion is located in the area where the first gap is located; The surface of the first part away from the driving layer is the first surface, and the surface of the second part away from the driving layer is the second surface; along the direction perpendicular to the surface of the control substrate, the maximum distance between the first surface and the second surface is D1, D1>0.

2. The control substrate according to claim 1, wherein: The height of the first gap along a direction perpendicular to the surface where the control substrate is located is D2; D1≤D2 / 5.

3. The control substrate according to claim 1, wherein: At least a portion of the periphery of the first gap includes no less than three first driving structures.

4. The control substrate according to claim 1, wherein: 20nm≤D1≤80nm.

5. The control substrate according to claim 1, wherein: The surface of the second portion facing away from the driving layer includes a first concave structure; along a direction perpendicular to the surface where the control substrate is located, the orthographic projection of the first slit surrounds the orthographic projection of the first concave structure; The width of the first gap corresponding to the first recessed structure along the first direction is W1, and the width of the first recessed structure along the first direction is W2, where W2≤W1 / 5.

6. The control substrate according to claim 5, wherein: 0<W2≤30nm.

7. The control substrate according to claim 1, wherein: The surface of the second portion facing away from the driving layer includes a plurality of first concave structures; along a direction perpendicular to the surface where the control substrate is located, the orthographic projection of the first slit surrounds the orthographic projection of the first concave structure; Among any two of the first concave structures, the depth of the one with the larger depth is D 11 The depth of the smaller one is D 12 , where D 11 With D 12 Satisfied: D 12 ≥D 11 *80%.

8. The control substrate according to claim 1, wherein: The first filling layer includes a plurality of stacked first sub-filling layers.

9. The control substrate according to claim 1, wherein: The refractive index of the microstructure is n1, the refractive index of the first filling layer is n2, and n1>n2.

10. The control substrate according to claim 9, wherein: n1-n2>1.

11. The control substrate according to claim 1, wherein: The control substrate further includes: a second filling layer, located on a side of the super surface layer facing away from the first filling layer; The second filling layer includes a third part and a fourth part, the third part is located in the area where the first part is located, and the fourth part is located in the area where the second part is located; the surface of the third part facing away from the drive layer is the third surface, and the surface of the fourth part facing away from the drive layer is the fourth surface; along the direction perpendicular to the surface where the control substrate is located, the maximum distance between the third surface and the fourth surface is D3, D3<D1.

12. The control substrate according to claim 1, wherein The driving layer includes a driving circuit and a first pixel electrode. The first pixel electrode is located on a side of the driving circuit close to the super-surface layer. The first driving structure is the first pixel electrode.

13. A spatial light modulator, characterized in that: It includes the control substrate according to claim 1.

14. The spatial light modulator according to claim 13, wherein The spatial light modulator further comprises: an opposing substrate, arranged opposite to the control substrate; The liquid crystal layer is located between the control substrate and the opposing substrate.

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