Digital circuit for multi-MIPI-RFFE interface, and radio frequency device

Abstract

The present invention is suitable for the technical field of radio frequency circuits, and particularly relates to a digital circuit for a multi-MIPI-RFFE interface, and a radio frequency device. The digital circuit comprises first and second MIPI protocol parsing modules, a logic parsing module, a control circuit module and a radio frequency circuit module, wherein an input end of the first MIPI protocol parsing module is connected to an external first MIPI host, and an output end of the first MIPI protocol parsing module is connected to a first input end of the logic parsing module; an input end of the second MIPI protocol parsing module is connected to an external second MIPI host, and an output end of the second MIPI protocol parsing module is connected to a second input end of the logic parsing module; an output end of the logic parsing module is connected to an input end of the control circuit module; and an output end of the control circuit module is connected to an input end of the radio frequency circuit module. The present invention prevents the problem of configuration conflicts caused by direct connection of different registers to a control circuit.

Description

Digital circuits and RF devices for multiple MIPI-RFFE interfaces Technical Field

[0001] The present invention is applicable to the field of radio frequency circuit technology, and in particular relates to a digital circuit and radio frequency device for multiple MIPI-RFFE interfaces. Background Art

[0002] The MIPI (Mobile Industry Processor Interface) protocol is a standardized communication protocol for inter-device communication in mobile terminal systems. The RF front-end control interface implemented in accordance with this protocol is called the MIPI RFFE (MIPI RF Front-end) interface. Figure 1 shows a system architecture diagram of an existing RF front-end device. This RF front-end device consists of a MIPI-RFFE interface circuit, a MIPI register circuit, a control circuit, and a RF circuit. Through this architecture, an external MIPI-RFFE host can connect to the MIPI-RFFE interface within the architecture to configure the RF front-end device for communication purposes.

[0003] However, the architecture shown in Figure 1 presents the following issues: If MIPI-RFFE Host 1 and MIPI-RFFE Host 3 need to implement the same functionality, they must have registers with the same functionality (MIPI1 registers and MIPI3 registers) on their corresponding buses. This is because registers with the same functionality have the same effect on controlling the RF circuit. If different types of registers are used, when MIPI-RFFE Host 1 and MIPI-RFFE Host 3 are simultaneously connected to the RF front-end device and input signals with the same functionality, the control circuit cannot correctly control the RF circuit.

[0004] In this case, priority processing can only be performed on the signals of MIPI-RFFE Host 1 and MIPI-RFFE Host 3 with the same function registers. However, the priority processing logic of the architecture shown in Figure 1 can only be set in the control circuit (in this case, it can receive two different signals). For the control circuit, it cannot identify the order in which the buses on which MIPI-RFFE Host 1 and MIPI-RFFE Host 3 are configured, which will cause configuration conflicts. Summary of the Invention

[0005] The present invention provides a digital circuit and radio frequency device for multiple MIPI-RFFE interfaces, aiming to solve the problem of configuration conflict in the control circuit when a radio frequency device is set with multiple MIPI-RFFE interfaces.

[0006] To solve the above technical problems, in a first aspect, the present invention provides a digital circuit for multiple MIPI-RFFE interfaces, the digital circuit comprising a first MIPI protocol parsing module, a second MIPI protocol parsing module, a logic parsing module, a control circuit module and a radio frequency circuit module; wherein,

[0007] The input end of the first MIPI protocol parsing module is connected to an external first MIPI host, the output end of the first MIPI protocol parsing module is connected to the first input end of the logic parsing module, and the first MIPI protocol parsing module is used to parse the first MIPI control signal sent by the first MIPI host and send the parsed signal to the logic parsing module;

[0008] The input end of the second MIPI protocol parsing module is connected to the external second MIPI host, the output end of the second MIPI protocol parsing module is connected to the second input end of the logic parsing module, and the second MIPI protocol parsing module is used to parse the second MIPI control signal sent by the second MIPI host and send the parsed signal to the logic parsing module;

[0009] The output end of the logic analysis module is connected to the input end of the control circuit module, and the logic analysis module is used to select one of the first MIPI control signal and the second MIPI control signal and send it to the control circuit module;

[0010] The output end of the control circuit module is connected to the input end of the radio frequency circuit module.

[0011] Furthermore, the logic parsing module includes a trigger, a selector and a common register, wherein:

[0012] The clock terminal CLK and the data input terminal D of the trigger are connected to a high level for a long time, the asynchronous reset terminal RB of the trigger is connected to the first input terminal of the logic analysis module, the asynchronous set terminal SETB of the trigger is connected to the second input terminal of the logic analysis module, and the data output terminal Q of the trigger is connected to the first input terminal of the selector;

[0013] The second input terminal and the third input terminal of the selector are connected to the first input terminal and the second input terminal of the logic parsing module respectively, and the output terminal of the selector is connected to the input terminal of the common register;

[0014] The output end of the common register serves as the output end of the logic analysis module and is connected to the input end of the control circuit module.

[0015] Furthermore, the first MIPI protocol parsing module includes a first MIPI parsing submodule and a first register, wherein:

[0016] The first MIPI parsing submodule is used to parse the first MIPI control signal generated by the first MIPI host through the MIPI-RFFE protocol to obtain a first write enable signal we1, a first write address signal addr1 and a first write data signal wdata1, and send them to the second input end of the selector;

[0017] The first register is used to write the first write data signal wdata1 into the common register, and combine the first write enable signal we1 and the first write address signal addr1 through a preset combination logic to obtain a first combination signal, and then send the first combination signal to the asynchronous reset terminal RB of the trigger through the first input terminal of the logic analysis module.

[0018] Furthermore, the preset combination logic is processed according to AND logic combination.

[0019] Furthermore, the first register is connected to the output end of the logic analysis module, and the first register is further used to:

[0020] The output of the common register is acquired to obtain first read-back data rdata1, and the first read-back data rdata1 is returned to the first MIPI host through the first MIPI parsing submodule.

[0021] Furthermore, the second MIPI protocol parsing module includes a second MIPI parsing submodule and a second register, wherein:

[0022] The second MIPI parsing submodule is used to parse the second MIPI control signal generated by the second MIPI host through the MIPI-RFFE protocol to obtain a second write enable signal we2, a second write address signal addr2, and a second write data signal wdata2, and send them to the third input terminal of the selector;

[0023] The second register is used to write the second write data signal wdata2 into the common register, and combine the second write enable signal we2 and the second write address signal addr2 through a preset combination logic to obtain a second combination signal, and then send the second combination signal to the asynchronous set end SETB of the trigger through the second input end of the logic analysis module.

[0024] Furthermore, the preset combination logic is processed according to AND logic combination.

[0025] Furthermore, the second register is connected to the output end of the logic analysis module, and the second register is further used to:

[0026] The output of the common register is obtained to obtain second read-back data rdata2, and the second read-back data rdata2 is returned to the second MIPI host through the second MIPI parsing submodule.

[0027] In a second aspect, the present invention also provides a radio frequency device, comprising a digital circuit for multiple MIPI-RFFE interfaces as described in any one of the above items.

[0028] The beneficial effect achieved by the present invention is that a digital circuit is proposed that includes a common register used uniformly by different MIPI-RFFE interfaces. In this digital circuit, a logic analysis module is used to read and write address signals for different MIPI host signals respectively, thereby identifying the writing order of different signals and outputting the last written register data to the subsequent control circuit. In this application, a logic analysis module is set as the only input of the control circuit in the RF device, which not only prevents the configuration conflict problem caused by the direct connection of different registers to the control circuit, but also can realize the correct logical sequential reading of multiple MIPI interface configurations, thereby improving the availability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a system framework diagram of a radio frequency front-end device in the prior art;

[0030] FIG2 is a logic diagram of a digital circuit for multiple MIPI-RFFE interfaces provided by an embodiment of the present invention;

[0031] FIG3 is a logic diagram of the logic analysis module 103 provided in an embodiment of the present invention;

[0032] FIG4 is a schematic diagram of a waveform of data written by the common register 1033 according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0034] Please refer to Figure 2, which is a logical diagram of a digital circuit for multiple MIPI-RFFE interfaces provided by an embodiment of the present invention. The digital circuit 100 for multiple MIPI-RFFE interfaces includes a first MIPI protocol parsing module 101, a second MIPI protocol parsing module 102, a logic parsing module 103, a control circuit module 104, and a radio frequency circuit module 105; wherein,

[0035] The input end of the first MIPI protocol parsing module 101 is connected to the external first MIPI host 201, and the output end of the first MIPI protocol parsing module 101 is connected to the first input end of the logic parsing module 103. The first MIPI protocol parsing module 101 is used to parse the first MIPI control signal sent by the first MIPI host 201 and send the parsed signal to the logic parsing module 103;

[0036] The input end of the second MIPI protocol parsing module 102 is connected to the external second MIPI host 202, and the output end of the second MIPI protocol parsing module 102 is connected to the second input end of the logic parsing module 103. The second MIPI protocol parsing module 102 is used to parse the second MIPI control signal sent by the second MIPI host 202 and send the parsed signal to the logic parsing module 103;

[0037] The output end of the logic analysis module 103 is connected to the input end of the control circuit module 104, and the logic analysis module 103 is used to select one of the first MIPI control signal and the second MIPI control signal and send it to the control circuit module 104;

[0038] The output end of the control circuit module 104 is connected to the input end of the RF circuit module 105 .

[0039] Please refer to FIG. 3 , which is a logic diagram of the logic analysis module 103 provided in an embodiment of the present invention. In the embodiment of the present invention, the logic analysis module 103 includes a trigger 1031, a selector 1032, and a common register 1033, wherein:

[0040] The clock terminal CLK and the data input terminal D of the flip-flop 1031 are connected to a high level for a long time, the asynchronous reset terminal RB of the flip-flop 1031 is connected to the first input terminal of the logic analysis module 103, the asynchronous set terminal SETB of the flip-flop 1031 is connected to the second input terminal of the logic analysis module 103, and the data output terminal Q of the flip-flop 1031 is connected to the first input terminal of the selector 1032;

[0041] The second input terminal and the third input terminal of the selector 1032 are connected to the first input terminal and the second input terminal of the logic parsing module 103 respectively, and the output terminal of the selector 1032 is connected to the input terminal of the common register 1033;

[0042] The output end of the common register 1033 serves as the output end of the logic analysis module 103 and is connected to the input end of the control circuit module 104 .

[0043] Specifically, under such a connection mode, the common register 1033 will output a unique signal output by the selector 1032 to the control circuit module 104. The control circuit module 104 generates a control signal for controlling the RF circuit module 105 based on the value stored in the specific register in the signal, thereby completing the signal processing of the RF device.

[0044] In the embodiment of the present invention, the first MIPI protocol parsing module 101 includes a first MIPI parsing submodule 1011 and a first register 1012, wherein:

[0045] The first MIPI parsing submodule 1011 is used to parse the first MIPI control signal generated by the first MIPI host 201 through the MIPI-RFFE protocol to obtain a first write enable signal we1, a first write address signal addr1, and a first write data signal wdata1, and send them to the second input end of the selector 1032;

[0046] The first register 1012 is configured to write the first write data signal wdata1 into the common register 1033, and to combine the first write enable signal we1 and the first write address signal addr1 through a preset combinational logic to obtain a first combination signal. The first combination signal is then sent to the asynchronous reset terminal RB of the flip-flop 1031 through the first input terminal of the logic analysis module 103. The preset combinational logic performs AND logic combination processing.

[0047] The first register 1012 is connected to the output end of the logic analysis module 103, and the first register 1012 is further used to:

[0048] The output of the public register 1033 is obtained to obtain the first read-back data rdata1 , and the first read-back data rdata1 is returned to the first MIPI host 201 through the first MIPI parsing submodule 1011 .

[0049] In the embodiment of the present invention, the second MIPI protocol parsing module 102 includes a second MIPI parsing submodule 1021 and a second register 1022, wherein:

[0050] The second MIPI parsing submodule 1021 is configured to parse the second MIPI control signal generated by the second MIPI host 202 through the MIPI-RFFE protocol to obtain a second write enable signal we2, a second write address signal addr2, and a second write data signal wdata2, and send the signals to the third input terminal of the selector 1032;

[0051] The second register 1022 is configured to write the second write data signal wdata2 into the common register 1033, and to combine the second write enable signal we2 and the second write address signal addr2 through a preset combinational logic to obtain a second combination signal. The second combination signal is then sent to the asynchronous set terminal SETB of the flip-flop 1031 through the second input terminal of the logic analysis module 103. The preset combinational logic performs AND logic combination processing.

[0052] The second register 1022 is connected to the output end of the logic analysis module 103, and the second register 1022 is further used to:

[0053] The output of the public register 1033 is obtained to obtain the second read-back data rdata2, and the second read-back data rdata2 is returned to the second MIPI host 202 through the second MIPI parsing submodule 1021.

[0054] In the above process, the logic analysis module 103 actually outputs the data corresponding to the last write enable signal (we) sent by the first MIPI host 201 and the second MIPI host 202 through the selector 1032 .

[0055] To facilitate understanding of the technical effects of the digital circuit 100 for multiple MIPI-RFFE interfaces in an embodiment of the present invention, please refer to Figure 4. Figure 4 is a schematic diagram of the data write waveform of the common register 1033 provided in an embodiment of the present invention. For the common register 1033 (reg0a), in the first box indicated by the arrow, the first write enable signal we1 corresponding to the first MIPI host 201 generates a high pulse, the first write address signal addr1 is a, and the first write data signal wdata1 is bb, and then written into the common register 1033 through the first register 1012. At this time, the common register 1033 is written as bb; in the second box indicated by the arrow, the second write enable signal we2 corresponding to the second MIPI host 202 generates a high pulse, the second write address signal addr2 is a, and the second write data signal wdata2 is aa, and then written into the common register 1033. The common register 1033 is written from bb to aa. In this way, the subsequent control circuit module 104 can obtain the corresponding configuration data from the output of the common register 1033 according to the correct data writing order, avoiding the configuration conflict problem caused by multiple MIPI-RFFE interface architectures.

[0056] The beneficial effect achieved by the present invention is that a digital circuit is proposed that includes a common register used uniformly by different MIPI-RFFE interfaces. In this digital circuit, a logic analysis module is used to read and write address signals for different MIPI host signals respectively, thereby identifying the writing order of different signals and outputting the last written register data to the subsequent control circuit. In this application, a logic analysis module is set as the only input of the control circuit in the RF device, which not only prevents the configuration conflict problem caused by the direct connection of different registers to the control circuit, but also can realize the correct logical sequential reading of multiple MIPI interface configurations, thereby improving the availability of the device.

[0057] The present invention also provides a radio frequency device, which includes a digital circuit 100 for multiple MIPI-RFFE interfaces as described in any one of the above embodiments. When the radio frequency device includes the digital circuit 100 for multiple MIPI-RFFE interfaces, it can read and write address signals for different MIPI host signals based on the logic parsing module in the digital circuit, thereby identifying the writing order of different signals and outputting the last written register data to the subsequent control circuit, thereby preventing configuration conflicts caused by direct connection of different registers to the control circuit, realizing the correct logical sequential reading of multiple MIPI interface configurations, and improving the availability of the device. Refer to the description in the above embodiment, which will not be repeated here.

[0058] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0059] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only a preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, which are all within the protection of the present invention.

Claims

1. A digital circuit for multiple MIPI-RFFE interfaces, characterized in that: The digital circuit includes a first MIPI protocol analysis module, a second MIPI protocol analysis module, a logic analysis module, a control circuit module and a radio frequency circuit module; wherein, The input end of the first MIPI protocol parsing module is connected to an external first MIPI host, the output end of the first MIPI protocol parsing module is connected to the first input end of the logic parsing module, and the first MIPI protocol parsing module is used to parse the first MIPI control signal sent by the first MIPI host and send the parsed signal to the logic parsing module; The input end of the second MIPI protocol parsing module is connected to the external second MIPI host, the output end of the second MIPI protocol parsing module is connected to the second input end of the logic parsing module, and the second MIPI protocol parsing module is used to parse the second MIPI control signal sent by the second MIPI host and send the parsed signal to the logic parsing module; The output end of the logic analysis module is connected to the input end of the control circuit module, and the logic analysis module is used to select one of the first MIPI control signal and the second MIPI control signal and send it to the control circuit module; The output end of the control circuit module is connected to the input end of the radio frequency circuit module.

2. The digital circuit for multiple MIPI-RFFE interfaces according to claim 1, wherein: The logic parsing module includes a trigger, a selector and a common register, wherein: The clock terminal CLK and the data input terminal D of the trigger are long connected to a high level, the asynchronous reset terminal RB of the trigger is connected to the first input terminal of the logic analysis module, the asynchronous set terminal SETB of the trigger is connected to the second input terminal of the logic analysis module, and the data output terminal Q of the trigger is connected to the first input terminal of the selector; The second input terminal and the third input terminal of the selector are connected to the first input terminal and the second input terminal of the logic parsing module respectively, and the output terminal of the selector is connected to the input terminal of the common register; The output end of the common register serves as the output end of the logic analysis module and is connected to the input end of the control circuit module.

3. The digital circuit for multiple MIPI-RFFE interfaces according to claim 2, wherein: The first MIPI protocol parsing module includes a first MIPI parsing submodule and a first register, wherein: The first MIPI parsing submodule is used to parse the first MIPI control signal generated by the first MIPI host through the MIPI-RFFE protocol to obtain a first write enable signal we1, a first write address signal addr1 and a first write data signal wdata1, and send them to the second input end of the selector; The first register is used to write the first write data signal wdata1 into the common register, and combine the first write enable signal we1 and the first write address signal addr1 through a preset combination logic to obtain a first combination signal, and then send the first combination signal to the asynchronous reset terminal RB of the trigger through the first input terminal of the logic analysis module.

4. The digital circuit for multiple MIPI-RFFE interfaces according to claim 3, wherein: The preset combination logic is to process according to AND logic combination.

5. The digital circuit for multiple MIPI-RFFE interfaces according to claim 3, wherein: The first register is connected to the output end of the logic analysis module, and the first register is further used to: The output of the common register is acquired to obtain first read-back data rdata1, and the first read-back data rdata1 is returned to the first MIPI host through the first MIPI parsing submodule.

6. The digital circuit for multiple MIPI-RFFE interfaces according to claim 2, wherein: The second MIPI protocol parsing module includes a second MIPI parsing submodule and a second register, wherein: The second MIPI parsing submodule is used to parse the second MIPI control signal generated by the second MIPI host through the MIPI-RFFE protocol to obtain a second write enable signal we2, a second write address signal addr2, and a second write data signal wdata2, and send them to the third input terminal of the selector; The second register is used to write the second write data signal wdata2 into the common register, and combine the second write enable signal we2 and the second write address signal addr2 through a preset combination logic to obtain a second combination signal, and then send the second combination signal to the asynchronous set end SETB of the trigger through the second input end of the logic analysis module.

7. The digital circuit for multiple MIPI-RFFE interfaces according to claim 6, wherein: The preset combination logic is to process according to AND logic combination.

8. The digital circuit for multiple MIPI-RFFE interfaces according to claim 6, wherein: The second register is connected to the output end of the logic analysis module, and the second register is further used to: The output of the common register is obtained to obtain second read-back data rdata2, and the second read-back data rdata2 is returned to the second MIPI host through the second MIPI parsing submodule.

9. A radio frequency device, characterized in that: The radio frequency device includes a digital circuit for multiple MIPI-RFFE interfaces as described in any one of claims 1-8.

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