Pixel circuit and display apparatus

Abstract

Provided in the present disclosure are a pixel circuit and a display apparatus. The pixel circuit comprises a driving circuit, a light-emitting element and a first capacitor, wherein the driving circuit is electrically connected to a first node and the light-emitting element, and is used for driving, under the control of the potential of the first node, the light-emitting element to emit light; and a back gate electrode of a transistor comprised in the driving circuit is electrically connected to a first electrode plate of the first capacitor, and a second electrode plate of the first capacitor is electrically connected to a control voltage end. In the embodiments of the present disclosure, the first capacitor is disposed between the back gate electrode of the transistor comprised in the driving circuit and the control voltage end; during compensation, the depletion capacitance of the transistor comprised in the driving circuit can be increased by means of compensation; and when the pixel circuit operates, an S-factor of the transistor comprised in the driving circuit and a corresponding data range are adjusted.

Description

Pixel circuit and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese Patent Application No. 202410353815.1 filed in China on March 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a pixel circuit and a display device. Background Art

[0004] In related technologies, the driving transistor in a pixel circuit may include a gate and a back gate, and a light-shielding metal layer is used as the back gate of the driving transistor. The back gate of the driving transistor can be connected to a fixed voltage, and the depletion capacitance of the driving transistor cannot be increased during compensation, and the S-factor (S factor) and corresponding Dr-Range (Data Range) of the driving transistor cannot be adjusted when the pixel circuit is working. Summary of the Invention

[0005] The main purpose of the present disclosure is to provide a pixel circuit and a display device that cannot improve the depletion capacitance of the transistor included in the driving circuit during compensation, and cannot adjust the S factor of the transistor included in the driving circuit and the corresponding data voltage range when the pixel circuit is working.

[0006] In one aspect, an embodiment of the present disclosure provides a pixel circuit, including a driving circuit, a light-emitting element, and a first capacitor;

[0007] The driving circuit is electrically connected to the first node and the light-emitting element respectively, and is used to drive the light-emitting element to emit light under the control of the potential of the first node;

[0008] The back gate of the transistor included in the driving circuit is electrically connected to the first plate of the first capacitor, and the second plate of the first capacitor is electrically connected to the control voltage terminal.

[0009] Optionally, the first capacitor is a depletion-type capacitor.

[0010] Optionally, the pixel circuit further includes an energy storage circuit; the energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0011] The capacitance value of the first capacitor is smaller than the capacitance value of the storage capacitor included in the energy storage circuit.

[0012] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a compensation control circuit and a data writing circuit;

[0013] The compensation control circuit is used to control the connection or disconnection between the first node and the third node under the control of the first scanning signal provided by the first scanning end; the driving circuit is electrically connected to the light-emitting element through the third node;

[0014] The data writing circuit is electrically connected to the second scanning end, the data line and the second node respectively, and is used to provide the data voltage provided by the data line to the second node under the control of the second scanning signal provided by the second scanning end during the data writing phase; the driving circuit is electrically connected to the power supply voltage end through the second node.

[0015] Optionally, the back gate of the transistor included in the compensation control circuit is electrically connected to the second plate of the first capacitor.

[0016] Optionally, the back gate of the transistor included in the data writing circuit is electrically connected to the second plate of the first capacitor.

[0017] Optionally, the transistors included in the compensation control circuit and the transistors included in the data writing circuit are both n-type transistors or both p-type transistors, and the back gates of the transistors included in the compensation control circuit and the back gates of the transistors included in the data writing circuit are both electrically connected to the second plate of the first capacitor.

[0018] Optionally, the control voltage terminal is used to provide a fixed voltage signal.

[0019] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit and a second light emitting control circuit;

[0020] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal during the light-emitting phase;

[0021] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the third node to be connected to the first electrode of the light-emitting element under the control of the light-emitting control signal during the light-emitting phase; and the second electrode of the light-emitting element is electrically connected to the first voltage terminal;

[0022] The control voltage terminal is used to provide a first control voltage signal during at least a partial period of time in the light emitting phase.

[0023] Optionally, the control voltage terminal is used to provide a second control voltage signal in a time period other than the partial time period;

[0024] When the second plate of the first capacitor is connected to the first control voltage signal, the capacitance value of the first capacitor is greater than the capacitance value of the first capacitor when the second plate of the first capacitor is connected to the second control voltage signal.

[0025] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes an initialization circuit;

[0026] The initialization circuit is electrically connected to the reset control terminal, the first initial voltage terminal and the third node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the third node under the control of the reset control signal provided by the reset control terminal during the reset phase;

[0027] The control voltage terminal is further used to provide a first control voltage signal during the reset phase and the data writing phase.

[0028] Optionally, the control voltage terminal is used to provide a second control voltage signal in a time period other than the partial time period, the reset phase and the data writing phase;

[0029] When the second plate of the first capacitor is connected to the first control voltage signal, the capacitance value of the first capacitor is greater than the capacitance value of the first capacitor when the second plate of the first capacitor is connected to the second control voltage signal.

[0030] Optionally, the driving circuit includes a driving transistor;

[0031] The gate of the driving transistor is electrically connected to the first node, the back gate of the driving transistor is electrically connected to the control voltage terminal, the first electrode of the driving transistor is electrically connected to the power supply voltage terminal through the second node, and the second electrode of the driving transistor is electrically connected to the light emitting element through the third node;

[0032] The compensation control circuit includes a first transistor; the data writing circuit includes a second transistor;

[0033] The gate of the first transistor is electrically connected to the first scanning end, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third node;

[0034] A gate of the second transistor is electrically connected to the second scanning end, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the second node.

[0035] Optionally, the back gate of the first transistor is electrically connected to the control voltage terminal; or, the back gate of the second transistor is electrically connected to the control voltage terminal; or, the first transistor and the second transistor are both n-type transistors or p-type transistors, and the back gate of the first transistor and the back gate of the second transistor are both electrically connected to the control voltage terminal.

[0036] In a second aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned pixel circuit.

[0037] In the embodiment of the present disclosure, a first capacitor is set between the back gate of the transistor included in the driving circuit and the control voltage terminal. The depletion capacitance of the transistor included in the driving circuit during compensation can be increased by compensation, and the S factor of the transistor included in the driving circuit and the corresponding data voltage range can be adjusted when the pixel circuit is working. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] FIG1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0039] FIG2A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0040] FIG2B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0041] FIG2C is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0042] FIG2D is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0043] FIG2E is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0044] FIG4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0045] FIG5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0046] FIG6 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0047] FIG7 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG6 ;

[0048] FIG8 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG6 ;

[0049] FIG9A is a schematic diagram illustrating the working state of at least one embodiment of the pixel circuit shown in FIG6 during a reset phase S1;

[0050] FIG9B is a schematic diagram illustrating the working state of at least one embodiment of the pixel circuit shown in FIG6 during the data writing phase S2;

[0051] FIG9C is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG6 during the light emitting stage S3;

[0052] FIG10 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0054] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0055] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0056] As shown in FIG1 , the pixel circuit according to the embodiment of the present disclosure includes a driving circuit 10 , a light emitting element E1 and a first capacitor C1 ;

[0057] The driving circuit 10 is electrically connected to the first node N1 and the light emitting element E1, respectively, and is configured to drive the light emitting element E1 to emit light under the control of the potential of the first node N1;

[0058] The back gate of the transistor included in the driving circuit 10 is electrically connected to the first plate of the first capacitor C1 , and the second plate of the first capacitor C1 is electrically connected to the control voltage terminal BG.

[0059] In FIG1 , VDD is a power supply voltage terminal.

[0060] In the pixel circuit of at least one embodiment of the present disclosure, a first capacitor C1 can be set between the back gate of the transistor included in the driving circuit 10 and the control voltage terminal BG. The depletion capacitance of the transistor included in the driving circuit 10 can be increased during compensation, and the S-factor and corresponding Dr-Range (Data Range) of the transistor included in the driving circuit 10 can be adjusted when the pixel circuit is working.

[0061] In at least one embodiment of the present disclosure, the control voltage terminal BG is used to provide a control voltage signal. When the voltage value of the control voltage signal connected to the second plate of the first capacitor increases, the capacitance value of the first capacitor C1 may increase accordingly.

[0062] In practice, on a transistor's transfer curve, at a specific Vds (drain-source voltage), different data voltages (Vdata) correspond to different drain-source currents (Ids), and thus to different brightness levels. The Data Range is the difference between the gate-source voltages (Vgs) corresponding to the currents (Ids) at two brightness levels. A larger Data Range value reduces the change in Ids current caused by Vdata errors, and thus reduces the corresponding brightness error.

[0063] In at least one embodiment of the present disclosure, the first capacitor is a depletion-mode capacitor.

[0064] In a specific implementation, the first capacitor may be a depletion capacitor.

[0065] In at least one embodiment of the present disclosure, the first plate of the first capacitor C1 may be a semiconductor plate, the second plate of the first capacitor C1 may be made of metal, an insulating layer may be provided between the first plate of the first capacitor C1 and the second plate of the first capacitor C1, and the capacitance value of the first capacitor C1 may be adjusted by adjusting the potential of the control voltage terminal BG.

[0066] Optionally, the light emitting element may be an OLED (organic light emitting diode), but is not limited thereto.

[0067] In at least one embodiment of the present disclosure, the pixel circuit further includes a tank circuit; the tank circuit is electrically connected to the first node and is configured to maintain the potential of the first node;

[0068] The capacitance value of the first capacitor is smaller than the capacitance value of the storage capacitor included in the energy storage circuit.

[0069] In a specific implementation, the pixel circuit may include an energy storage circuit, which can be used to maintain the potential of the first node. The capacitance value of the first capacitor is smaller than the capacitance value of the storage capacitor included in the energy storage circuit, so that the storage capacitor can well maintain the potential of the node.

[0070] As shown in FIG2A , based on at least one embodiment of the pixel circuit shown in FIG1 , the pixel circuit according to at least one embodiment of the present disclosure may include a tank circuit 20 ;

[0071] The energy storage circuit 20 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1;

[0072] The capacitance value of the first capacitor C1 is smaller than the capacitance value of the storage capacitor included in the energy storage circuit 20 .

[0073] The pixel circuit according to at least one embodiment of the present disclosure further includes a compensation control circuit and a data writing circuit;

[0074] The compensation control circuit is used to control the connection or disconnection between the first node and the third node under the control of the first scanning signal provided by the first scanning end; the driving circuit is electrically connected to the light-emitting element through the third node;

[0075] The data writing circuit is electrically connected to the second scanning end, the data line and the second node respectively, and is used to provide the data voltage provided by the data line to the second node under the control of the second scanning signal provided by the second scanning end during the data writing phase; the driving circuit is electrically connected to the power supply voltage end through the second node.

[0076] In a specific implementation, the pixel circuit may further include a compensation control circuit and a data writing circuit; the compensation control circuit controls the connection or disconnection between the first node and the third node under the control of the first scanning signal, and the data writing circuit provides the data voltage to the second node under the control of the second scanning signal during the data writing phase.

[0077] Optionally, the back gate of the transistor included in the compensation control circuit is electrically connected to the second plate of the first capacitor.

[0078] Optionally, the back gate of the transistor included in the data writing circuit is electrically connected to the second plate of the first capacitor.

[0079] Optionally, the transistors included in the compensation control circuit and the transistors included in the data writing circuit are both n-type transistors or both p-type transistors, and the back gates of the transistors included in the compensation control circuit and the back gates of the transistors included in the data writing circuit are both electrically connected to the second plate of the first capacitor.

[0080] In a specific implementation, the transistor included in the driving circuit, the transistor included in the compensation control circuit, and the transistor included in the data writing circuit are transistors in a compensation loop. The back gate of the transistor included in the compensation control circuit or the back gate of the transistor included in the data writing circuit can be set to be electrically connected to the back gate of the transistor included in the driving circuit. Alternatively, when the transistor included in the compensation control circuit and the transistor included in the data writing circuit are both n-type transistors or both p-type transistors, the back gate of the transistor included in the compensation control circuit and the back gate of the transistor included in the data writing circuit can be set to be electrically connected to the second plate of the first capacitor, which can improve the compensation unevenness caused by the difference in transistor characteristics in the compensation loop.

[0081] In the relevant pixel circuit, during compensation, each transistor in the compensation loop is controlled by an independent potential. However, in at least one embodiment of the present disclosure, during compensation, the back gate of the transistor in the compensation loop is connected to the control voltage signal through the control voltage terminal, and the active layer of the transistor in the compensation loop is not in a floating state. When, in the compensation loop, the back gate of the transistor included in the drive circuit and the back gate of the transistor included in the compensation control circuit are both electrically connected to the control voltage terminal, when the transistor included in the drive circuit generates a voltage change, the change will be reflected in the transistor included in the compensation control circuit. Through this process, complementary compensation of transistor potential changes can be achieved in the compensation loop.

[0082] In at least one embodiment of the present disclosure, the control voltage terminal is used to provide a fixed voltage signal.

[0083] In a specific implementation, the control voltage terminal may provide a fixed voltage signal, and the voltage value of the fixed voltage signal may be greater than or equal to -15V and less than or equal to 15V.

[0084] As shown in FIG2B , based on at least one embodiment of the pixel circuit shown in FIG2A , the pixel circuit according to at least one embodiment of the present disclosure further includes a compensation control circuit 21 and a data writing circuit 22 ;

[0085] The source of the transistor included in the driving circuit 10 is electrically connected to the second node N2, and the drain of the transistor included in the driving circuit 10 is electrically connected to the third node N3;

[0086] The compensation control circuit 21 is electrically connected to the first scanning terminal GN, the first node N1, and the third node N3, respectively, and is used to control the connection or disconnection between the first node N1 and the third node N3 under the control of the first scanning signal provided by the first scanning terminal GN; the second terminal of the driving circuit 10 is electrically connected to the third node N3;

[0087] The data writing circuit 22 is electrically connected to the second scanning terminal GP, the data line DT and the second node N2, respectively, and is used to provide the data voltage Vdata provided by the data line DT to the second node N2 under the control of the second scanning signal provided by the second scanning terminal GP during the data writing stage; the first end of the driving circuit 10 is electrically connected to the second node N2.

[0088] As shown in FIG2C , based on at least one embodiment of the pixel circuit shown in FIG2B ,

[0089] The gate of the transistor included in the compensation control circuit 21 is electrically connected to the first scanning terminal GN, the source of the transistor included in the compensation control circuit 21 is electrically connected to the first node N1, and the drain of the transistor included in the compensation control circuit 21 is electrically connected to the third node N3; the back gate of the transistor included in the compensation control circuit 21 is electrically connected to the control voltage terminal BG.

[0090] In FIG. 2C , the transistors included in the compensation control circuit 21 are n-type transistors, but the present invention is not limited thereto.

[0091] As shown in FIG2D , based on at least one embodiment of the pixel circuit shown in FIG2B ,

[0092] The gate of the transistor included in the data write circuit 22 is electrically connected to the second scanning terminal GP, the source of the transistor included in the data write circuit 22 is electrically connected to the data line DT, and the drain of the transistor included in the data write circuit 22 is electrically connected to the second node N2; the back gate of the transistor included in the data write circuit 22 is electrically connected to the control voltage terminal BG.

[0093] In FIG. 2D , the transistors included in the data writing circuit 22 are p-type transistors, but the present invention is not limited thereto.

[0094] As shown in FIG2E , based on at least one embodiment of the pixel circuit shown in FIG2B ,

[0095] The gate of the transistor included in the compensation control circuit 21 is electrically connected to the first scanning terminal GN, the source of the transistor included in the compensation control circuit 21 is electrically connected to the first node N1, and the drain of the transistor included in the compensation control circuit 21 is electrically connected to the third node N3; the back gate of the transistor included in the compensation control circuit 21 is electrically connected to the control voltage terminal BG;

[0096] The gate of the transistor included in the data write circuit 22 is electrically connected to the second scanning terminal GP, the source of the transistor included in the data write circuit 22 is electrically connected to the data line DT, and the drain of the transistor included in the data write circuit 22 is electrically connected to the second node N2; the back gate of the transistor included in the data write circuit 22 is electrically connected to the control voltage terminal BG.

[0097] In at least one embodiment shown in FIG2E , the transistors included in the compensation control circuit 21 and the transistors included in the data writing circuit 22 are both p-type transistors, but the present invention is not limited thereto. In actual operation, the transistors included in the compensation control circuit 21 and the transistors included in the data writing circuit 22 can both be n-type transistors.

[0098] The pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit and a second light emitting control circuit;

[0099] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal during the light-emitting phase;

[0100] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the third node to be connected to the first electrode of the light-emitting element under the control of the light-emitting control signal during the light-emitting phase; and the second electrode of the light-emitting element is electrically connected to the first voltage terminal;

[0101] The control voltage terminal is used to provide a first control voltage signal during at least a partial period of time in the light emitting phase.

[0102] In a specific implementation, the pixel circuit may further include a first light-emitting control circuit and a second light-emitting control circuit, wherein the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of a light-emitting control signal during the light-emitting stage, and the second light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the light-emitting control signal; the second pole of the light-emitting element is electrically connected to the first voltage terminal; and the control voltage terminal provides a first control voltage signal during the initial part of the time period including the light-emitting stage.

[0103] In at least one embodiment of the present disclosure, the control voltage terminal is used to provide a second control voltage signal in a time period other than the partial time period;

[0104] When the second plate of the first capacitor is connected to the first control voltage signal, the capacitance value of the first capacitor is greater than the capacitance value of the first capacitor when the second plate of the first capacitor is connected to the second control voltage signal.

[0105] In a specific implementation, in a time period other than the compensation time period included in the display cycle, the control voltage terminal can provide a second control voltage signal. When the second plate of the first capacitor is connected to the first control voltage signal, the capacitance value of the first capacitor is greater than the capacitance value of the first capacitor when the second plate of the first capacitor is connected to the second control voltage signal. This can ensure that at the beginning of the light-emitting time period, when the driving transistor included in the driving circuit changes from an off state to an on state, the speed at which the current value of the driving current generated by the driving transistor increases becomes slower.

[0106] Optionally, the first voltage end may be a low voltage end, but is not limited thereto.

[0107] In at least one embodiment of the present disclosure, when the voltage value of the voltage signal provided by the control voltage terminal is larger, the capacitance value of the first capacitor is larger.

[0108] As shown in FIG3 , based on at least one embodiment of the pixel circuit shown in FIG2A , the pixel circuit according to at least one embodiment of the present disclosure further includes a compensation control circuit 21 , a data writing circuit 22 , a first light emitting control circuit 31 and a second light emitting control circuit 32 ;

[0109] The compensation control circuit 21 is electrically connected to the first scanning terminal GN, the first node N1, and the third node N3, respectively, and is used to control the connection or disconnection between the first node N1 and the third node N3 under the control of the first scanning signal provided by the first scanning terminal GN; the second terminal of the driving circuit 10 is electrically connected to the third node N3;

[0110] The data writing circuit 22 is electrically connected to the second scanning terminal GP, the data line DT, and the second node N2, respectively, and is used to provide the data voltage Vdata provided by the data line DT to the second node N2 under the control of the second scanning signal provided by the second scanning terminal GP during the data writing phase; the first terminal of the driving circuit 10 is electrically connected to the second node N2;

[0111] The first light emitting control circuit 31 is electrically connected to the light emitting control terminal EM, the power supply voltage terminal VDD and the second node N2, respectively, and is used to control the connection between the power supply voltage terminal VDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control terminal EM during the light emitting phase;

[0112] The second light-emitting control circuit 32 is electrically connected to the light-emitting control terminal EM, the third node N3 and the first electrode of the light-emitting element E1, respectively, and is used to control the connection between the third node N3 and the first electrode of the light-emitting element E1 under the control of the light-emitting control signal during the light-emitting stage; the second electrode of the light-emitting element E1 is electrically connected to the first voltage terminal V1.

[0113] The pixel circuit according to at least one embodiment of the present disclosure further includes an initialization circuit;

[0114] The initialization circuit is electrically connected to the reset control terminal, the first initial voltage terminal and the third node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the third node under the control of the reset control signal provided by the reset control terminal during the reset phase;

[0115] The control voltage terminal is further used to provide a first control voltage signal during the reset phase and the data writing phase.

[0116] In a specific implementation, the pixel circuit may further include an initialization circuit, which writes a first initial voltage to the third node under the control of a reset control signal during a reset phase; the control voltage terminal is also used to provide a first control voltage signal during the reset phase and the data writing phase.

[0117] As shown in FIG4 , based on at least one embodiment shown in FIG3 , the pixel circuit according to at least one embodiment of the present disclosure may further include an initialization circuit 40 ;

[0118] The initialization circuit is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the third node N3 respectively, and is used to write the first initial voltage Vint1 provided by the first initial voltage terminal I1 into the third node N3 under the control of the reset control signal provided by the reset control terminal RST during the reset phase.

[0119] In at least one embodiment of the present disclosure, the control voltage terminal is used to provide a second control voltage signal in a time period other than the partial time period, the reset phase, and the data writing phase;

[0120] When the second plate of the first capacitor is connected to the first control voltage signal, the capacitance value of the first capacitor is greater than the capacitance value of the first capacitor when the second plate of the first capacitor is connected to the second control voltage signal.

[0121] In a specific implementation, the control voltage terminal can provide a second control voltage signal in a time period other than the partial time period, the reset phase and the data writing phase; when the second plate of the first capacitor is connected to the first control voltage signal, the capacitance value of the first capacitor is greater than the capacitance value of the first capacitor when the second plate of the first capacitor is connected to the second control voltage signal; so that at the beginning of the light-emitting time period, when the driving transistor included in the driving circuit changes from an off state to an on state, the speed at which the current value of the driving current generated by the driving transistor increases becomes slower; in this case, the characteristic fluctuation of the transistor in the compensation loop is smaller, which alleviates the characteristic fluctuation of the transistor in the compensation loop.

[0122] Optionally, the driving circuit includes a driving transistor;

[0123] The gate of the driving transistor is electrically connected to the first node, the back gate of the driving transistor is electrically connected to the control voltage terminal, the first electrode of the driving transistor is electrically connected to the power supply voltage terminal through the second node, and the second electrode of the driving transistor is electrically connected to the light emitting element through the third node;

[0124] The compensation control circuit includes a first transistor; the data writing circuit includes a second transistor;

[0125] The gate of the first transistor is electrically connected to the first scanning end, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third node;

[0126] A gate of the second transistor is electrically connected to the second scanning end, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the second node.

[0127] In at least one embodiment of the present disclosure, the back gate of the first transistor is electrically connected to the control voltage terminal; or, the back gate of the second transistor is electrically connected to the control voltage terminal; or, the first transistor and the second transistor are both n-type transistors or p-type transistors, and the back gate of the first transistor and the back gate of the second transistor are both electrically connected to the control voltage terminal.

[0128] The pixel circuit according to at least one embodiment of the present disclosure further includes a reset circuit;

[0129] The reset circuit is electrically connected to the reset control terminal, the second initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the reset control signal.

[0130] In a specific implementation, the pixel circuit may further include a reset circuit, which, under the control of the reset control signal, writes a second initial voltage into the first electrode of the light-emitting element to clear the residual charge in the first electrode of the light-emitting element.

[0131] As shown in FIG5 , based on at least one embodiment of the pixel circuit shown in FIG4 , the pixel circuit according to at least one embodiment of the present disclosure further includes a reset circuit 50 ;

[0132] The reset circuit 50 is electrically connected to the reset control terminal RST, the second initial voltage terminal I2 and the first electrode of the light-emitting element E1, respectively, and is used to write the second initial voltage Vint2 provided by the second initial voltage terminal I2 into the first electrode of the light-emitting element E1 under the control of the reset control signal provided by the reset control terminal RST.

[0133] Optionally, the first light emitting control circuit includes a third transistor, the second light emitting control circuit includes a fourth transistor, the initialization circuit includes a fifth transistor, and the reset circuit includes a sixth transistor;

[0134] The gate of the third transistor is electrically connected to the light emitting control terminal, the first electrode of the third transistor is electrically connected to the power supply voltage terminal, and the second electrode of the third transistor is electrically connected to the second node;

[0135] The gate of the fourth transistor is electrically connected to the light emitting control terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element;

[0136] The gate of the fifth transistor is electrically connected to the reset control terminal, the first electrode of the fifth transistor is electrically connected to the first initial voltage terminal, and the second electrode of the fifth transistor is electrically connected to the third node;

[0137] The gate of the sixth transistor is electrically connected to the reset control terminal, the first electrode of the sixth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light emitting element.

[0138] As shown in FIG6 , based on at least one embodiment of the pixel circuit shown in FIG5 , the driving circuit includes a driving transistor T0 ; the light emitting element is an organic light emitting diode O1 ;

[0139] The gate of the driving transistor T0 is electrically connected to the first node N1, the back gate of the driving transistor T0 is electrically connected to the control voltage terminal BG, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3;

[0140] The compensation control circuit includes a first transistor T1; the data writing circuit includes a second transistor T2;

[0141] The gate of the first transistor T1 is electrically connected to the first scanning terminal GN, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the third node N3; the back gate of the first transistor T1 is electrically connected to the control voltage terminal BG;

[0142] The gate of the second transistor T2 is electrically connected to the second scanning terminal GP, the source of the second transistor T2 is electrically connected to the data line DT, and the drain of the second transistor T2 is electrically connected to the second node N2;

[0143] The first light emitting control circuit includes a third transistor T3, the second light emitting control circuit includes a fourth transistor T4, the initialization circuit includes a fifth transistor T5, and the reset circuit includes a sixth transistor T6;

[0144] The gate of the third transistor T3 is electrically connected to the light emitting control terminal EM, the source of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the second node N2;

[0145] The gate of the fourth transistor T4 is electrically connected to the light emitting control terminal EM, the source of the fourth transistor T4 is electrically connected to the third node N3, and the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1;

[0146] The gate of the fifth transistor T5 is electrically connected to the reset control terminal RST, the source of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the third node N3;

[0147] The gate of the sixth transistor T6 is electrically connected to the reset control terminal RST, the source of the sixth transistor T6 is electrically connected to the second initial voltage terminal I2, the drain of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1; the cathode of O1 is electrically connected to the low voltage terminal VSS;

[0148] The energy storage circuit includes a storage capacitor Cst;

[0149] A first terminal of the storage capacitor Cst is electrically connected to the first node N1 , and a second terminal of the storage capacitor Cst is electrically connected to the high voltage terminal VDD.

[0150] In at least one embodiment of the pixel circuit shown in FIG. 6 , T1 may be an n-type transistor, and T0 , T2 , T3 , T4 , T5 , and T6 may all be p-type transistors, but the present invention is not limited thereto.

[0151] In at least one embodiment of the pixel circuit shown in FIG6 , the first capacitor C1 is a depletion-mode capacitor, and the first capacitor C1 is a variable capacitor.

[0152] As shown in FIG7 , when at least one embodiment of the pixel circuit shown in FIG6 of the present disclosure is in operation, a display period TS may include a reset phase S1 , a data writing phase S2 , and a light emitting phase S3 , which are arranged in sequence;

[0153] In the reset phase S1, EM provides a high voltage signal, RST provides a low voltage signal, GP provides a high voltage signal, GN provides a high voltage signal, and BG provides a first control voltage signal. As shown in FIG9A , T5 and T6 are turned on, T1 is turned on, and I1 provides a first initial voltage Vint1 to N3 and N1, so that T0 can be turned on when the data writing phase S2 begins; I2 provides a second initial voltage Vint2 to the anode of O1 to clear the residual charge on the anode of O1;

[0154] In the data writing phase S2, EM provides a high voltage signal, RST provides a high voltage signal, GP provides a low voltage signal, GN provides a high voltage signal, and BG provides a first control voltage signal. As shown in FIG9B , T2 is turned on, DT provides a data voltage Vdata to N2, T1 is turned on, and N1 and N3 are connected.

[0155] At the beginning of the data writing phase S2, as shown in FIG9B , T0 is turned on, and Cst is charged by Vdata, changing the potential of N1 until the potential of N1 becomes Vdata+Vth to perform threshold voltage compensation, and T0 is turned off; Vth is the threshold voltage of T0;

[0156] In the initial partial time period S31 included in the light-emitting stage S3, EM provides a low voltage signal, RST provides a high voltage signal, GP provides a high voltage signal, GN provides a low voltage signal, and BG provides a first control voltage signal. As shown in FIG9C , T3 and T4 are turned on, and T0 drives O1 to emit light.

[0157] In the light-emitting stage S3, except for the initial partial time period S31, EM provides a low voltage signal, RST provides a high voltage signal, GP provides a high voltage signal, GN provides a low voltage signal, BG provides a second control voltage signal, T3 and T4 are turned on, and T0 drives O1 to emit light;

[0158] During the time periods other than S1, S2 and S31 included in the display period TS, BG provides a second control voltage signal;

[0159] The voltage value of the first control voltage signal is greater than the voltage value of the second control voltage signal;

[0160] For example, when the voltage value of the first control voltage signal is 10V, the voltage value of the second control voltage signal may be 0V, but is not limited thereto.

[0161] In at least one embodiment of the pixel circuit shown in FIG6 of the present disclosure, C1 is a depletion-type capacitor. By adding C1 and connecting it to the back gate of the driving transistor T0, the capacitance value of C1 can be adjusted by adjusting the control voltage signal provided by BG, thereby ultimately controlling the CB value (depletion capacitance value) of T0 and adjusting the S factor and corresponding Dr-Range of the driving transistor T0 when the pixel circuit is operating.

[0162] When the capacitance value of C1 is much larger than the parasitic capacitance value of T0, the CB value of T0 is mainly determined by the capacitance value of C1.

[0163] As shown in Figure 7, when at least one embodiment of the pixel circuit shown in Figure 6 of the present disclosure is in operation, in the initial partial time period S31 included in the reset phase S1, the data writing phase S2 and the light-emitting phase, the BG provides a first control voltage signal, and in the time period other than S1, S2 and S31 included in the display period TS, the BG provides a second control voltage signal; the voltage value of the first control voltage signal is greater than the voltage value of the second control voltage signal; at this time, the characteristic fluctuation of the transistor in the compensation loop is small.

[0164] As shown in FIG8 , when at least one embodiment of the pixel circuit shown in FIG6 of the present disclosure is in operation, a display period TS may include a reset phase S1 , a data writing phase S2 , and a light emitting phase S3 , which are arranged in sequence;

[0165] In the reset phase S1, EM provides a high voltage signal, RST provides a low voltage signal, GP provides a high voltage signal, GN provides a high voltage signal, and BG provides a second control voltage signal. As shown in FIG9A , T5 and T6 are turned on, T1 is turned on, and I1 provides a first initial voltage Vint1 to N3 and N1, so that T0 can be turned on when the data writing phase S2 begins; I2 provides a second initial voltage Vint2 to the anode of O1 to clear the residual charge on the anode of O1;

[0166] In the data writing phase S2, EM provides a high voltage signal, RST provides a high voltage signal, GP provides a low voltage signal, GN provides a high voltage signal, and BG provides a second control voltage signal. As shown in FIG9B , T2 is turned on, DT provides a data voltage Vdata to N2, T1 is turned on, and N1 and N3 are connected.

[0167] At the beginning of the data writing phase S2, as shown in FIG9B , T0 is turned on, and Cst is charged by Vdata, changing the potential of N1 until the potential of N1 becomes Vdata+Vth to perform threshold voltage compensation, and T0 is turned off; Vth is the threshold voltage of T0;

[0168] In the initial partial time period S31 included in the light-emitting stage S3, EM provides a low voltage signal, RST provides a high voltage signal, GP provides a high voltage signal, GN provides a low voltage signal, and BG provides a first control voltage signal. As shown in FIG9C , T3 and T4 are turned on, and T0 drives O1 to emit light.

[0169] In the light-emitting stage S3, except for the initial partial time period S31, EM provides a low voltage signal, RST provides a high voltage signal, GP provides a high voltage signal, GN provides a low voltage signal, BG provides a second control voltage signal, T3 and T4 are turned on, and T0 drives O1 to emit light;

[0170] During the time period except S31 included in the display period TS, BG provides a second control voltage signal;

[0171] The voltage value of the first control voltage signal is greater than the voltage value of the second control voltage signal;

[0172] For example, when the voltage value of the first control voltage signal is 10V, the voltage value of the second control voltage signal may be 0V, but is not limited thereto.

[0173] As shown in FIG8 , in at least one embodiment of the pixel circuit shown in FIG6 of the present disclosure, during operation, during the initial partial time period S31 included in the light-emitting phase, the BG provides a first control voltage signal, and during the time period other than S31 included in the display period TS, the BG provides a second control voltage signal; the voltage value of the first control voltage signal is greater than the voltage value of the second control voltage signal; at this time, the impact on the charging time is small, and the S factor and Dr-Range can be adjusted more centrally.

[0174] As shown in FIG10 , based on at least one embodiment of the pixel circuit shown in FIG5 , the driving circuit includes a driving transistor T0 ; the light emitting element is an organic light emitting diode O1 ;

[0175] The gate of the driving transistor T0 is electrically connected to the first node N1, the back gate of the driving transistor T0 is electrically connected to the control voltage terminal BG, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3; the control voltage terminal BG is used to provide a fixed voltage signal;

[0176] The compensation control circuit includes a first transistor T1; the data writing circuit includes a second transistor T2;

[0177] The gate of the first transistor T1 is electrically connected to the first scanning terminal GN, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the third node N3; the back gate of the first transistor T1 is electrically connected to the control voltage terminal BG;

[0178] The gate of the second transistor T2 is electrically connected to the second scanning terminal GP, the source of the second transistor T2 is electrically connected to the data line DT, and the drain of the second transistor T2 is electrically connected to the second node N2;

[0179] The first light emitting control circuit includes a third transistor T3, the second light emitting control circuit includes a fourth transistor T4, the initialization circuit includes a fifth transistor T5, and the reset circuit includes a sixth transistor T6;

[0180] The gate of the third transistor T3 is electrically connected to the light emitting control terminal EM, the source of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the second node N2;

[0181] The gate of the fourth transistor T4 is electrically connected to the light emitting control terminal EM, the source of the fourth transistor T4 is electrically connected to the third node N3, and the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1;

[0182] The gate of the fifth transistor T5 is electrically connected to the reset control terminal RST, the source of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the third node N3;

[0183] The gate of the sixth transistor T6 is electrically connected to the reset control terminal RST, the source of the sixth transistor T6 is electrically connected to the second initial voltage terminal I2, the drain of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1; the cathode of O1 is electrically connected to the low voltage terminal VSS;

[0184] The energy storage circuit includes a storage capacitor Cst;

[0185] A first terminal of the storage capacitor Cst is electrically connected to the first node N1 , and a second terminal of the storage capacitor Cst is electrically connected to the high voltage terminal VDD.

[0186] In at least one embodiment of the pixel circuit shown in FIG. 10 , T1 may be an n-type transistor, and T0 , T2 , T3 , T4 , T5 , and T6 may all be p-type transistors, but the present invention is not limited thereto.

[0187] In at least one embodiment of the present disclosure, when at least one embodiment of the pixel circuit shown in FIG. 10 is in operation, the BG can provide a fixed voltage signal. In this case, the structure of the pixel circuit is relatively simpler; for example, the BG can provide a 5V voltage signal, but is not limited thereto.

[0188] The display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.

[0189] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A pixel circuit comprising a driving circuit, a light-emitting element, and a first capacitor; The driving circuit is electrically connected to the first node and the light-emitting element respectively, and is used to drive the light-emitting element to emit light under the control of the potential of the first node; The back gate of the transistor included in the driving circuit is electrically connected to the first plate of the first capacitor, and the second plate of the first capacitor is electrically connected to the control voltage terminal.

2. The pixel circuit according to claim 1, wherein: The first capacitor is a depletion-type capacitor.

3. The pixel circuit according to claim 1, wherein: The pixel circuit further includes an energy storage circuit; the energy storage circuit is electrically connected to the first node and is used to store electrical energy; The capacitance value of the first capacitor is smaller than the capacitance value of the storage capacitor included in the energy storage circuit.

4. The pixel circuit according to claim 1, wherein: Also includes a compensation control circuit and a data writing circuit; The compensation control circuit is used to control the connection or disconnection between the first node and the third node under the control of the first scanning signal provided by the first scanning end; the driving circuit is electrically connected to the light-emitting element through the third node; The data writing circuit is electrically connected to the second scanning end, the data line and the second node respectively, and is used to provide the data voltage provided by the data line to the second node under the control of the second scanning signal provided by the second scanning end during the data writing phase; the driving circuit is electrically connected to the power supply voltage end through the second node.

5. The pixel circuit according to claim 4, wherein: The back gate of the transistor included in the compensation control circuit is electrically connected to the second plate of the first capacitor.

6. The pixel circuit according to claim 4, wherein: The back gate of the transistor included in the data writing circuit is electrically connected to the second plate of the first capacitor.

7. The pixel circuit according to claim 4, wherein: The transistors included in the compensation control circuit and the transistors included in the data writing circuit are both n-type transistors or both p-type transistors, and the back gates of the transistors included in the compensation control circuit and the back gates of the transistors included in the data writing circuit are both electrically connected to the second plate of the first capacitor.

8. The pixel circuit according to any one of claims 1 to 7, wherein: The control voltage terminal is used to provide a fixed voltage signal.

9. The pixel circuit according to claim 4, wherein: Also includes a first light emitting control circuit and a second light emitting control circuit; The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal during the light-emitting phase; The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the third node to be connected to the first electrode of the light-emitting element under the control of the light-emitting control signal during the light-emitting phase; and the second electrode of the light-emitting element is electrically connected to the first voltage terminal; The control voltage terminal is used to provide a first control voltage signal during at least a partial period of time in the light emitting phase.

10. The pixel circuit according to claim 9, wherein: The control voltage terminal is used to provide a second control voltage signal in a time period other than the partial time period; When the second plate of the first capacitor is connected to the first control voltage signal, the capacitance value of the first capacitor is greater than the capacitance value of the first capacitor when the second plate of the first capacitor is connected to the second control voltage signal.

11. The pixel circuit according to claim 9, wherein: Also included is an initialization circuit; The initialization circuit is electrically connected to the reset control terminal, the first initial voltage terminal and the third node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the third node under the control of the reset control signal provided by the reset control terminal during the reset phase; The control voltage terminal is further used to provide a first control voltage signal during the reset phase and the data writing phase.

12. The pixel circuit according to claim 11, wherein: The control voltage terminal is used to provide a second control voltage signal in a time period other than the partial time period, the reset phase and the data writing phase; When the second plate of the first capacitor is connected to the first control voltage signal, the capacitance value of the first capacitor is greater than the capacitance value of the first capacitor when the second plate of the first capacitor is connected to the second control voltage signal.

13. The pixel circuit according to claim 4, wherein: The driving circuit includes a driving transistor; The gate of the driving transistor is electrically connected to the first node, the back gate of the driving transistor is electrically connected to the control voltage terminal, the first electrode of the driving transistor is electrically connected to the power supply voltage terminal through the second node, and the second electrode of the driving transistor is electrically connected to the light emitting element through the third node; The compensation control circuit includes a first transistor; the data writing circuit includes a second transistor; The gate of the first transistor is electrically connected to the first scanning end, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third node; A gate of the second transistor is electrically connected to the second scanning end, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the second node.

14. The pixel circuit according to claim 13, wherein: The back gate of the first transistor is electrically connected to the control voltage terminal; or, the back gate of the second transistor is electrically connected to the control voltage terminal; or, the first transistor and the second transistor are both n-type transistors or p-type transistors, and the back gate of the first transistor and the back gate of the second transistor are both electrically connected to the control voltage terminal.

15. A display device comprising the pixel circuit according to any one of claims 1 to 14.

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