Data processing method and apparatus, and storage medium

Abstract

The present application belongs to the field of computers. Disclosed are a data processing method and apparatus, and a storage medium. The method comprises: a computing device writing into a second cache a first data sub-block in a k-th column and an m-th row in a first data block, and writing, into the second cache and in N writings, N second data sub-blocks comprised in a k-th row in a second data block, wherein k is a positive integer less than or equal to K, and m is a positive integer less than or equal to M; and after an n-th second data sub-block is written into the second cache in an n-th writing, the n-th second data sub-block covers a second data sub-block in the second cache that has been processed with the first data sub-block; and the computing device processing the first data sub-block and the n-th second data sub-block which are comprised in the second cache, so as to obtain a k-th piece of intermediate data for acquiring an n-th data sub-block in an m-th row of a first result data block, wherein n is a positive integer less than or equal to N. The present application can improve the data processing efficiency.

Description

Data processing method, device and storage medium

[0001] This application claims priority to Chinese Patent Application No. 202410362601.0, filed on March 26, 2024, entitled “Matrix Computing Method and System,” the entire contents of which are hereby incorporated by reference into this application. Furthermore, this application claims priority to Chinese Patent Application No. 202410546877.4, filed on April 30, 2024, entitled “Data Processing Method, Device, and Storage Medium,” the entire contents of which are hereby incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of computers, and in particular to a method, device, and storage medium for processing data. Background Art

[0003] A two-dimensional data block includes multiple rows and columns of data. For example, a two-dimensional data block can be a matrix. Two-dimensional data blocks have a wide range of applications. For example, in image processing, matrices are used to store image information, such as the characteristics of pixels in an image. Another example is using matrices in trajectory data processing to store trajectory data, where each row of the matrix represents a trajectory data item.

[0004] In applications such as image processing and trajectory data processing, two-dimensional data blocks often have a large number of rows and columns, making processing them inefficient. For example, processing a two-dimensional data block might involve multiplying two matrices. However, when these matrices have large numbers of rows and columns, the multiplication is inefficient. Summary of the Invention

[0005] This application provides a method, device, and storage medium for processing data to improve the efficiency of data processing. The technical solution is as follows:

[0006] In a first aspect, the present application provides a method for processing data, the method being applied to a computing device, the computing device comprising a first cache and a second cache, the performance of the second cache being superior to that of the first cache, the first cache comprising a first data block and a second data block to be processed, the first data block comprising a sub-data block of M rows and K columns, the second data block comprising a sub-data block of K rows and N columns, where M, K, and N are all integers greater than 1. In the method, the computing device writes a first sub-data block of the kth column and mth row in the first data block into the second cache, and writes N second sub-data blocks of the kth row in the second data block into the second cache in N times, where k is a positive integer less than or equal to K, and m is a positive integer less than or equal to M. When the nth second sub-data block is written to the second cache for the nth time, the nth second sub-data block overwrites the second sub-data block in the second cache that has been processed with the first sub-data block, and the computing device processes the first sub-data block included in the second cache with the nth second sub-data block to obtain the kth intermediate data of the nth sub-data block in the mth row for obtaining the first result data block, where n is a positive integer less than or equal to N.

[0007] Because the computing device writes the first sub-data block in the kth column and mth row of the first data block into the second cache, and writes the N second sub-data blocks included in the kth row of the second data block into the second cache N times, and when writing the second sub-data block for the nth time, the computing device processes the first sub-data block and the nth second sub-data block included in the second cache, after writing the first sub-data block into the second cache, the first sub-data block is processed separately from the second sub-data block that was written to the second cache N times in a row, thereby avoiding repeated writing of the first sub-data block into the second cache and deletion of the first sub-data block from the second cache, thereby improving the reuse rate of the first sub-data block and the efficiency of data processing.

[0008] In one possible implementation, the computing device accumulates K intermediate data to obtain the nth sub-data block in the mth row of the first result data block, where the K intermediate data include the kth intermediate data. This ensures that the processing results of the first data block and the second data block are correctly obtained.

[0009] In another possible implementation, the computing device further includes a third cache, the performance of the third cache being superior to that of the second cache. The first sub-data block in the second cache includes a sub-data block in row I and column J, the nth second sub-data block includes a sub-data block in row J and column Q, where I, J, and Q are all integers greater than 1, and the kth intermediate data includes a sub-data block in row I and column Q. The computing device writes the J sub-data blocks in the i-th row of the first sub-data block included in the second cache into the third cache, and writes the J sub-data blocks in the q-th column of the nth second sub-data block included in the second cache into the third cache, where i is a positive integer less than or equal to 1, and q is a positive integer less than or equal to Q. The computing device processes the J sub-data blocks in the i-th row and the J sub-data blocks in the q-th column in the third cache to obtain the sub-data block in the i-th row and the q-th column included in the kth intermediate data.

[0010] When writing a data block from the first cache to the second cache, the kth column of the first data block and the kth row of the second data block are written to the second cache. When writing a data block from the second cache to the third cache, the ith row of the first sub-data block and the qth column of the second sub-data block are written to the third cache. By combining these two methods of writing data from the lower-level cache to the higher-level cache, the number of duplicate data writes and sub-data block deletions can be avoided or reduced, thereby improving data processing efficiency.

[0011] In another possible implementation, the computing device further includes a fourth cache, the performance of the first cache is superior to that of the fourth cache, the fourth cache includes a third data block and a fourth data block, the third data block includes a sub-data block in row X and column Y, the fourth data block includes a sub-data block in row Y and column Z, where X, Y, and Z are all integers greater than or equal to 1, the first data block is the sub-data block in row x and column y of the third data block, the second data block is the z-th sub-data block in row y of the fourth data block, where x is a positive integer less than or equal to X, y is a positive integer less than or equal to Y, and z is a positive integer less than or equal to Z. The computing device writes the first data block and the second data block to the first cache, with the second data block overwriting the sub-data block in the fourth data block in the first cache that has been processed with the first data block.

[0012] In this way, after writing a first data block to the first cache, the first data block is processed separately from the second data block written Z times consecutively to the second cache. This avoids repeated writing of the first data block to the first cache and deletion of the first data block from the first cache, thereby improving data processing efficiency. Furthermore, this data processing method can be applied to caches at four or more levels, enriching application scenarios.

[0013] In another possible implementation, the nth sub-data block in the mth row of the first result data block is used to obtain the yth intermediate data of the zth sub-data block in the yth row of the second result data block. The computing device accumulates the Y intermediate data to obtain the zth sub-data block in the yth row of the second result data block, where the Y intermediate data include the yth intermediate data. This ensures that the processing results of the third and fourth data blocks are correctly obtained.

[0014] In another possible implementation, the computing device determines the size of the sub-data blocks included in the first data block and the size of the sub-data blocks included in the second data block based on the bandwidth and spatial size of the second cache. The computing device divides the first data block into M rows and K columns of sub-data blocks based on the size of the sub-data blocks included in the first data block, and divides the second data block into K rows and N columns of sub-data blocks based on the size of the sub-data blocks included in the second data block. Because the size of the sub-data blocks included in the first data block and the size of the sub-data blocks included in the second data block are determined based on the spatial size and bandwidth of the second cache, the size of the sub-data blocks is combined with the characteristics of the second cache to balance the bandwidth of the second cache.

[0015] In another possible implementation, the processing operation of processing the first data block and the second data block is a multiplication operation between the first data block and the second data block.

[0016] In another possible implementation, the performance of the second cache is better than that of the first cache, including: the bandwidth of the second cache is higher than the bandwidth of the first cache, and / or the read and write latency of the second cache is shorter than the read and write latency of the first cache.

[0017] In a second aspect, the present application provides a device for processing data, configured to execute the method in the first aspect or any possible implementation of the first aspect. Specifically, the device includes a unit for executing the method in the first aspect or any possible implementation of the first aspect.

[0018] In a third aspect, the present application provides a chip comprising at least one processor and at least one memory, wherein the at least one memory stores computer-readable instructions; the at least one processor executes the computer-readable instructions so that the chip executes the instructions of the method in the first aspect or any possible implementation of the first aspect.

[0019] In a fourth aspect, the present application provides a server comprising the chip described in the third aspect.

[0020] In a fifth aspect, the present application provides a computer program product, which includes a computer program stored in a computer-readable storage medium, and the computer program is loaded by a processor to implement instructions of the method of the above-mentioned first aspect or any possible implementation method of the first aspect.

[0021] In a sixth aspect, the present application provides a computer-readable storage medium for storing a computer program, wherein the computer program is loaded by a processor to execute instructions of the method of the first aspect or any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG1 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0023] FIG2 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0024] FIG3 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0025] FIG4 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0026] FIG5 is a flow chart of a method for processing data provided by an embodiment of the present application;

[0027] FIG6 is a schematic diagram of dividing sub-data blocks provided in an embodiment of the present application;

[0028] FIG7 is a schematic diagram of another method of dividing sub-data blocks provided in an embodiment of the present application;

[0029] FIG8 is a schematic diagram of moving a sub-data block in a multi-level cache according to an embodiment of the present application;

[0030] FIG9 is a schematic diagram of another method for moving sub-data blocks in a multi-level cache according to an embodiment of the present application;

[0031] FIG10 is a schematic diagram of a result data block provided in an embodiment of the present application;

[0032] FIG11 is a schematic diagram of another method for moving sub-data blocks in a multi-level cache according to an embodiment of the present application;

[0033] FIG12 is a schematic diagram of another method for moving sub-data blocks in a multi-level cache according to an embodiment of the present application;

[0034] FIG13 is a schematic diagram of the structure of a data processing device provided in an embodiment of the present application;

[0035] FIG14 is a schematic diagram of the structure of another device for processing data provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] 1 , the present application provides a computing device 100 , which includes a processor 101 and a multi-level cache 102 . The processor 101 can read and write the multi-level cache 102 .

[0037] The multi-level cache 102 includes multiple caches. For a cache with higher performance, the cache space is smaller and the level is higher. For a cache with lower performance, the cache space is larger and the level is lower.

[0038] Optionally, cache performance includes one or more of the following: cache bandwidth or cache read / write latency. Optionally, cache bandwidth includes cache read bandwidth and / or cache write bandwidth. That is, a higher-performance cache has a higher cache bandwidth and a lower read / write latency for reading and writing a single piece of data from the cache. A lower-performance cache has a lower cache bandwidth and a higher read / write latency for reading and writing a single piece of data from the cache.

[0039] Optionally, the processor 101 may be a graphics processing unit (GPU) or a neural network processing unit (NPU), etc. The computing device 100 may be a chip, a terminal device (such as a computer), or a server, etc.

[0040] The lowest-level cache includes a first data block and a second data block to be processed. Processor 101 needs to process the first data block and the second data block. The first data block includes multiple sub-data blocks, and the second data block includes multiple sub-data blocks. Processor 101 has a very high processing rate. To match the processing speed of processor 101 and the performance of the cache, the sub-data blocks included in the first data block and the sub-data blocks included in the second data block are moved from the lowest-level cache to the highest-level cache one level at a time. Processor 101 processes the sub-data blocks belonging to the first data block and the sub-data blocks belonging to the second data block in the highest-level cache of multi-level cache 102.

[0041] In some embodiments, the first data block and the second data block may be a first matrix and a second matrix, respectively. The sub-data blocks included in the first data block are sub-matrices in the first matrix, and the sub-data blocks included in the second data block may be sub-matrices in the second matrix. The processing operation on the first matrix and the second matrix may be: multiplying the first matrix and the second matrix.

[0042] For example, referring to FIG2 , the multi-level cache 102 is a three-level cache, including a first cache 1021 , a second cache 1022 and a third cache 1023 , wherein the third cache 1023 has the highest level, the second cache 1022 has the second highest level, and the first cache 1021 has the lowest level.

[0043] The performance of the second cache 1022 is better than that of the first cache 1021, and the space size of the first cache 1021 is larger than that of the second cache 1022. Optionally, the performance of the second cache 1022 is better than that of the first cache 1021 in one or more of the following situations: the bandwidth of the second cache 1022 is higher than that of the first cache 1021, or the read and write latency of the second cache 1022 is lower than that of the first cache 1021.

[0044] The performance of the third cache 1023 is better than that of the second cache 1022, and the space size of the second cache 1022 is larger than that of the third cache 1023. Optionally, the performance of the third cache 1023 is better than that of the second cache 1022 in one or more of the following situations: the bandwidth of the third cache 1023 is higher than the bandwidth of the second cache 1022, or the read and write latency of the third cache 1023 is lower than the read and write latency of the second cache 1022.

[0045] First cache 1021 includes a first data block and a second data block to be processed. In first cache 1021, the first data block is divided into multiple first sub-data blocks, and the second data block is divided into multiple second sub-data blocks. Limited by the space available in second cache 1022, the first sub-data block in the first data block and the second sub-data block in the second data block can be read from first cache 1021 and written to second cache 1022. In second cache 1022, the first sub-data block is divided into multiple third sub-data blocks, and the second sub-data block is divided into multiple fourth sub-data blocks. Limited by the space available in third cache 1023, the third sub-data block in the first sub-data block and the fourth sub-data block in the second sub-data block can be read from second cache 1022 and written to third cache 1023. Processor 101 can then process the third and fourth sub-data blocks in third cache 1023.

[0046] If there are still unread sub-data blocks remaining in the first sub-data block included in the second cache 1022, the third sub-data block is read from the remaining sub-data blocks in the first sub-data block included in the second cache 1022. Furthermore, if there are still unread sub-data blocks remaining in the second sub-data block included in the second cache 1022, the fourth sub-data block is read from the remaining sub-data blocks in the second sub-data block included in the second cache 1022. The read third and fourth sub-data blocks are written to the third cache 1023. When writing to the third cache 1023, the read sub-data blocks automatically overwrite the processed sub-data blocks in the third cache 1023, thereby deleting the processed sub-data blocks from the third cache 1023. The processor 101 can then process the third and fourth sub-data blocks that have been most recently written to the third cache 1023.

[0047] If there are still unread sub-data blocks remaining in the first data block included in first cache 1021, the first sub-data block is read from the remaining sub-data blocks in the first data block included in first cache 1021. Furthermore, if there are still unread sub-data blocks remaining in the second data block included in first cache 1021, the second sub-data block is read from the remaining sub-data blocks in the second data block included in first cache 1021. The read first and second sub-data blocks are written to second cache 1022. When writing to second cache 1022, the read sub-data blocks automatically overwrite the processed sub-data blocks in second cache 1022, thereby deleting the processed sub-data blocks from second cache 1022. The above process is repeated until the first sub-data block included in the first data block and the second sub-data block included in the second data block in the first cache 1021 are moved one level at a time to the third cache 1023, so that the processor 101 completes processing of the first sub-data block included in the first data block and the second sub-data block included in the second data block in the third cache 1023 to obtain a first result data block, which is the result of processing the first data block and the second data block.

[0048] For another example, referring to FIG3 , multi-level cache 102 is a four-level cache, which includes, in addition to the aforementioned first cache 1021, second cache 1022, and third cache 1023, a fourth cache 1024. The performance of first cache 1021 is superior to that of fourth cache 1024, and the space size of fourth cache 1024 is larger than that of first cache 1021. Fourth cache 1024 is the lowest level. Optionally, the performance of first cache 1021 is superior to that of fourth cache 1024 because of one or more of the following: the bandwidth of first cache 1021 is higher than that of fourth cache 1024, or the read and write latency of first cache 1021 is lower than that of fourth cache 1024.

[0049] The fourth cache 1024 includes a third data block and a fourth data block to be processed. The third data block includes multiple sub-data blocks, and the fourth data block includes multiple sub-data blocks. The first data block in the first cache 1021 is a sub-data block from the third data block included in the fourth cache 1024. The sub-data block read from the third data block included in the fourth cache 1024 can be used as the first data block, and the read first data block can be written to the first cache 1021. The second data block in the first cache 1021 is a sub-data block from the fourth data block included in the fourth cache 1024. The sub-data block read from the fourth data block included in the fourth cache 1024 can be used as the second data block, and the read second data block can be written to the first cache 1021. Then, the first sub-data block of the first data block and the second sub-data block of the second data block in the first cache 1021 are moved one level at a time to the third cache 1023, so that the processor 101 completes processing of the first sub-data block of the first data block and the second sub-data block of the second data block in the third cache 1023.

[0050] The above process is repeated until the sub-data blocks included in the third data block and the sub-data blocks included in the fourth data block in the fourth cache 1024 are moved one level at a time to the third cache 1023, so that the processor 101 completes processing of the sub-data blocks included in the third data block and the sub-data blocks included in the fourth data block in the third cache 1023 to obtain a second result data block, which is the result of processing the fifth data block and the sixth data block.

[0051] Optionally, the third cache 1023 may be a static random-access memory (SRAM), etc., and may be located in the processor 101 or not in the processor 101. The second cache 1022 may be an SRAM, the first cache 1021 may be an SRAM or a high-bandwidth memory (HBM), etc., and the fourth cache 1024 may be an HBM or a dynamic random access memory (DRAM), etc. Alternatively, the third cache 1023 may be an L1 cache, the second cache 1022 may be an L2 cache, the first cache 1021 may be an L3 cache, or the fourth cache 1024 may be an L4 cache.

[0052] The multi-level cache 102 may also include more levels of cache. For example, the multi-level cache 102 is a five-level cache, a six-level cache, or a seven-level cache, etc., which will not be listed here one by one.

[0053] In some embodiments, referring to FIG4 , for the third cache 1023 with the highest level and the second cache 1022 with the second highest level in the multi-level cache 102, the second cache 1022 may include multiple first sub-caches, the third cache 1023 includes multiple second sub-caches, and the processor 101 includes multiple processor cores.

[0054] The multiple first sub-caches correspond one-to-one with the multiple second sub-caches, and the multiple second sub-caches correspond one-to-one with the multiple processor cores. Thus, multiple first sub-data blocks are read from the first data block included in the first cache 1021, and the multiple first sub-data blocks correspond one-to-one with the multiple first sub-caches, and each first sub-data block is written to the first sub-cache corresponding to each first sub-data block.

[0055] A plurality of second sub-data blocks are read from the second data block included in the first cache 1021 , the plurality of second sub-data blocks corresponding one-to-one to the plurality of first sub-caches, and each first sub-data block is written into the first sub-caches corresponding to each second sub-data block.

[0056] For each first sub-cache, as well as for the second sub-cache corresponding to the first sub-cache and the processor core corresponding to the second sub-cache, the third sub-data block is read from the first sub-data block included in the first sub-cache, and the fourth sub-data block is read from the second sub-data block included in the first sub-cache. The read third and fourth sub-data blocks are written to the second sub-cache, and the processor core can process the third and fourth sub-data blocks in the second sub-cache. This enables multiple processor cores to process data blocks in parallel, improving the efficiency of data block processing.

[0057] During the processing of the first data block and the second data block, for sub-data blocks stored in the lower-level cache, the sub-data blocks are repeatedly written to the higher-level cache and deleted from the higher-level cache. For example, for the first sub-data block in the first data block and the second sub-data block in the second data block in the first cache 1021, during the processing of the first data block and the second data block, the first sub-data block in the first data block and the second sub-data block in the second data block are repeatedly written to the second cache 1022 and deleted from the second cache 1022. Repeated writing and deleting may require a significant amount of time, reducing the efficiency of processing data blocks.

[0058] Therefore, by reducing the number of repeated writing and deletion of sub-data blocks from the low-level cache to the high-level cache or avoiding repeated writing and deletion of sub-data blocks from the low-level cache to the high-level cache through any of the following embodiments, the efficiency of processing data blocks can be improved.

[0059] Referring to FIG. 5 , an embodiment of the present application provides a method 500 for processing data. Method 500 is applied to the computing device 100 shown in FIG. 1 , FIG. 2 , FIG. 3 , or FIG. 4 . Method 500 is described using a three-level cache included in computing device 100 as an example. The three-level cache includes a first cache, a second cache, and a third cache. The first cache includes a first data block and a second data block to be processed. Method 500 includes the following process.

[0060] Step 501: The computing device determines the size of the sub-data blocks included in the first data block and the size of the sub-data blocks included in the second data block in the first cache based on the bandwidth and space size of the second cache.

[0061] The first data block includes data in multiple rows and columns, and the second data block includes data in multiple rows and columns. Optionally, the first data block and the second data block are two matrices. The operation of processing the first data block and the second data block is a multiplication operation between the first data block and the second data block.

[0062] In some embodiments, in the field of image processing, the multiple rows and columns of data included in the first data block may be image information of the first image, for example, the first data block includes feature information of multiple rows and columns of pixels in the first image. The multiple rows and columns of data included in the second data block may be image information of the second image, for example, the second data block includes feature information of multiple rows and columns of pixels in the second image. Calculating the similarity between a first image and a second image is an application example in the field of image processing. Calculating the similarity between the first image and the second image may require calculating the product of the first data block and the second data block.

[0063] In some embodiments, in the field of trajectory processing, the first data block and the second data block may be trajectory data for the same area at different times. The first data block includes multiple lines of data representing trajectory data for multiple moving objects, each of which includes multiple trajectory points. The second data block also includes multiple lines of data representing trajectory data for multiple moving objects. When processing trajectory data at different times, it may be necessary to calculate the product of the first data block and the second data block.

[0064] In some embodiments, in the field of AI model training, the data in each row and column included in the first data block are features obtained by processing the training samples, and the data in each row and column included in the second data block are network parameters of the AI ​​model. During the AI ​​model training process, it may be necessary to calculate the product of the first data block and the second data block.

[0065] In some embodiments, in the field of AI model reasoning, the data in each row and column included in the first data block are features obtained by processing the data to be reasoned. The data to be reasoned may be image data, video data, audio data, network information or messages, etc. The data in each row and column included in the second data block are network parameters of the AI ​​model. During the AI ​​model reasoning process, it may be necessary to calculate the product of the first data block and the second data block.

[0066] The size of the sub-data in the first data block includes the number of rows D and the number of columns H, and the size of the sub-data block in the second data block includes the number of rows H and the number of columns E.

[0067] In step 501, the computing device obtains the bandwidth and space size of the second cache, and based on the bandwidth and space size of the second cache, obtains the size of the sub-data block included in the first data block and the size of the sub-data block included in the second data block when the value of D*H*E can be maximized under the constraints of the following first formula.

[0068] The first formula is:

[0069] In the first formula above, Band_w1 is the bandwidth of the second cache (for example, the write bandwidth of the second cache), Band_w2 is the bandwidth of the first target cache (for example, the write bandwidth of the first target cache), the first target cache is used to store the results obtained by processing the data blocks in the second cache, the first target cache may be the second cache, or it may be a cache other than the second cache, for example, the first target cache may be the first cache or another cache, and Space is the space size of the second cache.

[0070] input data_type is the data type of the data included in the data block written to the second cache, sizeof(input data_type) is the size of a single data of the data type, and sizeof(input data_type) is a known fixed value.

[0071] For the two data blocks included in the second cache, the result data block is obtained by processing the two data blocks, output data_type is the data type of the data included in the result data block, sizeof(output data_type) is the size of a single data of the data type, and sizeof(output data_type) is a known fixed value.

[0072] Step 502: The computing device divides the first data block into M rows and K columns of sub-data blocks based on the size of the sub-data blocks included in the first data block, and divides the second data block into K rows and N columns of sub-data blocks based on the size of the sub-data blocks included in the second data block.

[0073] The size of the sub-data blocks of the first data block includes the number of rows D and the number of columns H, and the size of the sub-data blocks of the second data block includes the number of rows H and the number of columns E. The number of rows of each sub-data block included in the first data block obtained by division is less than or equal to the number of rows D, and the number of columns is less than or equal to the number of columns H. The number of rows of each sub-data block included in the second data block obtained by division is less than or equal to the number of rows H, and the number of columns is less than or equal to the number of columns E.

[0074] The size of each sub-data block included in the first data block may be the same or different, and the size of each sub-data block included in the second data block may be the same or different.

[0075] For example, referring to Figure 6 , first data block A includes 90 rows and 80 columns of data, while second data block B includes 80 rows and 90 columns of data. The number of rows D and columns of the sub-data blocks included in first data block A is 30, and the number of columns H is 40. The number of rows H and columns E of the sub-data blocks included in second data block B is 40. In the first cache, first data block A is partitioned into 3 rows and 2 columns of sub-data blocks, each of which includes 30 rows and 40 columns of data, with M = 3 and K = 2. Second data block B is partitioned into 2 rows and 3 columns of sub-data blocks, each of which includes 40 rows and 30 columns of data, with N = 3. Therefore, when the size of first data block A is an integer multiple of the size of its sub-data blocks, each sub-data block included in first data block A can be the same size. When the size of second data block B is an integer multiple of the size of its sub-data blocks, each sub-data block included in second data block B can be the same size.

[0076] For another example, referring to Figure 7 , a first data block A includes 100 rows and 80 columns of data, while a second data block B includes 80 rows and 70 columns of data. The number of rows D and columns of the sub-data blocks included in the first data block A is 30, and the number of columns H is 40. The number of rows H and columns E of the sub-data blocks included in the second data block B is 40. In the first cache, the first data block A is partitioned to obtain sub-data blocks with 4 rows and 2 columns. Each sub-data block in the first, second, or third row includes 30 rows and 40 columns of data, and each sub-data block in the fourth row includes 10 rows and 40 columns of data. M = 4, K = 2. The second data block B is partitioned to obtain sub-data blocks with 2 rows and 3 columns. Each sub-data block in the first and second columns includes 40 rows and 30 columns of data, and each sub-data block in the third column includes 40 rows and 10 columns of data. N = 3. Therefore, when the size of the first data block A is not an integer multiple of the size of the sub-data blocks of the first data block A, the sizes of the sub-data blocks included in the first data block A are not uniform. When the size of the second data block B is not an integer multiple of the size of the sub-data blocks of the second data block B, the size of each sub-data block included in the second data block B is not the same.

[0077] Step 503: The computing device writes the first sub-data block in the k-th column and the m-th row in the first data block into the second cache, and writes the N second sub-data blocks included in the k-th row in the second data block into the second cache N times, where k is a positive integer less than or equal to K, and m is a positive integer less than or equal to M.

[0078] In step 503, the computing device reads the first sub-data block in the kth column and the mth row from the first data block included in the first cache, writes the first sub-data block in the kth column and the mth row into the second cache, and reads N second sub-data blocks included in the kth row from the second data block included in the first cache N times, and writes the second sub-data blocks read each time into the second cache.

[0079] For example, referring to Figure 8, k=1, m=1, M=3, K=2, N=3, the computing device writes the first sub-data block A1 in the 1st column and 1st row of the first data block into the second cache, and writes the second sub-data blocks B1, B2, and B3 included in the 1st row of the second data block into the second cache in 3 times.

[0080] Step 504: When the nth second sub-data block is written to the second cache for the nth time, the nth second sub-data block overwrites the second sub-data block in the second cache that has been processed with the first sub-data block, and the computing device processes the first sub-data block included in the second cache with the nth second sub-data block to obtain the kth intermediate data of the nth sub-data block in the mth row for obtaining the first result data block, where n is a positive integer less than or equal to N.

[0081] The kth intermediate data is the sub-data block at the mth row and nth column of the kth first intermediate data block. The kth first intermediate data block corresponds to the kth column of the first data block. Steps 503-504 are performed on the K columns of the first data block to obtain a total of K first intermediate data blocks. These K first intermediate data blocks are accumulated to obtain a first result data block. The detailed implementation process for obtaining the K first intermediate data blocks will be described in detail later and will not be explained here.

[0082] In some embodiments, the computing device may write the obtained kth intermediate data to a first target cache. The first target cache may be the second cache or the first cache, or the first target cache may be a memory other than the multi-level cache in the computing device (such as other caches or memory in the computing device). The obtained K first intermediate data blocks may be stored in a second target cache, and the obtained first result data block may be stored in the second target cache. The second target cache may be the first cache, or the second target cache may be a memory other than the multi-level cache in the computing device (such as other caches or memory in the computing device).

[0083] In step 504 , the kth intermediate data for obtaining the nth sub-data block in the mth row of the first result data block can be obtained through the following operations 5041 - 5043 .

[0084] 5041: The computing device divides the first sub-data block in the second cache into sub-data blocks of I rows and J columns based on the sizes of the sub-data blocks included in the first sub-data block, and divides the n-th second sub-data block into sub-data blocks of J rows and Q columns based on the sizes of the sub-data blocks included in the second sub-data block, where I, J, and Q are all integers greater than 1.

[0085] The kth intermediate data includes a sub-data block of I rows and Q columns.

[0086] Before executing 5041 , the computing device determines the size of the sub-data blocks included in the first sub-data block and the size of the sub-data blocks included in the second sub-data block in the second cache based on the bandwidth and space size of the third cache.

[0087] Combining the sizes of the sub-data blocks included in the first data block and the sub-data blocks included in the second data block in the first cache, the following conclusions can be drawn:

[0088] For caches other than the highest level cache in the multi-level cache, the size of the sub-data blocks included in the data blocks in the cache is obtained based on the bandwidth and space size of another cache that is higher in level than the cache and adjacent to the cache.

[0089] For example, referring to FIG8 , where n=1, the computing device writes the first sub-data block A1 in the first column and first row of the first data block A into the second cache, and writes the second sub-data block B1 in the first row of the second data block B into the second cache for the first time. The computing device then divides the first sub-data block A1 in the second cache into sub-data blocks with two rows and two columns, and divides the second sub-data block B1 written into the second cache for the first time into sub-data blocks with two rows and two columns.

[0090] 5042: The computing device writes J sub-data blocks in the i-th row of the first sub-data block included in the second cache into the third cache, and writes J sub-data blocks in the q-th column of the n-th second sub-data block included in the second cache into the third cache, where i is a positive integer less than or equal to I, and q is a positive integer less than or equal to Q.

[0091] In 5042, the computing device reads J sub-data blocks in the i-th row from the first sub-data block included in the second cache, and writes the J sub-data blocks in the i-th row to the third cache. Furthermore, the computing device reads J sub-data blocks in the q-th column from the n-th second sub-data block included in the second cache, and writes the J sub-data blocks in the q-th column to the third cache.

[0092] In some embodiments, after writing the J sub-data blocks in the qth column of the nth second sub-data block to the third cache, if it is no longer necessary to read the J sub-data blocks in the qth column of the nth second sub-data block from the second cache, the computing device may read the J sub-data blocks in the qth column from the (n+1)th second sub-data block in the kth row of the second data block included in the first cache. The read J sub-data blocks in the qth column are written to the second cache, and the read J sub-data blocks in the qth column overwrite the J sub-data blocks in the qth column of the nth second sub-data block included in the second cache, thereby achieving parallel execution of processing and writing, thereby improving the efficiency of processing data blocks.

[0093] In some embodiments, after writing the J sub-data blocks in the i-th row of the first sub-data block to the third cache, if it is no longer necessary to read the J sub-data blocks in the i-th row of the first sub-data block from the second cache, the computing device may read the J sub-data blocks in the i-th row from the first sub-data block in the k-th column and the m+1-th row of the first data block included in the first cache. The read J sub-data blocks in the i-th row are written to the second cache, and the read J sub-data blocks in the i-th row overwrite the J sub-data blocks in the i-th row of the first sub-data block in the k-th column and the m-th row included in the second cache, thereby achieving parallel execution of processing and writing, thereby improving the efficiency of processing data blocks.

[0094] For example, referring to Figure 8, i=1, q=1, J=2, the computing device writes sub-data blocks A11 and A12 in the 1st row of the first sub-data block A1 included in the second cache into the third cache, and writes sub-data blocks B11 and B13 in the 1st column of the second sub-data block B1 included in the second cache into the third cache.

[0095] The first sub-data block is smaller in size, and the second sub-data block is smaller in size, so that the total amount of data of the J sub-data blocks in the i-th row of the first sub-data block and the total amount of data of the J sub-data blocks in the q-th column of the second sub-data block are smaller. Even if the space size of the third cache is smaller, the J sub-data blocks in the i-th row of the first sub-data block included in the second cache can be written to the third cache, and the J sub-data blocks in the q-th column of the n-th second sub-data block included in the second cache can be written to the third cache.

[0096] 5043: The computing device processes the J sub-data blocks in the i-th row and the J sub-data blocks in the q-th column in the third cache to obtain the sub-data block in the i-th row and the q-th column included in the k-th intermediate data.

[0097] 8 , an example of processing the first sub-data block A1 and the second sub-data block B1 will be described in detail below. The processing process of this example is as follows:

[0098] In the third cache, the computing device processes sub-data blocks A11 and A12 in the first row of the first sub-data block A1, and sub-data blocks B11 and B13 in the first column of the second sub-data block B1, to obtain first intermediate data A1*B1, including sub-data blocks A11*B11+A12*B13 in the first row and first column. First intermediate data A1*B1 is the first intermediate data used to obtain the first sub-data block in the first row of the first result data block.

[0099] If q = 2, the computing device writes sub-data blocks B12 and B14 in the second column of the second sub-data block B1 in the second cache to the third cache. Sub-data blocks B12 and B14 in the second column overwrite sub-data blocks B11 and B13 in the first column of the third cache. In the third cache, the computing device processes sub-data blocks A11 and A12 in the first row of the first sub-data block A1 with sub-data blocks B12 and B14 in the second column of the second sub-data block B1, resulting in the first intermediate data A1*B1 containing the sub-data blocks A11*B12+A12*B14 in the first row and second column.

[0100] i=2, q=1. The computing device writes sub-data blocks A13 and A14 in the second row of the first sub-data block A1, included in the second cache, to the third cache. It also writes sub-data blocks B11 and B13 in the first column of the second sub-data block B1, included in the second cache, to the third cache. Sub-data blocks A13 and A14 in the second row overwrite sub-data blocks A11 and A12 in the first row of the third cache, and sub-data blocks B11 and B13 in the first column overwrite sub-data blocks B12 and B14 in the second column of the third cache. In the third cache, the computing device processes sub-data blocks A13 and A14 in the second row of the first sub-data block A1 with sub-data blocks B11 and B13 in the first column of the second sub-data block B1, resulting in the first intermediate data A1*B1 containing the sub-data blocks A13*B11+A14*B13 in the second row and first column. Optionally, referring to FIG9 , after writing sub-data blocks B11 and B13 in the first column of the second sub-data block B1 included in the second cache into the third cache, sub-data blocks B11 and B13 in the first column of the second sub-data block B1 are no longer read from the second cache, and sub-data blocks B21 and B23 in the first column can be read from the second second sub-data block B2 in the first row of the second data block B included in the first cache. Sub-data blocks B21 and B23 in the first column are written into the second cache, and sub-data blocks B21 and B23 in the first column of the second cache overwrite sub-data blocks B11 and B13 in the first column of the first second sub-data block B1, thereby enabling parallel execution of processing and writing, thereby improving the efficiency of processing data blocks.

[0101] i=2, q=2. The computing device writes sub-data blocks B12 and B14 in the second column of the second sub-data block B1 included in the second cache to the third cache. Sub-data blocks B12 and B14 in the second column overwrite sub-data blocks B11 and B13 in the first column of the third cache. In the third cache, the computing device processes sub-data blocks A13 and A14 in the second row of the first sub-data block A1 with sub-data blocks B12 and B14 in the second column of the second sub-data block B1, resulting in the first intermediate data A1*B1 including the sub-data block A13*B12+A14*B14 in the second row and second column. Optionally, referring to FIG9 , after sub-data blocks B12 and B14 in the second column of the second sub-data block B1 included in the second cache are written into the third cache, sub-data blocks B12 and B14 in the second column of the second sub-data block B1 are no longer read from the second cache, and sub-data blocks B22 and B24 in the second column can be read from the second second sub-data block B2 in the first row of the second data block B included in the first cache. Sub-data blocks B22 and B24 in the second column are written into the second cache, and sub-data blocks B22 and B24 in the second column of the second cache overwrite sub-data blocks B12 and B14 in the second column of the first sub-data block B1, thereby enabling parallel execution of processing and writing, thereby improving the efficiency of processing data blocks.

[0102] Referring to FIG. 10 , at this time k=1, m=1, n=1, and the first intermediate data A1*B1 is the sub-data block in the first row and first column of the first first intermediate data block.

[0103] Referring to FIG9 , after obtaining the sub-data block in the first row and first column of the first first intermediate data block, n=2, the computing device writes the second sub-data block B2 included in the first row of the second data block B into the second cache for the second time. The computing device then divides the second sub-data block B2 written the second time into sub-data blocks in the second cache to obtain sub-data blocks in two rows and two columns. The computing device then processes the first sub-data block A1 and the second sub-data block B2 according to the above-described example to obtain the first intermediate data A1*B2. Referring to FIG10 , the first intermediate data A1*B2 is the sub-data block in the first row and second column of the first first intermediate data block, and is also the first intermediate data used to obtain the second sub-data block in the first row of the first result data block.

[0104] Referring to FIG11 , n=3, the computing device writes the second sub-data block B3 included in the first row of the second data block B into the second cache for the third time. The computing device then divides the second sub-data block B3 written the third time into sub-data blocks with two rows and two columns. The computing device then processes the first sub-data block A1 and the second sub-data block B3 according to the above-described example to obtain the third intermediate data A1*B3. Referring to FIG10 , the third intermediate data A1*B3 is the sub-data block in the first row and third column of the first intermediate data block, and is also the first intermediate data used to obtain the third sub-data block in the first row of the first result data block.

[0105] Referring to Figure 11 , after the computing device writes sub-data blocks A11 and A12 in the first row of the first sub-data block A1 included in the second cache to the third cache, it then processes sub-data blocks A11 and A12 in the first row of the first sub-data block A1 together with the first column (B31, B33) and second column (B32, B34) of the second sub-data block B3 in the third cache, and no longer needs to read sub-data blocks A11 and A12 in the first row of the first sub-data block A1 from the second cache. Therefore, the computing device can read sub-data blocks A31 and A32 in the first row of the first sub-data block A3 in the first column and second row of the first data block A included in the first cache. Sub-data blocks A31 and A32 in the first row are written to the second cache, and sub-data blocks A31 and A32 in the first row of the second cache overwrite sub-data blocks A11 and A12 in the first row of the first sub-data block A1.

[0106] Similarly, after the computing device writes sub-data blocks A13 and A14 in the second row of the first sub-data block A1 included in the second cache into the third cache, the computing device can read sub-data blocks A33 and A34 in the second row from the first sub-data block A3 in the first column and second row of the first data block A included in the first cache. Sub-data blocks A33 and A34 in the second row are written into the second cache. Sub-data blocks A33 and A34 in the second row of the second cache will overwrite sub-data blocks A13 and A14 in the second row of the first sub-data block A1, enabling parallel processing and writing, thereby improving the efficiency of data block processing. Repeating the above process yields the first and second first intermediate data blocks shown in FIG10 .

[0107] Step 505: The computing device accumulates K intermediate data to obtain the nth sub-data block in the mth row of the first result data block, where the K intermediate data include the kth intermediate data.

[0108] The K intermediate data are K intermediate data used to obtain the nth sub-data block in the mth row of the first result data block.

[0109] Referring to FIG10 , K = 2, and the K intermediate data used to obtain the nth sub-data block in the mth row of the first result data block include the sub-data block in the mth row and nth column of the first first intermediate data block and the sub-data block in the mth row and nth column of the second first intermediate data block, where m = 1, 2, 3, and n = 1, 2, 3. The sub-data block in the mth row and nth column of the first first intermediate data block and the sub-data block in the mth row and nth column of the second first intermediate data block are accumulated to obtain the sub-data block in the mth row and nth column of the first result data block C.

[0110] In some embodiments, referring to FIG12 , the second sub-cache includes a plurality of first sub-cache, and the third cache includes a plurality of second sub-cache. A different first sub-data block in the kth column of the first data block may be written to each first sub-cache, and N second sub-data blocks in the kth row of the second data block may be written to each first sub-cache N times.

[0111] For the nth second sub-data block written for the nth time, and for each first sub-cache corresponding to a second sub-cache in the third cache, J sub-data blocks in the i-th row of the first sub-data block included in the first sub-cache are written into the second sub-cache, and J sub-data blocks in the q-th column included in the nth second sub-data block included in the first sub-cache are written into the second sub-cache. The processor core corresponding to the second sub-cache processes the J sub-data blocks in the i-th row and the J sub-data blocks in the q-th column in the second sub-cache.

[0112] For example, as shown in Figure 12, k = 1. The first sub-data block A1 in the first column and first row of the first data block A is written to the first sub-cache 1. The three second sub-data blocks in the first row of the second data block B are written to the first sub-cache 1 in three steps. The first sub-data block A3 in the first column and second row of the first data block A is written to the first sub-cache 2. The three second sub-data blocks in the first row of the second data block B are written to the first sub-cache 2 in three steps. The first sub-data block A5 in the first column and third row of the first data block A is written to the first sub-cache 3. The three second sub-data blocks in the first row of the second data block B are written to the first sub-cache 3 in three steps.

[0113] For the second sub-data block B1 written to the first sub-cache 1 for the first time, sub-data blocks A11 and A12 in the first row of the first data block A1 included in the first sub-cache 1 are written to the second sub-cache 1. Sub-data blocks B11 and B13 in the first column of the second data block B1 included in the first sub-cache 1 are written to the second sub-cache 1. The processor core corresponding to the second sub-cache 1 processes sub-data blocks A11 and A12, as well as sub-data blocks B11 and B13. Similarly, the process of writing sub-data blocks from the first sub-cache 2 to the second sub-cache 2 and from the first sub-cache 3 to the second sub-cache 3 will not be further detailed.

[0114] The above example uses a computing device with a three-level multi-level cache. However, a computing device's multi-level cache may also include more levels of cache. For example, a computing device with a four-level multi-level cache may include, in addition to the first, second, and third caches described above, a fourth cache. The fourth cache is at a lower level than the first cache, meaning that the first cache performs better than the fourth cache, and the fourth cache is larger than the first cache.

[0115] The fourth cache includes a third data block and a fourth data block, the third data block includes a sub-data block in row X and column Y, and the fourth data block includes a sub-data block in row Y and column Z, where X, Y, and Z are all integers greater than or equal to 1. The first data block in the first cache is the sub-data block in row x and column y of the third data block, and the second data block in the first cache is the z-th sub-data block in row y of the fourth data block, where x is a positive integer less than or equal to X, y is a positive integer less than or equal to Y, and z is a positive integer less than or equal to Z. Thus, before executing step 501, the method 500 further includes:

[0116] The computing device writes the sub-data block in the yth column and xth row of the third data block to the first cache, that is, writes the first data block to the first cache. Furthermore, the computing device writes the Z sub-data blocks in the yth row to the first cache in Z times. The second data block is the zth sub-data block in the yth row written to the first cache for the zth time. The second data block overwrites the sub-data block in the fourth data block in the first cache that has been processed with the first data block.

[0117] At this time, the nth sub-data block in the mth row of the first result data block is used to obtain the yth intermediate data of the zth sub-data block in the yth row of the second result data block, and the second result data block is the result of processing the third data block and the fourth data block. Optionally, the computing device may write the yth intermediate data used to obtain the zth sub-data block in the yth row of the second result data block to a third target cache, where the third target cache is the first cache or the fourth cache, or the third target cache may be a memory other than the multi-level cache in the computing device (such as other caches or memory in the computing device).

[0118] In some embodiments, the first target cache, the second target cache, and the third target cache may be different caches, the same cache, or partially the same cache.

[0119] After obtaining Y intermediate data for obtaining the zth sub-data block in the yth row of the second result data block, the computing device accumulates the Y intermediate data to obtain the zth sub-data block in the yth row of the second result data block, and the Y intermediate data include the yth intermediate data.

[0120] In an embodiment of the present application, a computing device writes the first sub-data block in the kth column and mth row of a first data block into a second cache, and writes the N second sub-data blocks included in the kth row of a second data block into the second cache N times. When the nth second sub-data block is written to the second cache for the nth time, the nth second sub-data block overwrites the second sub-data block in the second cache that has already been processed with the first sub-data block, and the computing device processes the first sub-data block included in the second cache with the nth second sub-data block to obtain the kth intermediate data of the nth sub-data block in the mth row for obtaining the first result data block. In this way, the first sub-data block is multiplied by the N second sub-data blocks respectively, the first sub-data block is reused N times, and the number of times the first sub-data block is written to the second cache is reduced by N-1 times, thereby improving the efficiency of processing the first data block and the second data block. The computing device processes a first sub-data block in the kth column of the first data block and a second sub-data block in the kth row of the second data block to obtain intermediate data including sub-data blocks of multiple rows and columns. That is, after writing a first sub-data block and a second sub-data block to the second cache, multiple processing operations can be performed to obtain sub-data blocks of multiple rows and columns, thereby improving the efficiency of the first sub-data block and the second sub-data block.

[0121] Referring to Figure 13, an embodiment of the present application provides an apparatus 1300 for processing data. The apparatus 1300 can be deployed on the computing device 100 provided in any embodiment of Figures 1 to 4, or the apparatus 1300 can be deployed on the computing device in the method 500 shown in Figure 5.

[0122] The apparatus 1300 includes a first cache and a second cache, wherein the performance of the second cache is better than that of the first cache, the first cache includes a first data block and a second data block to be processed, the first data block includes a sub-data block of M rows and K columns, and the second data block includes a sub-data block of K rows and N columns, where M, K, and N are all integers greater than 1, and the apparatus 1300 further includes: a communication unit 1301 and a processing unit 1302;

[0123] Communication unit 1301 is configured to write a first sub-data block in the k-th column and the m-th row of a first data block into a second cache, and write N second sub-data blocks included in the k-th row of a second data block into the second cache in N times, where k is a positive integer less than or equal to K, and m is a positive integer less than or equal to M;

[0124] When the nth second sub-data block is written to the second cache for the nth time, the nth second sub-data block overwrites the second sub-data block in the second cache that has been processed with the first sub-data block, and the processing unit 1302 is used to process the first sub-data block included in the second cache with the nth second sub-data block to obtain the kth intermediate data of the nth sub-data block in the mth row for obtaining the first result data block, where n is a positive integer less than or equal to N.

[0125] Optionally, the communication unit 1301 writes the first sub-data block of the kth column and the mth row in the first data block into the second cache, and writes the N second sub-data blocks included in the kth row in the second data block into the second cache N times. For the detailed implementation process, please refer to the relevant content of step 503 of method 500 shown in Figure 5, which will not be described in detail here.

[0126] Optionally, the detailed implementation process of the processing unit 1302 processing the first sub-data block and the nth second sub-data block included in the second cache is shown in step 504 of the method 500 shown in FIG5 , which will not be described in detail here.

[0127] Optionally, the processing unit 1302 is further configured to:

[0128] K intermediate data are accumulated to obtain the nth sub-data block in the mth row of the first result data block, where the K intermediate data include the kth intermediate data.

[0129] Optionally, the detailed implementation process of the processing unit 1302 accumulating K intermediate data can be found in the relevant content of step 505 of the method 500 shown in FIG5 , which will not be described in detail here.

[0130] Optionally, the apparatus 1300 further includes a third cache, wherein performance of the third cache is better than performance of the second cache, the first sub-data block in the second cache includes a sub-data block of I rows and J columns, the nth second sub-data block includes a sub-data block of J rows and Q columns, where I, J, and Q are all integers greater than 1, and the kth intermediate data includes a sub-data block of I rows and Q columns;

[0131] The communication unit 1301 is further configured to write J sub-data blocks in the i-th row of the first sub-data block included in the second cache into the third cache, and to write J sub-data blocks in the q-th column of the n-th second sub-data block included in the second cache into the third cache, where i is a positive integer less than or equal to 1, and q is a positive integer less than or equal to Q;

[0132] The processing unit 1302 is configured to process the J sub-data blocks in the i-th row and the J sub-data blocks in the q-th column in the third cache to obtain the sub-data block in the i-th row and the q-th column included in the k-th intermediate data.

[0133] Optionally, the communication unit 1301 writes the J sub-data blocks in the i-th row of the first sub-data block included in the second cache into the third cache, and writes the J sub-data blocks in the q-th column of the n-th second sub-data block included in the second cache into the third cache. For the detailed implementation process, please refer to the relevant content of 5042 of the method 500 shown in Figure 5, which will not be described in detail here.

[0134] Optionally, the detailed implementation process of the processing unit 1302 processing the J sub-data blocks in the i-th row and the J sub-data blocks in the q-th column in the third cache can be found in the relevant content of 5043 of the method 500 shown in Figure 5, which will not be described in detail here.

[0135] Optionally, the apparatus 1300 further includes a fourth cache, performance of the first cache is better than performance of the fourth cache, the fourth cache includes a third data block and a fourth data block, the third data block includes a sub-data block in an X-th row and an Y-th column, the fourth data block includes a sub-data block in an Y-th row and an Z-th column, X, Y, and Z are all integers greater than or equal to 1, the first data block is the sub-data block in the y-th column and the x-th row of the third data block, the second data block is the z-th sub-data block in the y-th row of the fourth data block, x is a positive integer less than or equal to X, y is a positive integer less than or equal to Y, and z is a positive integer less than or equal to Z; the communication unit 1301 is further configured to:

[0136] The first data block and the second data block are written into the first cache, and the second data block overwrites the sub-data block in the fourth data block in the first cache that has been processed with the first data block.

[0137] Optionally, the detailed implementation process of the communication unit 1301 writing the first data block and the second data block into the first cache refers to the relevant content of step 505 of the method 500 shown in FIG5 , which will not be described in detail here.

[0138] Optionally, the nth sub-data block in the mth row of the first result data block is used to obtain the yth intermediate data of the zth sub-data block in the yth row of the second result data block; the processing unit 1302 is further configured to:

[0139] Y pieces of intermediate data are accumulated to obtain the zth sub-data block in the yth row of the second result data block, where the Y pieces of intermediate data include the yth intermediate data.

[0140] Optionally, the detailed implementation process of the processing unit 1302 accumulating Y intermediate data can be found in the relevant content of step 505 of the method 500 shown in FIG5 , which will not be described in detail here.

[0141] Optionally, the processing unit 1302 is further configured to:

[0142] Determining the size of the sub-data blocks included in the first data block and the size of the sub-data blocks included in the second data block based on the bandwidth and space size of the second cache;

[0143] Based on the size of the sub-data blocks included in the first data block, the first data block is divided into M rows and K columns of sub-data blocks, and based on the size of the sub-data blocks included in the second data block, the second data block is divided into K rows and N columns of sub-data blocks.

[0144] Optionally, the processing unit 1302 determines the size of the sub-data blocks included in the first data block and the size of the sub-data blocks included in the second data block based on the bandwidth and space size of the second cache. For the detailed implementation process, please refer to the relevant content of step 501 of method 500 shown in Figure 5, which will not be described in detail here.

[0145] Optionally, the processing unit 1302 divides the first data block based on the size of the sub-data blocks included in the first data block, and divides the second data block based on the size of the sub-data blocks included in the second data block. For the detailed implementation process, please refer to the relevant content of step 502 of method 500 shown in Figure 5, which will not be described in detail here.

[0146] Optionally, the processing operation of processing the first data block and the second data block is a multiplication operation between the first data block and the second data block.

[0147] Optionally, the performance of the second cache is better than that of the first cache, including: the bandwidth of the second cache is higher than the bandwidth of the first cache, and / or the read and write latency of the second cache is shorter than the read and write latency of the first cache.

[0148] In the embodiment of the present application, the communication unit writes the first sub-data block in the kth column and mth row of the first data block into the second cache, and writes the N second sub-data blocks included in the kth row of the second data block into the second cache N times, and when the second sub-data block is written for the nth time, the processing unit processes the first sub-data block and the nth second sub-data block included in the second cache. Thus, after writing the first sub-data block to the second cache, the processing unit processes the first sub-data block and the second sub-data block that was written to the second cache N times consecutively, thereby avoiding repeated writing of the first sub-data block to the second cache and deletion of the first sub-data block from the second cache, thereby improving data processing efficiency.

[0149] Referring to Figure 14 , an embodiment of the present application provides a schematic diagram of an apparatus 1400 for processing data. Apparatus 1400 may be a computing device in any of the aforementioned embodiments. For example, apparatus 1400 may be computing device 100 shown in Figures 1 through 4 , or apparatus 1400 may be the computing device in method 500 shown in Figure 5 . Apparatus 1400 includes at least one processor 1401, internal connections 1402, memory 1403, and at least one transceiver 1404.

[0150] The device 1400 is a hardware structure device that can be used to implement the functional modules in the device 1300 shown in Figure 13. For example, those skilled in the art can imagine that the communication unit 1301 and the processing unit 1302 in the device 1300 shown in Figure 13 can be implemented by the at least one processor 1401 calling the code in the memory 1403.

[0151] Optionally, the apparatus 1400 may also be used to implement the functions of the computing device in any of the above embodiments.

[0152] Optionally, the processor 1401 may be a general-purpose central processing unit (CPU), a network processor (NP), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present application.

[0153] The internal connection 1402 may include a path for transmitting information between the components. Optionally, the internal connection 1402 is a single board or a bus.

[0154] The transceiver 1404 is used to communicate with other devices or communication networks.

[0155] The memory 1403 may be a read-only memory (ROM) or other static storage device capable of storing static information and instructions, a random access memory (RAM) or other dynamic storage device capable of storing information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and capable of being accessed by a computer, but not limited thereto. The memory may be independent and connected to the processor via a bus. The memory may also be integrated with the processor.

[0156] Memory 1403 is used to store application code for executing the solution of the present application, and is controlled by processor 1401. Processor 1401 is used to execute the application code stored in memory 1403 and cooperate with at least one transceiver 1404, so that device 1400 can implement the functions of the method of the present invention.

[0157] In a specific implementation, as an embodiment, the processor 1401 may include one or more CPUs, such as CPU0 and CPU1 in FIG14 .

[0158] In a specific implementation, as an embodiment, the apparatus 1400 may include multiple processors, such as the processor 1401 and the processor 1407 in FIG14 . Each of these processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. The processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0159] The information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions.

[0160] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0161] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for processing data, characterized in that The method is applied to a computing device, the computing device including a first cache, a second cache, and a third cache, the performance of the second cache being better than that of the first cache, the performance of the third cache being better than that of the second cache, the first cache including a first data block and a second data block to be processed, the first data block including a sub-data block of M rows and K columns, the second data block including a sub-data block of K rows and N columns, where M, K, and N are all integers greater than 1, the method including: The computing device writes the first sub-data block in the k-th column and the m-th row of the first data block into the second cache, and writes N second sub-data blocks included in the k-th row of the second data block into the second cache in N times, where k is a positive integer less than or equal to K, and m is a positive integer less than or equal to M. The number of rows of the first sub-data block is less than or equal to D and the number of columns is less than or equal to H, and the number of rows of the second sub-data block is less than or equal to H and the number of columns is less than or equal to E, where D, H, and E are determined based on the bandwidth and space size of the second cache; When writing the nth second sub-data block to the second cache for the nth time, the nth second sub-data block overwrites the second sub-data block in the second cache that has been processed with the first sub-data block, where n is a positive integer less than or equal to N, the first sub-data block in the second cache includes a sub-data block with I rows and J columns, and the nth second sub-data block includes a sub-data block with J rows and Q columns, where I, J, and Q are all integers greater than 1, and the computing device writes the i-th row of the first sub-data block included in the second cache into the third cache, and writes the q-th column of the n-th second sub-data block included in the second cache into the third cache, where i is a positive integer less than or equal to 1, and q is a positive integer less than or equal to Q; The computing device processes the i-th row and the q-th column in the third cache to obtain the sub-data block of the i-th row and the q-th column included in the k-th intermediate data.

2. The method according to claim 1, wherein The method further comprises: The computing device accumulates K intermediate data to obtain the nth sub-data block in the mth row of the first result data block, where the K intermediate data include the kth intermediate data.

3. The method according to claim 1 or 2, wherein: The computing device further includes a fourth cache, performance of the first cache is better than performance of the fourth cache, the fourth cache includes a third data block and a fourth data block, the third data block includes a sub-data block in X rows and Y columns, the fourth data block includes a sub-data block in Y rows and Z columns, X, Y, and Z are all integers greater than or equal to 1, the first data block is the sub-data block in the yth column and xth row of the third data block, the second data block is the zth sub-data block in the yth row of the fourth data block, x is a positive integer less than or equal to X, y is a positive integer less than or equal to Y, and z is a positive integer less than or equal to Z; the method further includes: The computing device writes the first data block and the second data block to the first cache, where the second data block overwrites the sub-data block in the fourth data block in the first cache that has been processed with the first data block.

4. The method according to claim 3, wherein The nth sub-data block in the mth row of the first result data block is used to obtain the yth intermediate data of the zth sub-data block in the yth row of the second result data block; The method further comprises: The computing device accumulates Y intermediate data to obtain the zth sub-data block in the yth row of the second result data block, where the Y intermediate data include the yth intermediate data.

5. The method according to any one of claims 1 to 4, characterized in that The method further comprises: The computing device determines, based on the bandwidth and space size of the second cache, the size of the sub-data blocks included in the first data block and the size of the sub-data blocks included in the second data block; The computing device divides the first data block into M rows and K columns of sub-data blocks based on the size of the sub-data blocks included in the first data block, and divides the second data block into K rows and N columns of sub-data blocks based on the size of the sub-data blocks included in the second data block.

6. The method according to any one of claims 1 to 5, wherein: The processing operation of processing the first data block and the second data block is a multiplication operation between the first data block and the second data block.

7. The method according to any one of claims 1 to 6, wherein: The performance of the second cache is better than that of the first cache, including: the bandwidth of the second cache is higher than the bandwidth of the first cache, and / or the read and write latency of the second cache is shorter than the read and write latency of the first cache.

8. A device for processing data, characterized in that: The device includes a first cache, a second cache, and a third cache, wherein the performance of the second cache is better than that of the first cache, and the performance of the third cache is better than that of the second cache, the first cache includes a first data block and a second data block to be processed, the first data block includes a sub-data block of M rows and K columns, and the second data block includes a sub-data block of K rows and N columns, where M, K, and N are all integers greater than 1, and the device further includes: a communication unit and a processing unit; the communication unit being configured to write the first sub-data block in the k-th column and the m-th row of the first data block into the second cache, and to write N second sub-data blocks included in the k-th row of the second data block into the second cache in N times, where k is a positive integer less than or equal to K, and m is a positive integer less than or equal to M, the number of rows of the first sub-data block is less than or equal to D and the number of columns is less than or equal to H, the number of rows of the second sub-data block is less than or equal to H and the number of columns is less than or equal to E, and D, H, and E are determined based on the bandwidth and space size of the second cache; When writing the nth second sub-data block to the second cache for the nth time, the nth second sub-data block overwrites the second sub-data block in the second cache that has been processed with the first sub-data block, n is a positive integer less than or equal to N, the first sub-data block in the second cache includes a sub-data block with I rows and J columns, and the nth second sub-data block includes a sub-data block with J rows and Q columns, where I, J, and Q are all integers greater than 1; and the processing unit is configured to write the i-th row of the first sub-data block included in the second cache into the third cache, and write the q-th column of the n-th second sub-data block included in the second cache into the third cache, where i is a positive integer less than or equal to 1, and q is a positive integer less than or equal to Q; The processing unit is further configured to process the i-th row and the q-th column in the third cache to obtain the sub-data block of the i-th row and the q-th column included in the k-th intermediate data.

9. The device according to claim 8, wherein The processing unit is further configured to: Accumulate K intermediate data to obtain the nth sub-data block in the mth row of the first result data block, where the K intermediate data include the kth intermediate data.

10. The device according to claim 8 or 9, characterized in that The apparatus further includes a fourth cache, wherein performance of the first cache is superior to that of the fourth cache, the fourth cache includes a third data block and a fourth data block, the third data block includes a sub-data block in X rows and Y columns, the fourth data block includes a sub-data block in Y rows and Z columns, X, Y, and Z are all integers greater than or equal to 1, the first data block is the sub-data block in the yth column and xth row of the third data block, the second data block is the zth sub-data block in the yth row of the fourth data block, x is a positive integer less than or equal to X, y is a positive integer less than or equal to Y, and z is a positive integer less than or equal to Z; and the communication unit is further configured to: The first data block and the second data block are written into the first cache, and the second data block overwrites the sub-data block in the fourth data block in the first cache that has been processed with the first data block.

11. The device according to claim 10, wherein The nth sub-data block in the mth row of the first result data block is used to obtain the yth intermediate data of the zth sub-data block in the yth row of the second result data block; the processing unit is further used to: Y pieces of intermediate data are accumulated to obtain the zth sub-data block in the yth row of the second result data block, where the Y pieces of intermediate data include the yth intermediate data.

12. The device according to any one of claims 8 to 11, characterized in that The processing unit is further configured to: Determining, based on the bandwidth and space size of the second cache, the size of the sub-data blocks included in the first data block and the size of the sub-data blocks included in the second data block; Based on the size of the sub-data blocks included in the first data block, the first data block is divided into M rows and K columns of sub-data blocks, and based on the size of the sub-data blocks included in the second data block, the second data block is divided into K rows and N columns of sub-data blocks.

13. The device according to any one of claims 8 to 12, characterized in that The processing operation of processing the first data block and the second data block is a multiplication operation between the first data block and the second data block.

14. The device according to any one of claims 8 to 13, characterized in that The performance of the second cache is better than that of the first cache, including: the bandwidth of the second cache is higher than the bandwidth of the first cache, and / or the read and write latency of the second cache is shorter than the read and write latency of the first cache.

15. A chip, characterized in that: The chip includes at least one processor and at least one memory, wherein the at least one memory stores computer-readable instructions; the at least one processor executes the computer-readable instructions, so that the chip executes the method according to any one of claims 1 to 7.

16. A server, characterized in that: The server comprises the chip according to claim 15 .

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