Chip and chip system

Abstract

The embodiments of the present application relate to the technical field of chips. Provided are a chip and a chip system, which balance the mutual influence among the heat, power consumption and performance of the chip, thereby improving the reliability, performance and energy efficiency of the chip, and reducing the design cost. The specific solution is as follows: the chip comprises at least one control module and at least one data processing module, wherein the control module is configured to acquire a junction temperature of the at least one data processing module in a first time period and obtain, on the basis of the junction temperature, a power consumption budget of the at least one data processing module in a second time period; and the control module is further configured to control, on the basis of the power consumption budget of at least one data processing module, the amount of data that can be processed by the at least one data processing module in the second time period. The embodiments of the present application are used for a temperature-power consumption-flow closed-loop control process.

Description

Chips and chip systems

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on March 27, 2024, with application number 202410372219.8 and application name “Chip and Chip System”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of chip technology, and in particular to a chip and a chip system. Background Art

[0003] The demands for data traffic exchange between various devices in data center networks are becoming increasingly numerous and complex. Network equipment is experiencing an increase in the number of chips, chip capacity, and chip size. Furthermore, the number of die encapsulated within a chip is increasing, leading to higher total power consumption and more volatile chip loads. Consequently, balancing the interactions between heat, power consumption, and performance is becoming increasingly critical in the practical application of network equipment.

[0004] To balance the interactions between heat, power consumption, and performance, multiple worst-case scenarios are typically considered during chip design to address thermal issues while ensuring performance. However, in actual chip applications, the probability of multiple worst-case scenarios occurring simultaneously is low, resulting in significant cost and performance penalties for the designed chip. Summary of the Invention

[0005] The embodiments of the present application provide a chip and a chip system that balances the mutual influence between the heat, power consumption and performance of the chip, achieves load balancing and temperature balancing of the chip, improves the reliability, performance and energy efficiency of the chip, and reduces design costs.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions.

[0007] In a first aspect, embodiments of the present application provide a chip comprising at least one control module and at least one data processing module. The control module is configured to obtain a junction temperature of the at least one data processing module during a first time period and, based on the junction temperature, obtain a power consumption budget for the at least one data processing module during a second time period. The control module is further configured to control the amount of data that can be processed by the at least one data processing module during the second time period based on the power consumption budget of the at least one data processing module.

[0008] Thus, the chip provided in the embodiment of the present application can obtain the power consumption budget of the data processing module in the second time period based on the junction temperature of the data processing module in the first time period, and control the amount of data that the data processing module can process in the second time period based on the power consumption budget, thereby achieving closed-loop control of temperature, power consumption, and flow. This can balance the mutual influence between the chip's heat, power consumption, and performance, achieve load balancing and temperature balancing of the chip, and improve the chip's reliability, performance, and energy efficiency. In addition, the design margin can be reduced during the chip design phase to reduce design costs.

[0009] In one possible design, at least one data processing module is at least one data processing circuit. That is, the chip provided in the embodiments of the present application can implement closed-loop control of temperature, power consumption, and flow at the circuit level to achieve load balancing and temperature balancing for at least one data processing circuit.

[0010] In one possible design, the control module is specifically configured to: determine a thermal margin for the at least one data processing circuit based on the junction temperature of the at least one data processing circuit and a temperature control threshold corresponding to the at least one data processing circuit; and calculate a power consumption budget for the at least one data processing circuit during a second time period based on the thermal margin. Thus, by using the temperature of the data processing circuit as the control target, chip damage caused by excessive junction temperature of the data processing circuit can be avoided, thereby improving chip reliability.

[0011] In one possible design, the chip further includes multiple temperature sensors, and the control module is specifically configured to obtain multiple temperature values ​​of at least one data processing circuit transmitted by the multiple temperature sensors, and process the multiple temperature values ​​based on a temperature reconstruction algorithm to obtain a junction temperature of the at least one data processing circuit during a first time period. The junction temperature may be an average junction temperature or a maximum junction temperature. Using the temperature of the data processing circuit as the control target can prevent chip damage caused by excessive junction temperature of the data processing circuit.

[0012] In one possible design, the control module is specifically configured to control the amount of data that can be processed by the multiple data processing circuits within the second time period based on the power consumption budget of each data processing circuit. Thus, the chip provided by the embodiments of the present application can implement closed-loop control of temperature, power consumption, and flow rate, achieving load and temperature balancing across the multiple data processing circuits, thereby improving the chip's reliability, performance, and energy efficiency.

[0013] In one possible design, each of the at least one data processing module includes at least one data processing circuit. This means that the chip provided in this embodiment can simultaneously implement closed-loop control of temperature, power consumption, and flow at both the circuit and module levels to achieve load balancing and temperature balancing for the at least one data processing module.

[0014] In one possible design, the control module is specifically configured to obtain the junction temperature of at least one data processing circuit and, based on the junction temperature, determine the junction temperature of at least one data processing module during a first time period. Thus, the junction temperature of at least one data processing module can be determined using the junction temperature of the at least one data processing circuit. By using the temperature of the data processing module as the control target, chip damage caused by excessive junction temperature of the data processing module can be avoided.

[0015] In one possible design, the control module is specifically configured to control the amount of data that can be processed by the multiple data processing modules within the second time period based on the power consumption budget of each data processing module.

[0016] In one possible design, the amount of data that can be processed by at least one data processing circuit during the second time period is controlled based on the amount of data that can be processed by each data processing module. Thus, the chip provided by the embodiments of the present application can simultaneously implement closed-loop control of temperature, power consumption, and flow at both the circuit and module levels, achieving load and temperature balancing across multiple data processing modules and multiple data processing circuits, thereby improving the chip's reliability, performance, and energy efficiency.

[0017] In one possible design, the control module is specifically configured to: determine a thermal margin for the at least one data processing module based on the junction temperature of the at least one data processing module and a temperature control threshold corresponding to the at least one data processing module; and calculate a power consumption budget for the at least one data processing module during a second time period based on the thermal margin. Thus, by using the temperature of the data processing module as the control target, chip damage caused by excessive junction temperature of the data processing module can be avoided, thereby improving chip reliability.

[0018] In one possible design, at least one data processing module is at least one bare die, each of which includes at least one data processing circuit, or at least one data processing module, each of which includes at least one data processing circuit. In other words, the chip provided in the embodiments of the present application can implement closed-loop control of temperature, power consumption, and flow at the die level to achieve load balancing and temperature balancing for at least one data processing circuit.

[0019] In one possible design, the control module is further configured to obtain a junction temperature of the at least one die during a first time period, and obtain a power consumption budget of the at least one die during a second time period based on the junction temperature. The control module is further configured to control an amount of data that can be processed by the at least one die during the second time period based on the power consumption budget of the at least one die.

[0020] In one possible design, the control module is further configured to obtain the junction temperature of at least one data processing module or at least one data processing circuit, and to derive the junction temperature of at least one die during the first time period based on the junction temperature. Thus, the junction temperature of the die can be derived from the junction temperature of the data processing module or the data processing circuit. Using the die temperature as the control target can avoid chip damage caused by excessive die junction temperature, thereby improving chip reliability.

[0021] In one possible design, the control module is specifically configured to control the amount of data that can be processed by the multiple die in the second time period based on the power consumption budget of each die. Thus, the chip provided by the embodiment of the present application can implement closed-loop control of temperature, power consumption, and flow rate, achieving load and temperature balancing across the multiple die, thereby improving the chip's reliability, performance, and energy efficiency.

[0022] In one possible design, the control module is specifically configured to control the amount of data that can be processed by at least one data processing module or at least one data processing circuit during a second time period, based on the amount of data that each die can process. The chip provided in embodiments of the present application can simultaneously implement closed-loop control of temperature, power consumption, and flow at the die, circuit, and module levels, achieving load and temperature balancing across multiple dies, multiple data processing modules, and multiple data processing circuits, thereby improving chip reliability, performance, and energy efficiency.

[0023] In one possible design, the control module is specifically configured to: determine a thermal margin for the at least one die based on the junction temperature of the at least one die and a temperature control threshold corresponding to the at least one die; and calculate a power consumption budget for the at least one die during a second time period based on the thermal margin. Thus, by using the die temperature as the control target, chip damage caused by excessive die junction temperature can be avoided, thereby improving chip reliability.

[0024] In one possible design, if the thermal margin is a positive value, the amount of data that can be processed by the at least one data processing module in the second time period is increased. If the thermal margin is a negative value, the amount of data that can be processed by the at least one data processing module in the second time period is reduced.

[0025] In a second aspect, an embodiment of the present application provides a chip system, the chip system including a first chip and a second chip, the first chip including a first control module and a first data processing module, the second chip including a second control module and a second data processing module. The first control module is used to obtain the junction temperature of the first data processing module in a first time period, and obtain the power consumption budget of the first data processing module in a second time period based on the junction temperature. The first control module is also used to control the amount of data that can be processed by the first data processing module in the second time period based on the power consumption budget of the first data processing module. The second control module is used to obtain the junction temperature of the second data processing module in the first time period, and obtain the power consumption budget of the second data processing module in the second time period based on the junction temperature. The second control module is also used to control the amount of data that can be processed by the second data processing module in the second time period based on the power consumption budget of the second data processing module.

[0026] Therefore, the chip system provided by the embodiment of the present application can simultaneously realize closed-loop control of temperature-power consumption-flow at the chip level, bare die level, circuit level and module level, realize load balancing and temperature balancing of multiple chips, multiple bare dies, multiple data processing modules and multiple data processing circuits, and improve the reliability, performance and energy efficiency of the chip system.

[0027] In one possible design, the first data processing module is a first data processing circuit, and the second data processing module is a second data processing circuit.

[0028] In one possible design, the first data processing modules each include at least one first data processing circuit, and the second data processing modules each include at least one second data processing circuit.

[0029] In one possible design, the first control module is specifically configured to control the amount of data that can be processed by at least one first data processing circuit in a second time period based on the amount of data that can be processed by each first data processing module. The second control module is specifically configured to control the amount of data that can be processed by at least one second data processing circuit in a second time period based on the amount of data that can be processed by each second data processing module.

[0030] In one possible design, the first chip includes at least one first die, each of which includes at least one first data processing circuit, or at least one first data processing module, each of which includes at least one first data processing circuit. The second chip includes at least one second die, each of which includes at least one second data processing circuit, or at least one second data processing module, each of which includes at least one second data processing circuit.

[0031] In one possible design, the first control module is specifically configured to control the amount of data that can be processed by at least one first data processing circuit or at least one first data processing module in a second time period based on the amount of data that can be processed by each first die. The second control module is specifically configured to control the amount of data that can be processed by at least one second data processing circuit or at least one second data processing module in a second time period based on the amount of data that can be processed by each second die.

[0032] Some of the beneficial effects of the second aspect can be found in the description of the first aspect.

[0033] In a third aspect, embodiments of the present application provide a control method, which is applied to a chip comprising at least one control module and at least one data processing module. The method includes: the control module obtaining a junction temperature of the at least one data processing module during a first time period, and obtaining a power consumption budget of the at least one data processing module during a second time period based on the junction temperature. Based on the power consumption budget of the at least one data processing module, the control module controls the amount of data that can be processed by the at least one data processing module during the second time period.

[0034] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, including computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes the control method in any of the above aspects and any possible implementation methods.

[0035] In a fifth aspect, an embodiment of the present application provides a computer program product, which, when executed on a computer or a processor, enables the computer or the processor to execute the control method in any of the above aspects and any possible implementation methods.

[0036] It can be understood that any of the chips, chip systems, computer-readable storage media or computer program products provided above can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods and will not be repeated here.

[0037] These and other aspects of the present application will become more readily apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] FIG1 is a framework diagram of a data center network provided in an embodiment of the present application;

[0039] FIG2 is a schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0040] FIG3 is a schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0041] FIG4 is a flow chart of a control module provided in an embodiment of the present application;

[0042] FIG5 is a schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0043] FIG6 is a flow chart of another control module provided in an embodiment of the present application;

[0044] FIG7 is a schematic structural diagram of another chip provided in an embodiment of the present application;

[0045] FIG8 is a schematic structural diagram of a chip system provided in an embodiment of the present application;

[0046] FIG9 is a flow chart of a chip system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships can exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0048] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this embodiment, unless otherwise specified, "plurality" means two or more.

[0049] Chip design, also known as integrated circuit design (IC design) or very large-scale integration design (VLSI design), refers to the design process targeting integrated circuits or very large-scale integrated circuits. IC design involves modeling electronic components (such as transistors, resistors, and capacitors) and the interconnections between them. All these components and interconnects must be placed on a single semiconductor substrate (such as silicon). These components and interconnects are then placed on this single silicon substrate through semiconductor manufacturing processes (such as photolithography), forming a circuit.

[0050] The chip design process can include overall planning, design architecture / algorithms, code translation, simulation verification, process selection, timing and power analysis, formal verification, and automatic layout and routing. During the chip design phase, if the worst-case scenarios are combined to address thermal issues while ensuring performance, the following drawbacks will occur:

[0051] (1) Cost and energy efficiency costs. If the chip design process takes into account the worst-case scenarios of various design factors (such as differences in process technology, differences in junction temperature specifications of packaged bare chips, equipment ambient temperature ranges, use case differences, slot differences, and usage environment differences, etc.), since the probability of the worst-case scenarios of these design factors occurring at the same time is extremely low, it will lead to huge cost and energy efficiency costs, and it may be impossible to design the chip or the chip cannot be put into use.

[0052] (2) Reliability risk: Since it is impossible to exhaustively enumerate customer scenarios during the design phase, if certain atypical design scenarios occur during the chip application phase, the chip may also experience over-junction temperature, posing a thermal reliability risk. Alternatively, if abnormal conditions are not considered during the design phase, such as the device ambient temperature exceeding the specified temperature or the chip's external heat dissipation measures failing, the chip may also experience over-junction temperature, posing a thermal reliability risk.

[0053] (3) Performance cost: The chip is subject to power supply or environmental restrictions during application. In order to avoid problems such as reset and power failure, the chip's power consumption is also constrained, resulting in reduced chip performance.

[0054] In one possible implementation, a circuit module control method is proposed. The method obtains temperature information of the circuit module and allocates module power or throughput according to temperature threshold limits, thereby controlling the circuit module inside a system-on-a-chip (SOC).

[0055] However, this method is mainly targeted at mobile terminal chips, and relies on the correlation between different modules within the mobile terminal chip to achieve module power or throughput allocation, and is not suitable for high-performance network chips.

[0056] Thus, embodiments of the present application provide a chip that can determine the power consumption budget of a data processing module during a second time period based on the junction temperature of the data processing module during a first time period, and control the amount of data that can be processed by the data processing module during the second time period based on the power consumption budget. This achieves closed-loop control of temperature, power consumption, and flow, balancing the interactions among heat, power consumption, and performance of the chip, achieving load and temperature balancing of the chip, and improving the chip's reliability, performance, and energy efficiency. Furthermore, design margins can be reduced during the chip design phase to lower design costs.

[0057] In the above scenario, the device to which the chip provided in the embodiment of the present application is applied may be an execution device, which may be a terminal such as a mobile phone terminal, tablet computer, laptop computer, vehicle-mounted terminal, etc., or a server cluster, etc. The chip provided in the embodiment of the present application may be applied in fields involving traffic forwarding in the execution device.

[0058] In some embodiments, the chip provided in the embodiments of the present application may be a system-on-chip (SoC) or a network chip. The SoC may include a processor, memory, and input / output (I / O) interfaces. The processor may be a single-core processor or a multi-core processor. The processor may load data and applications from the memory and then process the data.

[0059] The network chip can be applied to the equipment of the data center network (DCN), that is, it can be applied to the equipment of the access layer (top of rack, TOR), the aggregation layer (spine) or the core layer (core). As shown in Figure 1, Figure 1 is a framework diagram of a data center network provided by an embodiment of the present application. Among them, the downlink port of the access layer network device is connected to multiple servers (not shown in Figure 1), the uplink port of the access layer network device is connected to the downlink port of the aggregation layer network device, and the uplink port of the aggregation layer network device is connected to the core layer network device. The network chip can be an access layer network device chip, an aggregation layer network device chip or a core layer network device chip. The data center network can realize data traffic exchange between different servers in the same group (pod) through the access layer network device chip, and can realize data traffic exchange between servers connected in different groups through the aggregation layer network device chip and the core layer network device chip.

[0060] It can be understood that the chip provided in the embodiment of the present application is a chip-level traffic performance management solution, which can be coordinated with the device-level traffic management solution and the network-level traffic management solution to implement a traffic management solution for the data center network.

[0061] The following is a further introduction to the chip provided in the embodiments of the present application.

[0062] An embodiment of the present application provides a chip, as shown in FIG2 , which is a schematic structural diagram of a chip provided in an embodiment of the present application. The chip includes at least one control module and multiple data processing modules. FIG2 only shows one control module and multiple data processing modules. The chip may also include a larger number of control modules and data processing modules. The embodiment of the present application does not limit the number of control modules and data processing modules.

[0063] For example, the chip may include a control module, which may exist independently of at least one data processing module, or may be integrated into one of the data processing modules. The chip may also include multiple control modules and multiple data processing modules, each of which may be integrated with a control module. If some data processing modules are fixed-flow data processing modules, these data processing modules may not be integrated with a control module. The control module can be set up in various ways, and the embodiments of the present application are not limited thereto.

[0064] Exemplarily, the functions of the multiple data processing modules may be different, and the data processing modules may realize functions such as receiving data, sending data, and performing operations on data.

[0065] Exemplarily, the control module may be a general-purpose processor, such as a central processing unit, etc. The control module may execute different types of tasks, such as the process of obtaining the junction temperature in the embodiment of the present application.

[0066] The control module is configured to obtain a junction temperature (Tj) of at least one data processing module in a first time period, and obtain a power budget (power budget) of at least one data processing module in a second time period based on the junction temperature.

[0067] For example, the first time period and the second time period may be temperature control periods, and the first time period and the second time period may be adjacent time periods, or non-adjacent time periods. Furthermore, the length of the first time period and the length of the second time period may be equal, or unequal. In one possible example, the length of the first time period or the second time period may be 8 ms or 10 ms, etc.

[0068] For example, the junction temperature refers to the junction temperature within a semiconductor device, that is, the temperature within the chip. When a semiconductor device is operating, it generates a certain amount of power consumption, which will cause the internal temperature of the chip to rise. If the internal temperature of the chip is too high, it will negatively affect the performance and reliability of the semiconductor device and may even cause damage to the device. The junction temperature provided in the embodiments of the present application can be the average junction temperature of the data processing module or the maximum junction temperature (Tjmax) of the data processing module.

[0069] In one example, the control module can obtain the maximum junction temperature of each data processing module, where the maximum junction temperature is greater than or equal to the maximum temperature value among multiple temperature values ​​of the multiple data processing modules. In other words, the maximum junction temperature can be the maximum temperature value among multiple temperature values, or the maximum junction temperature can be greater than the maximum temperature value among multiple temperature values. Because each data processing module performs different tasks, the maximum junction temperature of each data processing module can be different. In addition, the temperature control threshold of each data processing module can also be different, where the temperature control threshold is a parameter determined during the design and testing process of the semiconductor and can be used to characterize the maximum temperature at which the semiconductor device can safely operate.

[0070] Exemplarily, the power consumption and junction temperature of the data processing module are positively correlated, i.e., the greater the power consumption, the higher the junction temperature, and the lower the power consumption, the lower the junction temperature. If the maximum junction temperature of the data processing module during the first time period is less than the temperature control threshold, the power consumption budget of the data processing module can be increased during the second time period to improve chip performance. If the maximum junction temperature of the data processing module during the first time period is greater than the temperature control threshold, the power consumption budget of the data processing module can be reduced during the second time period to lower the junction temperature of the chip and improve chip reliability. If the maximum junction temperature of the data processing module during the first time period is equal to the temperature control threshold, the power consumption budget of the data processing module can be maintained during the second time period.

[0071] The control module is further configured to control the amount of data that can be processed by the at least one data processing module in the second time period based on the power consumption budget of the at least one data processing module.

[0072] For example, the amount of data that a data processing module can process can be understood as the traffic of the data processing module. The traffic of a data processing module is positively correlated with power consumption, i.e., the greater the traffic, the higher the power consumption, and the smaller the traffic, the lower the power consumption. If the power consumption budget of the data processing module needs to be increased during the second time period, the traffic that can be processed by at least one data processing module during the second time period can be increased. If the power consumption budget of the data processing module needs to be reduced during the second time period, the traffic that can be processed by at least one data processing module during the second time period can be reduced.

[0073] Exemplarily, the traffic of the data processing module includes the upstream traffic and / or downstream traffic of the data processing module. In one possible example, increasing the traffic of the data processing module may increase the length of the data packets of the data processing module or increase the bandwidth of the data processing module, while decreasing the traffic of the data processing module may decrease the length of the data packets of the data processing module or decrease the bandwidth of the data processing module. In another possible example, when the traffic of the data processing module changes, the device voltage of the data processing module also changes accordingly.

[0074] As a result, the chip provided by the embodiments of the present application implements closed-loop control of temperature, power consumption, and flow, balancing the interactions among the chip's heat, power consumption, and performance. This improves the chip's reliability, performance, and energy efficiency, achieving load and temperature balancing across the chip. Furthermore, design margins can be reduced during the chip design phase, lowering design costs.

[0075] Optionally, as shown in Figure 3, Figure 3 is a schematic diagram of the structure of another chip provided in an embodiment of the present application. Among them, at least one data processing module is at least one data processing circuit. Figure 3 shows a control module and multiple data processing circuits. Among them, the control module can exist independently of at least one data processing circuit, and the control module can also be integrated into one of the data processing circuits. The chip can also include multiple control modules and multiple data processing circuits, and each data processing circuit can be integrated with a control module. If part of the data processing circuit is a fixed-flow data processing circuit, the part of the data processing circuit may not be integrated with a control module.

[0076] Optionally, the control module is further configured to: obtain a thermal headroom of the at least one data processing circuit based on a junction temperature of the at least one data processing circuit and a temperature control threshold corresponding to the at least one data processing circuit, and obtain a power consumption budget of the at least one data processing circuit for a second time period based on the thermal headroom calculation.

[0077] For example, assuming the junction temperature of the data processing circuit is denoted as Tj, the temperature control threshold is denoted as T1, and the thermal margin is denoted as T2, in one possible embodiment, the junction temperature, temperature control threshold, and thermal margin of the data processing circuit can satisfy the following relationship: T2 = Tj - T1, that is, the thermal margin is the difference between the junction temperature and the temperature control threshold. In another possible embodiment, the junction temperature, temperature control threshold, and thermal margin of the data processing circuit can satisfy the following relationship: T2 = f(Tj, T1), where f(Tj, T1) represents a transformation function with respect to Tj and T2.

[0078] In one possible example, assuming that the temperature control threshold of a first data processing circuit among the multiple data processing circuits is 90 degrees Celsius, if the junction temperature of the first data processing circuit is 100 degrees Celsius, the thermal margin of the first data processing circuit may be 10 degrees Celsius. If the junction temperature of the first data processing circuit is 80 degrees Celsius, the thermal margin of the first data processing circuit may be -10 degrees Celsius.

[0079] In one possible implementation, the power consumption budget P and thermal margin of the data processing circuit can satisfy the following relationship: P = k * T2, where k is the power consumption coefficient. In another possible implementation, the mapping relationship between the power consumption budget and thermal margin can also be stored in a lookup table or chart. In yet another possible implementation, the control module can further process the thermal margin based on an interpolation method to obtain the power consumption budget of the data processing circuit.

[0080] In one possible example, assuming that the thermal margin of the first data processing circuit is 10 degrees Celsius, the power consumption budget of the first data processing circuit may be 10 W, that is, the increased power consumption of the first data processing circuit is 10 W. assuming that the thermal margin of the first data processing circuit is -10 degrees Celsius, the power consumption budget of the first data processing circuit may also be 10 W, that is, the reduced power consumption of the first data processing circuit is 10 W.

[0081] Optionally, if the thermal margin of the at least one data processing circuit is positive, the amount of data that can be processed by the at least one data processing circuit in the second time period is increased. If the thermal margin of the at least one data processing circuit is negative, the amount of data that can be processed by the at least one data processing circuit in the second time period is reduced.

[0082] Exemplarily, the thermal margin, power consumption, and flow rate are positively correlated. That is, when the thermal margin of the data processing circuit is positive, the power consumption of the data processing circuit in the second time period is increased, that is, the amount of data that the data processing circuit can process in the second time period is increased. When the thermal margin of the data processing circuit is negative, the power consumption of the data processing circuit in the second time period is reduced, that is, the amount of data that the data processing circuit can process in the second time period is reduced.

[0083] Optionally, the chip may also include multiple temperature sensors (not shown in Figure 3), and the control module is specifically used to: obtain multiple temperature values ​​of at least one data processing circuit transmitted by multiple temperature sensors, process the multiple temperature values ​​based on the temperature reconstruction algorithm, and obtain the junction temperature of at least one data processing circuit in the first time period.

[0084] Exemplarily, the temperature reconstruction algorithm is a method for processing and correcting temperature data, which can be implemented through techniques such as interpolation, power consumption estimation, and black box training.

[0085] Specifically, interpolation is a commonly used temperature reconstruction algorithm that infers the temperature value at an unknown location using multiple known temperature values. Common interpolation methods include linear interpolation, polynomial interpolation, and spline interpolation. These methods can infer the temperature value at an unknown location based on the relationship between multiple known temperature values, thereby obtaining the junction temperature of the data processing circuit.

[0086] Specifically, power estimation is a temperature reconstruction algorithm based on physical models. It establishes a power consumption model for a circuit or system and, based on the temperature-power consumption relationship, calculates the system's power consumption at different temperatures, thereby determining the junction temperature of the data processing circuit.

[0087] Specifically, black-box training is a temperature reconstruction algorithm based on machine learning. It collects input and output data from a system at different temperatures and builds a model to predict the system's temperature. This method uses machine learning algorithms such as neural networks and support vector machines to predict and reconstruct the system's temperature, thereby obtaining the junction temperature of the data processing circuit.

[0088] Optionally, the control module is specifically configured to control the amount of data that can be processed by the multiple data processing circuits within the second time period based on the power consumption budget of each data processing circuit.

[0089] For example, the control module can establish a mathematical model of flow rate and power consumption to predict the changes between flow rate and power consumption under different conditions. This mathematical model can be derived by selecting and modulating a linear model, a polynomial model, a logarithmic model, or an exponential model, for example, based on the application scenario and data. Specifically, by inputting the power consumption budget of each data processing circuit into this mathematical model, the amount of data that the data processing circuit can process in the second time period can be determined.

[0090] For example, assuming that the multiple data processing circuits include a first data processing circuit, a second data processing circuit, and a third data processing circuit, and the power consumption budget of the first data processing circuit is to increase by 10W, the power consumption budget of the second data processing circuit is to decrease by 20W, and the power consumption budget of the third data processing circuit is to increase by 25W, then the reduced traffic of the second data processing circuit can be distributed to the first data processing circuit and the second data processing circuit to avoid overheating of the junction temperature of the second data processing circuit.

[0091] Therefore, for the data processing circuit, the control module process is shown in Figure 4, which includes the following steps: S401: Acquire multiple temperature values ​​of at least one data processing circuit transmitted by multiple temperature sensors during a first time period. S402: Process the multiple temperature values ​​based on a temperature reconstruction algorithm to obtain the junction temperature of the at least one data processing circuit during the first time period. S403: Determine whether the junction temperature is greater than a temperature control threshold, and based on the junction temperature, obtain a power consumption budget for the at least one data processing circuit during a second time period. If the junction temperature is greater than the temperature control threshold, execute S404; if the junction temperature is less than or equal to the temperature control threshold, execute S405. S404: Determine, based on the power consumption budget, the amount of data that needs to be reduced for the at least one data processing circuit during the second time period. S405: Determine, based on the power consumption budget, the amount of data that needs to be increased for the at least one data processing circuit during the second time period. S406: Control the amount of data that can be processed by the at least one data processing circuit during the second time period.

[0092] Therefore, the chip provided in the embodiment of the present application uses fixed environmental conditions and temperature as control targets and flow rate as control variable to achieve closed-loop control of temperature-power consumption-flow rate, which can control the junction temperature deviation of the chip to approximately ±2°C and achieve a performance gain of 1% to 5%.

[0093] Optionally, as shown in FIG5 , FIG5 is a schematic diagram of the structure of another chip provided in an embodiment of the present application. Each of the at least one data processing module includes at least one data processing circuit. FIG5 shows a control module and multiple data processing modules, each of which includes multiple data processing circuits.

[0094] Optionally, the control module is specifically configured to: acquire a junction temperature of at least one data processing circuit, and obtain a junction temperature of at least one data processing module in a first time period based on the junction temperature.

[0095] Exemplarily, the control module may obtain multiple temperature values ​​of at least one data processing circuit via a temperature sensor and obtain the junction temperature of the at least one data processing circuit using a temperature reconstruction algorithm. Thus, based on the junction temperature of the at least one data processing circuit, the control module may continue to obtain the junction temperature of the at least one data processing module using the temperature reconstruction algorithm. The junction temperature of the data processing module is greater than or equal to the maximum junction temperature of the at least one data processing circuit.

[0096] Optionally, the control module is specifically configured to control the amount of data that can be processed by the multiple data processing modules within the second time period based on the power consumption budget of each data processing module.

[0097] Exemplarily, the control module may input the power consumption budget of each data processing module into a mathematical model of traffic and power consumption to obtain the amount of data that the data processing module can process in the second time period.

[0098] For example, assuming that the multiple data processing modules include a first data processing module, a second data processing module and a third data processing module, and the power consumption budget of the first data processing module is to increase by 15W, the power consumption budget of the second data processing module is to reduce by 20W, and the power consumption budget of the third data processing module is to increase by 5W, then the traffic that needs to be reduced in the second data processing module can be distributed to the first data processing module and the second data processing module to avoid the junction temperature of the second data processing module from overheating.

[0099] Optionally, the control module is specifically configured to control the amount of data that can be processed by at least one data processing circuit in the second time period based on the amount of data that can be processed by each data processing module.

[0100] Exemplarily, continuing to refer to the above example, at this time, it is necessary to increase the flow of the first data processing module and the third data processing module. Continuing to assume that the first data processing module includes a first data processing circuit, a second data processing circuit, and a third data processing circuit, that is, the control module needs to increase the flow of the first data processing circuit, reduce the flow of the second data processing circuit, and increase the flow of the third data processing circuit. Specifically, the control module can distribute the flow that the first data processing module needs to increase to the first data processing circuit and the third data processing circuit, and distribute the flow that the third data processing module needs to increase to the data processing circuit included in the third data processing module. In other words, the data processing module sends the amount of data that it needs to increase or decrease to be processed to at least one data processing circuit for processing, which can achieve load balancing and temperature balancing of multiple data processing modules, avoid excessively high local peak temperatures of the chip, and thus achieve the purpose of reducing power consumption and improving energy efficiency.

[0101] Optionally, the control module is specifically used to: obtain the thermal margin of at least one data processing module based on the junction temperature of at least one data processing module and the temperature control threshold corresponding to at least one data processing module, and obtain the power consumption budget of at least one data processing module in the second time period based on the thermal margin calculation.

[0102] For example, each data processing module may correspond to a different temperature control threshold. The correspondence between the junction temperature of the data processing module and the temperature control threshold can refer to the correspondence between the data processing circuit and the temperature control threshold, which will not be repeated here.

[0103] Therefore, for the data processing module, the control module's processing flow is shown in FIG6 : S601: Obtain the junction temperature of at least one data processing circuit, and based on the junction temperature, obtain the junction temperature of at least one data processing module for a first time period. S602: Determine whether the junction temperature is greater than a temperature control threshold, and based on the junction temperature, obtain a power consumption budget for at least one data processing module for a second time period. If the junction temperature is greater than the temperature control threshold, execute S603; if the junction temperature is less than or equal to the temperature control threshold, execute S604. S603: Determine, based on the power consumption budget, the amount of data that needs to be processed by at least one data processing module in the second time period needs to be reduced. S604: Determine, based on the power consumption budget, the amount of data that needs to be processed by at least one data processing module in the second time period needs to be increased. S605: Control the amount of data that can be processed by at least one data processing module in the second time period. S606: Control the amount of data that can be processed by at least one data processing circuit in the second time period.

[0104] Therefore, the chip provided in the embodiment of the present application can simultaneously realize closed-loop control of temperature-power consumption-flow at the circuit level and the module level, realize load balancing and temperature balancing of multiple data processing modules and multiple data processing circuits, and improve the reliability, performance and energy efficiency of the chip.

[0105] Optionally, as shown in FIG7 , FIG7 is a schematic diagram of the structure of another chip according to an embodiment of the present application. In this embodiment, at least one data processing module is at least one bare die, each bare die including at least one data processing circuit, or at least one data processing module, each data processing module including at least one data processing circuit. FIG7 shows two bare dies, namely, bare die 0 and bare die 1, wherein bare die 1 is integrated with a control module. In addition, a control module may also be integrated into bare die 0.

[0106] The embodiments of the present application do not limit the type of chip. The chip can be 2D, that is, all the dies are placed on the substrate of the same plane. The chip can also be 2.5D, that is, multiple dies are stacked together through a silicon substrate. The chip can also be 3D, that is, multiple dies are vertically stacked together through a silicon substrate or silicon interconnects. Among them, die 0 and die 1 can be isomorphic or heterogeneous, that is, the type of die 0 and die 1 can be the same, or the type of die 0 and die 1 can be different.

[0107] Optionally, the control module is also used to obtain the junction temperature of at least one bare chip in the first time period, and obtain the power consumption budget of at least one bare chip in the second time period based on the junction temperature. The control module is also used to control the amount of data that can be processed by at least one bare chip in the second time period based on the power consumption budget of at least one bare chip.

[0108] For example, the die's thermal margin, power consumption, and throughput are positively correlated. That is, when the die's thermal margin is positive, the die's power consumption in the second time period increases, which in turn increases the amount of data the die can process in the second time period. When the die's thermal margin is negative, the die's power consumption in the second time period decreases, which in turn decreases the amount of data the die can process in the second time period.

[0109] Optionally, the control module is specifically configured to: acquire a junction temperature of at least one data processing module or at least one data processing circuit, and obtain a junction temperature of at least one bare chip in a first time period based on the junction temperature.

[0110] Exemplarily, the control module may obtain the junction temperature of the at least one die based on a temperature reconstruction algorithm using the junction temperature of the at least one data processing module or the at least one data processing circuit, wherein the junction temperature of the die is greater than or equal to the maximum junction temperature of the at least one data processing module or the at least one data processing circuit.

[0111] Optionally, the control module is specifically configured to control the amount of data that can be processed by the plurality of bare chips in the second time period based on the power consumption budget of each bare chip.

[0112] For example, the control module may input the power consumption budget of each die into a mathematical model of traffic and power consumption to obtain the amount of data that the die can process in the second time period.

[0113] Optionally, the control module is specifically configured to control the amount of data that can be processed by at least one data processing module or at least one data processing circuit in the second time period based on the amount of data that can be processed by each die.

[0114] For example, assuming that the first die among multiple die includes a first data processing module and a second data processing module, and the first data processing module includes a first data processing circuit and a second data processing circuit, and assuming that the first die needs to increase the amount of data that can be processed in the second time period, the control module can distribute the required increased traffic to the first data processing module and the second data processing module, and the control module can further distribute the required increased traffic to the first data processing circuit and the second data processing circuit.

[0115] Optionally, the control module is specifically used to: obtain a thermal margin of at least one die based on the junction temperature of at least one die and a temperature control threshold corresponding to at least one die, and calculate a power consumption budget of at least one die in a second time period based on the thermal margin.

[0116] For example, the temperature control threshold corresponding to each die may be different. The correspondence between the junction temperature of the die and the temperature control threshold can refer to the correspondence between the data processing circuit and the temperature control threshold, which will not be repeated here.

[0117] Therefore, the chip provided in the embodiment of the present application may include multiple bare chips, each bare chip may include multiple data processing modules, and each data processing module may include multiple data processing circuits. Among them, the control module can obtain multiple temperature values ​​of the data processing circuit to obtain the junction temperature of the data processing circuit, obtain the junction temperature of the data processing module through the junction temperature of the data processing circuit, and further obtain the junction temperature of the bare chip. The control module then controls the amount of data that can be processed by the multiple bare chips through an adaptive temperature control mechanism. Controlling the amount of data that can be processed by the multiple bare chips can be achieved by controlling the amount of data that can be processed by the multiple data processing modules, and controlling the amount of data that can be processed by the multiple data processing modules can be achieved by controlling the amount of data that can be processed by the multiple data processing circuits.

[0118] The present application also provides a chip system, as shown in Figure 8, which is a schematic diagram of the structure of a chip system provided by the present application. The chip system includes a first chip and a second chip, the first chip including a first control module and a first data processing module, and the second chip including a second control module and a second data processing module.

[0119] The first control module is configured to obtain a junction temperature of the first data processing module during a first time period, and obtain a power consumption budget of the first data processing module during a second time period based on the junction temperature. The first control module is further configured to control the amount of data that can be processed by the first data processing module during the second time period based on the power consumption budget of the first data processing module. The second control module is configured to obtain a junction temperature of the second data processing module during the first time period, and obtain a power consumption budget of the second data processing module during the second time period based on the junction temperature. The second control module is further configured to control the amount of data that can be processed by the second data processing module during the second time period based on the power consumption budget of the second data processing module.

[0120] For example, the type of the first chip and the type of the second chip may be the same, or the type of the first chip and the type of the second chip may be different. Data traffic between the first chip and the second chip may be communicated, scheduled, and allocated.

[0121] For example, each chip can report its processable flow rate to the control module, and the control module can allocate the flow rate among multiple chips according to allocation criteria, wherein the allocation criteria can be related to thermal margin ratio and average temperature ratio.

[0122] It is understandable that the chip system can also be a single board or a device, etc.

[0123] Optionally, the chip system may further include a third control module (not shown in FIG8 ), wherein the third control module may respectively obtain the junction temperatures of the first chip and the second chip in the first time period, and obtain the power consumption budgets of the first chip and the second chip in the second time period based on the junction temperatures. The third control module may also control the amount of data that the first chip and the second chip can process in the second time period based on the power consumption budgets of the first chip and the second chip, respectively. In other words, the chip system provided in the embodiment of the present application can implement closed-loop control of temperature-power consumption-flow at the chip level, balance the mutual influence between the heat, power consumption and performance of the chip system, achieve load balancing and temperature balancing of each chip, and improve the reliability, performance and energy efficiency of the chip system.

[0124] Optionally, the first data processing module is a first data processing circuit, and the second data processing module is a second data processing circuit.

[0125] Illustratively, the chip system provided in the embodiment of the present application can implement closed-loop control of temperature-power consumption-flow at the circuit level, balance the mutual influence between the heat, power consumption and performance of the chip system, achieve load balancing and temperature balancing of the data processing circuit of each chip, and improve the reliability, performance and energy efficiency of the chip system.

[0126] Optionally, the first data processing modules each include at least one first data processing circuit, and the second data processing modules each include at least one second data processing circuit.

[0127] Optionally, the first control module is specifically configured to: control the amount of data that can be processed by the at least one first data processing circuit in the second time period based on the amount of data that can be processed by each first data processing module. The second control module is specifically configured to: control the amount of data that can be processed by the at least one second data processing circuit in the second time period based on the amount of data that can be processed by each second data processing module.

[0128] Exemplarily, the chip system provided in the embodiment of the present application can simultaneously implement closed-loop control of temperature-power consumption-flow at the circuit level and the module level to achieve load balancing and temperature balancing of at least one data processing module. Among them, the control module obtains multiple temperature values ​​of the data processing circuit to obtain the junction temperature of the data processing circuit, and further obtains the junction temperature of the data processing module. The control module controls the amount of data that can be processed by multiple data processing modules through an adaptive temperature control mechanism, wherein controlling the amount of data that can be processed by multiple data processing modules can be achieved by controlling the amount of data that can be processed by multiple data processing circuits.

[0129] Optionally, the first chip includes at least one first die, each of which includes at least one first data processing circuit, or at least one data processing module, each of which includes at least one first data processing circuit. The second chip includes at least one second die, each of which includes at least one second data processing circuit, or at least one second data processing module, each of which includes at least one second data processing circuit.

[0130] Optionally, the first control module is specifically configured to control the amount of data that can be processed by at least one first data processing circuit or at least one first data processing module in the second time period based on the amount of data that can be processed by each first die. The second control module is specifically configured to control the amount of data that can be processed by at least one second data processing circuit or at least one second data processing module in the second time period based on the amount of data that can be processed by each second die.

[0131] For example, the chip system provided by the embodiment of the present application can simultaneously implement closed-loop control of temperature-power consumption-flow at the circuit level, module level, and die level to achieve load balancing and temperature balancing of at least one die. The control module can obtain multiple temperature values ​​of the data processing circuit to obtain the junction temperature of the data processing circuit, obtain the junction temperature of the data processing module through the junction temperature of the data processing circuit, and further obtain the junction temperature of the die. The control module then controls the amount of data that can be processed by the multiple dies through an adaptive temperature control mechanism. Controlling the amount of data that can be processed by the multiple dies can be achieved by controlling the amount of data that can be processed by the multiple data processing modules, and controlling the amount of data that can be processed by the multiple data processing modules can be achieved by controlling the amount of data that can be processed by the multiple data processing circuits.

[0132] Furthermore, the chip system provided in the embodiment of the present application can also simultaneously implement closed-loop control of temperature-power consumption-flow at the circuit level, module level, die level, and chip level. As shown in Figure 9, Figure 9 is a flowchart of a chip system provided in the embodiment of the present application. The process may include: S901, determining the flow of the first chip and the flow of the second chip based on the allocation criteria. S902, obtaining the junction temperature of the first data processing circuit, and obtaining the junction temperature of the first data processing module in the first time period based on the junction temperature. S903, determining whether the junction temperature is greater than the temperature control threshold, and obtaining the power consumption budget of the first data processing module in the second time period based on the junction temperature. If the junction temperature is greater than the temperature control threshold, execute S904; if the junction temperature is less than or equal to the temperature control threshold, execute S905. S904, obtain the amount of data that the first data processing module needs to reduce processing in the second time period based on the power consumption budget. S905, obtain the amount of data that the first data processing module needs to increase processing in the second time period based on the power consumption budget. S906, control the amount of data that the first data processing module can process in the second time period. S907. Obtain the junction temperature of the second data processing circuit, and obtain the junction temperature of the second data processing module in the first time period based on the junction temperature. S908. Determine whether the junction temperature is greater than the temperature control threshold, and obtain the power consumption budget of the second data processing module in the second time period based on the junction temperature. If the junction temperature is greater than the temperature control threshold, execute S909; if the junction temperature is less than or equal to the temperature control threshold, execute S9010. S909. Obtain the amount of data that needs to be reduced and processed by the second data processing module in the second time period based on the power consumption budget. S9010. Obtain the amount of data that needs to be increased and processed by the second data processing module in the second time period based on the power consumption budget. S9011. Control the amount of data that can be processed by the second data processing module in the second time period.

[0133] It is understandable that when the junction temperature of the chip exceeds the limit, the chip provided in the embodiment of the present application can avoid chip overheating through an adaptive temperature control mechanism, but this will cause chip performance to degrade. However, the negative impact of the performance degradation of a single chip can be offset by other chips in the chip system. Thus, for the entire chip system, load balancing and temperature balancing of the chip system are achieved, thereby improving the reliability, performance, and energy efficiency of the chip system. In addition, the design margin can also be reduced during the chip design phase to reduce design costs.

[0134] Embodiments of the present application also provide a control method, which is applied to a chip comprising at least one control module and at least one data processing module. The method includes: the control module obtaining a junction temperature of the at least one data processing module during a first time period, and obtaining a power consumption budget of the at least one data processing module during a second time period based on the junction temperature. Based on the power consumption budget of the at least one data processing module, the control module controls the amount of data that can be processed by the at least one data processing module during the second time period.

[0135] An embodiment of the present application further provides a computer storage medium storing computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the control method in the above-mentioned embodiment.

[0136] An embodiment of the present application further provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the above-mentioned related steps to implement the control method executed by the electronic device in the above-mentioned embodiment.

[0137] In addition, an embodiment of the present application also provides a device, which can specifically be a chip, component or module, and the device may include a connected processor and memory; wherein the memory is used to store computer-executable instructions, and when the device is running, the processor can execute the computer-executable instructions stored in the memory to enable the chip to execute the control method executed by the electronic device in the above-mentioned method embodiments.

[0138] Among them, the chip, chip system, computer storage medium, computer program product or chip provided in this embodiment is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above, and will not be repeated here.

[0139] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0140] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0141] The units described as separate components may or may not be physically separate, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0142] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0143] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0144] The above content is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A chip, characterized in that: including at least one control module and at least one data processing module, The control module is configured to obtain a junction temperature of the at least one data processing module in a first time period, and obtain a power consumption budget of the at least one data processing module in a second time period based on the junction temperature; The control module is further configured to control the amount of data that can be processed by the at least one data processing module in the second time period based on the power consumption budget of the at least one data processing module.

2. The chip according to claim 1, characterized in that The at least one data processing module is at least one data processing circuit.

3. The chip according to claim 2, characterized in that The control module is specifically used for: obtaining a thermal margin of the at least one data processing circuit based on a junction temperature of the at least one data processing circuit and a temperature control threshold corresponding to the at least one data processing circuit; A power consumption budget of the at least one data processing circuit in the second time period is obtained based on the thermal margin calculation.

4. The chip according to claim 2 or 3, characterized in that: The chip further includes a plurality of temperature sensors, and the control module is specifically configured to: acquiring a plurality of temperature values ​​of the at least one data processing circuit transmitted by the plurality of temperature sensors; The multiple temperature values ​​are processed based on a temperature reconstruction algorithm to obtain a junction temperature of the at least one data processing circuit during the first time period.

5. The chip according to any one of claims 2 to 4, characterized in that: The control module is specifically used for: Based on the power consumption budget of each data processing circuit, the amount of data that can be processed by the plurality of data processing circuits during the second time period is controlled.

6. The chip according to claim 1, characterized in that Each of the at least one data processing module includes at least one data processing circuit.

7. The chip according to claim 6, characterized in that The control module is specifically used for: The junction temperature of the at least one data processing circuit is acquired, and the junction temperature of the at least one data processing module in the first time period is obtained based on the junction temperature.

8. The chip according to claim 6 or 7, characterized in that: The control module is specifically used for: Based on the power consumption budget of each data processing module, the amount of data that can be processed by the multiple data processing modules within the second time period is controlled.

9. The chip according to claim 8, characterized in that The control module is specifically used for: Based on the amount of data that each data processing module can process, the amount of data that can be processed by the at least one data processing circuit in the second time period is controlled.

10. The chip according to any one of claims 6 to 9, characterized in that: The control module is specifically used for: Obtaining a thermal margin of the at least one data processing module based on a junction temperature of the at least one data processing module and a temperature control threshold corresponding to the at least one data processing module; A power consumption budget of the at least one data processing module in the second time period is obtained based on the thermal margin calculation.

11. The chip according to claim 1, characterized in that The at least one data processing module is at least one bare chip, each bare chip includes at least one data processing circuit, or at least one data processing module, each data processing module includes at least one data processing circuit.

12. The chip according to claim 11, characterized in that The control module is further configured to obtain a junction temperature of the at least one die in a first time period, and obtain a power consumption budget of the at least one die in a second time period based on the junction temperature; The control module is further configured to control the amount of data that can be processed by the at least one die in the second time period based on the power consumption budget of the at least one die.

13. The chip according to claim 11 or 12, characterized in that: The control module is further configured to: A junction temperature of the at least one data processing module or the at least one data processing circuit is acquired, and a junction temperature of the at least one die during the first time period is obtained based on the junction temperature.

14. The chip according to any one of claims 11 to 13, characterized in that: The control module is specifically used for: Based on the power consumption budget of each die, the amount of data that can be processed by the plurality of die during the second time period is controlled.

15. The chip according to claim 14, characterized in that The control module is specifically used for: Based on the amount of data that each die can process, the amount of data that can be processed by the at least one data processing module or the at least one data processing circuit during the second time period is controlled.

16. The chip according to any one of claims 11 to 15, characterized in that: The control module is specifically used for: Obtaining a thermal margin of the at least one die based on a junction temperature of the at least one die and a temperature control threshold corresponding to the at least one die; A power consumption budget of the at least one die during the second time period is calculated based on the thermal margin.

17. The chip according to any one of claims 1 to 16, characterized in that: If the thermal margin is a positive value, increasing the amount of data that can be processed by the at least one data processing module in the second time period; If the thermal margin is a negative value, the amount of data that can be processed by the at least one data processing module in the second time period is reduced.

18. A chip system, characterized in that: The system comprises a first chip and a second chip, wherein the first chip comprises a first control module and a first data processing module, and the second chip comprises a second control module and a second data processing module; The first control module is configured to obtain a junction temperature of the first data processing module in a first time period, and obtain a power consumption budget of the first data processing module in a second time period based on the junction temperature; The first control module is further configured to control the amount of data that can be processed by the first data processing module in the second time period based on the power consumption budget of the first data processing module; the second control module being configured to obtain a junction temperature of the second data processing module in the first time period, and obtain a power consumption budget of the second data processing module in the second time period based on the junction temperature; The second control module is further configured to control the amount of data that can be processed by the second data processing module in the second time period based on the power consumption budget of the second data processing module.

19. The chip system according to claim 18, characterized in that: The first data processing module is a first data processing circuit, and the second data processing module is a second data processing circuit.

20. The chip system according to claim 18, characterized in that: The first data processing modules each include at least one first data processing circuit, and the second data processing modules each include at least one second data processing circuit.

21. The chip system according to claim 20, characterized in that: The first control module is specifically configured to: control the amount of data that can be processed by at least one first data processing circuit in the second time period based on the amount of data that can be processed by each first data processing module; The second control module is specifically configured to control the amount of data that can be processed by at least one second data processing circuit in the second time period based on the amount of data that can be processed by each second data processing module.

22. The chip system according to claim 18, characterized in that The first chip includes at least one first die, each first die includes at least one first data processing circuit, or at least one first data processing module, each first data processing module includes at least one first data processing circuit; The second chip includes at least one second die, each second die includes at least one second data processing circuit, or at least one second data processing module, each second data processing module includes at least one second data processing circuit.

23. The chip system according to claim 22, characterized in that: The first control module is specifically configured to: control the amount of data that can be processed by the at least one first data processing circuit or the at least one first data processing module in the second time period based on the amount of data that can be processed by each first die; The second control module is specifically configured to control the amount of data that can be processed by the at least one second data processing circuit or the at least one second data processing module in the second time period based on the amount of data that can be processed by each second die.

Images