Capacitor structure and preparation method therefor, and radio frequency device

Abstract

Provided in the present disclosure is a capacitor structure, comprising a substrate, and a first electrode, a dielectric layer and a second electrode, which are sequentially stacked on one side of the substrate in a direction away from the substrate, wherein at least one of the first electrode and the second electrode comprises a first sub-layer, a second sub-layer and a third sub-layer, which are sequentially stacked in the direction away from the substrate; the first sub-layer has a first edge portion; the third sub-layer has a second edge portion; and the first edge portion and the second edge portion overlap each other around the second sub-layer. Further provided in the present disclosure are a preparation method for the capacitor structure, and a radio frequency device.

Description

Capacitor structure and preparation method thereof and radio frequency device Technical Field

[0001] The embodiments of the present disclosure belong to the technical field of capacitor structures, and specifically relate to a capacitor structure, a preparation method thereof, and a radio frequency device. Background Art

[0002] With the continuous development of electronic technology, the integration level of active electronic components has been greatly improved, and the demand for passive components used with them has also increased accordingly. Electronic products are developing in the direction of miniaturization and micro-miniaturization. How to reduce the cost and space occupied by passive components while improving their performance has become one of the important issues that need to be solved urgently. Integrated Passive Devices (IPD) technology is a passive device integration technology based on semiconductor technology. Through semiconductor fine processing technology, passive components such as resistors, capacitors, and inductors can be integrated on glass or silicon substrates to achieve highly integrated and high-performance devices to meet certain functional requirements. System-in-a-Package (SiP) is a packaging technology that integrates RF passive components such as filters, couplers, and antennas composed of resistors and capacitors into a substrate through thin film lamination or other methods to form a packaged component with system functions. IPD technology is considered to be one of the effective ways to achieve SiP.

[0003] Metal-Insulator-Metal (MIM) capacitors are a typical passive component with advantages such as low parasitic capacitance and low electrode resistivity. With their unique performance advantages, they can be widely used in RF microwave, optical communications and other fields, and have broad application space in the future. Summary of the Invention

[0004] In a first aspect, an embodiment of the present disclosure provides a capacitor structure, comprising a substrate, and a first electrode, a dielectric layer, and a second electrode stacked sequentially on one side of the substrate in a direction away from the substrate;

[0005] At least one of the first electrode and the second electrode includes a first sublayer, a second sublayer, and a third sublayer stacked in sequence in a direction away from the substrate, wherein the first sublayer has a first edge portion, the third sublayer has a second edge portion, and the first edge portion and the second edge portion are stacked on each other around the second sublayer.

[0006] In some embodiments, the first sublayer has a first central portion, the third sublayer has a second central portion, the second sublayer completely covers the surface of the first central portion facing away from the substrate; the second central portion completely covers the surface and side of the second sublayer facing away from the substrate.

[0007] In some embodiments, a minimum distance between an orthographic projection outline of the first edge portion and the second edge portion on the substrate and an orthographic projection outline of the second sub-layer on the substrate is greater than or equal to 7 μm and less than or equal to 15 μm.

[0008] In some embodiments, an angle between a side surface of the second sublayer in the first electrode and a surface of the second sublayer close to the substrate is greater than or equal to 20° and less than or equal to 45°.

[0009] In some embodiments, an angle between a side surface of the second sublayer in the second electrode and a surface of the second sublayer close to the substrate is greater than or equal to 10° and less than or equal to 30°.

[0010] In some embodiments, the dielectric layer includes a third central portion and a third edge portion, wherein the third central portion completely covers the surface of the first electrode facing away from the substrate; and the third edge portion is located around the first electrode and overlaps the substrate.

[0011] In some embodiments, the orthographic projection of the second electrode on the substrate is located within the orthographic projection outline of the dielectric layer on the substrate;

[0012] The orthographic projection of the dielectric layer on the substrate is located within the orthographic projection outline of the first electrode on the substrate.

[0013] In some embodiments, the orthographic projection profiles of the second electrode, the dielectric layer, and the first electrode on the substrate are the same in shape and parallel to each other;

[0014] The distance between the orthographic projection outline of the second electrode on the substrate and the orthographic projection outline of the dielectric layer on the substrate is a first distance, the distance between the orthographic projection outline of the first electrode on the substrate and the orthographic projection outline of the dielectric layer on the substrate is a second distance, and the first distance is equal to the second distance.

[0015] In some embodiments, the first spacing and the second spacing are greater than or equal to 7 μm and less than or equal to 15 μm.

[0016] In some embodiments, the orthographic projection outlines of the second electrode, the dielectric layer, and the first electrode on the substrate include a rectangle or a rounded rectangle.

[0017] In some embodiments, the capacitor structure further includes a first flat layer and a connection structure provided on a side of the first flat layer facing away from the substrate, wherein the first flat layer at least covers a surface of the second electrode facing away from the substrate;

[0018] A first opening is formed in the first flat layer, wherein an orthographic projection of the first opening on the substrate is located within an orthographic projection outline of the second electrode on the substrate; the connecting structure contacts and is electrically connected to the second electrode through the first opening;

[0019] A surface material of a region of the second electrode exposed in the first opening is metal.

[0020] In some embodiments, an angle between a sidewall of the first opening and a surface of the second electrode facing away from the substrate is greater than or equal to 70° and less than or equal to 90°.

[0021] In some embodiments, a depth of the first opening is greater than or equal to 2 μm and less than or equal to 10 μm.

[0022] In some embodiments, a minimum radial dimension of the first opening is greater than or equal to 10 μm.

[0023] In some embodiments, the capacitor structure further includes a second planar layer, wherein the second planar layer is located between the first planar layer and the substrate;

[0024] A second opening is defined in the second planar layer, and the first electrode is located in the second opening.

[0025] In a second aspect, an embodiment of the present disclosure further provides a radio frequency device, which includes the above-mentioned capacitor structure provided by an embodiment of the present disclosure.

[0026] In a third aspect, an embodiment of the present disclosure further provides a method for preparing a capacitor structure, comprising: sequentially preparing on a substrate a first electrode, a dielectric layer, and a second electrode, which are sequentially stacked on one side of the substrate in a direction away from the substrate;

[0027] A method of preparing at least one of the first electrode and the second electrode comprises:

[0028] sequentially forming a first sub-layer film and a second sub-layer film stacked together;

[0029] performing a first patterning process on the second sub-layer film to form a second sub-layer;

[0030] forming a third sub-layer film; the third sub-layer film covers the second sub-layer and the area of ​​the first sub-layer film around the second sub-layer;

[0031] At the same time, the third sublayer film and the first sublayer film are subjected to a second patterning process to form a third sublayer and a first sublayer, wherein the first sublayer has a first edge portion, the third sublayer has a second edge portion, and the first edge portion and the second edge portion overlap each other around the second sublayer.

[0032] In some embodiments, it further includes:

[0033] forming a first planarization layer on the substrate having the first electrode, the dielectric layer, and the second electrode, wherein the first planarization layer at least covers a surface of the second electrode facing away from the substrate;

[0034] preparing a patterned mask layer on a side of the first planar layer facing away from the substrate;

[0035] dry-etching the first planarization layer through the mask layer to form a first opening;

[0036] removing the oxide layer of the region of the second electrode exposed in the first opening;

[0037] A connection structure is prepared on a side of the first planar layer facing away from the substrate, and the connection structure contacts and is electrically connected to the second electrode through the first opening.

[0038] In some embodiments, the mask layer includes a metal hard mask layer or a PR photoresist. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed exemplary embodiments with reference to the accompanying drawings, in which:

[0040] FIG1 is a schematic cross-sectional view of the structure of a MIM capacitor in the related art.

[0041] [Corrected 21.05.2025 according to Rule 91] FIG2 is a schematic cross-sectional view of the structure of a method for preparing a MIM capacitor in the related art after completing step S1.

[0042] [Corrected 21.05.2025 according to Rule 91] FIG3 is a schematic cross-sectional view of the structure of a method for preparing a MIM capacitor in the related art after completing step S2.

[0043] [Corrected 21.05.2025 according to Rule 91] FIG4 is a schematic cross-sectional view of the structure of a method for preparing a MIM capacitor in the related art after completing step S3.

[0044] [Corrected 21.05.2025 according to Rule 91] FIG5 is a schematic cross-sectional view of the structure of a method for preparing a MIM capacitor in the related art after completing step S4.

[0045] [Corrected 21.05.2025 according to Rule 91] FIG6 is a schematic cross-sectional view of the structure of a method for preparing a MIM capacitor in the related art after completing step S5.

[0046] [Corrected 21.05.2025 according to Rule 91] FIG7 is a schematic cross-sectional view of the structure of a method for preparing a MIM capacitor in the related art after completing step S6.

[0047] [Corrected 21.05.2025 according to Rule 91] FIG8 is a schematic cross-sectional view of the structure of a method for preparing a MIM capacitor in the related art after completing step S7.

[0048] [Corrected 21.05.2025 according to Rule 91] Figure 9 is a schematic cross-sectional view of a capacitor structure provided in an embodiment of the present disclosure.

[0049] [Corrected 21.05.2025 according to Rule 91] Figure 10 is a schematic cross-sectional view of the structure of the second electrode used in the embodiment of the present disclosure.

[0050] [Corrected 21.05.2025 according to Rule 91] Figure 11 is a schematic top view of the structure of the third sublayer of the second electrode used in the embodiment of the present disclosure.

[0051] [Corrected 21.05.2025 according to Rule 91] Figure 12 is a schematic top view of the structure of the second sublayer and the first sublayer of the second electrode used in the embodiment of the present disclosure.

[0052] [Corrected 21.05.2025 according to Rule 91] Figure 13 is a scanning electron microscope image of the second electrode in the embodiment of the present disclosure.

[0053] [Corrected 21.05.2025 according to Rule 91] Figure 14 is a schematic cross-sectional view of a portion of the structure of another capacitor structure provided in an embodiment of the present disclosure.

[0054] [Corrected 21.05.2025 according to Rule 91] FIG15 is a comparison diagram of the edge of the first electrode / second electrode used in an embodiment of the present disclosure and the edge of an electrode with edge serrations;

[0055] [Corrected 21.05.2025 according to Rule 91] Figure 16 is a schematic top view of a partial structure of a capacitor structure in an embodiment of the present disclosure.

[0056] [Corrected 21.05.2025 according to Rule 91] Figure 17 is a top view schematic diagram of another partial structure of the capacitor structure in an embodiment of the present disclosure.

[0057] [Corrected 21.05.2025 according to Rule 91] Figure 18 is a schematic cross-sectional view of a portion of the structure of another capacitor structure provided in an embodiment of the present disclosure.

[0058] [Corrected 21.05.2025 in accordance with Rule 91] FIG19 is a flow chart of a method for preparing a capacitor structure according to an embodiment of the present disclosure;

[0059] [Corrected 21.05.2025 according to Rule 91] FIG20 is a schematic cross-sectional view of the structure of the capacitor structure preparation method provided in an embodiment of the present disclosure after completing step S101.

[0060] [Corrected 21.05.2025 according to Rule 91] FIG21 is a schematic cross-sectional view of the structure of the capacitor structure preparation method provided in an embodiment of the present disclosure after completing step S102.

[0061] [Corrected 21.05.2025 according to Rule 91] FIG22 is a schematic cross-sectional view of the structure of the capacitor structure preparation method provided in an embodiment of the present disclosure after completing step S103.

[0062] [Corrected 21.05.2025 according to Rule 91] FIG23 is a schematic cross-sectional view of the structure of the capacitor structure preparation method provided in an embodiment of the present disclosure after completing step S104.

[0063] [Corrected 21.05.2025 according to Rule 91] FIG24 is a schematic cross-sectional view of the structure of the capacitor structure preparation method provided in an embodiment of the present disclosure after completing step S105.

[0064] [Corrected 21.05.2025 according to Rule 91] FIG25 is a schematic cross-sectional view of the structure of the capacitor structure preparation method provided in an embodiment of the present disclosure after completing step S106.

[0065] [Corrected 21.05.2025 according to Rule 91] FIG26 is a schematic cross-sectional view of the structure of the capacitor structure preparation method provided in an embodiment of the present disclosure after completing step S107.

[0066] [Corrected 21.05.2025 according to Rule 91] FIG27 is a schematic cross-sectional view of the structure of the capacitor structure preparation method provided in an embodiment of the present disclosure after completing step S108.

[0067] [Corrected 21.05.2025 according to Rule 91] FIG28 is a schematic cross-sectional view of the structure of the capacitor structure preparation method provided in an embodiment of the present disclosure after completing step S109. DETAILED DESCRIPTION

[0068] To enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, a capacitor structure, a preparation method thereof, and a radio frequency device provided by the embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0069] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully enable those skilled in the art to understand the scope of this disclosure.

[0070] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate specific shapes of the regions, but are not intended to be limiting.

[0071] Referring to Figure 1 , the related art provides a miniaturized glass-based MIM (Metal Insulator Metal) capacitor for use in the field of radio frequency devices. The glass-based MIM capacitor includes a glass substrate 1, and a lower electrode 9, an intermediate dielectric layer 10, and an upper electrode 11, sequentially formed on one side of the glass substrate 1. The lower electrode 9, the intermediate dielectric layer 10, and the upper electrode 11 constitute the MIM capacitor. The glass substrate 1 further includes a first flat layer 12 formed on the surface of the side where the MIM capacitor is formed. The first flat layer 12 includes an opening, and the lower electrode 9 is located within the opening of the first flat layer 12. The first flat layer 12 further includes a second flat layer 13 formed on the surface facing away from the glass substrate 1. A portion of the second flat layer 13 covers the surface of the upper electrode 11 facing away from the glass substrate 1. Furthermore, the second flat layer 13 further includes a metal lead 14 formed on the surface facing away from the glass substrate 1. The upper electrode 11 is electrically connected to the metal lead 14 via a via 130 provided in the second flat layer 13, thereby achieving signal conduction between the upper electrode 11 and the metal lead 14.

[0072] The accuracy of MIM capacitors is mainly related to the fluctuation of the area S between the upper and lower electrodes of the capacitor and the thickness d of the intermediate dielectric layer. The calculation formula of the capacitor capacitance C can be expressed as:

[0073] Where S is the area of ​​the upper and lower electrodes of the capacitor, ε0 is the dielectric constant of vacuum, and ε r is the dielectric constant of the intermediate dielectric layer; d is the thickness of the intermediate dielectric layer.

[0074] Typically, the dielectric constant of the intermediate dielectric layer is primarily determined by the material and is selected based on the desired capacitance of the capacitor, resulting in minimal fluctuation. However, the facing area S between the upper and lower electrodes and the thickness d of the intermediate dielectric layer often fluctuate due to variations in equipment, process, and capacitor structural design, thus affecting capacitor processing accuracy. Therefore, controlling the facing area S and the thickness d of the intermediate dielectric layer is crucial.

[0075] With the continuous development of radio frequency, microwave, and optical communication devices, the size of capacitors continues to shrink, and the area of ​​their top electrodes has also decreased. However, this also places higher demands on capacitor performance, including capacitance consistency, operating frequency band, and loss. Therefore, how to ensure the consistency of the size of the capacitor's top electrode and form a via in the second planar layer that reliably connects to the top electrode have become urgent issues to be solved.

[0076] [Corrected 21.05.2025 according to Rule 91] Referring to Figures 2 to 8, the preparation of the MIM capacitor of the related art shown in Figure 1 mainly includes the following steps:

[0077] [Corrected 21.05.2025 according to Rule 91] Step S1: Referring to Figure 2, a patterned first flat layer 12 is formed on one side of the glass substrate 1.

[0078] In this step, a first planar layer 12 is first applied to one side of the glass substrate 1. A photolithography process is then performed to form a pattern of the first planar layer 12. The pattern has openings 120 for accommodating the lower electrode 9 in subsequent steps. The thickness of the first planar layer 12 after curing is generally between 2 μm and 10 μm.

[0079] [Corrected 21.05.2025 according to Rule 91] Step S2: Referring to FIG. 3 , the lower electrode 9 is formed at the opening 120 .

[0080] In this step, first, a Ti (titanium) layer and a Cu (copper) seed layer are sequentially prepared on the surface of the first flat layer 12 on the side away from the glass substrate 1 and the surface in the opening 120; wherein the thickness of the Ti layer is 20nm to 200nm, and the thickness of the Cu seed layer is 100nm to 1000nm; then, a copper layer is formed (i.e., thickened) on the Cu (copper) seed layer by an electroplating process; the thickness of the copper layer needs to be greater than the thickness of the first flat layer 12, generally 4μm to 12μm; then, the copper layer is polished by a chemical mechanical polishing (CMP) method, with the first flat layer 12 serving as a stop layer for the CMP, so as to remove the copper layer and the titanium seed layer on the surface of the first flat layer 12 on the side away from the glass substrate 1, leaving the copper layer filling the opening 120; then, a physical vapor deposition (PVD) method is used to deposit the copper layer. A titanium layer is deposited using a deposition process; the thickness of the titanium layer is between 20 nm and 200 nm. Finally, a single-step photolithography and etching process forms a pattern of the titanium layer on the side of the copper layer facing away from the glass substrate 1. This pattern only covers the surface of the copper layer, ultimately forming a lower electrode 9 comprising a Ti / Cu / Ti metal stack. The titanium layer on the side of the copper layer facing away from the glass substrate 1 primarily serves to enhance adhesion between the copper layer and the intermediate dielectric layer 10 (e.g., SiNx material) and prevent copper from diffusing into the intermediate dielectric layer 10. By first polishing the copper layer using CMP and then depositing the titanium layer, the titanium layer can be used to compensate for depressions and micro-scratches on the copper layer surface after the CMP process. It is readily understood that since the copper layer will develop micron-scale depressions after the CMP process, after the titanium layer is deposited, the surface of the titanium layer facing away from the glass substrate 1 may be flush with the surface of the first planarizing layer 12 facing away from the glass substrate 1, or it may be slightly lower than the first planarizing layer 12. Of course, the positional relationship between the surface of the titanium layer facing away from the glass substrate 1 and the surface of the first flat layer 12 facing away from the glass substrate 1 can be determined according to the specific process for preparing the lower electrode 9 .

[0081] [Corrected 21.05.2025 according to Rule 91] Step S3: Referring to FIG. 4 , an intermediate dielectric layer film 101 is formed by deposition.

[0082] In this step, an intermediate dielectric layer film 101 is formed on the surface of the first flat layer 12 facing away from the glass substrate 1 and the surface of the lower electrode 9 facing away from the glass substrate 1 through a coating process. The material of the intermediate dielectric layer film 101 can be a dielectric material such as SiNx, SiO2, AL2O3, etc., with a thickness of 0.1μm to 0.2μm.

[0083] [Corrected 21.05.2025 according to Rule 91] Step S4: Referring to FIG5 , the upper electrode 11 is formed.

[0084] In this step, a Ti / Cu / Ti (titanium / copper / titanium) metal stack is sequentially deposited on the surface of the intermediate dielectric layer film 101 facing away from the glass substrate 1 through a physical vapor deposition (PVD) process, and then a single photolithography, development, and wet etching process is performed to form the pattern of the upper electrode 11.

[0085] It should be noted that, in the subsequent process, the top layer of Ti metal in the upper electrode 11 will come into contact with air and water vapor, causing the Ti metal surface to oxidize and form TiO2. The TiO2 layer will cause the resistivity of the upper electrode 11 to increase, thereby resulting in greater loss of capacitor performance and poor reliability.

[0086] [Corrected 21.05.2025 according to Rule 91] Step S5: Referring to FIG. 6 , the intermediate dielectric layer film 101 is patterned to form the intermediate dielectric layer 10 .

[0087] In this step, the intermediate dielectric layer 10 is patterned by photolithography and dry etching processes.

[0088] [Corrected 21.05.2025 according to Rule 91] Step S6: Referring to FIG. 7 , a second planarization layer 13 is formed.

[0089] In this step, a second planar layer is first formed on the surface of the first planar layer 12 facing away from the glass substrate 1 and on the surface of the top electrode 11 facing away from the glass substrate 1 by spin coating. The portion of the second planar layer covering the surface of the top electrode 11 facing away from the glass substrate 1 (i.e., the portion where the orthographic projection of the second planar layer on the glass substrate 1 overlaps with the orthographic projection of the top electrode 11 on the glass substrate 1) has a thickness of 2 μm to 10 μm. Then, a patterned second planar layer 13 is formed by photolithography and development. The second planar layer 13 has vias 130. The diameters of the vias 130 at different axial locations generally range from 15 μm to 100 μm. For example, the opening diameter of the via 130 near the top electrode 11 is 15 μm, while the opening diameter of the via 130 away from the top electrode 11 is 100 μm.

[0090] [Corrected 21.05.2025 according to Rule 91] Step S7: Referring to FIG. 8 , metal leads 14 are formed.

[0091] In this step, a Ti (titanium) layer and a Cu (copper) seed layer are first deposited sequentially on the surface of the second planar layer 13 facing away from the glass substrate 1 using a physical vapor deposition (PVD) process. Then, a copper layer is deposited (i.e., thickened) using electroplating. Finally, photolithography, development, and wet etching processes are used to form the pattern of the metal lead 14. The metal lead 14 is connected to the top electrode 11 through a via 130 in the second planar layer 13, enabling signal conduction between the top electrode 11 and the metal lead 14.

[0092] In the above-mentioned related art, the upper electrode 11 of the MIM capacitor is made of a Ti / Cu / Ti metal stack and patterned by wet etching. However, this process has the following problems:

[0093] On the one hand, the patterning of the Ti / Cu / Ti metal stack is achieved through a single photolithography, development and wet etching process. Since the underlying Ti metal is thinner than the Cu metal, the etching rates of the two are not matched, and the underlying Ti metal is very prone to side etching, resulting in abnormal size and morphology of the upper electrode 11, which in turn affects the consistency of the capacitor.

[0094] On the other hand, the via 130 for realizing electrical connection between the upper electrode 11 and the metal lead 14 is usually prepared by photolithography and development technology. The slope angle θ1 of the formed via 130 (as shown in Figure 1) is too gentle (θ1 is less than 50°), resulting in a smaller bottom diameter of the via 130 and insufficient contact area between the upper electrode 11 and the metal lead 14. This not only limits the minimum size of the capacitor, but also affects its performance.

[0095] Furthermore, the top layer of metal Ti in the upper electrode 11 is easily oxidized during the process to form titanium oxide (TiO2). Titanium oxide has a high resistivity and poor conductivity, which increases the contact resistance between the upper electrode 11 and the metal lead 14, resulting in increased capacitor performance loss. Furthermore, the oxidation of the metal Ti at the bottom of the via 130 can also reduce the overlap adhesion between the upper electrode 11 and the metal lead 14, affecting the connection reliability of the capacitor.

[0096] To address at least one of the aforementioned issues in the related art, in a first aspect, referring to FIG. 3 a , an embodiment of the present disclosure provides a capacitor structure comprising a substrate 20, and a first electrode 2, a dielectric layer 3, and a second electrode 4 sequentially stacked on one side of the substrate 20 in a direction away from the substrate 20. The orthographic projections of the first electrode 2, the dielectric layer 3, and the second electrode 4 on the substrate 20 at least partially overlap to form a MIM capacitor. At least one of the first electrode 2 and the second electrode 4 comprises a first sublayer, a second sublayer, and a third sublayer sequentially stacked in a direction away from the substrate 20, wherein the first sublayer has a first edge portion, the third sublayer has a second edge portion, and the first edge portion and the second edge portion overlap each other around the second sublayer.

[0097] [Corrected 21.05.2025 in accordance with Rule 91] In some examples, as shown in Figures 10 to 12, the second electrode 4 includes a first sublayer 41, a second sublayer 42, and a third sublayer 43, stacked in sequence in a direction away from the substrate 20. The first sublayer 41 has a first edge portion 411, and the third sublayer 43 has a second edge portion 431. The first edge portion 411 and the second edge portion 431 overlap each other around the second sublayer 42. In this example, the first electrode 2 includes, for example, a fourth sublayer 21, a fifth sublayer 22, and a sixth sublayer 23, stacked in sequence in a direction away from the substrate 20. The orthographic projections of the fourth sublayer 21, the fifth sublayer 22, and the sixth sublayer 23 on the substrate 20 completely overlap. In other words, the structure of the metal stack included in the first electrode 2 differs from the aforementioned structure of the metal stack included in the second electrode 4. However, the embodiments of the present disclosure are not limited thereto. In other examples, the structure of the metal stack included in the first electrode 2 may also be the same as the above-mentioned structure of the metal stack included in the second electrode 4, as shown in FIG14 . Alternatively, the metal stack included in the first electrode 2 may adopt the above-mentioned structure including the first sublayer 41, the second sublayer 42, and the third sublayer 43, while the metal stack included in the second electrode 4 may adopt another structure, for example, the same structure as the metal stack including the fourth sublayer 21, the fifth sublayer 22, and the sixth sublayer 23.

[0098] It should be noted that the first edge portion 411 and the second edge portion 431 overlap each other around the second sub-layer 42, which means that the orthographic projections of the first edge portion 411 and the second edge portion 431 on the substrate 20 are outside the orthographic projection outline of the second sub-layer 42 on the substrate 20, and the orthographic projections of the first edge portion 411 and the second edge portion 431 on the substrate 20 at least partially overlap.

[0099] [Corrected on 21.05.2025 according to Rule 91] Compared with the related art in which the patterning of the Ti / Cu / Ti metal stack is achieved by a single photolithography, development and wet etching process, the embodiment of the present disclosure can adopt two patterning processes to achieve the patterning of the Ti / Cu / Ti metal stack by overlapping the first edge portion 411 of the first sub-layer 41 and the second edge portion 431 of the third sub-layer 43 around the second sub-layer 42, that is, firstly, the stacked first sub-layer film and the second sub-layer film are formed in sequence; then the second sub-layer film is subjected to a first patterning process to form the second sub-layer 42; then the third sub-layer film is formed; the third sub-layer film covers the second sub-layer 42 and the first sub-layer film in the area around the second sub-layer 42; then the third sub-layer film and the first sub-layer film are simultaneously subjected to a second patterning process to form the third sub-layer 43 and the first sub-layer 41. That is to say, the embodiment of the present disclosure can improve the method of preparing at least one of the first electrode 2 and the second electrode 4 by making the first edge portion 411 of the first sublayer 41 and the second edge portion 431 of the third sublayer 43 overlap each other around the second sublayer 42, so as to optimize the stacked structure morphology included in the electrode, improve the size consistency of the stacked structure, and thus improve the capacitance consistency of the capacitor structure. The reason why the above-mentioned method improved by the embodiment of the present disclosure can achieve such an effect is that: the two-patterning process adopted can separate the patterning of the Cu layer from the patterning of the two Ti layers, thereby avoiding the side etching problem of the bottom Ti layer caused by the mismatch of the etching rates of Cu and Ti in the Ti / Cu / Ti layer. Moreover, the thickness of the two Ti layers is increased compared to the etching of a single Ti layer, which can more accurately control the etching rate. At the same time, the sawtooth effect of the electrode edge can be avoided (as shown in the left figure in Figure 15), thereby optimizing the stacked structure morphology of the electrode, thereby improving the size consistency of the stacked structure, improving the capacitance consistency of the capacitor structure, and optimizing the electrical performance of the capacitor structure. The dimensional consistency here can be the consistency of the critical dimension (CD), specifically referring to the dimensions (such as width, length, etc.) of the upper electrode and / or lower electrode of the capacitor structure being highly consistent in different locations and during different batches of manufacturing, thereby reducing the capacitance fluctuation of the capacitor structure and improving device performance and reliability. The capacitor structure provided by the embodiment of the present disclosure has the advantages of low insertion loss (referring to inserting the capacitor structure into the RF circuit), high integration, high reliability, etc., which can achieve better electrical performance and match the development trend of RF products.

[0100] In this embodiment, the fourth sublayer 21, the fifth sublayer 22, and the sixth sublayer 23 included in the first electrode 2 are Ti / Cu / Ti layers, respectively; the first sublayer 41, the second sublayer 42, and the third sublayer 43 included in the second electrode 4 are Ti / Cu / Ti layers, respectively. The Ti metal can enhance the adhesion between the Cu metal and the substrate 20 or the dielectric layer 3, thereby preventing the Cu metal from peeling off or falling off during subsequent processes (such as photolithography, etching, chemical mechanical polishing, etc.), thereby improving the stability and reliability of the device. At the same time, the Ti layer can also act as a diffusion barrier to prevent the Cu metal from diffusing into the dielectric layer 3 or other materials, thereby helping to maintain the integrity and performance stability of the capacitor structure. The Ti layer can also protect the Cu metal from oxidation or corrosion. For example, the top layer of Ti metal can prevent the Cu metal from being exposed to air and oxidized during subsequent processes (such as via formation, metal lap joints, etc.). In addition, the Ti layer can form an electrode together with the Cu layer to improve the overall electrical performance of the electrode. For example, the Ti layer can reduce the resistivity of the electrode and reduce the series resistance (ESR) of the capacitor, thereby improving the Q value and high-frequency performance of the capacitor. Of course, in practical applications, the stacked structure of the electrode used in the embodiment of the present disclosure is also applicable to stacked structures of other different materials.

[0101] [Corrected 21.05.2025 in accordance with Rule 91] On this basis, in order to enable the first sublayer 41 and the third sublayer 43 (both, for example, Ti metal) to better perform the aforementioned functions (including enhancing adhesion, preventing diffusion, providing protection, and improving electrical properties), as shown in Figures 10 to 12 , the first sublayer 41 has a first central portion 412, and the third sublayer 43 has a second central portion 432. The second sublayer 42 completely covers the surface of the first central portion 412 facing away from the substrate 20, i.e., the orthographic projection of the second sublayer 42 on the substrate 20 completely overlaps with the orthographic projection of the first central portion 412 on the substrate 20. The second central portion 432 completely covers the surface and side surfaces of the second sublayer 42 facing away from the substrate 20, i.e., the orthographic projection of the second sublayer 42 on the substrate 20 completely overlaps with the orthographic projection of the second central portion 432 on the substrate 20. In this way, the first sublayer 41 and the third sublayer 43 can completely enclose the second sublayer 42, thereby better performing the aforementioned functions. It should be noted that in actual applications, according to specific needs, the second sub-layer 42 can partially cover the surface of the first central part 412 away from the substrate 20, and / or the second central part 432 can partially cover the surface and side of the second sub-layer 42 away from the substrate 20. The embodiments of the present disclosure are not limited to this.

[0102] In some embodiments, in order to ensure the alignment of the photolithography of the first sub-layer 41 and the third sub-layer 43 with the photolithography of the second sub-layer 42, and at the same time minimize the footprint of the capacitor, the minimum distance between the orthographic outline of the first edge portion 411 and the second edge portion 431 on the substrate 20 and the orthographic outline of the second sub-layer 42 on the substrate 20 is greater than or equal to 7 μm and less than or equal to 15 μm, preferably 10 μm.

[0103] [Corrected 21.05.2025 according to Rule 91] In a specific embodiment, as shown in Figures 9, 10, and 12, the orthographic projection contours of the first edge portion 411 and the second edge portion 431 on the substrate 20 coincide with each other. In this case, the distance between the orthographic projection contours of the first edge portion 411 and the second edge portion 431 on the substrate 20 and the orthographic projection contour of the second sub-layer 42 on the substrate 20 is the same. The distance L between the orthographic projection contours of the first edge portion 411 and the second edge portion 431 on the substrate 20 and the orthographic projection contour of the second sub-layer 42 on the substrate 20 is the same everywhere. In addition, the orthographic projection contours of the first edge portion 411 and the second edge portion 431 on the substrate 20 and the orthographic projection contour of the second sub-layer 42 on the substrate 20 have the same shape, for example, a polygon such as a rectangle, a square, or a rounded polygon, a circle, an ellipse, or an irregular shape.

[0104] [Corrected 21.05.2025 according to Rule 91] In some embodiments, for the case where the second electrode 4 includes a first sublayer 41, a second sublayer 42, and a third sublayer 43, as shown in Figures 9 and 10, the angle θ between the side surface of the second sublayer 42 and the surface of the second sublayer 42 on the side close to the substrate 20 is greater than or equal to 20° and less than or equal to 45°, for example, 20°. That is, the side surface of the second sublayer 42 is a sloped surface, and by selecting the size of the angle θ within the above range, the slope coverage of the third sublayer 43 can be effectively ensured during the process of preparing the third sublayer 43, thereby avoiding the process defect of discontinuous slope of the third sublayer 43. Figure 13 is a scanning electron microscope image of the second electrode 4 in the embodiment of the present disclosure. As can be seen from Figure 13, the angle θ is 20°.

[0105] [Corrected 21.05.2025 in accordance with Rule 91] In some embodiments, where the first electrode 2 includes a first sublayer 41, a second sublayer 42, and a third sublayer 43, as shown in FIG14 , the angle β between the side surface of the second sublayer 42 in the first electrode 2 and the surface of the second sublayer 42 on the side closest to the substrate 20 is greater than or equal to 10° and less than or equal to 30°. That is, the side surface of the second sublayer 42 in the first electrode 2 is a sloped surface, and by selecting the angle β within the above range, the slope coverage of the third sublayer 43 in the first electrode 2 can be effectively ensured during the process of preparing the third sublayer 43, thereby avoiding process defects such as discontinuous slope of the third sublayer 43. It should be noted that, as shown in Figure 14, when the second electrode 4 and the first electrode 2 both include a first sublayer 41, a second sublayer 42 and a third sublayer 43, since the size of each sublayer of the first electrode 2 is larger than the size of the corresponding sublayer of the second electrode 4, the angle β of the first electrode 2 can be smaller than the angle θ of the second electrode 4, but the embodiments of the present disclosure are not limited to this.

[0106] [Corrected 21.05.2025 according to Rule 91] In the embodiments shown in Figures 9 and 14, the dielectric layer 3 partially covers the surface of the first electrode 2 on the side facing away from the substrate 20, for example, only covers the central area of ​​the surface of the first electrode 2 on the side facing away from the substrate 20, that is, the orthographic projection of the dielectric layer 3 on the substrate 20 is located within the orthographic projection of the edge of the surface of the first electrode 2 on the side facing away from the substrate 20 on the substrate 20. In this case, as shown in Figures 16 and 17, in some embodiments, the orthographic projection of the second electrode 4 on the substrate 20 is located within the outline of the orthographic projection of the dielectric layer 3 on the substrate 20; the orthographic projection of the dielectric layer 3 on the substrate 20 is located within the outline of the orthographic projection of the first electrode 2 on the substrate 20. In actual manufacturing processes, it is difficult to achieve completely accurate alignment of the upper electrode, dielectric layer, and lower electrode of the capacitor, and there will always be a certain amount of alignment deviation (overlay). In order to ensure that the effective area of ​​the capacitor remains consistent and reduce the difficulty of alignment during the process, the first electrode 2, dielectric layer 3, and second electrode 4 of the embodiment of the present disclosure form a stepped stacked structure. By adopting this structure, a certain process margin can be reserved for the alignment process, so that even in the presence of alignment deviation, the effective area of ​​the capacitor can remain relatively stable, thereby improving the process stability and consistency of the capacitor.

[0107] [Corrected 21.05.2025 in accordance with Rule 91] Furthermore, in some embodiments, the orthographic projections of the second electrode 4, dielectric layer 3, and first electrode 2 on the substrate 20 have the same shape and are parallel to each other. For example, as shown in Figures 16 and 17, the orthographic projections of the second electrode 4, dielectric layer 3, and first electrode 2 on the substrate 20 are rectangular or rounded. In this case, the orthographic projections of the second electrode 4, dielectric layer 3, and first electrode 2 on the substrate 20 each have four sides, which are parallel to each other in a one-to-one correspondence.

[0108] In one specific embodiment, the spacing between the orthographic projection of the second electrode 4 on the substrate 20 and the orthographic projection of the dielectric layer 3 on the substrate 20 is a first spacing n1, and the spacing between the orthographic projection of the first electrode 2 on the substrate 20 and the orthographic projection of the dielectric layer 3 on the substrate 20 is a second spacing n2, with the first spacing n1 being equal to the second spacing n2. By making the first spacing n1 equal to the second spacing n2, process control can be more easily achieved. Under high-frequency signals, the electric fields formed by the first electrode 2 and the second electrode 4 with respect to the intermediate dielectric layer 3 are made symmetrical, which further helps to improve the polarization of the dielectric layer and reduce leakage. Of course, in actual applications, the first spacing n1 and the second spacing n2 can also be unequal according to specific needs.

[0109] In some embodiments, to reserve sufficient process tolerance, the first interval n1 and the second interval n2 are greater than or equal to 3 μm.

[0110] [Corrected 21.05.2025 in accordance with Rule 91] In other embodiments, as shown in FIG18 , the dielectric layer 3 includes a third central portion 32 and a third edge portion 31. The third central portion 32 completely covers the surface of the first electrode 2 facing away from the substrate 20, i.e., the orthographic projection of the third central portion 32 on the substrate 20 completely overlaps with the orthographic projection of the first electrode 2 on the substrate 20. The third edge portion 31 is located around the first electrode 2 and overlaps the substrate 20. This dielectric layer 3 structure can wrap around the first electrode 2, i.e., it covers not only the surface of the first electrode 2 facing away from the substrate 20 but also the side surfaces of the first electrode 2, thereby better protecting the first electrode 2. Furthermore, by setting the angle β between the side surface of the second sublayer 42 in the first electrode 2 and the surface of the second sublayer 42 closer to the substrate 20, for example, setting the angle β to be greater than or equal to 10° and less than or equal to 30°, the dielectric layer 3 can effectively ensure slope coverage during the fabrication process, avoiding process defects such as slope discontinuities, thereby improving device reliability. In addition, in some embodiments, in order to enable the first sublayer 41 and the third sublayer 43 (for example, both are Ti metal) to better play the above-mentioned roles (including enhancing adhesion, preventing diffusion, protective effects and improving electrical properties, etc.), the ratio of the thickness a of the first sublayer 41 of the first electrode 2 to the maximum value b of the total thickness of the first electrode 2 is greater than or equal to 0.1 and less than or equal to 0.2.

[0111] [Corrected 21.05.2025 in accordance with Rule 91] In some embodiments, as shown in FIG9 , the capacitor structure further includes a first planar layer 5 and a connection structure 6 disposed on a side of the first planar layer 5 facing away from the substrate 20. The first planar layer 5 at least covers the surface of the second electrode 4 facing away from the substrate 20. A first opening 50 is defined in the first planar layer 5. The orthographic projection of the first opening 50 on the substrate 20 lies within the orthographic projection of the second electrode 4 on the substrate 20. The connection structure 6 contacts and is electrically connected to the second electrode 4 through the first opening 50. The connection structure 6 can serve as a signal lead for the capacitor structure.

[0112] In some embodiments, connection structure 6 includes a seventh sublayer 61 and an eighth sublayer 62 stacked sequentially on first planar layer 5 in a direction away from substrate 20. Seventh sublayer 61 and eighth sublayer 62 are, for example, a titanium layer and a copper layer, respectively. The titanium layer is used to enhance adhesion between the copper layer and second electrode 4 and first planar layer 5, thereby improving device reliability.

[0113] [Corrected 21.05.2025 according to Rule 91] On this basis, the surface material of the area where the second electrode 4 is exposed in the first opening 50 is metal. In this way, the contact resistance between the connecting structure 6 and the second electrode 4 at the bottom of the first opening 50 can be reduced, and the adhesion between the connecting structure 6 and the second electrode 4 at the bottom of the first opening 50 can be increased, thereby effectively improving the performance and reliability of the capacitor structure. It should be noted that the top metal (such as Ti) in the second electrode 4 is easily oxidized to form metal oxides, such as titanium oxide (TiO2) during the process, which is difficult to avoid during the process. Since the resistivity of the metal oxide is relatively large and the conductivity is poor, this will increase the contact resistance between the second electrode 4 and the connecting structure 6, and at the same time reduce the adhesion between the connecting structure 6 and the second electrode 4 at the bottom of the first opening 50, affecting the connection reliability of the capacitor. Based on this, the surface material of the area where the second electrode 4 is exposed in the first opening 50 used in the embodiment of the present disclosure can be a metal material obtained after removing the metal oxide. Of course, in actual applications, the second electrode 4 can also adopt other methods or other structures to achieve that the surface material of the area where the second electrode 4 is exposed in the first opening 50 is metal. It is easy to understand that, as shown in Figure 9, the metal oxide in the area of ​​the second electrode 4 exposed in the first opening 50 is removed, and the surface material of the other areas of the second electrode 4 outside the first opening 50 is metal oxide 44, which is generated by the oxidation of the top metal (i.e., the third sublayer 43) in the second electrode 4 due to contact with air and water vapor.

[0114] In some embodiments, an angle α between a sidewall of the first opening 50 and a surface of the second electrode 4 facing away from the substrate 20 is greater than or equal to 70° and less than or equal to 90°.

[0115] With this arrangement, compared to the situation in which the via slope angle θ1 (as shown in FIG1 ) in the second flat layer in the related art is too gentle, the embodiment of the present disclosure can effectively solve the problem of the via bottom diameter becoming smaller in the related art by increasing the angle α, thereby increasing the bottom diameter size of the first opening 50, thereby increasing the contact area between the connection structure 6 and the second electrode 4 at the bottom of the first opening 50, thereby improving the stability and reliability of the connection. The above-mentioned angle α can effectively increase the contact area between the connection structure 6 and the second electrode 4 by adopting an angle range of greater than or equal to 70° and less than or equal to 90°, thereby reducing the contact resistance between the connection structure 6 and the second electrode 4, thereby effectively improving the performance of the capacitor structure.

[0116] In some embodiments, the surface of the connection structure 6 facing away from the substrate 20 is parallel to the substrate 20, and the distance h1 between the surface of the connection structure 6 facing away from the substrate 20 and the substrate 20 is greater than the distance h2 between the surface of the first flat layer 5 facing away from the substrate 20 and the substrate 20.

[0117] In some embodiments, in the second electrode 4 , the thicknesses of the first sublayer 41 and the third sublayer 43 are respectively in the range of 20 nm to 200 nm; the thickness of the second sublayer 42 is in the range of 200 nm to 1 μm; and the thickness of the metal oxide 44 of the second electrode 4 is in the range of 10 nm to 30 nm.

[0118] In some embodiments, the depth s of the first opening 50 ranges from 2 μm to 10 μm, and the radial dimension difference of the first opening 50 at different depth positions is less than 2 μm. With this arrangement, on the one hand, the precise control of the depth and radial dimension of the first opening 50 can ensure a reliable electrical connection between the second electrode 4 and the connecting structure 6. On the other hand, since the radial dimension difference of the first opening 50 at different depth positions is small, the angle α between its side wall and the surface of the second electrode 4 facing away from the substrate 20 can be in the range of 70° to 90°. The optimization of this angle range effectively solves the problem of the smaller bottom diameter of the via in the related art. By increasing the angle α, the bottom diameter of the first opening 50 is significantly increased, thereby significantly increasing the area of ​​the exposed second electrode 4 at the first opening 50, reducing the contact resistance, and further improving the performance and reliability of the device.

[0119] In this embodiment, the first opening 50 extends through the thickness of the portion of the first planar layer covering the surface of the second electrode 4 facing away from the substrate 20. This thickness is the depth of the first opening 50. In some embodiments, the depth of the first opening 50 is greater than or equal to 2 μm and less than or equal to 10 μm. On this basis, the radial dimensions of the first opening 50 at different depths are approximately equal.

[0120] Furthermore, in some embodiments, the minimum radial dimension of the first opening 50 is greater than or equal to 10 μm. Due to the limitation of the manufacturing process of the first opening 50, the radial dimension of the first opening 50 close to the second electrode 4 is the smallest, preferably 10 μm.

[0121] [Corrected 21.05.2025 according to Rule 91] In some embodiments, as shown in FIG9 , the capacitor structure further includes a second planar layer 7, which is located between the first planar layer 5 and the substrate 20. That is, the first planar layer 5 covers not only the surface of the second electrode 4 facing away from the substrate 20, but also the second planar layer 7, the dielectric layer 3, and the surface of the first electrode 2 facing away from the substrate 20. Furthermore, a second opening 70 is defined in the second planar layer 7, the first electrode 2 is located in the second opening 70, and the orthographic projections of the first electrode 2 and the second opening 70 on the substrate 20 coincide. Furthermore, the first electrode 2 includes a fourth sublayer 21, a fifth sublayer 22, and a sixth sublayer 23, which are stacked sequentially in a direction away from the substrate 20. The orthographic projections of the fourth sublayer 21, the fifth sublayer 22, and the sixth sublayer 23 on the substrate 20 completely coincide.

[0122] In some embodiments, the first sublayer 41 of at least one of the first electrode 2 and the second electrode 4 is made of titanium, the second sublayer 42 is made of copper, and the third sublayer 43 is made of titanium. The thickness of the second sublayer 42 is greater than the thickness of the first sublayer 41, and the thickness of the second sublayer 42 is greater than the thickness of the third sublayer 43.

[0123] In some embodiments, the first electrode 2 includes a fourth sublayer 21, a fifth sublayer 22, and a sixth sublayer 23 stacked in sequence in a direction away from the substrate 20, the fourth sublayer 21 is made of titanium metal, the fifth sublayer 22 is made of copper metal, and the sixth sublayer 23 is made of titanium metal. The thickness of the fifth sublayer 22 is greater than the thickness of the fourth sublayer 21, and the thickness of the fifth sublayer 22 is greater than the thickness of the sixth sublayer 23.

[0124] In some embodiments, the material of the dielectric layer 3 may be SiNx, SiO2, Al2O3 or the like, and the thickness of the dielectric layer 3 is 0.1 μm to 0.2 μm.

[0125] In some embodiments, the substrate 20 may be made of glass or silicon. The first flat layer 5 and the second flat layer 7 may be made of high molecular weight organic polymer materials, such as polyimide. The thickness of the second flat layer 7 is generally 2 μm to 10 μm.

[0126] Based on the above structure of the capacitor structure, the embodiment of the present disclosure also provides a method for preparing the capacitor structure, including: sequentially preparing a first electrode, a dielectric layer, and a second electrode on a substrate, which are sequentially stacked on one side of the substrate in a direction away from the substrate.

[0127] [Corrected 21.05.2025 according to Rule 91] Referring to FIG. 19 , a method of preparing at least one of the first electrode and the second electrode comprises:

[0128] S10, sequentially forming a first sub-layer film and a second sub-layer film stacked together;

[0129] S20, performing a first patterning process on the second sub-layer film to form a second sub-layer;

[0130] S30, forming a third sub-layer film; the third sub-layer film covers the second sub-layer and the area around the first sub-layer film;

[0131] S40. Perform a second patterning process on the third sublayer film and the first sublayer film at the same time to form a third sublayer and a first sublayer, wherein the first sublayer has a first edge portion, the third sublayer has a second edge portion, and the first edge portion and the second edge portion overlap each other around the second sublayer.

[0132] [Corrected 21.05.2025 according to Rule 91] Compared to the related art in which the patterning of the Ti / Cu / Ti metal stack is achieved through a single photolithography, development, and wet etching process, taking the preparation of the second electrode 4 shown in FIG9 as an example, the embodiment of the present disclosure adopts two patterning processes to achieve the patterning of the Ti / Cu / Ti metal stack, that is, first, a stacked first sub-layer film and a second sub-layer film are formed in sequence; then the second sub-layer film is subjected to a first patterning process to form a second sub-layer 42; then a third sub-layer film is formed; the third sub-layer film covers the second sub-layer 42 and the area around the first sub-layer film in the second sub-layer 42; then the third sub-layer film and the first sub-layer film are simultaneously subjected to a second patterning process to form a third sub-layer 43 and a first sub-layer 41. The above method can achieve the effect of optimizing the morphology of the stacked structure included in the electrode, improving the dimensional consistency of the stacked structure, and thereby improving the consistency of the capacitance value of the capacitor structure. This effect can be achieved because the two-patterning process can separate the patterning of the Cu layer from the patterning of the two Ti layers, thereby avoiding the problem of side etching of the bottom Ti layer due to the mismatch in the etching rates of Cu and Ti in the Ti / Cu / Ti layer. Moreover, the thickness of the two Ti layers is increased compared to the etching of a single Ti layer, which can more accurately control the etching rate. At the same time, the serration effect of the electrode edge can be avoided (as shown in the left figure in Figure 15), thereby optimizing the stacked structure morphology of the electrode, thereby improving the dimensional consistency of the stacked structure, improving the capacitance consistency of the capacitor structure, and optimizing the electrical performance of the capacitor structure. The dimensional consistency here can be the consistency of the critical dimension (Critical Dimension, referred to as CD), specifically referring to the size (such as width, length, etc.) of the upper electrode and / or lower electrode of the capacitor structure being highly consistent at different locations and in different batches of manufacturing processes, thereby reducing the capacitance fluctuation of the capacitor structure and improving device performance and reliability. The capacitor structure provided by the embodiment of the present disclosure has the advantages of low insertion loss (referring to inserting the capacitor structure into the radio frequency circuit), high integration, high reliability, etc., which can achieve better electrical performance and match the development trend of radio frequency products.

[0133] [Corrected 21.05.2025 according to Rule 91] Specifically, taking the second electrode 4 shown in FIG9 as an example, its preparation method is described in detail.

[0134] The method includes:

[0135] [Corrected 21.05.2025 according to Rule 91] S101. As shown in FIG20 , a first sub-layer film 410 and a second sub-layer film 420 are sequentially stacked on the surface of the dielectric layer 3 facing away from the substrate 20;

[0136] In the above step S101 , the first sub-layer film 410 and the second sub-layer film 420 may be deposited by a physical vapor deposition (PVD) process.

[0137] [Corrected 21.05.2025 according to Rule 91] S102, as shown in FIG21, performing a first patterning process on the second sub-layer film 420 to form the second sub-layer 42;

[0138] The first patterning process, for example, includes steps such as photoresist coating, exposure, development, and etching. Wet etching can be employed. The angle θ between the side of the second sublayer 42 formed after etching and the surface of the second sublayer 42 on the side closest to the substrate 20 is greater than or equal to 20° and less than or equal to 45°, for example, 20°. That is, the side of the second sublayer 42 is a sloped surface, and by selecting the angle θ within the aforementioned range, the slope coverage of the third sublayer 43 can be effectively ensured during the subsequent process of preparing the third sublayer 43, thereby avoiding process defects such as discontinuous slope coverage of the third sublayer 43.

[0139] [Corrected 21.05.2025 according to Rule 91] S103. As shown in FIG22 , a third sub-layer film 430 is formed; the third sub-layer film 430 covers the second sub-layer 42 and the area around the first sub-layer film 410;

[0140] In the above step S103 , a physical vapor deposition (PVD) process may be used to deposit the third sub-layer film 430 . The deposited third sub-layer film 430 and the first sub-layer film 410 together completely cover the second sub-layer 42 .

[0141] [Corrected 21.05.2025 according to Rule 91] S104. As shown in FIG23 , the third sub-layer film 430 and the first sub-layer film 410 are simultaneously subjected to a second patterning process to form a third sub-layer 43 and a first sub-layer 41, wherein, in conjunction with FIG10 , the first sub-layer 41 has a first edge portion 411, and the third sub-layer 43 has a second edge portion 431, and the first edge portion 411 and the second edge portion 431 overlap with each other around the second sub-layer 42.

[0142] In step S104, the second patterning process can process the third sub-layer film 430 and the first sub-layer film 410 together to form the patterns of the third sub-layer 43 and the first sub-layer 41. The second patterning process includes the steps of photoresist coating, exposure, development, and etching. The etching can be wet etching.

[0143] In step 104 , the surface of the second electrode 4 facing away from the substrate 20 is oxidized during the process to form a metal oxide 44 .

[0144] In some embodiments, the preparation method provided by the embodiments of the present disclosure further includes:

[0145] [Corrected 21.05.2025 according to Rule 91] S105. As shown in FIG24 , a first planarization layer 51 is formed on the substrate 20 having the first electrode 2, the dielectric layer 3, and the second electrode 4. The first planarization layer 51 covers at least the surface of the second electrode 4 facing away from the substrate 20.

[0146] The first planar layer film 51 can be prepared by coating.

[0147] [Corrected 21.05.2025 according to Rule 91] S106, as shown in FIG25, a patterned mask layer 8 is formed on the side of the first planarization layer 51 facing away from the substrate 20;

[0148] The mask layer 8, for example, includes a metal hard mask layer, which can be used as a mask for patterning the first flat layer film 51, and can also be used as a barrier layer in the subsequent step of removing the oxide layer of the second electrode 4. The material of the metal hard mask layer includes, for example, metals such as Al, Ti, Au, or metal nitrides such as TiN, TaN, etc. The thickness of the metal hard mask layer is, for example, greater than or equal to 500 nm and less than or equal to 1000 nm. The metal hard mask layer is usually prepared by metal-organic chemical vapor deposition (MOCVD, Metal-organic Chemical Vapor Deposition), physical vapor deposition (PVD, Physical Vapor Deposition) or atomic layer deposition (ALD, Atomic Layer Deposition), and then the metal hard mask layer is patterned by wet etching using a patterned photoresist (PR glue) to form a third opening pattern 80 in the metal hard mask layer.

[0149] [Corrected 21.05.2025 according to Rule 91] S107, as shown in FIG26, the first planarization layer 51 is dry-etched through the mask layer 8 to form a first planarization layer 5 having a first opening 50;

[0150] The pattern of the first planar layer 5 (having the first opening 50 ) is obtained by transferring the pattern of the mask layer 8 (having the third opening pattern 80 ).

[0151] By using the mask layer 8 to dry-etch the first flat layer film 51, the anisotropic characteristics of dry etching can be utilized to achieve a high-precision etching effect, and the radial dimension difference of the obtained first opening 50 at different depth positions is small (that is, an opening with steep sidewalls is formed). In some embodiments, the angle α between the sidewall of the first opening 50 and the surface of the second electrode 4 facing away from the substrate 20 is in the range of 70° to 90°. The optimization of this angle range effectively solves the problem of the smaller bottom diameter of the via hole in the related art. By increasing the angle α, the bottom diameter of the first opening 50 is significantly increased, thereby significantly increasing the area of ​​the exposed second electrode 4 at the first opening 50, reducing the contact resistance, and further improving the performance and reliability of the device. It should be noted that in the above step S107, the mask layer 8 should use a metal hard mask layer, which is an essential prerequisite for implementing the dry etching process.

[0152] [Corrected 21.05.2025 according to Rule 91] S108, as shown in FIG27 , removing the oxide layer 44 of the area of ​​the second electrode 4 exposed in the first opening 50;

[0153] The mask layer 8 serves as a barrier layer in this step. Plasma bombardment is performed on the second electrode 4 exposed at the first opening 50 through the third opening pattern 80 in the mask layer 8, thereby dry etching the oxide layer 44 (e.g., titanium oxide in the case of titanium) in the region of the second electrode 4 exposed in the first opening 50. The etching gas may be hydrogen or argon.

[0154] The metal oxide 44 is formed by oxidation of the top metal layer (i.e., the third sublayer 43) in the second electrode 4 due to contact with air and water vapor. Since the resistivity of the metal oxide is relatively large and the conductivity is poor, this will increase the contact resistance between the second electrode 4 and the connecting structure 6, and at the same time reduce the adhesion between the connecting structure 6 and the second electrode 4 at the bottom of the first opening 50, affecting the connection reliability of the capacitor. Based on this, through the above-mentioned step S108, the contact resistance between the connecting structure 6 and the second electrode 4 at the bottom of the first opening 50 can be reduced, and the adhesion between the connecting structure 6 and the second electrode 4 at the bottom of the first opening 50 can be increased, thereby effectively improving the performance and reliability of the capacitor structure.

[0155] In addition, after completing the above step S108, the mask layer 8 is removed. In some embodiments, the metal hard mask layer can be removed by a wet etching process.

[0156] [Corrected 21.05.2025 according to Rule 91] S109. As shown in FIG28 , a connection structure 6 is prepared on the side of the first planar layer 5 facing away from the substrate 20 . The connection structure 6 contacts and is electrically connected to the second electrode 4 through the first opening 50 .

[0157] In the above embodiment, the mask layer 8 uses a metal hard mask layer. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the mask layer 8 can also use a PR photoresist material with high etching resistance (a corrosion-resistant material whose solubility changes after exposure to light). The photolithography process used to prepare the pattern of the mask layer 8 (having the third opening pattern 80) includes the steps of exposure and development. The sidewalls of the prepared third opening pattern 80 are approximately perpendicular to the first flat layer film 51, and the first opening 50 with steep sidewalls can be formed through the third opening pattern 80. After completing the above step S108, the PR photoresist material can be removed by a degumming solution.

[0158] In some embodiments, the connection structure 6 includes a seventh sublayer 61 and an eighth sublayer 62 stacked sequentially on the first planar layer 5 in a direction away from the substrate 20. The seventh sublayer 61 and the eighth sublayer 62 are, for example, a titanium layer and a copper layer, respectively. The titanium layer is used to enhance the adhesion between the copper layer and the second electrode 4 and the first planar layer 5, thereby improving the reliability of the device. On this basis, the connection structure 6 can be prepared by first forming a titanium seed layer and a copper seed layer through a physical vapor deposition process; then thickening the copper layer through an additive electroplating process; and finally, forming the pattern of the connection structure 6 through photolithography, development, and wet etching processes. Since this composition process is a relatively mature traditional process, it will not be described in detail here.

[0159] In this embodiment, the preparation process of the first electrode 2 and the dielectric layer 3 is the same as that in the related art, and will not be described again here.

[0160] In a second aspect, an embodiment of the present disclosure further provides a radio frequency device, comprising the capacitor structure in the above embodiment.

[0161] By adopting the capacitor structure in the above embodiment, the performance of the radio frequency device can be improved.

[0162] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A capacitor structure, wherein: The method comprises a substrate, and a first electrode, a dielectric layer, and a second electrode sequentially stacked on one side of the substrate in a direction away from the substrate; At least one of the first electrode and the second electrode includes a first sublayer, a second sublayer, and a third sublayer stacked in sequence in a direction away from the substrate, wherein the first sublayer has a first edge portion, the third sublayer has a second edge portion, and the first edge portion and the second edge portion are stacked on each other around the second sublayer.

2. The capacitor structure according to claim 1, wherein: The first sublayer has a first central portion, the third sublayer has a second central portion, the second sublayer completely covers the surface of the first central portion facing away from the substrate; the second central portion completely covers the surface and side of the second sublayer facing away from the substrate.

3. The capacitor structure according to claim 1, wherein: A minimum distance between an orthographic projection outline of the first edge portion and the second edge portion on the substrate and an orthographic projection outline of the second sub-layer on the substrate is greater than or equal to 7 μm and less than or equal to 15 μm.

4. The capacitor structure according to claim 1, wherein: An angle between a side surface of the second sublayer in the first electrode and a surface of the second sublayer close to the substrate is greater than or equal to 20° and less than or equal to 45°.

5. The capacitor structure according to claim 1, wherein: An angle between a side surface of the second sublayer in the second electrode and a surface of the second sublayer close to the substrate is greater than or equal to 10° and less than or equal to 30°.

6. The capacitor structure according to any one of claims 1 to 5, wherein: The dielectric layer includes a third central portion and a third edge portion. The third central portion completely covers the surface of the first electrode facing away from the substrate. The third edge portion is located around the first electrode and overlaps the substrate.

7. The capacitor structure according to any one of claims 1 to 5, wherein: The orthographic projection of the second electrode on the substrate is located within the orthographic projection outline of the dielectric layer on the substrate; The orthographic projection of the dielectric layer on the substrate is located within the orthographic projection outline of the first electrode on the substrate.

8. The capacitor structure according to claim 7, wherein: The orthographic projection profiles of the second electrode, the dielectric layer, and the first electrode on the substrate are identical in shape and parallel to each other; The distance between the orthographic projection outline of the second electrode on the substrate and the orthographic projection outline of the dielectric layer on the substrate is a first distance, the distance between the orthographic projection outline of the first electrode on the substrate and the orthographic projection outline of the dielectric layer on the substrate is a second distance, and the first distance is equal to the second distance.

9. The capacitor structure according to claim 8, wherein: The first interval and the second interval are greater than or equal to 7 μm and less than or equal to 15 μm.

10. The capacitor structure according to claim 8, wherein: The orthographic projection contours of the second electrode, the dielectric layer, and the first electrode on the substrate include a rectangle or a rounded rectangle.

11. The capacitor structure according to claim 1, wherein: The capacitor structure further includes a first flat layer and a connection structure provided on a side of the first flat layer facing away from the substrate, wherein the first flat layer at least covers a surface of the second electrode facing away from the substrate; A first opening is formed in the first flat layer, wherein an orthographic projection of the first opening on the substrate is located within an orthographic projection outline of the second electrode on the substrate; the connecting structure contacts and is electrically connected to the second electrode through the first opening; A surface material of a region of the second electrode exposed in the first opening is metal.

12. The capacitor structure according to claim 11, wherein: An angle between a sidewall of the first opening and a surface of the second electrode facing away from the substrate is greater than or equal to 70° and less than or equal to 90°.

13. The capacitor structure according to claim 11, wherein: The depth of the first opening is greater than or equal to 2 μm and less than or equal to 10 μm.

14. The capacitor structure according to claim 11, wherein: The minimum radial dimension of the first opening is greater than or equal to 10 μm.

15. The capacitor structure according to claim 1, wherein: The capacitor structure further includes a second flat layer, wherein the second flat layer is located between the first flat layer and the substrate; A second opening is defined in the second planar layer, and the first electrode is located in the second opening.

16. A radio frequency device, wherein: The capacitor structure comprises any one of claims 1-15.

17. A method for preparing a capacitor structure, wherein: include: On a substrate, a first electrode, a dielectric layer, and a second electrode are sequentially prepared and stacked on one side of the substrate in a direction away from the substrate; A method of preparing at least one of the first electrode and the second electrode comprises: sequentially forming a first sub-layer film and a second sub-layer film stacked together; performing a first patterning process on the second sub-layer film to form a second sub-layer; forming a third sub-layer film; the third sub-layer film covers the second sub-layer and the area of ​​the first sub-layer film around the second sub-layer; At the same time, a second patterning process is performed on the third sub-layer film and the first sub-layer film to form a third sub-layer and a first sub-layer, wherein the first sub-layer has a first edge portion, the third sub-layer has a second edge portion, and the first edge portion and the second edge portion overlap each other around the second sub-layer.

18. The method for preparing a capacitor structure according to claim 17, wherein: Also includes: forming a first planarization layer on the substrate having the first electrode, the dielectric layer, and the second electrode, wherein the first planarization layer at least covers a surface of the second electrode facing away from the substrate; preparing a patterned mask layer on a side of the first planar layer facing away from the substrate; dry-etching the first planarization layer through the mask layer to form a first opening; removing the oxide layer of the region of the second electrode exposed in the first opening; A connection structure is prepared on a side of the first planar layer facing away from the substrate, and the connection structure contacts and is electrically connected to the second electrode through the first opening.

19. The method for preparing a capacitor structure according to claim 18, wherein: The mask layer includes a metal hard mask layer or a PR photoresist.

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