Display device

Abstract

The present invention provides a novel display device. The present invention includes first to seventh transistors, a capacitive element, and a light-emitting device. The second terminal of the sixth transistor and the second terminal of the seventh transistor are electrically connected to an initialization line, respectively. The second terminal of the light emitting device is electrically connected to a common potential line. A first control signal is supplied to the gate of the sixth transistor. A second control signal is supplied to the back gate of the sixth transistor. A third control signal is supplied to the gate of the seventh transistor. A fourth control signal is supplied to the back gate of the seventh transistor. The potential of the initialization line is lower than the potential of the common potential line. The low-level potential of the second control signal and the low-level potential of the fourth control signal are different from the low-level potential of the first control signal and the low-level potential of the third control signal.

Description

display device

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. More specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, arithmetic units, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, electronic devices, and driving methods thereof or manufacturing methods thereof.

[0003] Display devices have become increasingly commoditized as a result of recent technological innovations, and in order to gain a competitive edge in this environment, products with higher added value are required.

[0004] For example, a display device using a transistor (also referred to as an OS transistor) having an oxide semiconductor in a semiconductor layer having a channel formation region and a transistor (also referred to as an LTPS transistor) having low-temperature polysilicon (LTPS) in a semiconductor layer having a channel formation region is known (see Patent Document 1). A display device using an OS transistor and an LTPS transistor can be a display device with high added value, such as high definition, low power consumption, high switching speed, and / or a narrow panel frame. Note that a structure in which an LTPS transistor and an OS transistor are combined is sometimes referred to as LTPO.

[0005] JP 2018-5237 A

[0006] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0007] OS transistors have low off-state current characteristics. Therefore, display devices having pixel circuits employing LTPO structures can be driven at low driving frequencies, resulting in reduced power consumption. On the other hand, tests such as NBTIS (Negative Bias Temperature Illumination Stress) have shown that OS transistors have a problem of threshold voltage fluctuation due to stresses such as light, heat, and voltage. To address the fluctuation in the threshold voltage of an OS transistor due to NBTIS, a configuration in which the threshold voltage of the transistor is negatively shifted is effective. However, if the off-state current of an OS transistor increases, the data voltage in the pixel circuit may not be retained when driven at a low driving frequency. This may impair the display quality of the display device.

[0008] To suppress a negative shift in the threshold voltage of an OS transistor, a back gate electrode is provided facing the gate electrode across a channel formation region, and the potential of the back gate electrode is controlled. For example, a configuration in which the same control signal is applied to the gate electrode and the back gate electrode may be used. However, when the low-level potential of the control signal is high, for example, higher than the source potential of the OS transistor, a problem occurs in that the negative shift in the threshold voltage of the OS transistor is not sufficiently suppressed. This may result in a loss of reliability of the display device.

[0009] An object of one embodiment of the present invention is to provide a display device with excellent display quality, a display device with excellent reliability, or a novel display device.

[0010] The above-listed problems do not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of the above-listed problems. Note that problems other than the above-listed problems will become apparent from the description of this specification, drawings, claims, etc., and problems other than the above-listed problems can be extracted from the description of this specification, drawings, claims, etc.

[0011] One embodiment of the present invention includes first to seventh transistors, a capacitor, and a light-emitting device. The first to fifth transistors each have a gate, a first terminal, and a second terminal. The sixth and seventh transistors each have a gate, a back gate, a first terminal, and a second terminal. The first terminal of the first transistor is electrically connected to the first terminal of the second transistor and the first terminal of the third transistor. The second terminal of the third transistor is electrically connected to the first terminal of the fourth transistor and the first terminal of the sixth transistor. The second terminal of the fourth transistor is electrically connected to the first terminal of the light-emitting device and the first terminal of the fifth transistor. The second terminal of the light-emitting device is electrically connected to a common potential line. The gate of the third transistor is electrically connected to the second terminal of the sixth transistor, the first terminal of the seventh transistor, and the first terminal of the capacitor. a second terminal of the fifth transistor and a second terminal of the seventh transistor are each electrically connected to an initialization line; a gate of the sixth transistor is electrically connected to a first gate line to which a first control signal is supplied; a back gate of the sixth transistor is electrically connected to a second gate line to which a second control signal is supplied; a gate of the seventh transistor is electrically connected to a third gate line to which a third control signal is supplied; and a back gate of the seventh transistor is electrically connected to a fourth gate line to which a fourth control signal is supplied; the first control signal and the second control signal are signals of the same logic; the third control signal and the fourth control signal are signals of the same logic; and a low-level potential of the second control signal and a low-level potential of the fourth control signal are different potentials from the low-level potential of the first control signal and the low-level potential of the third control signal.

[0012] One embodiment of the present invention includes first to seventh transistors, a capacitor, and a light-emitting device. The first to fifth transistors each have a gate, a first terminal, and a second terminal. The sixth and seventh transistors each have a gate, a back gate, a first terminal, and a second terminal. The first terminal of the first transistor is electrically connected to a data line. The second terminal of the first transistor is electrically connected to a first terminal of the second transistor and a first terminal of the third transistor. The second terminal of the second transistor is electrically connected to a current supply line. The second terminal of the third transistor is electrically connected to a first terminal of the fourth transistor and a first terminal of the sixth transistor. The second terminal of the fourth transistor is electrically connected to a first terminal of the light-emitting device and a first terminal of the fifth transistor. The second terminal of the fifth transistor is electrically connected to an initialization line. The second terminal of the light-emitting device is electrically connected to a common potential line. the gate of the sixth transistor is electrically connected to a first gate line to which a first control signal is supplied, the back gate of the sixth transistor is electrically connected to a second gate line to which a second control signal is supplied, the gate of the seventh transistor is electrically connected to a third gate line to which a third control signal is supplied, and the back gate of the seventh transistor is electrically connected to a fourth gate line to which a fourth control signal is supplied, the first control signal and the second control signal are signals of the same logic, the third control signal and the fourth control signal are signals of the same logic, the potential of the initialization line is lower than the potential of the common potential line, and the low-level potential of the second control signal and the low-level potential of the fourth control signal are equal to or lower than the potential of the initialization line.

[0013] One embodiment of the present invention includes first to seventh transistors, a capacitor, and a light-emitting device. The first to fifth transistors each have a gate, a first terminal, and a second terminal. The sixth and seventh transistors each have a gate, a back gate, a first terminal, and a second terminal. The first terminal of the first transistor is electrically connected to a data line. The second terminal of the first transistor is electrically connected to a first terminal of the second transistor and a first terminal of the third transistor. The second terminal of the second transistor is electrically connected to a current supply line. The second terminal of the third transistor is electrically connected to a first terminal of the fourth transistor and a first terminal of the sixth transistor. The second terminal of the fourth transistor is electrically connected to a first terminal of the light-emitting device and a first terminal of the fifth transistor. The second terminal of the fifth transistor is electrically connected to an initialization line. The second terminal of the light-emitting device is electrically connected to a common potential line. the second terminal of the capacitance element is electrically connected to a current supply line, the second terminal of the seventh transistor is electrically connected to an initialization line, the gate of the sixth transistor is electrically connected to a first gate line to which a first control signal is supplied, the back gate of the sixth transistor is electrically connected to a second gate line to which a second control signal is supplied, the gate of the seventh transistor is electrically connected to a third gate line to which a third control signal is supplied, and the back gate of the seventh transistor is electrically connected to a fourth gate line to which a fourth control signal is supplied, the first control signal and the second control signal are signals of the same logic, the third control signal and the fourth control signal are signals of the same logic, the potential of the initialization line is lower than the potential of the common potential line, the potential of the initialization line is lower than the potential of the data line, and a low-level potential of the second control signal and a low-level potential of the fourth control signal are equal to or lower than the potential of the initialization line.

[0014] In one embodiment of the present invention, the display device is preferably such that the first to fifth transistors are p-channel transistors, and the sixth and seventh transistors are n-channel transistors.

[0015] In one embodiment of the present invention, the display device is preferably such that the back gate of the n-channel transistor faces the gate of the n-channel transistor with a channel formation region of the n-channel transistor interposed therebetween.

[0016] In one embodiment of the present invention, the display device preferably includes an n-channel transistor having a first semiconductor layer, and the first semiconductor layer includes indium oxide.

[0017] In one embodiment of the present invention, the display device preferably includes a p-channel transistor having a second semiconductor layer, and the second semiconductor layer includes silicon.

[0018] In one aspect of the present invention, the display device is preferably such that the high level potential of the second control signal and the high level potential of the fourth control signal are the same potential as the high level potential of the first control signal and the high level potential of the third control signal.

[0019] In one embodiment of the present invention, the display device is preferably such that the channel length of the third transistor is longer than the channel length of the first transistor, the channel length of the second transistor, the channel length of the fourth transistor, and the channel length of the fifth transistor.

[0020] One embodiment of the present invention includes a structure in which at least one of a gate, a source, and a drain of a transistor is not connected to anything or is connected to any node.Another embodiment of the present invention includes a structure in which a wiring to which a transistor is connected is not connected to anything or can receive any signal or voltage.

[0021] Other aspects of the present invention will be described in the following embodiments and drawings.

[0022] According to one embodiment of the present invention, a display device with excellent display quality, a display device with excellent reliability, or a novel display device can be provided.

[0023] The effects listed above do not preclude the existence of other effects. It is not necessary for one embodiment of the present invention to have all of the effects listed above. Effects other than the effects listed above will become apparent from the description in this specification, drawings, claims, etc., and other effects other than the effects listed above can be extracted from the description in this specification, drawings, claims, etc.

[0024] FIGS. 1A and 1B are a block diagram and a circuit diagram illustrating a display device. FIG. 2 is a circuit diagram illustrating a display device. FIGS. 3A to 3D are circuit diagrams and waveform diagrams illustrating a display device. FIGS. 4A to 4D are circuit diagrams and waveform diagrams illustrating a display device. FIG. 5 is a circuit diagram illustrating a display device. FIG. 6 is a timing chart illustrating a display device. FIGS. 7A and 7B are circuit diagrams and timing charts illustrating the operation of a display device. FIGS. 8A and 8B are circuit diagrams and timing charts illustrating the operation of a display device. FIGS. 9A and 9B are circuit diagrams and timing charts illustrating the operation of a display device. FIGS. 10A and 10B are circuit diagrams and timing charts illustrating the operation of a display device. FIGS. 11A and 11B are circuit diagrams and timing charts illustrating the operation of a display device. FIGS. 12A and 12B are circuit diagrams illustrating a display device. FIGS. 13A and 13B are circuit diagrams illustrating a display device. FIGS. 14A and 14B are circuit diagrams illustrating a display device. FIG. 15 is a circuit diagram illustrating a display device. FIG. 16 is a circuit diagram illustrating a display device. FIGS. 17A and 17B are circuit diagrams illustrating a display device. FIGS. 18A and 18B are circuit diagrams and waveform diagrams illustrating a display device. FIGS. 19A and 19B are circuit diagrams and block diagrams illustrating a display device. FIGS. 20A and 20B are block diagrams and circuit diagrams illustrating a display device. FIG. 21 is a circuit diagram illustrating a display device. FIG. 22 is a circuit diagram illustrating a display device. FIG. 23 is a circuit diagram illustrating a display device. FIG. 24 is a timing chart illustrating a display device. FIGS. 25A and 25B are circuit diagrams and timing charts illustrating the operation of a display device. FIGS. 26A and 26B are circuit diagrams and timing charts illustrating the operation of a display device. FIGS. 27A and 27B are circuit diagrams and timing charts illustrating the operation of a display device. FIGS. 28A and 28B are circuit diagrams and timing charts illustrating the operation of a display device. FIGS. 29A and 29B are circuit diagrams and timing charts illustrating the operation of a display device.FIG. 30 is a block diagram illustrating a display device. FIG. 31 is a circuit diagram illustrating a display device. FIGS. 32A to 32C are block diagrams and waveform diagrams illustrating a display device. FIG. 33 is a circuit diagram illustrating a display device. FIG. 34 is a circuit diagram illustrating a display device. FIG. 35 is a timing chart illustrating a display device. FIGS. 36A and 36B are circuit diagrams illustrating the operation of the display device. FIG. 37 is a timing chart illustrating a display device. FIGS. 38A and 38B are circuit diagrams and timing charts illustrating the operation of the display device. FIGS. 39A and 39B are circuit diagrams and timing charts illustrating the operation of the display device. FIGS. 40A and 40B are circuit diagrams and timing charts illustrating the operation of the display device. FIGS. 41A and 41B are circuit diagrams and timing charts illustrating the operation of the display device. FIGS. 42A and 42B are circuit diagrams and timing charts illustrating the operation of the display device. FIG. 43 is a perspective view showing an example of the configuration of a display device. FIGS. 44A to 44C are cross-sectional views showing an example of the configuration of a display device. 45A and 45B are cross-sectional views showing an example of the configuration of a display device. FIG. 46 is a plan view showing an example of the configuration of a display device. FIGS. 47A to 47C are cross-sectional views showing an example of the configuration of a display device. FIG. 48 is a schematic view showing an example of the configuration of a display device. FIG. 49 is a plan view showing an example of the configuration of a display device. FIGS. 50A to 50C are cross-sectional views showing an example of the configuration of a display device. FIG. 51 is a plan view showing an example of the configuration of a display device. FIGS. 52A to 52C are cross-sectional views showing an example of the configuration of a display device. FIGS. 53A and 53B are diagrams explaining the carrier concentration dependence of Hall mobility. FIG. 53C is a cross-sectional view explaining an indium oxide film. FIGS. 54A and 54B are diagrams explaining an example of an electronic device. FIGS. 55A to 55D are diagrams explaining an example of an electronic device. FIGS. 56A to 56G are diagrams explaining an example of an electronic device. FIGS. 57A1 to 57A7 and 57B1 to 57B6 are diagrams explaining electrical connections.

[0025] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways. Therefore, it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, one aspect of the present invention should not be interpreted as being limited to the description of the embodiments.

[0026] In this specification and the like, the configuration shown in each embodiment can be appropriately combined with the configuration shown in another embodiment to form one aspect of the present invention. Furthermore, when multiple configurations are shown in one embodiment, these configurations can be appropriately combined to form one aspect of the present invention.

[0027] In addition, in the drawings illustrating the embodiments, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions in the configuration of the invention, thereby omitting repeated explanations. Furthermore, when the drawings indicate similar functions, for example, the same hatching patterns may be used and no particular reference numerals may be used. Furthermore, in the drawings, for example, in perspective views or plan views (also called "top views"), the illustration of some components may be omitted for ease of understanding. Furthermore, in the drawings, for example, the illustration of some hidden lines may be omitted. Furthermore, in the drawings, for example, the illustration of hatching patterns may be omitted.

[0028] In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the drawings are not limited to, for example, their size or aspect ratio. Note that the drawings are schematic representations of ideal examples and are not limited to, for example, the shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, layers or resist masks may be unintentionally thinned by processes such as etching, but these may not be reflected in the drawings to facilitate understanding. In addition, for example, in actual circuit operation, variations in voltage or current may occur due to noise or timing errors, but these may not be reflected in the drawings to facilitate understanding.

[0029] In addition, in this specification and drawings, the components of the present invention may be classified by function and shown as independent elements. However, it may be difficult to separate the components by function, and one element may be involved in multiple functions, or one function may be involved across multiple elements. Therefore, the elements shown in this specification and drawings may not be limited to the descriptions therein and may be rephrased appropriately.

[0030] Furthermore, in this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "A", "b", "_1", "[n]", or "[m, n]". Furthermore, when explaining matters common to multiple elements accompanied by identifying symbols, or when it is not necessary to distinguish between them, the elements may be described without the identifying symbol.

[0031] A display device according to one embodiment of the present invention will be described with reference to the drawings. The display device described in this embodiment has a display portion provided with pixels whose operations are controlled by a gate line side driver circuit and a data line side driver circuit.

[0032] 1A is a block diagram illustrating a display device according to one embodiment of the present invention. The display device 100 illustrated in FIG. 1A includes, for example, a display portion 20, a gate line side driver circuit 30, a gate line side driver circuit 31, a gate line side driver circuit 32, an integrated circuit 40, and the like.

[0033] The display unit 20 has a plurality of pixels 11 arranged in a matrix. Each pixel 11 has sub-pixels 10_R, 10_G, and 10_B. Each of the sub-pixels 10_R, 10_G, and 10_B has a light-emitting device that functions as a display device.

[0034] The pixel 11 is connected to the wiring GI, wiring GI_BG, wiring GW, wiring EM, wiring GB, wiring GC, wiring GC_BG, wiring DLR, wiring DLG, and wiring DLB. The wiring GI, wiring GI_BG, wiring GW, wiring EM, wiring GB, wiring GC, and wiring GC_BG function as gate lines. The wiring DLR, wiring DLG, and wiring DLB function as data lines.

[0035] A gate line is a wiring that supplies a control signal that controls the on / off state of a transistor that functions as a switch. A gate line may also be called a gate signal line, a scanning line, or simply a wiring. A data line is a wiring that supplies a data voltage (also called a video potential or video data) based on an image signal to a pixel. A data line may also be called a data signal line, a source line, or simply a wiring.

[0036] The wirings DLR, DLG, and DLB are each connected to an integrated circuit 40. The wirings DLR, DLG, and DLB are each connected to a plurality of sub-pixels 10_R, a plurality of sub-pixels 10_G, or a plurality of sub-pixels 10_B arranged in the column direction (the extension direction of the wirings DLR, DLG, and DLB). The integrated circuit 40 functions as a circuit (also referred to as a source line driving circuit, a source line side driving circuit, or a source driver) that supplies a data voltage to the pixels 11.

[0037] The wirings GW, GC, and GC_BG are connected to the gate line side driving circuit 30. The wirings GW, GC, and GC_BG are each connected to the sub-pixels 10_R, 10_G, and / or 10_B arranged in the row direction (the extension direction of the wirings GI, GI_BG, GW, EM, GB, GC, or GC_BG). The wirings GI, GI_BG, and GB are each connected to the gate line side driving circuit 31. The wirings GI, GI_BG, and GB are connected to the sub-pixels 10_R, 10_G, and / or 10_B arranged in the row direction. The wiring EM is connected to the gate line side driving circuit 32. The wiring EM is connected to the sub-pixels 10_R, 10_G, and / or 10_B arranged in the row direction. The gate line side driving circuits 30, 31, and 32 each function as a circuit (also called a gate line driving circuit, a gate line side driving circuit, or a gate driver) that supplies control signals to pixels.

[0038] The subpixels 10_R, 10_G, and 10_B included in the display unit 20 each include an OS transistor and an LTPS transistor. The OS transistor and the LTPS transistor can be thin film transistors (TFTs). The thin film transistors can be formed over a light-transmitting substrate such as a glass substrate, which allows the display device 100 to be large and inexpensive.

[0039] The gate line side driver circuits 30, 31, and 32 can be fabricated on a substrate using thin film transistors included in the display unit 20. This configuration can narrow the frame and / or reduce the number of components, such as external driver circuits. The gate line side driver circuits 30, 31, and 32 can also be configured as integrated circuits provided on a substrate, similar to the integrated circuit 40 that functions as a source line side driver circuit.

[0040] 1B is a diagram showing an example of a circuit diagram of a subpixel (hereinafter referred to as pixel 10) that can be applied to subpixels 10_R, 10_G, and 10_B of the display device 100. The pixel 10 includes a transistor M11, a transistor M12, a transistor M13, a transistor M14, a transistor M15, a transistor M16, a transistor M17, a capacitance element C1, and a light-emitting device 61.

[0041] 1B, wirings GI, GI_BG, GW, EM, GB, GC, GC_BG, DL, ELVDD, ELVSS, and INI are connected to the transistors included in the pixel 10. The wiring DL functions as, for example, any one of the wirings DLR, DLG, and DLB.

[0042] The wiring ELVDD, wiring ELVSS, and wiring INI are wirings that supply a constant potential (constant potential) for controlling, for example, a light-emitting device included in the pixel 10. The wiring ELVDD may be called a current supply line. The wiring ELVSS may be called a common potential line or a common electrode. The wiring INI may be called an initialization line.

[0043] A high power supply potential (VDD) is supplied to the wiring ELVDD, and a low power supply potential (VSS) is supplied to the wiring ELVSS. That is, a current flows from the wiring ELVDD to the wiring ELVSS via the transistors M12, M13, and M14 to the light-emitting device 61. With this configuration, light emission of the light-emitting device 61 can be controlled according to the drain current of the transistor M13 during the light-emitting period (the period during which the transistors M12 and M14 are turned on).

[0044] The wiring INI is connected to a potential V ＩＮＩ (V ＩＮＩ (also called) is supplied. ＩＮＩ is a potential that is supplied to the gate of the transistor M13 to turn on the transistor M13. ＩＮＩWhen the transistor M13 is a p-channel transistor, the potential of V can be lower than the potential of V supplied to the wiring ELVSS. ＩＮＩ can be used as a potential to make the light emitting device 61 non-emitting by applying it as an anode potential of the light emitting device 61 .

[0045] The transistor M11, the transistor M12, the transistor M14, the transistor M15, the transistor M16, and the transistor M17 function as switches. The transistor M13 functions as a transistor for controlling the current flowing through the light-emitting device 61. The transistor M13 functions as a drive transistor.

[0046] The transistors M11, M12, M14, M15, M16, and M17 have the function of setting a voltage corresponding to the data voltage to the gate (node ​​ND1) of a drive transistor for passing a current through the light-emitting device 61. The transistors M16 and M17 have the function of holding a voltage corresponding to the data voltage held at the node ND1.

[0047] In the circuit diagrams described in this specification, nodes may be labeled with symbols to facilitate understanding. For example, in FIG. 1B, the node connected to the gate of transistor M13 is designated as node ND1. Note that a node refers to an element (e.g., a wiring) that allows the connection of elements that constitute a circuit. Therefore, a "node connected to A" refers to a wiring that is connected to A and can be considered to have the same potential as A.

[0048] The semiconductor layers of the transistors M11 to M15, each having a channel formation region, contain silicon. Examples of silicon used in the semiconductor layers of the transistors M11 to M15 include single crystal silicon, polycrystalline silicon, and amorphous silicon. LTPS transistors having low-temperature polysilicon in the semiconductor layer are particularly preferred. The transistors M11 to M15 can be LTPS transistors with high field-effect mobility and favorable frequency characteristics. In particular, the transistor M13, which functions as a driving transistor, can be an LTPS transistor, thereby increasing the current flowing through the light-emitting device.

[0049] Furthermore, it is preferable to use p-channel transistors for the transistors M11 to M15, which are LTPS transistors. In Figure 1B and other figures, the transistors M11 to M15 included in the pixel 10 are shown as p-channel transistors. When an organic electroluminescence element is used as a light-emitting device, the circuit design of p-channel transistors is relatively easier than that of n-channel transistors.

[0050] The transistors M16 and M17 included in the pixel 10 are n-channel OS transistors having a back gate. FIG. 1B illustrates a circuit configuration in which the transistors M16 and M17 have a back gate.

[0051] The pixel 10 can have a circuit configuration in which the OS transistor is an n-channel transistor and the LTPS transistor is a p-channel transistor. The pixel 10 can have a complementary circuit configuration. In the case of a complementary circuit configuration, for example, in the case of an inverter circuit, applying a potential of the same logic to the gates of both transistors can turn one of them on and the other off. In this case, providing an n-channel transistor and a p-channel transistor between power supply lines can reduce the current flowing between the power supply lines, thereby achieving low power consumption.

[0052] The semiconductor layer having a channel formation region of an OS transistor includes an oxide semiconductor (also referred to as a metal oxide), such as indium gallium zinc oxide (IGZO). Alternatively, the semiconductor layer having a channel formation region of an OS transistor includes an oxide semiconductor with high mobility and excellent crystallinity, such as indium oxide (IO). An oxide semiconductor with high mobility and excellent crystallinity is sometimes called low temperature poly-indium oxide (LTPI). Because the band gaps of the oxide semiconductor and LTPI are 2 eV or more, the OS transistor has an extremely low off-state current. The off-state current of an OS transistor per 1 μm of channel width at room temperature is 1×10 −１２ A or less, 1aA (1×10 −１８ A) Below, 1zA (1×10 −２１ A) or less, or 1 yA (1 x 10 −２４ A) It can be as follows:

[0053] The node ND1 to which the transistors M16 and M17 are connected is electrically floating when the transistors M16 and M17 are turned off, and can hold a charge according to the potential. The drain current of the transistor M13 is determined by the potential of the node ND1. Furthermore, the light-emitting luminance of the light-emitting device 61 is determined by the magnitude of the drain current of the transistor M13. Therefore, by using OS transistors for the transistors M16 and M17 connected to the node ND1, fluctuations in the potential of the node ND1 can be suppressed, thereby improving the display quality of the display device. Furthermore, by using OS transistors for the transistors M16 and M17 connected to the node ND1, the potential of the node ND1 can be maintained even when the frame frequency is significantly reduced (for example, 1 fps or less). Therefore, the integrated circuit 40 can be stopped when displaying a still image, thereby reducing power consumption.

[0054] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environment of room temperature or higher and 200° C. or lower. Furthermore, the on-state current of an OS transistor is unlikely to decrease even in a high-temperature environment. Furthermore, the OS transistor can perform favorable switching operation even in an environment of 125° C. or higher and 150° C. or lower because of its large ratio of on-state current to off-state current. Therefore, a display device using an OS transistor can operate stably and with high reliability even in a high-temperature environment.

[0055] Furthermore, the OS transistor can be provided in a layer different from that of the LTPS transistor. This structure allows the OS transistor and the LTPS transistor to be fabricated in separate layers, thereby reducing the influence of hydrogen addition to a semiconductor layer having a channel formation region during fabrication of the OS transistor. Furthermore, a layer including an LTPS transistor and a layer including an OS transistor can be stacked. This structure reduces the area occupied by the pixel 10. In particular, a display device using an organic EL element requires more transistors to drive a pixel than a display device using a liquid crystal element. In this case, it is particularly preferable to provide the OS transistor in a layer different from that of the LTPS transistor to reduce the area occupied by the pixel 10.

[0056] Note that the OS transistor and the LTPS transistor can have various structures, such as a planar type, a staggered type, a fin type, a tri-gate type, a top-gate type, a bottom-gate type, or a dual-gate type (a structure in which gates are arranged on both sides (e.g., above and below) of a channel formation region) transistor.

[0057] Note that the transistors M16 and M17 may be transistors other than OS transistors. Any n-channel transistor with a higher withstand voltage than an LTPS transistor used as a p-channel transistor can be used as the transistors M16 and M17. For example, in an n-channel LTPS transistor, the withstand voltage can be increased by increasing the channel length and the thickness of the gate insulating film, and thus the transistors M16 and M17 can be used as n-channel transistors with a higher withstand voltage than an LTPS transistor used as a p-channel transistor.

[0058] In one embodiment of the present invention, the gate and back gate of the OS transistors included in the pixel 10, specifically, the transistors M16 and M17, are arranged opposite to each other with a channel formation region of the semiconductor layer interposed therebetween. In addition, a control signal applied to the gate of the OS transistor and a control signal applied to the back gate of the OS transistor have the same logic. Furthermore, a potential (low-level potential of the control signal) applied to the back gate when turning the OS transistor off is different from a low-level potential of the control signal applied to the gate when turning the OS transistor off. The gate of an OS transistor may be referred to as a first gate, and the back gate of an OS transistor may be referred to as a second gate.

[0059] In one embodiment of the present invention, the potential V ＩＮＩ is set to be lower than the potential VSS of the wiring ELVSS, and the potential (low-level potential of the control signal) applied to the back gate when turning off the OS transistor is set to be the potential V ＩＮＩ A potential below, preferably a potential V ＩＮＩ Let's say.

[0060] In one embodiment of the present invention, the potential V ＩＮＩ is the potential VSS of the wiring ELVSS and the data voltage V of the wiring DL. ＤＡ The potential applied to the back gate when turning off the OS transistor (the low-level potential of the control signal) is set to be lower than the potential V ＩＮＩ A potential below, preferably a potential V ＩＮＩ Let's say.

[0061] With this configuration, the potential of the control signal applied to the back gate of the OS transistor can be set lower than the potential (low-level potential) of the control signal applied to the gate of the OS transistor. For an n-channel OS transistor, the potential applied to the back gate can be set lower than the potential (low-level potential) applied to the gate, thereby shifting the threshold voltage in the positive direction. Therefore, even when the OS transistor is driven at a significantly lower frame frequency, the potential fluctuation of the node ND1 can be suppressed, resulting in a display device with excellent display quality.

[0062] Furthermore, with this configuration, the low-level potential of the control signal applied to the back gates of the transistors M16 and M17 can be set to be equal to or lower than the source potential of the transistors M16 and M17. The source potential of the transistors M16 and M17 can be set to be equal to or lower than the potential based on the data voltage or the potential V of the wiring INI. ＩＮＩ Therefore, the voltage between the back gate and the source of the transistors M16 and M17 can be set to 0 V or less. This can suppress fluctuations in the threshold voltage of the transistors M16 and M17, thereby improving the long-term reliability of the transistors. Therefore, the reliability of a display device including these transistors can be improved.

[0063] In addition, with this configuration, the potential V ＩＮＩ Therefore, it is possible to configure the low-level potential of the control signal to be applied to the back gates of the transistors M16 and M17 without increasing the number of potentials required. ＩＮＩ can be set to a potential lower than the potential VSS by several volts (for example, by the amount of fluctuation in the threshold voltage of the transistor). Therefore, the low-level potential applied to the back gates of the transistors M16 and M17 is not set to a potential lower than necessary. Therefore, it is possible to prevent the amplitude voltage of the control signal applied to the back gate from becoming larger than necessary.

[0064] Furthermore, with this structure, a semiconductor layer having a channel formation region of an OS transistor is sandwiched between the gate and the back gate, so that an electric field generated outside the transistor is less likely to act on the channel formation region (also referred to as an "electric field shielding effect"). Therefore, providing a back gate in a transistor stabilizes the operation of the transistor. Furthermore, providing a back gate in a transistor reduces variations in characteristics among multiple transistors. Furthermore, providing a back gate in a transistor can improve the reliability of the transistor. Therefore, the reliability of a display device including the transistor can be improved.

[0065] Furthermore, with this structure, a light-blocking conductive material can be provided for both the gate and back gate of an OS transistor. When a channel formation region of a transistor is irradiated with light, the electrical characteristics of the transistor may fluctuate. Furthermore, when the channel formation region of the transistor is irradiated with light while a voltage is applied to the transistor, the electrical characteristics of the transistor may deteriorate. That is, the reliability of the transistor may decrease. By using a light-blocking conductive material for both the gate and back gate, deterioration of the electrical characteristics of the transistor can be suppressed and the reliability can be improved.

[0066] Furthermore, with this structure, when a transistor is turned on, the potential of a control signal for controlling the on state of the transistor can be supplied from both the gate and the back gate. By supplying a potential for turning on the transistor to both the gate and the back gate, the on-state current can be increased compared to when the potential is supplied to only one of them.

[0067] Each transistor included in the pixel 10 is connected to each wiring as shown in FIG. 1B , for example. One of the source or drain of the transistor M11 is connected to a wiring DL. The other of the source or drain of the transistor M11 is connected to one of the source or drain of the transistor M12 and one of the source or drain of the transistor M13. The other of the source or drain of the transistor M12 is connected to a wiring ELVDD. The other of the source or drain of the transistor M13 is connected to one of the source or drain of the transistor M14 and one of the source or drain of the transistor M16. The other of the source or drain of the transistor M14 is connected to one of the source or drain of the transistor M15 and a first terminal of the light-emitting device 61. A second terminal of the light-emitting device 61 is connected to a wiring ELVSS.

[0068] The other of the source and drain of transistor M15 is connected to wiring INI. The other of the source and drain of transistor M16 is connected to the gate of transistor M13, one electrode of capacitor C1, and one of the source and drain of transistor M17. The other electrode of capacitor C1 is connected to wiring ELVDD. The other of the source and drain of transistor M17 is connected to wiring INI.

[0069] The gate of transistor M11 is connected to wiring GW. The gate of transistor M12 is connected to wiring EM. The gate of transistor M14 is connected to wiring EM. The gate of transistor M15 is connected to wiring GB. The gate of transistor M16 is connected to wiring GC. The back gate of transistor M16 is connected to wiring GC_BG. The gate of transistor M17 is connected to wiring GI. The back gate of transistor M17 is connected to wiring GI_BG.

[0070] In the pixel 10, a first terminal of the light-emitting device 61 functions as an anode, and a second terminal of the light-emitting device 61 functions as a cathode. As the light-emitting device 61, it is possible to use a display element such as an EL element (an EL element including an organic material and an inorganic material, an organic EL element, or an inorganic EL element), an LED (a white LED, a red LED, a green LED, a blue LED, or the like), a micro LED, a QLED (Quantum-dot Light Emitting Diode), or an electron-emitting element.

[0071] The control signal supplied to the wiring GW is a signal that controls the on / off state of the transistor M11. For example, the control signal supplied to the wiring GW controls whether or not a data voltage supplied to the wiring DL is written to the pixel 10. For example, the transistor M11, which is a p-channel transistor, is turned off when the control signal supplied to the wiring GW is at an H level, and turned on when the control signal supplied to the wiring GW is at an L level.

[0072] The control signal supplied to the wiring EM is a signal that controls the on or off state of the transistors M12 and M14. For example, the control signal supplied to the wiring EM controls the current path that flows between the wiring ELVDD and the wiring ELVSS. For example, the transistors M12 and M14, which are p-channel transistors, are turned off when the control signal supplied to the wiring EM is at an H level, and turned on when the control signal supplied to the wiring EM is at an L level.

[0073] The control signal supplied to the wiring GB is a signal that controls the on / off state of the transistor M15. For example, the control signal supplied to the wiring GB controls the potential of the first terminal of the light emitting device 61 that functions as an anode to the potential V ＩＮＩ For example, the transistor M15, which is a p-channel transistor, is turned off when the control signal supplied to the wiring GB is at H level, and turned on when the control signal supplied to the wiring GB is at L level.

[0074] The control signal supplied to the wiring GC and the control signal supplied to the wiring GC_BG are signals that control the on / off state of the transistor M16. For example, the control signal supplied to the wiring GC and the control signal supplied to the wiring GC_BG control whether the potential of the gate of the transistor M13 is set to the potential of the other of the source or drain of the transistor M13. For example, the transistor M16, which is an n-channel transistor, is turned on when the control signal supplied to the wiring GC and the control signal supplied to the wiring GC_BG are both H level, and turned off when the control signal supplied to the wiring GC and the control signal supplied to the wiring GC_BG are both L level.

[0075] The control signal supplied to the wiring GI and the control signal supplied to the wiring GI_BG are signals that control the on / off state of the transistor M17. For example, the control signal supplied to the wiring GI and the control signal supplied to the wiring GI_BG controls the potential of the gate of the transistor M13 to the potential V ＩＮＩ For example, the transistor M17, which is an n-channel transistor, is turned on when the control signal supplied to the wiring GI and the control signal supplied to the wiring GI_BG are both at H level, and turned off when the control signal supplied to the wiring GI and the control signal supplied to the wiring GI_BG are both at L level.

[0076] 2 is an example of a block diagram of gate line side drive circuits 30 and 31 that output control signals to the above-mentioned lines GI, GI_BG, GW, GB, GC, and GC_BG. The gate line side drive circuit 30 is connected to the lines GW, GC, and GC_BG, and supplies control signals to the pixels 10. The gate line side drive circuit 31 shown in FIG. 1A is connected to the lines GI, GB, and GI_BG, and supplies control signals to the pixels 10. Although not shown, the gate line side drive circuit 32 supplies a control signal to the lines EM at a timing different from that of the gate line side drive circuits 30 and 31.

[0077] The gate line side driver circuit 30 is provided with pulse output circuits PO_1 to PO_m corresponding to the number of rows of the pixels 10 provided in the display unit 20, for example, m rows (m is an integer of 2 or more). Similarly, the gate line side driver circuit 31 is also provided with pulse output circuits PO_1 to PO_m corresponding to the number of rows of the pixels 10. The pulse output circuits PO_1 to PO_m are circuits that output control signals, the timing of which is shifted to select pixels, to the wirings of each row (wirings GI_1 to GI_m, wirings GI_BG_1 to GI_BG_m, wirings GW_1 to GW_m, wirings GB_1 to GB_m, wirings GC_1 to GC_m, and wirings GC_BG_1 to GC_BG_m) via buffers BUF1 to BUF3 in response to a start pulse SP1 (or SP2) and a clock signal CLK.

[0078] Control signals output from pulse output circuits PO_1 to PO_m of the gate line side driver circuits 30 and 31 are supplied to the respective wirings via buffers BUF1, BUF2, and BUF3. For example, the control signal output from the pulse output circuit PO_1 of the gate line side driver circuit 30 is supplied to wiring GW_1 via buffer BUF1. The control signal output from the pulse output circuit PO_1 of the gate line side driver circuit 30 is supplied to wiring GC_1 via buffer BUF2. The control signal output from the pulse output circuit PO_1 of the gate line side driver circuit 30 is supplied to wiring GC_BG_1 via buffer BUF3. The control signal output from the pulse output circuit PO_1 of the gate line side driver circuit 31 is supplied to wiring GB_1 via buffer BUF1. The control signal output from the pulse output circuit PO_1 of the gate line side driver circuit 31 is supplied to wiring GI_1 via buffer BUF2. Furthermore, a control signal output from the pulse output circuit PO_1 of the gate line side driver circuit 31 is supplied to a line GI_BG_1 via a buffer BUF3.

[0079] Similarly, the pulse output circuits PO_2 to PO_m output control signals to the wirings of each row (wirings GI_2 to GI_m, wirings GI_BG_2 to GI_BG_m, wirings GW_2 to GW_m, wirings GB_2 to GB_m, wirings GC_2 to GC_m, and wirings GC_BG_2 to GC_BG_m) via buffers BUF1 to BUF3.

[0080] Here, the amplitude voltage of the control signal output from the buffers BUF1 to BUF3 will be described. Fig. 3A illustrates the pulse output circuit PO and the buffers BUF1 to BUF3, which are applicable to the pulse output circuits PO_1 to PO_m described in Fig. 2. The control signal output from the pulse output circuit PO is a low-active signal (a signal that is in a selected state at a low-level potential).

[0081] The buffers BUF1 to BUF3 are circuits having transistors provided between each wiring to which a control signal is output and a wiring that provides an amplitude voltage of the control signal. For ease of understanding, the buffers BUF1 to BUF3 are illustrated as blocks independent of the pulse output circuit PO, but it is also possible for a part of the pulse output circuit PO to function as the buffers BUF1 to BUF3. The wiring that provides the amplitude voltage of the control signal in the buffers BUF1 to BUF3 is described as wiring that provides a constant potential, but it is also possible for them to be clock signal lines that provide an amplitude voltage of a clock signal.

[0082] The buffer BUF1 in FIG. 3A outputs a control signal to the gates of p-channel transistors M11 and M15 via the wiring GW or the wiring GB. The buffer BUF1 outputs a low-active signal. As shown in FIG. 3A, the buffer BUF1 is supplied with a potential VH1 as a potential that provides an H level and a potential VL1 as a potential that provides an L level. The potential VL1 is a potential that turns on a p-channel transistor when applied to its gate. The potential VH1 is a potential that turns off a p-channel transistor when applied to its gate. In the following description, terms representing potentials or voltages, such as the potentials VH1 and VL1, may be abbreviated as VH1 and VL1.

[0083] The buffer BUF2 in FIG. 3A outputs a control signal to the gates of n-channel transistors M16 and M17 via wiring GI or wiring GC. The buffer BUF2 outputs a high-active signal (a signal that is in a selected state at a high-level potential). As shown in FIG. 3A, the buffer BUF2 is supplied with VH2 as a potential that provides an H level and VL2 as a potential that provides an L level. VH2 is a potential that is supplied to the gate of an n-channel transistor to turn it on. VL2 is a potential that is supplied to the gate of an n-channel transistor to turn it off.

[0084] 1A and 1B, a low-active signal is output via a shift register and a buffer included in the gate line side drive circuit 32 at a timing different from that of the gate line side drive circuits 30 and 31. A buffer BUF1 can be used as the buffer included in the gate line side drive circuit 32.

[0085] 3A outputs a control signal to the back gates of the transistors M16 and M17, which are n-channel transistors, via the wiring GI_BG or the wiring GC_BG. The buffer BUF3 outputs a high-active signal, which is a signal of the same logic as the control signal output to the wiring GI or the wiring GC. As shown in FIG. 3A, the buffer BUF3 is supplied with VH2 as a potential for providing an H level and V ＩＮＩ is supplied.

[0086] The control signal on the wiring GW or the wiring GB is a selection signal with an amplitude voltage according to VH1 and VL1 during the selection period P as shown in the waveform diagram of FIG. ＳＥＬ 3C, the control signal on the wiring GI or GC is supplied to the gate of the transistor M11 or M15. As shown in the waveform diagram of FIG. 3C, the selection signal of the amplitude voltage according to VH2 and VL2 is supplied to the gate of the transistor M11 or M15 during the selection period P ＳＥＬ3B, VL1 is set to a potential higher than VL2. In FIG. 3C, VH1 is set to a potential higher than VH2. With this configuration, the amplitude voltage Am1 of the control signal on the wiring GW or GB becomes the same amplitude voltage as the amplitude voltage Am2 of the control signal on the wiring GI or GC. By making the H-level and L-level potentials supplied to the buffer BUF1 different from the H-level and L-level potentials supplied to the buffer BUF2, the amplitude voltage can be made smaller than when a common potential is supplied to the buffers BUF1 and BUF2.

[0087] The control signal on the wiring GI_BG or the wiring GC_BG is VH2, V ＩＮＩ A selection signal of an amplitude voltage according to ＳＥＬ 3D, VH1 is a potential higher than VH2. By setting the H-level potential supplied to buffer BUF3 to be the same as the H-level potential supplied to buffer BUF2, a common potential can be supplied to buffers BUF2 and BUF3, and the amplitude voltage Am3 can be made smaller than when VH1 is supplied as the H-level potential.

[0088] As shown in FIG. 3D, V ＩＮＩ is set to a potential lower than VL2, which is the low-level potential of the control signal applied to the gates of the transistors M16 and M17. Therefore, by setting the potential applied to the back gate lower than the potential applied to the gate, the threshold voltage can be shifted in the positive direction. Therefore, even when the display device is driven at a significantly lower frame frequency, the potential fluctuation of the node ND1 can be suppressed, resulting in a highly reliable display device.

[0089] As shown in FIG. 3D, V ＩＮＩ is the data voltage V ＤＡ V, which represents the maximum gradation of ＤＡ＿Ｈand V representing the minimum gradation ＤＡ＿Ｌ With this configuration, the voltage between the back gate and the source of the transistors M16 and M17 can be set to 0 V or less. This can suppress fluctuations in the threshold voltage of the transistors M16 and M17, thereby improving the long-term reliability of the transistors. Therefore, the reliability of a display device including these transistors can be improved.

[0090] As shown in FIG. 3D, V ＩＮＩ is set to a potential lower than VSS of the wiring ELVSS. ＩＮＩ By making it higher, the gate of the driving transistor M13 is V ＩＮＩ In the initialization operation, a current can be more reliably caused to flow through the driving transistor. Also, the source potential of M16 and M17 can be set to the potential of the node ND1.

[0091] Furthermore, the amplitude voltages of the control signals output from the buffers BUF1 to BUF3 may have configurations different from those shown in Figures 3A to 3D. Figures 4A to 4D will explain configurations different from those shown in Figures 3A to 3D. In the explanation of Figures 4A to 4D, repeated explanations of parts common to Figures 3A to 3D will be omitted.

[0092] Buffer BUF1 in Fig. 4A is supplied with VH as a potential for providing an H level and VL as a potential for providing an L level. Buffer BUF2 in Fig. 4A is also supplied with VH as a potential for providing an H level and VL as a potential for providing an L level. VL is a potential that is applied to the gate of a p-channel transistor to turn it on and to the gate of an n-channel transistor to turn it off. VH is a potential that is applied to the gate of a p-channel transistor to turn it off and to the gate of an n-channel transistor to turn it on.

[0093] 4B and 4C, the control signal for the wiring GW or the wiring GB and the control signal for the wiring GI or the wiring GC have the same amplitude voltage Am3 because common VH and VL are supplied to the buffers BUF1 and BUF2. By applying a common potential to the buffers BUF1 and BUF2, the number of potentials required in the gate line side driver circuits 30 and 31 can be reduced.

[0094] The buffer BUF3 in FIG. 4A has a potential VH that provides an H level and a potential V ＩＮＩ is supplied.

[0095] The control signal on the wiring GI_BG or the wiring GC_BG is VH, V ＩＮＩ A selection signal of an amplitude voltage according to ＳＥＬ In FIG. 4D, V ＩＮＩ is a potential greater than VL. Therefore, the amplitude voltage Am4 of the control signal output from the buffer BUF3 can be made smaller than the amplitude voltage Am3 of the control signal supplied from the buffers BUF1 and BUF2. This makes it possible to reduce power consumption. In addition, in the transistor M16 or M17 to which the control signal output from the buffer BUF2 is supplied, V ＩＮＩ Supplying a lower VL can shift the threshold voltage in the positive direction, so that even when the display device is driven at a significantly lower frame frequency, the potential fluctuation of the node ND1 can be suppressed, resulting in a display device with excellent display quality.

[0096] As shown in FIG. 4D, V ＩＮＩ is the data voltage V ＤＡ V, which represents the maximum gradation of ＤＡ＿Ｈ , and V representing the minimum gradation ＤＡ＿ＬWith this configuration, the voltage between the back gate and the source of the transistors M16 and M17 can be set to 0 V or less. This can suppress fluctuations in the threshold voltage of the transistors M16 and M17, thereby improving the long-term reliability of the transistors. Therefore, the reliability of a display device including these transistors can be improved.

[0097] As shown in FIG. 4D, V ＩＮＩ is set to a potential lower than VSS of the wiring ELVSS. ＩＮＩ By making it higher, the gate of the driving transistor M13 is V ＩＮＩ In the initialization operation, a current can be more reliably caused to flow through the driving transistor. Also, the source potential of M16 and M17 can be set to the potential of the node ND1.

[0098] As described above, the low level potential of the control signal to be applied to the back gate is V ＩＮＩ Therefore, as shown in FIG. 5, the wiring INI connected to the pixel 10 can be connected as a wiring that supplies the low-level potential of the buffer BUF3. As a result, it is possible to achieve a configuration that does not increase the number of potentials required as the low-level potential of the control signal to be supplied to the buffer BUF3. ＩＮＩ can be set to a potential several volts lower than VSS. Therefore, the low-level potential to be applied to the back gate is not set to a potential that is smaller than necessary. This makes it possible to prevent the amplitude voltage of the control signal to be applied to the back gate from becoming larger than necessary.

[0099] <Operation Example 1 of Display Device> Next, an operation example of the pixel 10 applicable to the display device 100 of one embodiment of the present invention will be described. FIG. 6 is a timing chart illustrating an operation example of the pixel 10. FIG. 6 illustrates waveforms of control signals supplied to the wirings GI, GI_BG, GB, GW, GC, GC_BG, and EM connected to the pixel 10, and changes in the potential at the node ND1. FIGS. 7A to 11B also illustrate a schematic diagram of the operation of the pixel 10 during periods T11 to T15 illustrated in FIG. 6, along with a timing chart. In the diagrams illustrating the operation of the pixel 10 in FIGS. 7A to 11B, a cross is superimposed on the circuit symbol of a transistor that is turned off. A thick dashed arrow indicates a current that flows when the transistor is turned on.

[0100] For ease of understanding, the potentials of the control signals supplied to the wirings GI, GI_BG, GB, GW, GC, GC_BG, and EM, and the potentials of the wirings to which a constant potential is supplied, can be configured as described with reference to Figures 3A to 3D. For example, an amplitude voltage of VH1 and VL1 is applied to the gate of a p-channel transistor, an amplitude voltage of VH2 and VL2 is applied to the gate of an n-channel transistor, and an amplitude voltage of VH2 and VL3 is applied to the back gate of an n-channel transistor. ＩＮＩ 6, it is also possible to apply the configuration in which the amplitude voltage control signals are the amplitude voltages described with reference to FIGS. 4A to 4D.

[0101] In the initial state, VL2 is supplied to the wirings GI and GC, VL1 is supplied to the wiring EM, and VH1 is supplied to the wirings GB and GW. Therefore, the transistors M11, M15, M16, and M17 are in the off state, and the transistors M12 and M14 are in the on state. In addition, when the potential of the node ND1 is equal to the data voltage V ＤＡ +Vth, and the transistor M13 is in an on state. Note that since the transistor M13 of the pixel 10 shown in FIG. 1B is a p-channel transistor, the Vth of the transistor M13 is negative (a voltage lower than the reference voltage). Therefore, the data voltage VＤＡ +Vth is the data voltage V ＤＡ is a lower potential than

[0102] [Period T11] During period T11, VH2 is supplied to the wiring GI, VH2 is supplied to the wiring GI_BG, and VL1 is supplied to the wiring GB (see FIGS. 7A and 7B). When VH2 is supplied to the wiring GI and the wiring GI_BG, the transistor M17 is turned on, and VL1 of the wiring INI is supplied to the node ND1. ＩＮＩ is supplied.

[0103] Furthermore, when VL1 is supplied to the wiring GB, the transistor M15 is turned on. This changes the path of the current that previously flowed to the light-emitting device 61 via the channel formation regions of the transistors M11, M13, and M14. Specifically, the current no longer flows to the light-emitting device 61, but instead flows toward the wiring INI via the channel formation region of the transistor M15. This causes the light-emitting device 61 to stop emitting light.

[0104] Furthermore, during the period T11, VH2 can be supplied to the wiring EM. By supplying VH2 to the wiring EM, the transistors M12 and M14 are turned off. This blocks the current flowing from the wiring ELVDD to the wiring INI, reducing power consumption. Furthermore, since the state is the same as that of the subsequent period T12, the period T12 can be omitted. This allows the operating speed of the display device including the pixel 10 to be increased.

[0105] [Period T12] During period T12, VH2 is supplied to the wiring EM (see FIGS. 8A and 8B). When VH2 is supplied to the wiring EM, the transistors M12 and M14 are turned off. In addition, since the transistor M15 is turned on, the first terminal of the light-emitting device 61 is connected to VH2 of the wiring INI. ＩＮＩ is supplied.

[0106] [Period T13] During period T13, VL2 is supplied to the wiring GI, and V ＩＮＩis supplied to the wiring GW, and VH1 is supplied to the wiring GB (see FIGS. 9A and 9B). Then, the transistors M17 and M15 are turned off. Furthermore, VL1 is supplied to the wiring GW, VH2 is supplied to the wiring GC, and VH2 is supplied to the wiring GC_BG.

[0107] Note that it is preferable to supply VL1 to the wiring GW, VH2 to the wiring GC, and VH2 to the wiring GC_BG after supplying VL2 to the wiring GI and VH1 to the wiring GB. This prevents the wiring DL and the wiring INI from becoming conductive, thereby reducing the power consumption of the display device 100 having the pixel 10.

[0108] When VL1 is supplied to the wiring GW, the transistor M11 is turned on, and the data voltage V ＤＡ When VH2 is supplied to the wirings GC and GC_BG, the transistor M16 is turned on. Since the transistor M13 is also turned on, the data voltage V ＤＡ Therefore, the potential of the node ND1 rises.

[0109] The potential rise of the node ND1 is the data voltage V ＤＡ +Vth (see FIG. 6). ＤＡ When the potential of the node ND1 reaches +Vth, the transistor M13 is turned off, and the potential rise of the node ND1 ends.

[0110] In order to shorten the time required for the potential of the node ND1 to increase in the period T13, it is preferable to use a transistor with a large on-state current as the transistor M16. This can shorten the time required for the transistor M13 to be turned off, thereby improving the operating speed.

[0111] By improving the operating speed, the operation of the period T13, which is the operation of initializing the potential of the gate of the transistor M13, can be performed multiple times. By performing the operation of the period T13 multiple times, the potential held at the node ND1 is initialized multiple times, thereby suppressing the influence of hysteresis, which is a change in the electrical characteristics of the transistor M13 depending on the state of the potential held at the node ND1. Since the influence of the hysteresis of the transistor M13 is large when a p-channel Si transistor is used as the transistor M13, performing the operation of the period T13 multiple times can provide a display device with excellent display quality.

[0112] In one embodiment of the present invention, for example, indium oxide can be used for semiconductor layers including channel formation regions of the transistors M16 and M17, which are transistors with high on-state current. Note that details of the transistors including indium oxide will be described in Embodiment 3 below.

[0113] [Period T14] During period T14, VH1 is supplied to the wiring GW, VL2 is supplied to the wiring GC, and V ＩＮＩ is supplied to the wiring GW (see FIGS. 10A and 10B). When VH1 is supplied to the wiring GW, the transistor M11 is turned off. Furthermore, VL2 is supplied to the wiring GC, and V ＩＮＩ When this voltage is supplied, the transistor M16 is turned off and the potential of the node ND1 is maintained (ND1=V ＤＡ +Vth). In this way, the data voltage V ＤＡ When the transistor M13 functioning as a driving transistor is a p-channel transistor, the data voltage V ＤＡ +Vth is a potential equal to or lower than Vth.

[0114] [Period T15] During period T15, VL1 is supplied to the wiring EM (see FIGS. 11A and 11B). When VL1 is supplied to the wiring EM, the transistors M12 and M14 are turned on. Here, the data voltage (ND1=VＤＡ +Vth) is a potential below Vth, and VDD of the wiring ELVDD is the data voltage V ＤＡ Since the potential is higher than +Vth, the transistor M13 is turned on. In this way, a current flows from the wiring ELVDD to the wiring ELVSS via the transistors M12, M13, and M14 and the light-emitting device 61. The value of the current flowing from the wiring ELVDD to the wiring ELVSS is determined by the potential of the node ND1. The pixel 10 applies a data voltage V ＤＡ Since the data voltage V ＤＡ Therefore, a current having an accurate current value according to the current value can be passed through the light-emitting device 61.

[0115] As shown in the above operation example, the pixels included in the display device according to one embodiment of the present invention can correct the Vth of the driving transistor for each pixel (also referred to as "internal correction"). Therefore, the display device according to one embodiment of the present invention can correct variations in the Vth of the driving transistor between pixels. Furthermore, the influence of hysteresis of the driving transistor can be suppressed. By using the display device according to one embodiment of the present invention, the display quality of the display portion can be improved.

[0116] In addition, in the pixel 10, the data voltage V ＤＡ The holding of the data voltage V and the correction of the Vth of the driving transistor are performed simultaneously. ＤＡ This allows for faster operation than pixels in which the holding of the first and second signals is performed in separate operations.

[0117] In order to maintain the data voltage held at the node ND1 during the period T15, it is preferable to use a transistor with low off-state current as each of the transistor M16 and the transistor M17, thereby stabilizing the light emission intensity.

[0118] In one embodiment of the present invention, for example, indium oxide can be used for semiconductor layers including channel formation regions of the transistors M16 and M17, which are transistors with extremely low off-state current. Note that details of the transistors including indium oxide will be described in Embodiment 3 below.

[0119] <Structure Example of Pixel> Next, a structure example that can be applied to the pixel 10 included in the display device 100 of one embodiment of the present invention will be described. Note that in the following description of FIGS. 1A to 11B , repeated description of parts common to those in FIGS. 1A to 11B may be omitted.

[0120] The transistors M11, M12, M14, and M15 in Fig. 1B function as switches. Thus, the pixel 10 in Fig. 1B can be shown as a pixel 10A in Fig. 12A by replacing the transistor M11 with a switch SW11, the transistor M12 with a switch SW12, the transistor M14 with a switch SW14, and the transistor M15 with a switch SW15. In Fig. 12A, one of the source and the drain of the transistor corresponds to a first terminal of the switch, and the other of the source and the drain of the transistor corresponds to a second terminal of the switch.

[0121] It is also possible to use mechanical switches as switches SW11, SW12, SW14, and SW15. An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. Such a switch has a mechanically movable electrode, and the movement of the electrode selects a conductive state or a non-conductive state.

[0122] Each switch described in the pixel 10A of FIG. 12A can be replaced with a transistor. The transistor functioning as a switch is not limited to a p-channel transistor, but can also be an n-channel transistor. Since an n-channel transistor has a higher field-effect mobility than a p-channel transistor, the operating speed of a display device including the pixel can be increased. For example, as in the pixel 10B illustrated in FIG. 12B, the transistor M15 described as a p-channel transistor in the pixel 10 of FIG. 1B can be replaced with an n-channel transistor.

[0123] The transistor M15 of the pixel 10B can be turned on or off at the same timing as the transistor M16. Therefore, the transistor M15 can be an n-channel transistor having a gate and a back gate, with the gate connected to the wiring GC and the back gate connected to the wiring GC_BG. This configuration can eliminate the need for the wiring GB for controlling the on or off state of the transistor M15. As a result, the number of wirings connected to the pixel 10B can be reduced, thereby improving the resolution and / or definition of the display device 100 using the pixel 10B in the display unit 20.

[0124] Also, for example, as in a pixel 10C illustrated in FIG. 13A, the transistor M11 described as a p-channel transistor in the pixel 10 of FIG. 1B can be an n-channel transistor.

[0125] The transistor M11 of the pixel 10C can be turned on or off at the same timing as the transistor M16. Therefore, the transistor M11 can be an n-channel transistor having a gate and a back gate, with the gate connected to the wiring GC and the back gate connected to the wiring GC_BG. This configuration can eliminate the need for a wiring GW for controlling the on or off state of the transistor M11. As a result, the number of wirings connected to the pixel 10C can be reduced, thereby improving the resolution and / or definition of the display device 100 using the pixel 10C in the display unit 20.

[0126] Note that the exemplary configuration of pixel 10C can be combined with the exemplary configuration of pixel 10B described above. For example, as shown in FIG. 13B , the transistors M11 and M15 described as p-channel transistors in pixel 10 of FIG. 1B can be n-channel transistors. This configuration makes it possible to omit the wiring GW for controlling the on / off state of transistor M11 and the wiring GB for controlling the on / off state of transistor M15. As a result, the number of wirings connected to pixel 10D can be reduced, thereby further improving one or both of the resolution and definition of a display device 100 using pixel 10D in the display unit 20.

[0127] 12B to 13B , in the configuration in which the transistor functioning as a switch is replaced with an n-channel transistor, a configuration having a gate and a back gate is illustrated. However, this is not limited to this. For example, as in the pixel 10E illustrated in FIG. 14A , the transistor M15 can be an n-channel transistor having a gate, and the gate can be connected to a wiring GC. This is because the transistor M15 is not as susceptible to fluctuations in the electrical characteristics of the transistor as other n-channel transistors M16 and M17, which affect display quality. This configuration can omit the wiring GB for controlling the on / off state of the transistor M15 and the back gate of the transistor M15. As a result, the resolution and / or definition of the display device 100 using the pixel 10E in the display unit 20 can be improved. The configuration of the transistor M15 in the pixel 10E can also be applied to the transistor M11 in the pixel 10C described above.

[0128] 12B to 13B , in a configuration in which the transistor functioning as a switch is replaced with an n-channel transistor, the transistor has a gate and a back gate, and separate control signals are supplied to both the gate and the back gate. However, this is not limited to this. For example, as in the pixel 10F shown in FIG. 14B , both the gate and the back gate of the transistor M15 can be connected to the wiring GC. This configuration can eliminate the need for the wiring GB for controlling the on / off state of the transistor M15. As a result, the resolution and / or definition of the display device 100 using the pixel 10F in the display unit 20 can be improved. Note that the configuration of the transistor M15 in the pixel 10F can also be applied to the transistor M11 in the pixel 10C described above.

[0129] The transistor described for pixel 10 in FIG. 1B can be a single-gate transistor having one gate between the source and drain. However, double-gate transistors can also be used. As shown in FIG. 15, a configuration can be adopted in which the circuit symbol of a double-gate transistor is applied to transistors M16 and M17. Because double-gate transistors have multiple transistors connected in series, they have a high withstand voltage between terminals functioning as source or drain. Therefore, they are highly reliable. Note that the double-gate transistor shown in FIG. 15 may be a triple-gate transistor. A triple-gate transistor has a higher withstand voltage between terminals functioning as source or drain than a double-gate transistor. Therefore, they are even more reliable.

[0130] 15A and 15B may have a configuration in which four or more transistors are connected in series. Although Fig. 15A shows an example in which the double-gate structure is applied to an n-channel transistor, it can also be applied to a p-channel transistor.

[0131] Multi-gate transistors, including the double-gate and triple-gate transistors described above, are equivalent to transistors with a long channel length. Therefore, multi-gate transistors can reduce leakage current in an off state more than single-gate transistors. Therefore, using multi-gate transistors is effective for improving the display quality of the display device 100.

[0132] 1B, the wiring INI may be configured to be separate wirings for the transistors M15 and M17. For example, as in the pixel 10H illustrated in FIG. 16, the wiring connected to the transistor M15 may be a wiring INI_S, and the wiring connected to the transistor M17 may be a wiring INI.

[0133] By making the wiring INI and the wiring INI_S different wirings, the wiring INI is V ＩＮＩ , wiring INI_S to V ＩＮＩFor example, the wiring INI_S can be set to a potential higher than VSS by the threshold voltage of the light-emitting device 61 (the voltage at which a current starts to flow through the light-emitting device 61), thereby initializing the potential of the first terminal of the light-emitting device 61 that functions as an anode.

[0134] Furthermore, by dividing the wiring INI into two wirings, the wirings can have different functions, for example, one as a signal line and the other as a wiring for applying a constant potential. The added wiring INI_S can be used as a monitor line for flowing a current between the pixel 10H and the outside.

[0135] For example, to correct variations in electrical characteristics, such as field-effect mobility, of the transistor M13 included in the pixel 10H between pixels, the transistors M12, M13, M14, and M15 are turned on and the other transistors are turned off, and the potential of the wiring ELVSS is set to VDD (ELVSS=VDD) and the potential of the wiring INI_S is set to VSS (INI_S=VSS) (see FIG. 17A). As shown in FIG. 17A, a configuration can be used in which the current flowing through the transistor M13 flows to the wiring INI_S. With this configuration, the current flowing through the transistor M13 can be measured outside the pixel 10H. The electrical characteristics, such as the field-effect mobility, of the transistor M13 can be obtained from the relationship between the potential of the node ND1 and the value of the current flowing through the wiring INI_S.

[0136] As described with reference to FIGS. 3B and 4B, in one aspect of the present invention, VSS of the wiring ELVSS is ＩＮＩ Therefore, a current flowing through the transistor M13 can flow to the wiring INI_S without switching the potential of the wiring ELVSS to VDD. With this configuration, it is not necessary to switch the potential of the wiring ELVSS to VDD, which leads to low power consumption.

[0137] Furthermore, for example, when correcting variations in the electrical characteristics of the light-emitting device 61 of pixel 10H between pixels, all transistors except for transistor M15 are turned off, the potential of the wiring ELVSS is set to VSS (ELVSS=VSS), and the potential of the wiring INI_S is set to VDD (INI_S=VDD) (see FIG. 17B ). As shown in FIG. 17B , a configuration can be adopted in which a current flows from the wiring INI_S to the light-emitting device 61. This configuration allows the current flowing through the light-emitting device 61 to be measured outside the pixel 10H. Furthermore, since the characteristic fluctuations of the light-emitting device can be monitored, the characteristics of the light-emitting device can also be corrected.

[0138] The current acquired using the wiring INI_S as a monitor line can be output to an external device by converting it into an analog voltage or a digital signal, for example. The external device uses the analog voltage or the digital signal to output a data voltage V ＤＡ correction (also called external correction).

[0139] By performing not only internal correction but also both internal and external correction, the display quality of the display device can be further improved. Note that internal correction is preferably performed every time an image is rewritten. On the other hand, external correction requires a longer processing time than internal correction, so it does not have to be performed every time an image is rewritten. For example, external correction may be performed only during a predetermined period.

[0140] 3A and 4A, the potential (low-level potential of the control signal) applied to the back gate when turning off the OS transistor is V ＩＮＩ For example, VSS of the wiring ELVSS can be used as a potential (low-level potential of the control signal) applied to the back gate when turning off the OS transistor (see FIG. 18A).

[0141] In this case, V of the wiring INI ＩＮＩ is set higher than VSS of the wiring ELVSS (see FIG. 18B). ＩＮＩThe voltage (potential difference) between VSS and VSS is set to be equal to or lower than the threshold voltage of the light-emitting device 61 (the voltage at which a current starts to flow through the light-emitting device 61). ＩＮＩ If the potential is lower, current flow through the light emitting device 61 can be prevented.

[0142] 3A and 4A, the control signal applied to the back gate of the OS transistor when turning it off is described as having the same logic as the control signal applied to the gate of the OS transistor, but other configurations are also possible. ＩＮＩ It is also possible to provide a configuration that gives:

[0143] For example, in the pixel 10I shown in FIG. 19A, the wiring INI is connected to the back gates of the transistors M16 and M17 described in the pixel 10 of FIG. 1B. ＩＮＩ is the VSS of the wiring ELVSS and the data voltage V of the wiring DL ＤＡ By adopting this configuration, even in the on state, the back gate is ＩＮＩ Although the potential applied to the back gate of the OS transistor is added, the potential can be set to be equal to or lower than the source potential of the transistors M16 and M17. ＩＮＩ Therefore, the voltage between the back gate and the source of the transistors M16 and M17 can be set to 0 V or less. This can suppress fluctuations in the threshold voltage of the transistors M16 and M17, thereby improving the long-term reliability of the transistors. Therefore, the reliability of a display device including these transistors can be improved.

[0144] 1A, the wirings GI_BG and GC_BG for supplying control signals to the back gates of the OS transistors can be omitted. The configuration of the display device 100I when the wirings GI_BG and GC_BG are omitted is illustrated in FIG. 19B. By applying the pixel 10I to the subpixels 10_R, 10_G, and 10_B of the pixel 11 as illustrated in FIG. 19B, the number of wirings in the display unit 20 can be reduced, thereby improving either or both of the resolution and definition of the display device 100I.

[0145] <Configuration Example 2 of Display Device> Next, a configuration example different from the configuration example of the display device described above will be described. Note that in the following description of Figures 20A to 29B, repeated description of parts common to Figures 1A to 19B may be omitted.

[0146] 20A is a block diagram illustrating a display device of one embodiment of the present invention. A display device 100A illustrated in FIG. 20A includes, for example, a display portion 20, a gate line side driver circuit 33, a gate line side driver circuit 32, an integrated circuit 40, and the like.

[0147] The pixel 11 is connected to the wiring GN_k-1, the wiring GNBG_k-1, the wiring GP_k-1, the wiring EM_k, the wiring GN_k, the wiring GNBG_k, the wiring GP_k, the wiring DLR, the wiring DLG, and the wiring DLB. The wiring DLR, the wiring DLG, and the wiring DLB function as data lines.

[0148] The wirings GN_k, GNBG_k, GP_k, and EM_k function as gate lines in the kth row (k is an integer). The wirings GN_k-1, GNBG_k-1, and GP_k-1 function as gate lines in the k-1th row. Therefore, in the pixel 11 of FIG. 20A , the pixel 11 in the kth row is connected to the gate line in the kth row and also to the gate line in the k-1th row. The gate line in the kth row and the gate line in the k-1th row are each supplied with control signals from the gate line side driver circuit 33, with the timing of pixel selection shifted. Therefore, the display device of FIG. 20A can reduce the number of gate lines in the display unit and the number of gate line side driver circuits.

[0149] 20B shows an example of a circuit diagram of a subpixel (hereinafter referred to as pixel 10J) that can be used for the subpixels 10_R, 10_G, and 10_B of the display device 100A. Like the pixel 10 described in FIG. 1B , the pixel 10J includes transistors M11 to M17, a capacitor C1, and a light-emitting device 61. The transistors included in the pixel 10J shown in FIG. 20B are connected to wirings GN_k-1, GNBG_k-1, GP_k-1, EM_k, GN_k, GNBG_k, GP_k, DL, ELVDD, ELVSS, and INI.

[0150] 1B , the pixel 10J according to one embodiment of the present invention has the following characteristics: the gates and back gates of the transistors M16 and M17 are arranged to sandwich the channel formation region of the semiconductor layer, etc. Therefore, like the pixel 10 described in FIG. 1B , the pixel 10J can be a display device with excellent reliability.

[0151] The source and drain of each transistor in pixel 10J are the same as those in pixel 10 described in FIG. 1B. Specifically, transistors M11 to M17 are connected as shown in FIG. 20B. Furthermore, the terminals of capacitive element C1 and light-emitting device 61 in pixel 10J are the same as those in pixel 10 described in FIG. 1B. Specifically, capacitive element C1 and light-emitting device 61 are connected as shown in FIG. 20B.

[0152] The gate of the transistor M11 included in the pixel 10J is connected to the wiring GP_k. The gate of the transistor M12 is connected to the wiring EM_k. The gate of the transistor M14 is connected to the wiring EM_k. The gate of the transistor M15 is connected to the wiring GP_k-1. The gate of the transistor M16 is connected to the wiring GN_k. The back gate of the transistor M16 is connected to the wiring GNBG_k. The gate of the transistor M17 is connected to the wiring GN_k-1. The back gate of the transistor M17 is connected to the wiring GNBG_k-1.

[0153] The control signal supplied to the wiring GP_k in the kth row is a signal that controls the on / off state of the transistor M11. For example, the control signal supplied to the wiring GP_k controls whether or not the data voltage supplied to the wiring DL is written to the pixel 10. For example, the transistor M11, which is a p-channel transistor, is turned off when the control signal supplied to the wiring GP_k is at H level, and turned on when the control signal supplied to the wiring GW is at L level.

[0154] The control signal supplied to the wiring GP_k-1 in the k-1th row is a signal that controls the on / off state of the transistor M15. For example, the control signal supplied to the wiring GP_k-1 controls the potential of the first terminal of the light-emitting device 61 functioning as an anode to V ＩＮＩ For example, the transistor M15, which is a p-channel transistor, is turned off when a control signal supplied to the wiring GP_k-1 is at H level and turned on when a control signal supplied to the wiring GB is at L level.

[0155] The control signal supplied to the wiring EM_k in the kth row is a signal that controls the on or off state of the transistor M12 and the transistor M14. For example, the control signal supplied to the wiring EM controls the current path that flows between the wiring ELVDD and the wiring ELVSS. For example, the transistors M12 and M14, which are p-channel transistors, are turned off when the control signal supplied to the wiring EM is at an H level, and turned on when the control signal supplied to the wiring EM is at an L level.

[0156] The control signal supplied to the wiring GN_k on the kth row and the control signal supplied to the wiring GNBG_k on the kth row are signals that control the on / off state of the transistor M16. For example, the control signal supplied to the wiring GN_k and the control signal supplied to the wiring GNBG_k control whether the potential of the gate of the transistor M13 is set to the potential of the other of the source or drain of the transistor M13. For example, the transistor M16, which is an n-channel transistor, is turned on when the control signal supplied to the wiring GN_k and the control signal supplied to the wiring GNBG_k are both H level, and turned off when the control signal supplied to the wiring GN_k and the control signal supplied to the wiring GNBG_k are both L level.

[0157] A control signal supplied to the wiring GN_k-1 in the k-1th row and a control signal supplied to the wiring GNBG_k-1 in the k-1th row are signals that control the on / off state of the transistor M17. For example, the control signal supplied to the wiring GN_k-1 and the control signal supplied to the wiring GI_BG controls the potential of the gate of the transistor M13 to V ＩＮＩ For example, the transistor M17, which is an n-channel transistor, is turned on when the control signal supplied to the wiring GN_k-1 and the control signal supplied to the wiring GNBG_k-1 are both at H level, and turned off when the control signal supplied to the wiring GN_k-1 and the control signal supplied to the wiring GNBG_k-1 are both at L level.

[0158] FIG. 21 illustrates wirings GN (GN_k-2 to GN_k), GNBG (GNBG_k-2 to GNBG_k), GP (GP_k-2 to GP_k), and EM (EM_k-1 and EM_k) when pixel 10J_k-1 is the pixel 10J provided in the k-1th row and pixel 10J_k is the pixel 10J provided in the kth row.

[0159] 21, the wirings GP_k-1, GN_k-1, and GNBG_k-1 arranged between the pixel 10J and the pixel 10J_k-1 are connected to transistors in both the pixel 10J and the pixel 10J_k-1, which allows the number of wirings to be reduced compared to the configuration of the pixel 10 described in FIG.

[0160] FIG. 22 also illustrates wirings GN (GN_k-2 to GN_k), GNBG (GNBG_k-2 to GNBG_k), GP (GP_k-2 to GP_k), and EM (EM_k-1 and EM_k) when the pixel 10J provided in the k-1th row is a pixel 10J_k-1, and the pixel 10J provided in the kth row is a pixel 10J_k, and a gate line side driver circuit 33 that outputs control signals to the wirings GN, GNBG, and GP.

[0161] 22 shows a circuit diagram in which the configuration described in Fig. 3A is applied as an example of the configuration of the shift register and buffer that output control signals to the wirings GN, GNBG, and GP in the k-1th and kth rows. The configuration described in Fig. 4A can also be applied to the gate line side drive circuit 33 in Fig. 22. Fig. 22 shows a pulse output circuit PO_k-1 provided in the k-1th row, a pulse output circuit PO_k provided in the kth row, and buffers BUF1 to BUF3 provided in each row.

[0162] 22 outputs control signals at different timings to gates of p-channel transistors M11 and M15 via wirings GP_k and GP_k−1. As shown in FIG. 22 , the buffer BUF1 is supplied with VH1 as a potential that provides an H level and VL1 (<VH1) as a potential that provides an L level.

[0163] 22 outputs control signals at different timings to gates of n-channel transistors M16 and M17 via wirings GN_k and GC_k−1. As shown in FIG. 22 , the buffer BUF2 is supplied with VH2 as a potential that provides an H level and VL2 (<VH2) as a potential that provides an L level.

[0164] 22 outputs control signals at different timings to the back gates of n-channel transistors M16 and M17 via the wiring GNBG_k and the wiring GNBG_k−1. ＩＮＩ (<VH2) is supplied.

[0165] Note that the buffer BUF3 shown in FIG. ＩＮＩ The wiring that supplies V can be the wiring INI connected to the pixel 10J. In FIG. 23, the wiring INI connected to the pixels 10J_k−1 and 10J_k supplies V of the buffer BUF3. ＩＮＩ 3B, the wiring for supplying V is used. By using this configuration, it is possible to achieve a configuration without increasing the number of potentials required as low-level potentials to be supplied to the buffer BUF3. ＩＮＩ can be set to a potential several volts lower than VSS. Therefore, the low-level potential applied to the back gates of the OS transistors of the pixels 10J_k-1 and 10J_k is not set to a potential that is lower than necessary. This prevents the amplitude voltage of the control signal applied to the back gate from becoming larger than necessary.

[0166] 20B and the pixels 10J_k-1 and 10J_k shown in FIGS. 21 to 23 can be appropriately combined with modified examples of the pixels described in FIGS. 12A and 19B. For example, as in the pixel 10G described in FIG. 15, double-gate transistors can be applied as the transistors M16 and M17. This configuration has multiple transistors connected in series, which can increase the withstand voltage between terminals that function as sources or drains, thereby improving the reliability of the display device.

[0167] <Operation Example 2 of Display Device> Next, an operation example of the pixel 10J applicable to the display device 100A of one embodiment of the present invention will be described. FIG. 24 is a timing chart illustrating an operation example of the pixel 10J. FIG. 24 illustrates waveforms of control signals supplied to the wirings GN_k-1, GNBG_k-1, GP_k-1, EM_k, GN_k, GNBG_k, and GP_k connected to the pixel 10J, and changes in the potential at the node ND1. FIGS. 25A to 29B also illustrate a schematic diagram of the operation of the pixel 10J during the periods T21 to T25 illustrated in FIG. 24 and a timing chart. Note that in the following descriptions of FIGS. 25A and 29B, repeated description of parts common to the description of the operation examples in FIGS. 7A to 11B may be omitted.

[0168] For ease of understanding, the potentials of the control signals supplied to the wirings GN_k-1, GNBG_k-1, GP_k-1, EM_k, GN_k, GNBG_k, and GP_k, and the potentials of the wirings to which a constant potential is supplied, can be configured as described with reference to Figures 3A and 3B. For example, an amplitude voltage of VH1 and VL1 is applied to the gate of a p-channel transistor, an amplitude voltage of VH2 and VL2 is applied to the gate of an n-channel transistor, and an amplitude voltage of VH2 and VL3 is applied to the back gate of an n-channel transistor. ＩＮＩ 24. In the timing chart shown in FIG. 24, it is also possible to apply the configuration in which the amplitude voltage control signal is the one described with reference to FIGS. 4A and 4B.

[0169] In an initial state, VL2 is supplied to the wiring GN_k and the wiring GN_k-1, VL1 is supplied to the wiring EM_k, and VH1 is supplied to the wiring GP_k and the wiring GP_k-1. Therefore, the transistors M11, M15, M16, and M17 are in an off state, and the transistors M12 and M14 are in an on state. In addition, when the potential of the node ND1 is equal to or higher than the data voltage V ＤＡ +Vth, and the transistor M13 is in an on state. Note that since the transistor M13 of the pixel 10J shown in FIG. 20B is a p-channel transistor, the Vth of the transistor M13 is negative (a voltage lower than the reference voltage). Therefore, the data voltage V ＤＡ +Vth is the data voltage V ＤＡ is a lower potential than

[0170] [Period T21] During period T21, VH1 is supplied to the wiring EM_k (see FIGS. 25A and 25B). As a result, the transistors M11 to M17 are turned off. The current path between the wiring ELVDD and the wiring ELVSS is cut off. As a result, the light-emitting device 61 stops emitting light.

[0171] [Period T22] During period T22, VH2 is supplied to the wiring GN_k-1 and the wiring GNBG_k-1, and VL1 is supplied to the wiring GP_k-1 (see FIGS. 26A and 26B). When VH2 is supplied to the wiring GN_k-1 and the wiring GNBG_k-1, the transistor M17 is turned on, and VL1 of the wiring INI is supplied to the node ND1. ＩＮＩ is supplied.

[0172] When VL1 is supplied to the wiring GP_k-1, the transistor M15 is turned on. ＩＮＩ is supplied.

[0173] [Period T23] During period T23, VL2 is supplied to the wiring GN_k-1, and V ＩＮＩis supplied to the wiring GP_k, and VH1 is supplied to the wiring GP_k−1 (see FIGS. 27A and 27B ). Then, the transistors M17 and M15 are turned off. Furthermore, VL1 is supplied to the wiring GP_k, VH2 is supplied to the wiring GN_k, and VH2 is supplied to the wiring GNBG_k.

[0174] When VL1 is supplied to the wiring GP_k, the transistor M11 is turned on, and the data voltage V ＤＡ When VH2 is supplied to the wirings GN_k and GNBG_k, the transistor M16 is turned on. Since the transistor M13 is also turned on, the data voltage V ＤＡ Therefore, the potential of the node ND1 rises.

[0175] The potential rise of the node ND1 is the data voltage V ＤＡ +Vth (see FIG. 24). ＤＡ When the potential of the node ND1 reaches +Vth, the transistor M13 is turned off, and the potential rise of the node ND1 ends.

[0176] [Period T24] During period T24, VH1 is supplied to the wiring GP_k, VL2 is supplied to the wiring GN_k, and V ＩＮＩ When VH1 is supplied to the wiring GP_k, the transistor M11 is turned off. When VL2 is supplied to the wiring GN_k, and when V ＩＮＩ When this voltage is supplied, the transistor M16 is turned off and the potential of the node ND1 is maintained (ND1=V ＤＡ +Vth). In this way, the data voltage V ＤＡ When the transistor M13 functioning as a driving transistor is a p-channel transistor, the data voltage V ＤＡ +Vth is a potential equal to or lower than Vth.

[0177] [Period T25] During period T25, VL1 is supplied to the wiring EM_k (see FIGS. 29A and 29B). When VL1 is supplied to the wiring EM, the transistors M12 and M14 are turned on. Here, the data voltage (ND1=V ＤＡ +Vth) is at a potential equal to or lower than Vth, and the VDD of the wiring ELVDD is at a potential higher than the data voltage, so the transistor M13 is turned on. In this way, a current flows from the wiring ELVDD to the wiring ELVSS via the transistors M12, M13, and M14 and the light-emitting device 61. The value of the current flowing from the wiring ELVDD to the wiring ELVSS is determined by the potential of the node ND1. The pixel 10J_k applies to the node ND1 a data voltage V corrected by the Vth of the transistor M13, which functions as a drive transistor. ＤＡ Since the data voltage V ＤＡ Therefore, a current having an accurate current value according to the current value can be passed through the light-emitting device 61.

[0178] As shown in the above operation example, the pixels included in the display device according to one embodiment of the present invention can correct the Vth of the driving transistor for each pixel (also referred to as "internal correction"). Therefore, the display device according to one embodiment of the present invention can correct variations in the Vth of the driving transistor between pixels. Furthermore, the influence of hysteresis of the driving transistor can be suppressed. By using the display device according to one embodiment of the present invention, the display quality of the display portion can be improved.

[0179] In addition, in the pixel 10, the data voltage V ＤＡ The holding of the data voltage V and the correction of the Vth of the driving transistor are performed simultaneously. ＤＡ This allows for faster operation than pixels in which the holding of the first and second signals is performed in separate operations.

[0180] <Configuration Example 3 of Display Device> Next, a configuration example different from the display device described above will be described. Note that in the following description of Figures 30 to 42B, repeated description of parts common to Figures 1A to 29B may be omitted.

[0181] 30 is a block diagram illustrating a display device of one embodiment of the present invention. A display device 100C illustrated in FIG. 30 includes, for example, a display portion 20, a gate line side driver circuit 34, a gate line side driver circuit 35, a gate line side driver circuit 36, an integrated circuit 40, and the like. The display portion 20 includes a pixel 10P that functions as a subpixel. The gate line side driver circuit 34 includes a shift register 38 that includes a plurality of unit circuits 39.

[0182] 31 shows a pixel circuit configuration applicable to the pixel 10P shown in FIG. 30. The pixel 10P includes a transistor M41, a transistor M42, a transistor M43, a transistor M44, a transistor M45, a transistor M46, a capacitance element C41, and a light-emitting device 61.

[0183] The pixel 10P is connected to the wiring GI, the wiring GI_BG, the wiring GW, the wiring EM1, the wiring EM2, the wiring DL, the wiring ELVDD, the wiring ELVSS, and the wiring INI2.

[0184] The lines GI, GI_BG, GW, EM1, and EM2 function as gate lines. The line DL functions as a data line. The lines GI and GI_BG are connected to a gate line side drive circuit 34. The line GW is connected to a gate line side drive circuit 35. The lines EM1 and EM2 are connected to a gate line side drive circuit 36.

[0185] VDD is supplied to the wiring ELVDD, and VSS is supplied to the wiring ELVSS. That is, in the pixel 10P, a current flows from the wiring ELVDD to the wiring ELVSS via the transistors M42, M43, and M44 to the light-emitting device 61. With this configuration, light emission of the light-emitting device 61 can be controlled in accordance with the drain current of the transistor M43 during the light-emitting period (the period during which the transistors M42 and M44 are turned on).

[0186] The wiring INI2 is supplied with an initialization potential V ＩＮＩ２ (V ＩＮＩ２ (also called) is supplied. ＩＮＩ２is a constant potential applied to one electrode of the capacitance element C41 in order to maintain the potential of the gate of the transistor M43 to which one electrode of the capacitance element C41 is connected. ＩＮＩ２ can be used as a potential to make the light emitting device 61 non-emitting by applying it as an anode potential of the light emitting device 61. ＩＮＩ２ can be used as a potential for initializing the potential of the anode of the light-emitting device 61.

[0187] The transistors M41, M42, M44, M45, and M46 function as switches, and the transistor M43 functions as a drive transistor.

[0188] The transistors M41, M42, M44, M45, and M46 have a function of setting the gate (node ​​ND2) of the transistor M43, which is used to pass current through the light-emitting device 61, to a potential corresponding to the data voltage. The transistor M46 has a function of maintaining a potential corresponding to the data voltage maintained at the node ND2 by being turned off.

[0189] The transistors M41 to M45 are preferably LTPS transistors. Alternatively, the transistors M41 to M45 are preferably LTPI transistors which are high-mobility oxide semiconductors with excellent crystallinity. By using the LTPS transistors or LTPI transistors as the transistors M41 to M45, the transistors can have high field-effect mobility and favorable frequency characteristics.

[0190] It is preferable to use n-channel transistors for the transistors M41 to M45. N-channel transistors are preferable because they have higher field-effect mobility than p-channel transistors. Furthermore, the use of n-channel transistors allows the application of the above-described LTPI transistor. Although not shown, the transistors M41 to M45 can also have a backgate. This configuration allows the transistors to have excellent electrical characteristics in a saturation region (also referred to as "saturation characteristics"). The backgate of the transistors M41 to M45 can be configured to supply the same signal as the gate, or can be connected to one or both of the source and drain. This configuration allows the transistors to have excellent electrical characteristics, such as saturation characteristics.

[0191] The transistor M46 included in the pixel 10P can be an n-channel OS transistor having a back gate. Alternatively, the transistor M46 can be an LTPI transistor as an n-channel transistor having a back gate. FIG. 31 illustrates a circuit configuration in which a transistor having a back gate is used as the transistor M46.

[0192] The pixel 10P may have a circuit configuration in which all transistors are n-channel transistors. For example, the transistors M41 to M46 may all be LTPS transistors, LTPI transistors, or OS transistors. In this case, the number of steps for manufacturing the transistors can be reduced compared to when an LTPO structure including LTPS transistors and OS transistors is used.

[0193] In one embodiment of the present invention, the gate and back gate of the transistor M46 included in the pixel 10P are arranged opposite to each other with a channel formation region of the semiconductor layer sandwiched therebetween. In addition, the control signal applied to the gate of the transistor M46 and the control signal applied to the back gate of the transistor M46 are signals of the same logic. In addition, the potential applied to the back gate when turning off the transistor M46 (the low-level potential of the control signal) is different from the low-level potential of the control signal applied to the gate when turning off the transistor M46. Specifically, the potential V of the wiring INI2 ＩＮＩ２ is the potential VSS of the wiring ELVSS and the data voltage V of the wiring DL. ＤＡ The potential (low level potential of the control signal) applied to the back gate when the transistor M46 is turned off is set to the potential V ＩＮＩ２ A potential below, preferably a potential V ＩＮＩ２ The gate of the transistor M46 may be referred to as the first gate, and the back gate of the transistor M46 may be referred to as the second gate.

[0194] With this configuration, the potential of the control signal applied to the back gate of the transistor M46 can be set lower than the potential (low-level potential) of the control signal applied to the gate of the transistor M46. For an n-channel OS transistor, the threshold voltage can be shifted in the positive direction by setting the potential applied to the back gate lower than the potential (low-level potential) applied to the gate. Therefore, even when the OS transistor is driven at a significantly lower frame frequency, fluctuations in the gate potential of the transistor M46 can be suppressed, resulting in a display device with excellent display quality.

[0195] In addition, with this configuration, the low-level potential of the control signal applied to the back gate of the transistor M46 is the potential V ＩＮＩ２ Therefore, it is possible to configure the low-level potential of the control signal to be applied to the back gate of the transistor M46 without increasing the number of potentials required. ＩＮＩ２can be set to a potential that is several volts lower than the potential VSS (for example, the threshold voltage of the light-emitting device 61 (the voltage at which current begins to flow through the light-emitting device 61)). Therefore, the low-level potential that is applied to the back gate of the transistor M46 is not set to a potential that is lower than necessary. Therefore, it is possible to prevent the amplitude voltage of the control signal that is applied to the back gate from becoming larger than necessary.

[0196] Furthermore, with this configuration, the semiconductor layer having the channel formation region of the transistor M46 is sandwiched between the gate and the back gate, making it difficult for an electric field generated outside the transistor M46 to act on the channel formation region. Therefore, providing a back gate to the transistor M46 stabilizes its operation. Furthermore, providing a back gate to the transistor M46 reduces variations in characteristics among multiple transistors. Providing a back gate to the transistor M46 also improves reliability. Therefore, the reliability of a display device including the transistor M46 can be improved.

[0197] Furthermore, this structure allows a light-blocking conductive material to be provided on both the gate and back gate of the transistor M46. When the channel formation region of the transistor M46 is irradiated with light, the electrical characteristics may fluctuate. Furthermore, when the channel formation region of the transistor M46 is irradiated with light while a voltage is applied to the transistor M46, the electrical characteristics may deteriorate. In other words, the reliability of the transistor M46 may decrease. By using a light-blocking conductive material on both the gate and back gate, deterioration of the electrical characteristics of the transistor M46 can be suppressed and the reliability can be improved.

[0198] Furthermore, with this configuration, when the transistor M46 is turned on, a potential for controlling the on state of the transistor M46 can be supplied from both the gate and the back gate. By supplying a potential that turns on the transistor M46 to both the gate and the back gate, the on-state current can be increased compared to when a potential is supplied to only one of them.

[0199] As shown in FIG. 31 , each transistor included in the pixel 10P is connected to each wiring. One of the source or drain of the transistor M41 is connected to the wiring DL. The other of the source or drain of the transistor M41 is connected to one of the source or drain of the transistor M43 and one of the source or drain of the transistor M44. One of the source or drain of the transistor M42 is connected to the wiring ELVDD. The other of the source or drain of the transistor M42 is connected to the other of the source or drain of the transistor M43 and one of the source or drain of the transistor M46. The other of the source or drain of the transistor M44 is connected to one of the source or drain of the transistor M45, one electrode of the capacitance element C41, and the first terminal of the light-emitting device 61. The second terminal of the light-emitting device 61 is connected to the wiring ELVSS. The other of the source or drain of the transistor M45 is connected to the wiring INI2. The other of the source and the drain of the transistor M46 is connected to the gate of the transistor M43 and the other electrode of the capacitive element C41.

[0200] The gate of transistor M41 is connected to wiring GW. The gate of transistor M42 is connected to wiring EM2. The gate of transistor M44 is connected to wiring EM1. The gate of transistor M45 is connected to wiring GI. The gate of transistor M46 is connected to wiring GI. The back gate of transistor M46 is connected to wiring GI_BG.

[0201] The control signal supplied to the wiring GW is a signal that controls the on / off state of the transistor M41. For example, the control signal supplied to the wiring GW controls whether or not the data voltage supplied to the wiring DL is written to the pixel 10P. For example, the transistor M41, which is an n-channel transistor, is turned on when the control signal is at an H level and turned off when the control signal is at an L level.

[0202] The control signal supplied to the wiring EM1 is a signal that controls the on / off state of the transistor M44. The control signal supplied to the wiring EM2 is a signal that controls the on / off state of the transistor M42. For example, the control signals supplied to the wirings EM1 and EM2 control the current path that flows between the wirings ELVDD and ELVSS. For example, the transistors M42 and M44, which are n-channel transistors, are turned on when the control signal is at H level and turned off when the control signal is at L level.

[0203] Furthermore, the control signal supplied to the wiring EM2 is a signal that initializes the potential of the node ND2. For example, during a period when the transistors M46 and M42 are in the on state, the potential VDD of the wiring ELVDD is supplied to the node ND2 to perform initialization. This initialization can be configured to apply a constant voltage between the gate and source of the transistor M46. Therefore, when the gate potential of the transistor M46 differs for each pixel depending on the data voltage written, the effect of hysteresis, in which the electrical characteristics of the transistor M43 fluctuate depending on the state of the potential held at the node ND2, can be mitigated.

[0204] The control signal supplied to the wiring GI and the control signal supplied to the wiring GI_BG are signals that control the on / off state of the transistor M46. For example, the control signal supplied to the wiring GI and the control signal supplied to the wiring GI_BG control whether the potential of the gate of the transistor M46 is set to the potential of the other of the source or drain of the transistor M46. The transistor M46, which is an n-channel transistor, is turned on when the control signal supplied to the wiring GI and the control signal supplied to the wiring GI_BG are both at H level, and is turned off when the control signal supplied to the wiring GI and the control signal supplied to the wiring GI_BG are both at L level.

[0205] 32A is an example of a block diagram of a unit circuit 39 included in the gate line side driver circuit 34 that outputs control signals to the above-mentioned wirings GI and GI_BG. The unit circuit 39 includes a pulse output circuit PO and buffers BUF1 and BUF2.

[0206] In the unit circuit 39, the pulse output circuit PO outputs a pulse signal in response to a clock signal, a start pulse, etc. The buffer BUF1 outputs the output signal of the pulse output circuit PO to the wiring GI as a control signal of an amplitude voltage between the potentials VH3 and VL3. The buffer BUF2 outputs the output signal of the pulse output circuit PO to the wiring GI_BG as a control signal of an amplitude voltage between the potentials VH3 and VSS2.

[0207] VH3 is a potential equal to or higher than VDD supplied to the wiring ELVDD of the pixel 10P. VL3 is a potential equal to or higher than VSS supplied to the wiring ELVSS of the pixel 10P. VSS2 is a potential lower than VL3, preferably a potential VSS2 supplied to the wiring INI2 of the pixel 10P. ＩＮＩ２ Hereinafter, more preferably, the potential V of the wiring INI2 ＩＮＩ２ With this configuration, the amplitude voltage of the control signal supplied from the buffer BUF1 to the wiring GI can be made different from the amplitude voltage of the control signal supplied from the buffer BUF2 to the wiring GI_BG.

[0208] The amplitude voltage of the control signals output from the buffers BUF1 and BUF2 will be described.

[0209] 32B is a waveform diagram illustrating the amplitude voltage of the control signal output by the buffer BUF1 of FIG. 32A. The control signal output by the buffer BUF1 is output to the wiring GI. As shown in FIGS. 32A and 32B, the buffer BUF1 is supplied with VH3 as a potential that provides an H level and VL3 as a potential that provides an L level. VH3 is a potential that is applied to the gate of an n-channel transistor to turn it on. VL3 is a potential that is applied to the gate of an n-channel transistor to turn it off.

[0210] 32C is a waveform diagram illustrating the amplitude voltage of the control signal output by the buffer BUF2 in FIG. 32A. The control signal output by the buffer BUF2 is output to the wiring GI_BG. As shown in FIGS. 32A and 32C, VH3 is a potential that provides an H level, and VSS2 is a potential that provides an L level, to the buffer BUF2. VH3 is a potential that is applied to the gate of an n-channel transistor to turn it on. The potential VSS2 is a potential that is applied to the gate of an n-channel transistor to turn it off, and is a potential lower than VL3. With this configuration, the potential V of the wiring INI2 is applied as VSS2. ＩＮＩ２ The potential V ＩＮＩ２ This is preferable because the potential VSS2 can be set to be lower than the potential VSS of the wiring ELVSS and can be used without increasing the number of potentials to be applied to VSS2.

[0211] As shown in the waveform diagram of FIG. 32B, the control signal on the wiring GI is a selection signal of amplitude voltage Am4 according to VH3 and VL3 during the selection period P ＳＥＬ The control signal on the wiring GI_BG is supplied to the gate of the transistor M46 during the selection period P as shown in the waveform diagram of FIG. 32C. ＳＥＬ The control signal Am4 is supplied to the back gate of the transistor M46 in the ON state. This configuration ensures that the transistor M46 can be turned on without increasing the amplitude voltage Am4 to be greater than the amplitude voltage Am5. Furthermore, the amplitude voltage Am4 of the control signal on the wiring GI can be made smaller than when the control signal on the wiring GI_BG is also applied to the control signal on the wiring GI.

[0212] The low-level potential of the control signal on the wiring GI_BG is set to a potential lower than VL3 and VSS. With this configuration, the voltage between the back gate and source of the transistor M46 can be set to 0 V or less. This allows the threshold voltage of the transistor M46 to be shifted in the positive direction and fluctuations in the threshold voltage to be suppressed, thereby improving the long-term reliability of the transistor.

[0213] 33 is a block diagram of the shift register 38 included in the gate line side driver circuit 34 of the display device 100C described above. The shift register 38 shown in FIG. 33 includes unit circuits 39_1 to 39_m (m is an integer of 2 or more) as a plurality of unit circuits 39. The unit circuits 39_1 to 39_m are connected to wirings CKL1, CKL2, power supply lines VDL, VSL1, VSL2, LIN1, LIN2, GI, GI_BG, and GO3, respectively.

[0214] The wiring CKL1 is a wiring that transmits a clock signal CK1 to the unit circuits 39_1 to 39 — m provided in each row. The wiring CKL2 is a wiring that transmits a clock signal CK2 to the unit circuits 39_1 to 39 — m provided in each row. The wirings CKL1 and CKL2 may be referred to as clock signal lines. In the unit circuits 39_1 to 39 — m shown in FIG. 33 , terminals connected to the wirings CKL1 and CKL2 are shown as CK1 and CK2.

[0215] The power supply line VDL is a power supply line that transmits a power supply potential, for example, a potential VH3, to the unit circuits 39_1 to 39_m provided in each row. The power supply line VSL1 is a power supply line that transmits a power supply potential, for example, a potential VL3, to the unit circuits 39_1 to 39_m provided in each row. The power supply line VSL2 is a power supply line that transmits a power supply potential, for example, a potential VSS2, to the unit circuits 39_1 to 39_m provided in each row. In the unit circuits 39_1 to 39_m shown in FIG. 33 , the terminal connected to the power supply line VDL is shown as VDD1, the terminal connected to the power supply line VSL1 is shown as VSS1, and the terminal connected to the power supply line VSL2 is shown as VSS2.

[0216] The wiring LIN1 is a wiring that transmits a control signal, for example, a start pulse signal SP1, to the unit circuit 39_1 provided in the first row. The wiring LIN1 is sometimes referred to as a signal line. In the unit circuit 39_1 illustrated in FIG. 33, a terminal connected to the wiring LIN1 is illustrated as SP1. The wiring LIN2 is a wiring that transmits a control signal, for example, a start pulse signal SP2, to the unit circuit 39_1 provided in the first row. The wiring LIN2 is sometimes referred to as a signal line. In the unit circuit 39_1 illustrated in FIG. 33, a terminal connected to the wiring LIN2 is illustrated as SP2.

[0217] 33, in the unit circuits 39_2 to 39_m provided in the second row and thereafter, a signal output by the unit circuit 39 in the previous row functions as a start pulse signal. Therefore, terminals connected to the wirings GO3_1 to GO3_m-1 in the previous row are illustrated as SP1, and terminals connected to the wirings GI_1 to GI_m-1 in the previous row are illustrated as SP2.

[0218] The wirings GI_1 to GI_m are wirings that transmit output signals output by the unit circuits 39_1 to 39_m provided in each row. The wirings GI_BG_1 to GI_BG_m are wirings that transmit output signals output by the unit circuits 39_1 to 39_m provided in each row. The wirings GO3_1 to GO3_m are wirings that transmit output signals output by the unit circuits 39_1 to 39_m provided in each row. The wirings GI_1 to GI_m, the wirings GI_BG_1 to GI_BG_m, and the wirings GO3_1 to GO3_m may be referred to as output signal lines. In the unit circuits 39_1 to 39_m shown in FIG. 33, terminals connected to GI_BG_1 to GI_BG_m are illustrated as OUT1. In the unit circuits 39_1 to 39 — m shown in Fig. 33, terminals connected to GI_1 to GI_m are shown as OUT2. In the unit circuits 39_1 to 39 — m shown in Fig. 33, terminals connected to GO3_1 to GO3_m are shown as OUT3.

[0219] Fig. 34 is an example of a circuit diagram of a unit circuit 39 applicable to the unit circuits 39_1 to 39_m in Fig. 33. Fig. 35 is a timing chart illustrating the operation of the unit circuit 39 shown in the circuit diagram in Fig. 34.

[0220] The unit circuit 39 includes transistors M21 to M31 and capacitors C21 to C23. The unit circuit 39 is connected to the wirings CKL1, CKL2, power supply lines VDL, VSL1, VSL2, LIN1, LIN2, GI, GI_BG, and GO3 described in FIG. 33. The transistors M21 to M31 are n-channel transistors. LTPS transistors, LTPI transistors, or OS transistors can be used as the transistors M21 to M31.

[0221] In the unit circuit 39, the pulse output circuit PO corresponds to a circuit having transistors M25 to M31 and a capacitance element C23. The buffer BUF1 corresponds to a circuit having transistors M21 and M22 and a capacitance element C21. The buffer BUF2 corresponds to a circuit having transistors M23 and M24 and a capacitance element C22.

[0222] One of the source and the drain of transistor M21 is connected to wiring CKL1. The other of the source and the drain of transistor M21 is connected to one of the source and the drain of transistor M22, one electrode of capacitor C21, and wiring GI. The gate of transistor M21 is connected to one of the source and the drain of transistor M25, the gate of transistor M23, the other electrode of capacitor C21, and one electrode of capacitor C22. The other of the source and the drain of transistor M22 is connected to power supply line VSL1. The gate of transistor M22 is connected to the gate of transistor M24, one of the source and the drain of transistor M26, the gate of transistor M28, and one of the source and the drain of transistor M29. One of the source and the drain of transistor M23 is connected to wiring CKL1. The other of the source and the drain of transistor M23 is connected to one of the source and the drain of transistor M24, the other electrode of capacitor C22, and wiring GI_BG. The other of the source or drain of transistor M24 is connected to power supply line VSL2. The gate of transistor M25 is connected to power supply line VDL. The other of the source or drain of transistor M25 is connected to the gate of transistor M26, one of the source or drain of transistor M27, one of the source or drain of transistor M28, and wiring GO3. The other of the source or drain of transistor M26 is connected to power supply line VSL1. The other of the source or drain of transistor M27 is connected to power supply line VDL. The gate of transistor M27 is connected to wiring LIN1. The other of the source or drain of transistor M28 is connected to power supply line VSL1. The other of the source or drain of transistor M29 is connected to one electrode of capacitor C23 and wiring CKL2. The gate of transistor M29 is connected to one of the source or drain of transistor M30, one of the source or drain of transistor M31, and the other electrode of capacitor C23. The other of the source and the drain of the transistor M30 is connected to the power supply line VSL1, and the gate of the transistor M30 is connected to the line CKL1.The other of the source and the drain of the transistor M31 is connected to the power supply line VSL1, and the gate of the transistor M31 is connected to the line LIN2.

[0223] CKL1 shown in FIG. 35 is a clock signal supplied to the wiring CKL1. CKL2 shown in FIG. 35 is a clock signal supplied to the wiring CKL2. LIN1 shown in FIG. 35 is a control signal supplied to the wiring LIN1. LIN2 shown in FIG. 35 is a control signal supplied to the wiring LIN2. GI_BG shown in FIG. 35 is a control signal output to the wiring GI_BG. GI shown in FIG. 35 is a control signal output to the wiring GI. PO3 shown in FIG. 35 is a control signal output to the wiring GO3. Furthermore, in FIG. 35, periods T91 to T98 are added to explain the operation.

[0224] In the following description, the potential of the power supply line VDL is VH3, the potential of the power supply line VSL1 is VL3, and the potential of the power supply line VSL2 is VSS2. An n-channel transistor is turned on when the logic level of a signal applied to the gate is H level, and turned off when it is L level. Therefore, the logic level at which a transistor is turned on may be called an on level, and the logic level at which a transistor is turned off may be called an off level. The H level and L level potentials of clock signals, control signals, etc. are based on the potentials indicated in the drawings.

[0225] During period T91, CKL2 changes to H level, causing the gate of transistor M29 to go H level via capacitive element C23, turning transistor M29 on. As a result, transistors M22, M24, and M28 go on. Because transistor M28 is on, the gates of transistors M21 and M23 go L level via transistor M25. As a result, GI, GI_BG, and GO3 go L level.

[0226] During period T92, CKL1 changes to H level, turning transistor M30 on. The gate of transistor M29 goes L level, turning transistor M29 off. LIN1 is L level and transistor M27 is off, so the gates of transistors M22, M24, and M28 are held H level. Therefore, transistors M22, M24, and M28 remain on. Furthermore, the gate of transistor M26 remains L level, so transistor M26 remains off. Therefore, GI, GI_BG, and GO3 are held L level.

[0227] During period T93, CKL1 changes to the L level, turning transistor M30 off. CKL2 changes to the H level, but because LIN2 is at the H level, transistor M31 turns on and transistor M29 remains off. Because LIN1 goes to the H level, transistor M27 turns on. The gate of transistor M26 goes to the H level, turning transistor M26 on. The gates of transistors M22, M24, and M28 go to the L level. Therefore, transistors M22, M24, and M28 go off. Because transistor M27 goes on, the gates of transistors M21 and M23 go to the H level via transistor M25. Because CKL1 is at the L level, GI and GI_BG go to the L level, and GO3 goes to the H level.

[0228] During period T94, CKL1 changes to H level, turning transistor M30 on. The gate of transistor M29 goes L level, turning transistor M29 off. LIN1 is L level, turning transistor M27 off. The gate of transistor M26 remains H level, so transistor M26 remains on. The gates of transistors M22, M24, and M28 are held L level. Therefore, transistors M22, M24, and M28 remain off. The gates of transistors M21 and M23 remain H level. Because CKL1 is H level, GI, GI_BG, and GO3 are H level.

[0229] During period T95, CKL1 changes to the L level, turning transistor M30 off. CKL2 changes to the H level, but because LIN2 is at the H level, transistor M31 is turned on and transistor M29 remains off. Because LIN1 is at the H level, transistor M27 is turned on. The gate of transistor M26 is at the H level, turning transistor M26 on. The gates of transistors M22, M24, and M28 are at the L level. Therefore, transistors M22, M24, and M28 are turned off. Because transistor M27 is at the ON state, the gates of transistors M21 and M23 are at the H level via transistor M25. Because CKL1 is at the L level, GI and GI_BG are at the L level, and GO3 is at the H level.

[0230] During period T96, CKL1 changes to H level, turning transistor M30 on. The gate of transistor M29 goes L level, turning transistor M29 off. LIN1 is L level, turning transistor M27 off. The gate of transistor M26 remains H level, so transistor M26 remains on. The gates of transistors M22, M24, and M28 are held L level. Therefore, transistors M22, M24, and M28 remain off. The gates of transistors M21 and M23 remain H level. Because CKL1 is H level, GI, GI_BG, and GO3 are H level.

[0231] During period T97, CKL2 changes to the H level, causing the gate of transistor M29 to go H level via capacitive element C23, turning transistor M29 on. As a result, transistors M22, M24, and M28 go on. Because transistor M28 is on, the gates of transistors M21 and M23 go L level via transistor M25. As a result, GI, GI_BG, and GO3 go L level.

[0232] During period T98, CKL1 changes to H level, turning transistor M30 on. The gate of transistor M29 goes L level, turning transistor M29 off. LIN1 is L level and transistor M27 is off, so the gates of transistors M22, M24, and M28 are held H level. Therefore, transistors M22, M24, and M28 remain on. Furthermore, the gate of transistor M26 remains L level, so transistor M26 remains off. Therefore, GI, GI_BG, and GO3 are held L level.

[0233] The wiring INI2 connected to the pixel 10P can be used as the power supply line VSL2 connected to the unit circuit 39. Specifically, as shown in FIG. 36A, the wiring INI2 connected to the plurality of pixels 10P can be used as the power supply line connected to the terminal VSS2 of the unit circuit 39. The potential of the wiring INI2 is V ＩＮＩ２ is supplied. This is therefore suitable as the potential VSS2 to be supplied to the power supply line VSL2. Therefore, a configuration can be achieved in which the number of potentials required as the low-level potential of the control signal to be supplied to the back gate of the transistor M46 does not increase.

[0234] 36B shows a specific circuit diagram of the configuration shown in Fig. 36A. As shown in Fig. 36B, the wiring INI2 connected to the pixel 10P can be used as the power supply line VSL2 of the unit circuit 39. By arranging the wiring INI2 in a direction parallel to the wiring GI and the wiring GI_BG, it is possible to efficiently arrange the connections between the unit circuit 39 and the pixel 10P for each row.

[0235] <Operation Example 3 of Display Device> Next, an operation example of the pixel 10P applicable to the display device 100C of one embodiment of the present invention will be described. FIG. 37 is a timing chart illustrating an operation example of the pixel 10P described in FIG. 31 . FIG. 37 illustrates waveforms of control signals supplied to the wirings GI, GI_BG, GW, EM1, and EM2 connected to the pixel 10P, and changes in the potential at the node ND2. FIGS. 38A to 42B also illustrate schematic diagrams and timing charts of the operation of the pixel 10P during the periods T31 to T35 illustrated in FIG. 37 . Note that in the following descriptions of FIGS. 38A to 42B , repeated description of parts common to the descriptions of the operation examples in FIGS. 7A to 11B , 25A , and 29B may be omitted.

[0236] To facilitate understanding, the potentials of the control signals supplied to the wirings GI, GI_BG, GW, EM1, and EM2, and the potentials of the wirings to which a constant potential is supplied, can be configured as described in Figures 32A to 32C.

[0237] In the initial state, VL3 is supplied to the wiring GI and the wiring GW, and V ＩＮＩ２ is supplied to the wiring EM1 and the wiring EM2, and VH3 is supplied to the wiring EM1 and the wiring EM2. Therefore, the transistors M41, M45, and M46 are in the off state, and the transistors M42 and M44 are in the on state. In addition, the data voltage V ＤＡ V is the voltage according to ＤＡ Assume that +Vth+dV is held and the transistor M43 is in an on state.

[0238] [Period T31] During period T31, VH3 is supplied to the wirings GI and GI_BG, and VL3 is supplied to the wiring EM1 (see FIGS. 38A and 38B). As a result, the transistors M45 and M46 are turned on, and the transistor M44 is turned off. The current path between the wirings ELVDD and ELVSS is cut off. As a result, the light-emitting device 61 stops emitting light. The potential of the node ND2, which is one electrode of the capacitance element C41, is initialized to VDD. Furthermore, the other electrode of the capacitance element C41 is set to V ＩＮＩ２ The capacitance element C41 is initialized to a voltage VDD-V ＩＮＩ２ The operation in the period T31 is also called an initialization operation.

[0239] [Period T32] During period T32, VL3 is supplied to the wiring GI, and V ＩＮＩ２ is supplied to the wiring GW, VH3 is supplied to the wiring EM2, and VL3 is supplied to the wiring EM2 (see FIGS. 39A and 39B). The transistor M41 is turned on, and the transistors M42, M45, and M46 are turned off. The capacitance element C41 is connected to the voltage VDD-V ＩＮＩ２ is maintained, the potential of the source of the transistor M43 is the data voltage V ＤＡ The current flows through the transistor M43, and the voltage stress is applied to the transistor M43, thereby mitigating the influence of hysteresis of the transistor M43. The operation in the period T32 is also referred to as a voltage stress application operation.

[0240] [Period T33] During period T33, VH3 is supplied to the wirings GI and GI_BG (see FIGS. 40A and 40B). This turns on the transistors M45 and M46. The potential of the node ND2 is set to the data voltage V ＤＡ Since the potential of the node ND2 is higher than the data voltage V ＤＡ +Vth (see FIG. 37). ＤＡ When the potential reaches +Vth, the transistor M43 is turned off, and the potential drop at the node ND2 ends.

[0241] The potential of the node ND2 is V ＩＮＩ In this state, the voltage between the gate and source of the transistor M43 becomes Vth, which is the threshold voltage Vth. ＤＡ +Vth. The capacitance element C41 is connected to the voltage V ＤＡ +Vth-V ＩＮＩ２ is maintained. Since the influence of hysteresis is alleviated in the period T32, the variation in Vth between pixels is reduced. The operation in the period T33 is also called a data sampling operation.

[0242] [Period T34] During period T34, VL3 is supplied to the wiring GI, and V ＩＮＩ２ is supplied to the wiring GW, and VH3 is supplied to the wiring GW (see FIGS. 41A and 41B). The transistors M41, M42, M45, and M46 are turned off. The transistor M46 is turned off, and the potential of the node ND2 is maintained (ND2=V ＤＡ +Vth). In this way, the data voltage V ＤＡ The potential obtained by adding the Vth of the transistor M43 to the potential of the transistor M41 is maintained. The operation in the period T34 is also called a transition operation.

[0243] [Period T35] During period T35, VH3 is supplied to the wirings EM1 and EM2 (see FIGS. 42A and 42B). When VH3 is supplied to the wirings EM1 and EM2, the transistors M42 and M44 are turned on. Here, VSS of the wiring ELVSS is at a potential lower than VDD, and the potential held in the node ND2 (ND2=V ＤＡ When the potential difference (V+Vth) is greater than Vth, the transistor M43 is turned on. In this way, a current flows from the wiring ELVDD to the wiring ELVSS via the transistors M42, M43, and M44 and the light-emitting device 61. As a result of the current flow, the potential of the other electrode of the capacitance element C41 rises (for example, to +dV). One electrode of the capacitance element C41 on the node ND2 side is in an electrically floating state. Therefore, the potential of the node ND2 rises to V ＤＡ +Vth+dV. During this time, the capacitance element C41 ＤＡ +Vth-V ＩＮＩ２ Therefore, the data voltage V ＤＡTherefore, a current having an accurate current value according to the current value can be passed through the light-emitting device 61.

[0244] As shown in the above operation example, the pixels included in the display device according to one embodiment of the present invention can have the Vth of the driving transistor corrected for each pixel. Therefore, the display device according to one embodiment of the present invention can correct variations in the Vth of the driving transistor between pixels. Furthermore, the influence of hysteresis of the driving transistor can be suppressed. By using the display device according to one embodiment of the present invention, the display quality of the display portion can be improved.

[0245] In addition, in the pixel 10P, the data voltage V ＤＡ The holding of the data voltage V and the correction of the Vth of the driving transistor are performed simultaneously. ＤＡ This allows for faster operation than pixels in which the holding of the first and second signals is performed in separate operations.

[0246] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0247] Embodiment 2 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS. 43 to 52C.

[0248] <Perspective View and Cross-Sectional View of Display Device> Fig. 43 shows a perspective view of a display device 300A, and Fig. 44A shows a cross-sectional view of the display device 300A. Fig. 44B and Fig. 44C are diagrams illustrating structural examples of transistors in the cross-sectional view of Fig. 44A.

[0249] The display device 300A has a configuration in which a substrate 352 and a substrate 351 are bonded together. In Fig. 43, the substrate 352 is clearly indicated by a dashed line.

[0250] The display device 300A has a display portion 362, a connection portion 340, a gate line side driver circuit 364, wiring 365, etc. Fig. 43 shows an example in which an IC 373 and an FPC 372 are mounted on the display device 300A. Therefore, the configuration shown in Fig. 43 can also be said to be a display module having the display device 300A, an IC (integrated circuit), and an FPC.

[0251] The connection portion 340 is provided on the outside of the display portion 362. The connection portion 340 can be provided along one side or multiple sides of the display portion 362. The connection portion 340 may be single or multiple. FIG. 43 shows an example in which the connection portion 340 is provided so as to surround the four sides of the display portion. The connection portion 340 connects the common electrode of the light-emitting device to the conductive layer, thereby making it possible to supply a potential to the common electrode.

[0252] The gate line side driver circuit 364 corresponds to, for example, the gate line side driver circuits 30 to 33 described in Embodiment 1. By reducing the number of the gate line side driver circuits 364 or the circuit area, the area of ​​the display portion 362 provided between the substrate 351 and the substrate 352 can be increased.

[0253] The wiring 365 has a function of supplying signals and power to the display portion 362 and the gate line side driver circuit 364. The signals and power are input to the wiring 365 from the outside via the FPC 372 or from the IC 373.

[0254] 43 shows an example in which an IC 373 is provided on a substrate 351 by a COG (chip on glass) method, a COF (chip on film) method, or the like. For example, an IC having a signal line side driver circuit or the like can be used as the IC 373. The display device 300A and the display module may be configured without an IC. The IC may also be mounted on an FPC by a COF method or the like.

[0255] Figure 44A shows an example of a cross section of a portion of the region including the FPC 372 of the display device 300A, a portion of the gate line side driving circuit 364, a portion of the display unit 362, a portion of the connection portion 340, and a portion of the region including the end portion.

[0256] A display device 300A shown in FIG. 44A includes a layer 301 having a transistor 201A and a transistor 202, a light-emitting device 330, and the like between a substrate 351 and a substrate 352.

[0257] The light-emitting device 330 includes a conductive layer 311, a conductive layer 312 on the conductive layer 311, and a conductive layer 326 on the conductive layer 312. The conductive layers 311, 312, and 326 may all be referred to as pixel electrodes, or some of them may be referred to as pixel electrodes. The light-emitting device 330 may be a self-luminous light-emitting device such as an LED (Light Emitting Diode), an organic EL (Electro Luminescence) element (also called an OLED (Organic LED)), an inorganic EL element, or a semiconductor laser. Examples of the LED include a mini LED and a micro LED. The following description will be given of the case where an organic EL element is used.

[0258] The conductive layer 311 is connected to the transistor 202 provided in the display portion 362 through an opening provided in the insulating layer 324. For example, a conductive layer functioning as a reflective electrode can be used for the conductive layer 311 and the conductive layer 312. For example, a conductive layer functioning as a transparent electrode can be used for the conductive layer 326.

[0259] A recess is formed in the conductive layer 311 so as to cover the opening provided in the insulating layer 324. For example, a layer 328 is filled in the recess. The layer 328 has a function of planarizing the recess of the conductive layer 311. A conductive layer 312 is provided over the conductive layer 311 and the layer 328. A region overlapping with the recess of the conductive layer 311 can also be used as a light-emitting region, thereby increasing the aperture ratio of the pixel. If the surface of the conductive layer 311 is sufficiently flat, the layer 328 can be omitted.

[0260] The layer 328 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 328. In particular, the layer 328 is preferably formed using an insulating material.

[0261] An insulating layer containing an organic material can be suitably used for the layer 328. For example, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, or precursors of these resins can be used for the layer 328. Alternatively, a photosensitive resin can be used for the layer 328. The photosensitive resin can be a positive material or a negative material.

[0262] By using a photosensitive resin, the layer 328 can be formed only through exposure and development steps, and the influence of dry etching, wet etching, or the like on the surface of the conductive layer 311 can be reduced. Furthermore, by forming the layer 328 using a negative photosensitive resin, the layer 328 can be formed using the same photomask (exposure mask) as that used to form the openings in the insulating layer 324 in some cases.

[0263] The upper and side surfaces of the conductive layer 312 and the conductive layer 326 are covered with the layer 313. Therefore, the entire region where the conductive layer 312 is provided can be used as the light-emitting region of the light-emitting device 330, thereby increasing the aperture ratio of the pixel.

[0264] The side surfaces of the layer 313 are covered with an insulating layer 325 and an insulating layer 327, respectively. A sacrificial layer 318 is located between the layer 313 and the insulating layer 325. A layer 314 is provided on the layer 313, the insulating layer 325, and the insulating layer 327. A common electrode 315 is provided on the layer 314. The layer 314 and the common electrode 315 are each a continuous film provided in common to a plurality of light-emitting devices 330. In addition, a protective layer 331 is provided on the light-emitting devices 330.

[0265] The protective layer 331 and the substrate 352 are bonded via an adhesive layer 342. A solid sealing structure, a hollow sealing structure, or the like can be applied to seal the light-emitting device 330. In FIG. 44A , the space between the substrates 352 and 351 is filled with the adhesive layer 342, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 342 may be provided so as not to overlap with the light-emitting device. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 342.

[0266] In the connection portion 340, a conductive layer 323 is provided on an insulating layer 324. The conductive layer 323 has an example of a stacked structure including a conductive film obtained by processing the same conductive film as the conductive layer 311, a conductive film obtained by processing the same conductive film as the conductive layer 312, and a conductive film obtained by processing the same conductive film as the conductive layer 326. The end of the conductive layer 323 is covered with a sacrificial layer 318, an insulating layer 325, and an insulating layer 327. A layer 314 is provided on the conductive layer 323, and a common electrode 315 is provided on the layer 314. The conductive layer 323 and the common electrode 315 are connected via the layer 314. The layer 314 does not necessarily have to be provided in the connection portion 340. In this case, the conductive layer 323 and the common electrode 315 are directly connected to each other.

[0267] The display device 300A is, for example, a top-emission type. Light L emitted by the light-emitting device is emitted toward the substrate 352. The substrate 352 is preferably made of a material that is highly transparent to visible light. The pixel electrode includes a material that reflects visible light, and the counter electrode (common electrode 315) includes a material that transmits visible light. The display device may also be a bottom-emission type.

[0268] The insulating layer 220 is provided to cover the transistor. The insulating layer 324 is provided to cover the transistor and functions as a planarization layer. Note that the number of insulating layers covering the transistor is not limited, and each may be a single layer or two or more layers.

[0269] It is preferable that at least one insulating layer covering the transistor is made of a material that is resistant to the diffusion of impurities such as water and hydrogen. This allows the insulating layer to function as a barrier layer. With this structure, it is possible to effectively prevent impurities from diffusing into the transistor from the outside, thereby improving the reliability of the display device.

[0270] The insulating layer 220 is preferably made of an inorganic insulating film. Examples of inorganic insulating films that can be used include a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, and an aluminum nitride film. Alternatively, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film may also be used. Two or more of the above insulating films may be stacked.

[0271] An organic insulating film can be suitably used for the insulating layer 324, which functions as a planarizing layer. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins.

[0272] A connection portion 204 is provided in a region of the substrate 351 where the substrate 352 does not overlap. In the connection portion 204, a wiring 365 is connected to the FPC 372 via a conductive layer 366 and a connection layer 203. The conductive layer 366 has an example of a stacked structure including a conductive film obtained by processing the same conductive film as the conductive layer 311, a conductive film obtained by processing the same conductive film as the conductive layer 312, and a conductive film obtained by processing the same conductive film as the conductive layer 326. The conductive layer 366 is exposed on the top surface of the connection portion 204. This allows the connection portion 204 and the FPC 372 to be connected via the connection layer 203.

[0273] A light-shielding layer 317 is preferably provided on the surface of the substrate 352 facing the substrate 351. The light-shielding layer 317 can be provided between adjacent light-emitting devices 330, in the connection section 340, in the gate line side driving circuit 364, and the like. Various optical members can be disposed on the outer surface of the substrate 352. Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. An antistatic film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, an impact absorbing layer, and the like may also be disposed on the outer surface of the substrate 352.

[0274] By providing the protective layer 331 that covers the light emitting device 330, it is possible to prevent impurities such as water from entering the light emitting device 330, thereby improving the reliability of the light emitting device.

[0275] The substrate 351 and the substrate 352 can each be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting device is extracted. Using a flexible material for the substrate 351 and the substrate 352 can increase the flexibility of the display device. A polarizing plate may also be used for the substrate 351 or the substrate 352.

[0276] Substrates 351 and 352 can each be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. One or both of substrates 351 and 352 may be made of glass having a thickness sufficient to provide flexibility.

[0277] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has small birefringence (or a small amount of birefringence).

[0278] The adhesive layer 342 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability, such as epoxy resin, is preferable. Alternatively, a two-component resin may be used. Alternatively, an adhesive sheet or the like may be used.

[0279] The connection layer 203 may be made of an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0280] A layer 301 including a transistor is provided between the substrate 351 and the insulating layer 220. The layer 301 includes a transistor 201A and a transistor 202. The transistor 201A is, for example, an OS transistor having a back gate electrode in addition to the gate electrode described in Embodiment 1. The transistor 202 is the LTPS transistor described in Embodiment 1. The transistors 201A and 202 are formed over the substrate 351. The transistors 201A and 202 can be manufactured using the same material and through the same process.

[0281] FIG. 44B is an enlarged view of a cross section including the transistor 201A. FIG. 44C is an enlarged view of a cross section including the transistor 202. The transistor 201A illustrated in FIG. 44B can be an n-channel OS transistor, and the transistor 202 illustrated in FIG. 44C can be a p-channel LTPS transistor. The transistors 201A and 202 can be transistors included in the display portion 362. The transistors 201A and 202 can be transistors included in the gate line driver circuit 364 in addition to the display portion 362. The transistor included in the gate line driver circuit 364 can be either the transistor 201A or the transistor 202.

[0282] The transistor 201A includes an insulating layer 211, a conductive layer 212A, an insulating layer 213, an insulating layer 214, a semiconductor layer 215, an insulating layer 216, a conductive layer 217, an insulating layer 218, and conductive layers 219a and 219b stacked in this order over a substrate 351. The insulating layer 213, the insulating layer 214, and a part of the insulating layer 218 function as gate insulating layers of the transistor 201A. The conductive layer 212A functions as a bottom gate electrode of the transistor 201A. The conductive layer 217 functions as a top gate electrode of the transistor 201A. The conductive layers 219a and 219b function as source and drain electrodes.

[0283] The semiconductor layer 215 is, for example, a metal oxide containing indium oxide (referred to as indium oxide). The conductive layer 219a and the conductive layer 219b are connected to a low-resistance region 215n of the semiconductor layer 215 through openings provided in the insulating layer 216 and the insulating layer 218, respectively. The low-resistance region 215n can also be referred to as a region with lower resistance, a region with a higher carrier concentration, a region with a higher oxygen vacancy density, a region with a higher impurity concentration, or an n-type region compared to the channel formation region of the transistor 201A. For example, the low-resistance region 215n is a region containing an impurity element. Examples of the impurity element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, and noble gases. Typical examples of noble gases include helium, neon, argon, krypton, and xenon. The low-resistance region 215n preferably contains boron or phosphorus. The low-resistance region 215n may contain two or more of the above elements.

[0284] Examples of metal oxides that can be used for the semiconductor layer 215 include indium zinc oxide, indium tin oxide, indium titanium oxide, indium gallium oxide, indium gallium aluminum oxide, indium gallium tin oxide (also referred to as IGTO), gallium zinc oxide, aluminum zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, indium gallium zinc oxide (also referred to as IGZO), indium gallium tin zinc oxide, and indium gallium aluminum zinc oxide.

[0285] As a metal oxide applicable to the semiconductor layer 215, for example, indium oxide (also referred to as IO) can be used.

[0286] The transistor 202 includes a semiconductor layer 210, an insulating layer 211, a conductive layer 212B, an insulating layer 213, an insulating layer 214, an insulating layer 216, an insulating layer 218, and conductive layers 219c and 219d stacked in this order over a substrate 351. A part of the insulating layer 211 functions as a gate insulating layer of the transistor 202. The conductive layer 212B functions as a top gate electrode of the transistor 202. The conductive layers 219c and 219d function as source and drain electrodes.

[0287] The semiconductor layer 210 contains silicon such as low-temperature polysilicon. The conductive layer 219c and the conductive layer 219d are connected to a low-resistance region 210p of the semiconductor layer 210 through openings formed in the insulating layers 211, 213, 214, 216, and 218, respectively. The low-resistance region 210p can also be referred to as a region with lower resistance, a region with a higher impurity concentration, or a p-type region than the channel formation region of the transistor 202. For example, the low-resistance region 210p is a region containing an impurity element for forming a p-channel transistor. To form a p-channel transistor, boron and / or aluminum may be added to the low-resistance region 210p. Furthermore, the above-described impurities may be added to the channel formation region of the transistor 202 to control the threshold voltage of the transistor 202.

[0288] Components other than the semiconductor layers of the transistor 201A and the transistor 202 can be formed in the same process, which can prevent an increase in the number of processes even when two types of transistors are mixed.

[0289] Materials that can be used for conductive layers such as gate electrodes, source electrodes, and drain electrodes of transistors, as well as various wirings and electrodes that constitute display devices, include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, as well as alloys containing these metals as main components, etc. Films containing these materials can be used as a single layer or a stacked structure.

[0290] Examples of light-transmitting conductive materials include conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide containing gallium, or graphene. Alternatively, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, and titanium, or alloy materials containing such metal materials, can be used. Alternatively, nitrides of such metal materials (e.g., titanium nitride) can be used. When using metal materials or alloy materials (or their nitrides), it is preferable to thin them sufficiently to ensure light-transmitting properties. Furthermore, stacked films of the above materials can be used as conductive layers. For example, stacked films of silver-magnesium alloys and indium tin oxide are preferred because they can enhance conductivity. These materials can also be used for conductive layers such as various wirings and electrodes constituting display devices, and conductive layers (conductive layers functioning as pixel electrodes or common electrodes) in light-emitting devices.

[0291] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic resin and epoxy resin, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

[0292] 44B, the conductive layer 212A functioning as the bottom gate electrode is preferably made of a conductive material having a light-shielding property. In addition, the conductive layer 212A functioning as the bottom gate electrode in FIG. 44B preferably has a structure in which the area overlapping with the semiconductor layer 215 is larger than that of the conductive layer 217 functioning as the top gate electrode.

[0293] For example, the cross-sectional schematic diagram of a display device 300A1 shown in FIG. 45A includes a transistor 201B in which the conductive layer 212A functioning as a bottom gate electrode in FIG. 44B is replaced with the conductive layer 212C functioning as a light-shielding layer. Note that the display device 300A1 shown in FIG. 45A is a modified example of the display device 300A described above. FIG. 45B also shows an enlarged cross-sectional view including the transistor 201B shown in FIG. 45A. With this configuration, the conductive layer 212C functioning as a bottom gate electrode in FIGS. 45A and 45B can be a light-shielding layer that blocks stray light from the substrate 351 side toward the semiconductor layer 215. Therefore, fluctuations in the electrical characteristics of the transistor due to stray light from the substrate 351 side toward the semiconductor layer 215 can be suppressed.

[0294] Furthermore, the conductive layer 212C functioning as the bottom gate electrode preferably has a larger overlapping area with the semiconductor layer 215 than the conductive layer 217 functioning as the top gate electrode and is wider than the area where the semiconductor layer 215 is provided, so as to cover the semiconductor layer 215 when viewed from the substrate 351, for example. This structure can improve the flatness of the top surfaces of the insulating layers 213 and 214 on which the semiconductor layer 215 is provided, thereby achieving favorable electrical characteristics of the transistor. Note that detailed descriptions of the display device 300A1 and the transistor 201B are omitted because they have much in common with the display device 300A and the transistor 201A described in FIGS. 44A and 44B .

[0295] 45A illustrates a configuration in which all of the transistors included in the gate line side driver circuit 364 that drives pixels are LTPS transistors such as the transistor 202. Silicon used in the semiconductor layer of the LTPS transistor can be low-temperature polysilicon, as well as single crystal silicon, polycrystalline silicon, amorphous silicon, or the like. LTPS transistors have high field-effect mobility and good frequency characteristics, so a configuration in which they are used in the gate line side driver circuit 364 is particularly preferable.

[0296] 44A , at least one of the transistors included in the gate line side driver circuit 364 that drives the pixel can be an OS transistor such as the transistors 201A and 201B. The OS transistor has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, the OS transistor has a significantly smaller off-state current and can hold charge accumulated in a capacitor connected in series with the OS transistor for a long period of time.

[0297] <Plan View and Cross-Sectional View of Pixel> FIG. 46 is a plan view illustrating a case where the transistor 201B and the transistor 202 described in FIGS. 44A to 45B are applied to the pixel 10 described in Embodiment 1. The circuit configuration of the pixel 10_X in the plan view of FIG. 46 is an example and is not limited to this. FIG. 47A is a cross-sectional view taken along the X1-X2 line indicated by the thick dashed line in FIG. 46. FIG. 47B is a cross-sectional view taken along the Y1-Y2 line indicated by the thick dashed line in FIG. 46. FIG. 47C is a cross-sectional view taken along the Z1-Z2 line indicated by the thick dashed line in FIG. 46. FIG. 48 is a schematic diagram illustrating a stacking order of a layer 62 in which a transistor and the like are provided, a layer 63 in which wirings such as a wiring DL and a wiring ELVDD are provided, and a layer 64 in which a conductive layer 311, a common electrode 315 functioning as a wiring ELVSS, and the like are provided. In FIG. 48, dashed arrows indicate connections between the wirings provided in the layer 63 and the wirings or semiconductor layers of the transistors provided in the layer 62.

[0298] 46 illustrates the pixel 10_X including the transistors M11 to M17 and the capacitor C1 described in the above embodiment 1. Also illustrated in Fig. 46 are the wirings GI, GI_BG, GW, EM, GB, GC, GC_BG, and DL described in the above embodiment 1. Also illustrated in Fig. 46 are conductive layers BG1 to BG7, ME1 to ME6, conductive layers GE1 and GE2, semiconductor layers SI1 to SI5, semiconductor layers OI1 and OI2, contact holes CO1 to CO7, contact holes BC1 and BC2, and contact hole TC1 as components constituting the transistors M11 to M17, the capacitor C1, the wirings GI, GI_BG, GW, EM, GB, GC, GC_BG, and DL described in the above embodiment 1.

[0299] The conductive layers BG1 to BG7 are conductive layers provided in the same layer as the conductive layers 212A, 212B, and 212C described in FIGS. 44B, 44C, and 45B. The conductive layers ME1 to ME7 are conductive layers provided in the same layer as the conductive layers 219a to 219d described in FIGS. 44B and 44C. The conductive layers GE1 and GE2 are conductive layers provided in the same layer as the conductive layer 217 described in FIGS. 44B and 44C. The semiconductor layers SI1 to SI5 are semiconductor layers provided in the same layer as the semiconductor layer 210 described in FIGS. 44B and 44C. The semiconductor layers OI1 and OI2 are semiconductor layers provided in the same layer as the semiconductor layer 215 described in FIGS. 44B and 44C. Contact holes CO1 to CO7 are openings for connecting semiconductor layers SI1 to SI5 and semiconductor layers OI1 and OI2 with conductive layers ME1 to ME7. Contact holes BC1 and BC2 are openings for connecting conductive layers ME1 to ME6 with semiconductor layers BG1 to BG7. Contact hole TC1 is an opening for connecting conductive layer ME5 with a conductive layer 311 (not shown) that functions as a pixel electrode provided in the upper layer.

[0300] As shown in FIGS. 46 and 47A, the conductive layer BG1 functions as the wiring GW and the gate of the transistor M11. As shown in FIGS. 46 and 47A, the conductive layer BG2 functions as the wiring EM, the gate of the transistor M12, and the gate of the transistor M14. As shown in FIGS. 46, 47B, and 48, the conductive layer BG3 functions as the gate of the transistor M13 and the first terminal of the capacitance element C1. As shown in FIG. 46, the conductive layer BG4 functions as the wiring GC_BG and the back gate of the transistor M16. As shown in FIG. 46, the conductive layer BG5 functions as the wiring GB and the gate of the transistor M15. As shown in FIG. 46, the conductive layer BG6 functions as the wiring GI_BG and the back gate of the transistor M17. As shown in FIGS. 46 and 48, the conductive layer BG7 functions as an interconnect INI.

[0301] As shown in FIGS. 46, 47A, and 48, the conductive layer ME1 functions as the wiring DL and the first terminal of the transistor M11. As shown in FIGS. 46, 47A, and 48, the conductive layer ME2 functions as the second terminal of the transistor M11, the first terminal of the transistor M12, and the first terminal of the transistor M13. As shown in FIGS. 46, 47A, and 48, the conductive layer ME3 functions as the wiring ELVDD, the second terminal of the transistor M12, and the second terminal of the capacitor C1. As shown in FIGS. 46, 47B, and 48, the conductive layer ME4 functions as the second terminal of the transistor M13, the first terminal of the transistor M14, and the first terminal of the transistor M16. As shown in FIGS. 46 and 48, the conductive layer ME5 functions as the second terminal of the transistor M14 and the first terminal of the transistor M15. The conductive layer ME6 functions as a second terminal of the transistor M15 and a second terminal of the transistor M17, as shown in Figures 46, 47C, and 48. The conductive layer ME7 functions as a second terminal of the transistor M16 and a first terminal of the transistor M17, as shown in Figures 46, 47C, and 48.

[0302] The conductive layer GE1 functions as the wiring GC and the gate of the transistor M16, as shown in Fig. 46. The conductive layer GE2 functions as the wiring GI and the gate of the transistor M17, as shown in Figs. 46 and 47C.

[0303] As shown in FIGS. 46 and 47A, contact hole CO1 functions as an opening provided in an insulating layer to connect semiconductor layer SI1 with conductive layers ME1 and ME2. Contact hole CO2 functions as an opening provided in an insulating layer to connect semiconductor layer SI2 with conductive layers ME2 and ME3. Contact hole CO3 functions as an opening provided in an insulating layer to connect semiconductor layer SI3 with conductive layers ME2 and ME4. Contact hole CO4 functions as an opening provided in an insulating layer to connect semiconductor layer SI4 with conductive layers ME4 and ME5. Contact hole CO5 functions as an opening provided in an insulating layer to connect semiconductor layer SI5 with conductive layers ME5 and ME6. The contact hole CO6 functions as an opening provided in an insulating layer to connect the semiconductor layer OI1 with the conductive layers ME4 and ME7, as shown in Fig. 46. The contact hole CO7 functions as an opening provided in an insulating layer to connect the semiconductor layer OI2 with the conductive layers ME6 and ME7, as shown in Fig. 46 and 47C.

[0304] As shown in Fig. 46, contact hole BC1 functions as an opening provided in an insulating layer to connect conductive layer ME7 and conductive layer BG3. As shown in Fig. 46 and 47C, contact hole BC2 functions as an opening provided in an insulating layer to connect conductive layer ME6 and conductive layer BG7. As shown in Fig. 46 and 48, contact hole TC1 functions as an opening provided in an insulating layer to connect conductive layer ME5 and conductive layer 311.

[0305] As can be seen from the plan view shown in Figure 46, the cross-sectional views of Figures 47A to 47C, and the schematic diagram of Figure 48, in pixel 10_X, the line width of the conductive layer ME3 that functions as the wiring ELVDD is larger than the line width of other wirings, such as the wiring GI, wiring GI_BG, wiring GW, wiring EM, wiring GB, wiring GC, and wiring GC_BG. This configuration can reduce the resistance of the wiring ELVDD. Therefore, this configuration can reduce the voltage drop caused by current flowing through the wiring ELVDD.

[0306] As can be seen from the plan view shown in FIG. 46 , the cross-sectional views shown in FIGS. 47A to 47C , and the schematic diagram shown in FIG. 48 , pixel 10_X has a configuration in which a conductive layer GE1 functioning as wiring GC and a conductive layer BG4 functioning as wiring GC_BG are overlappingly arranged. Furthermore, the line width of the upper conductive layer GE1 is configured to be smaller than the line width of the conductive layer BG4 functioning as wiring GC_BG. This configuration allows the resistance of the conductive layer BG4 to be smaller than the resistance of the conductive layer GE1. Compared to the conductive layer GE1, the conductive layer BG4 has a larger overlapping area with other conductive layers or semiconductor layers and therefore a larger parasitic capacitance. Therefore, this configuration allows the voltage drop caused by current flowing through wiring GC_BG to be smaller than the voltage drop caused by current flowing through wiring GC_BG.

[0307] 46, the cross-sectional views of Fig. 47A to 47C, and the schematic view of Fig. 48, in the pixel 10_X, the transistors M11 to M15, which are LTPS transistors, and the transistors M16 and M17, which are OS transistors, are connected using conductive layers ME1 to ME7 provided in the layer 63. By using conductive layers provided in the same layer for the transistors M11 to M17, the process can be simplified compared to a configuration in which conductive layers connecting transistors are provided across multiple layers, and this is expected to lead to an improvement in yield.

[0308] 46, the cross-sectional views of Fig. 47A to 47C, and the schematic diagram of Fig. 48, in the pixel 10_X, the transistors are provided so as to overlap with portions of a conductive layer branched from a conductive layer extending in one direction and functioning as the gates or back gates of the transistors M11 to M17. This configuration allows for greater design freedom than a configuration in which transistors are provided on a conductive layer extending in one direction.

[0309] As can be seen from the plan view shown in Fig. 46, the cross-sectional views of Figs. 47A to 47C, and the schematic diagram of Fig. 48, pixel 10_X is configured such that a conductive layer BG7 functioning as wiring INI and a conductive layer ME3 functioning as wiring ELVDD are disposed at the boundary of pixel 10_X. The conductive layer BG7 and the conductive layer ME3 function as wiring to which a constant potential is applied. Therefore, this configuration can suppress noise in the pixel that is caused by fluctuations in the potential of the wiring of an adjacent pixel.

[0310] In addition to the above effect, as can be seen from the plan view in FIG. 46 , the cross-sectional views in FIGS. 47A to 47C , and the schematic view in FIG. 48 , in the pixel 10_X, for example, the V ＩＮＩ The voltage between the back gate and the source of the transistors M16 and M17 can be set to a negative voltage. Fluctuations in the threshold voltage of the transistors M16 and M17 can be suppressed, and the long-term reliability of the transistors can be improved. The reliability of a display device including the transistors can be improved.

[0311] FIG. 49 is a plan view of a configuration different from the plan view of a pixel applicable to pixel 10 of embodiment 1 described in FIG. 46 . FIG. 50A is a cross-sectional view taken along X3-X4 indicated by a thick dashed line in FIG. 49 . FIG. 50B is a cross-sectional view taken along Y3-Y4 indicated by a thick dashed line in FIG. 49 . FIG. 50C is a cross-sectional view taken along Z3-Z4 indicated by a thick dashed line in FIG. 49 . Note that in the description of the plan view shown in FIG. 49 , repeated description of configurations common to the plan view shown in FIG. 46 will be omitted. Description of each transistor included in pixel 10_Y in FIG. 49 will be omitted because many parts are common to transistors 201A, 201B, and 202 described in FIGS. 44A to 45B .

[0312] Note that the cross-sectional views of a predetermined portion of Fig. 49 shown in Figs. 50A to 50C illustrate a different portion from the cross-sectional views of a predetermined portion of Fig. 46 shown in Figs. 47A to 47C. For example, the cross-sectional view of Fig. 50A illustrates transistors M11 and M12 as well as an opening MH1 provided in conductive layer ME3. Furthermore, the cross-sectional view of Fig. 50B illustrates transistor M13 as well as a capacitance element C1 provided between conductive layer BG3 and conductive layer ME3. Furthermore, the cross-sectional view of Fig. 50C illustrates transistor M17 as well as an opening MH4 provided in conductive layer ME3.

[0313] 49 and 50A to 50C differ from the plan view configuration shown in Fig. 46 in that the arrangement of the transistor M12 is different. Also, the plan view configuration shown in Fig. 49 differs from the plan view configuration shown in Fig. 46 in that the conductive layer ME3 having the function of the wiring ELVDD has openings MH1 to MH4 in regions overlapping with the conductive layers BG1, BG2, BG3, BE1, BG4, BG5, BG6, BE2, and BG7.

[0314] By positioning transistor M12 closer to transistor M11, the length of the conductive layer ME2 between transistors M11 and M13 and between transistors M12 and M13 can be shortened. The conductive layer ME2 intersects with the conductive layer BG2, which functions as the wiring EM to which a control signal is supplied. Therefore, this configuration can reduce delays or waveform distortions of signals transmitted to the conductive layer ME2. This configuration is effective for wiring connected to transistors that intersect with other conductive layers BG1 to BG7, such as transistors M13 and M14, and transistors M15 and M17.

[0315] By providing openings MH1 to MH4 in the conductive layer ME3 in areas overlapping with the conductive layers BG1, BG2, BG3, BE1, BG4, BG5, BG6, BE2, and BG7, it is possible to reduce the crossing capacitance between the wiring GI, wiring GI_BG, wiring GW, wiring EM, wiring GB, wiring GC, and wiring GC_BG that transmit various control signals and the wiring ELVDD that transmits VDD. For example, as shown in FIG. 50A , the opening MH1 is provided so as to remove the conductive layer ME3 on the conductive layer BG1 that functions as wiring GW, and as shown in FIG. 50C , the opening MH4 is provided so as to remove the conductive layer ME3 on the conductive layer GE2 that functions as wiring GI and on the conductive layer BG6 that functions as wiring GI_BG, thereby reducing the parasitic capacitance due to the crossing of the wirings. Therefore, this configuration can reduce noise in the transmitted control signals, signal delay, and waveform distortion.

[0316] The capacitance element C1, formed by the overlapping of the conductive layer ME3 and the conductive layer BG3 shown in FIG. 50B, can be divided into multiple elements as needed. Furthermore, by increasing the parasitic capacitance of the conductive layer ME3, the capacitance element C1 can be omitted. While FIGS. 49 and 50B show the conductive layer ME3 and the conductive layer BG3 overlapping to form the capacitance element C1, it is also possible to configure the capacitance element C1 by placing another conductive layer, for example, a conductive layer provided in the same layer as the wiring GE1 and GE2, in a position overlapping the conductive layer BG3. This configuration allows the insulating layer between the conductive layers to be thinner, resulting in a capacitance element with a large capacitance value.

[0317] Note that the pixel 10_Y described using the plan view shown in Figure 49 and the cross-sectional views of Figures 50A to 50C has features common to the pixel 10_X. Therefore, in addition to the effects described above, it is possible to achieve the effects described in Figure 10_X. Furthermore, each configuration of the pixel 10_Y can be combined with the configuration of the pixel 10_X.

[0318] FIG. 51 is a plan view of a configuration different from the plan views of a pixel applicable to pixel 10 of embodiment 1 described in FIGS. 46 and 49 . FIG. 52A is a cross-sectional view taken along line X5-X6 indicated by a thick dashed line in FIG. 51 . FIG. 52B is a cross-sectional view taken along line Y5-Y6 indicated by a thick dashed line in FIG. 51 . FIG. 52C is a cross-sectional view taken along line Z5-Z6 indicated by a thick dashed line in FIG. 51 . Note that in describing the plan view shown in FIG. 51 , repeated description of configurations common to the plan views shown in FIGS. 46 and 49 will be omitted. Description of each transistor included in pixel 10_Z in FIG. 51 will be omitted because many parts are common to transistors 201A, 201B, and 202 described in FIGS. 44A to 45B .

[0319] Note that the cross-sectional views of a predetermined portion of Fig. 51 shown in Figs. 52A to 52C illustrate a different portion from the cross-sectional views of a predetermined portion of Fig. 46 shown in Figs. 47A to 47C and the cross-sectional views of a predetermined portion of Fig. 49 shown in Figs. 50A to 50C. For example, the cross-sectional view of Fig. 52A illustrates cross-sectional views of transistors M11 and M14. Furthermore, for example, the cross-sectional view of Fig. 52B illustrates a cross-sectional view of transistor M13, which has a different configuration from Figs. 46 and 49. Furthermore, for example, the cross-sectional view of Fig. 52C illustrates a cross-sectional view of transistor M15 instead of transistor M17.

[0320] The plan views and cross-sectional views shown in FIGS. 51 and 52A to 52C differ from the plan views shown in FIGS. 46 and 49 in that the shape of the semiconductor layer SI3 of the transistor M13 is different. As shown in FIGS. 51 and 52B, the transistor M13 has a meandering structure in which the semiconductor layer SI3 is formed between the source and drain. This structure allows the channel length of the transistor M13 to be longer than that of other transistors, such as the transistors M11, M12, M14, and M15. The transistor M13, which functions as a driving transistor, is preferably a transistor capable of passing a current corresponding to a data voltage. Therefore, the transistor M13 preferably has good electrical characteristics in the saturation region (also referred to as "saturation characteristics"). A long channel length of the transistor M13 allows it to have good saturation characteristics. The channel length can be determined from the region where the semiconductor layer and the conductive layer overlap.

[0321] 51 and 52A to 52C, the overlapping area between the conductive layer BG3 functioning as the gate of the transistor M13 and the semiconductor layer SI3 is preferably larger than the overlapping area between the conductive layer BG1 functioning as the gate of another transistor, for example, the transistor M11, and the semiconductor layer SI1. This configuration increases the channel width of the transistor, thereby increasing the amount of current flowing through the transistor M13. The channel width can be determined from the overlapping area between the semiconductor layer and the conductive layer.

[0322] Note that pixel 10_Z described using the plan view shown in Figure 51 and the cross-sectional views of Figures 52A to 52C has features common to pixel 10_X or pixel 10_Y. Therefore, in addition to the effects described above, pixel 10_Z can also have the effects described for pixel 10_X or pixel 10_Y. Furthermore, each configuration of pixel 10_Z can be combined with the configuration of pixel 10_X or pixel 10_Y.

[0323] This embodiment mode can be combined with other embodiment modes as appropriate.

[0324] Embodiment 3 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a display device of one embodiment of the present invention will be described.

[0325] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0326] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0327] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 53A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ), and FIG. 53B is a schematic diagram showing the carrier concentration dependence of the Hall mobility for IGZO.

[0328] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 53B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 53A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 53A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 53A.

[0329] 53A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0330] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0331] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0332] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of the element include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0333] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 53A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0334] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0335] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0336] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0337] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0338] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0339] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0340] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0341] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0342] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 53C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0343] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0344] Furthermore, as shown in FIG. 53C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with the oxygen contained in the membrane and is released as water molecules.

[0345] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0346] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0347]

[0348] A layer (hereinafter referred to as a seed layer) in contact with at least a portion of the crystalline indium oxide film is preferably made of a material containing crystals with a small difference in lattice constant (also referred to as lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0349] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0350] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0351] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0352] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0353] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0354] Embodiment 4 In this embodiment, electronic devices according to one embodiment of the present invention will be described with reference to FIGS. 54 to 56 . The electronic devices of this embodiment include a display device according to one embodiment of the present invention in a display portion. The display device according to one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, the display device can be used in the display portion of various electronic devices.

[0355] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0356] The electronic device 6500 shown in FIG. 54A is a portable information terminal that can be used as a smartphone.

[0357] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display portion 6502 has a touch panel function.

[0358] The display device of one embodiment of the present invention can be applied to the display portion 6502 .

[0359] FIG. 54B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0360] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0361] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0362] In a region outside the display portion 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0363] A flexible display can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while suppressing the thickness of the electronic device. In addition, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0364] 55A shows an example of a television set. A television set 7100 has a display portion 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0365] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0366] 55A can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and an image displayed on the display portion 7000 can be controlled.

[0367] The television device 7100 is configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers, etc.) information communication.

[0368] 55B shows an example of a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, and an external connection port 7214. The housing 7211 includes a display portion 7000.

[0369] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0370] 55C and 55D show an example of digital signage.

[0371] 55C includes a housing 7301, a display portion 7000, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0372] 55D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0373] 55C and 55D, the display device of one embodiment of the present invention can be applied to the display portion 7000.

[0374] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it will attract people's attention, which can increase the advertising effectiveness of, for example, advertisements.

[0375] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.

[0376] 55C and 55D , the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. By operating the information terminal 7311 or the information terminal 7411, the display on the display unit 7000 can be switched.

[0377] Furthermore, the digital signage 7300 or the digital signage 7400 can be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0378] The electronic device shown in Figures 56A to 56G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9008, etc.

[0379] The electronic devices shown in Figures 56A to 56G have various functions. For example, they may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing using various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. Note that the functions of the electronic devices are not limited to these, and they may have various other functions. The electronic devices may have multiple display units. Furthermore, the electronic devices may have a function to include a camera or the like to capture still images or videos and store them on a recording medium (external or built-in to the camera), a function to display the captured images on a display unit, etc.

[0380] Details of the electronic devices shown in Figures 56A to 56G will be described below.

[0381] FIG. 56A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. Note that the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on multiple surfaces. FIG. 56A shows an example in which three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the title of the email or SNS message, the sender's name, the date and time, the remaining battery level, and radio wave intensity. Alternatively, an icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

[0382] 56B is a perspective view showing the mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is placed in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether to answer a call.

[0383] 56C is a perspective view showing a tablet terminal 9103. The tablet terminal 9103 is capable of executing various applications such as mobile phone calls, e-mail, text browsing and creation, music playback, internet communication, and computer games, for example. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of a housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.

[0384] FIG. 56D is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free calling by communicating with, for example, a wirelessly capable headset. The mobile information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0385] 56E to 56G are perspective views showing a foldable mobile information terminal 9201. Also, FIG. 56E is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 56G is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 56F is a perspective view of a state in the process of changing from one of FIG. 56E and FIG. 56G to the other. The mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area when unfolded, providing excellent visibility of the display. The display portion 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display portion 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.

[0386] This embodiment mode can be combined with other embodiment modes as appropriate.

[0387] (Additional Notes Regarding the Description of the Present Specification, etc.) The following additional notes will be given regarding the above-described embodiments and the explanation of each configuration in the embodiments.

[0388] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0389] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or the content (or even a part of the content) described in one or more other embodiments.

[0390] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0391] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0392] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as mutually independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately.

[0393] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0394] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like.

[0395] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0396] Furthermore, in this specification and the like, the terms voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0397] In this specification and the like, terms such as "film" and "layer" can be interchanged. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0398] In this specification, a switch refers to a device that has a function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0399] In this specification, the channel length refers to, for example, in a plan view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0400] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0401] In this specification and the like, the "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor can be considered to be short-circuited. For example, the "on state" refers to a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage. Note that the "on state" of a transistor refers to a state in which current can flow between the source and drain. Therefore, the "on state" of a transistor may also be referred to as the "conducting state" of the transistor.

[0402] In this specification and the like, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be cut off. For example, the "off state" refers to a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage. The "off state" of a transistor may also be referred to as the "non-conducting state" of the transistor.

[0403] In this specification and the like, the voltage between the gate and the source (gate-source) may be referred to as the “gate voltage,” the voltage between the drain and the source (drain-source) may be referred to as the “drain voltage,” and the voltage between the backgate and the source (backgate-source) may be referred to as the “backgate voltage.” Also, the current flowing from the drain to the source may be referred to as the “drain current.”

[0404] In this specification and the like, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification and the like, the off-state current and the current flowing from the gate to the source and drain (also referred to as gate leakage current) may also be referred to as leakage current.

[0405] In this specification, "connection" includes, as an example, "electrical connection." When the term "electrical connection" is used to define the connection relationship between circuit elements as a physical entity, "electrical connection" includes, as examples, "direct connection" and "indirect connection." "A and B are directly connected" refers to a case where A and B are connected without a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a case where A and B are connected via one or more circuit elements.

[0406] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time during the operation of the circuit when electrical signal transmission or potential interaction does not occur between A and B, "A and B are indirectly connected" can be defined as an entity when there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B. Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0407] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 57A1 and 57A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," assuming that the circuit is operating, it is assumed that there is at least one time when a transistor between A and B is in an on state, a conductive state, or a state in which a current can flow. Note that "A and B are indirectly connected" also includes cases in which there is a time when a transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that there is at least one time when each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which a current can flow, assuming that the circuit is operating. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 57A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0408] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 57A4. Another example of a case where A and B are connected via an insulator is when a transistor gate insulating film or the like is interposed between A and B, as shown in FIG. 57A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0409] Another example of a case where it cannot be said that "A and B are indirectly connected" is when there is no timing at which an electrical signal is exchanged or there is no interaction of potential between A and B. An example of this is when, as shown in Figures 57A6 and 57A7, multiple transistors are connected via their sources and drains in the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 57A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, the connection relationship will be the same as in Figures 57A6 and 57A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0410] Although an example of "indirect connection" has been given above, as an example, the provision of "indirect connection" is included in the provision of "electrical connection," so when "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0411] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit elements between them, as shown in FIGS. 57B1, 57B2, and 57B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit elements between them, as shown in FIGS. 57B4 and 57B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 57B6. Because A and V or B and V are connected via the source and drain of a transistor, it cannot be said that they are directly connected; instead, it can be said that "A and V are indirectly connected" or "B and V are indirectly connected."

[0412] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0413] DL: wiring, ELVDD: wiring, ELVSS: wiring, EM: wiring, GB: wiring, GC: wiring, GI: wiring, GN: wiring, GNBG: wiring, GW: wiring, INI: wiring, M11: transistor, M12: transistor, M13: transistor, M14: transistor, M15: transistor, M16: transistor, M17: transistor, ND1: node, 10: pixel, 20: display unit, 30: gate line side driving circuit, 31: gate line side driving circuit, 32: gate line side driving circuit, 33: gate line side driving circuit, 40: integrated circuit, 61: light emitting device, 100: display device

Claims

a first to seventh transistors, a capacitance element, and a light-emitting device; each of the first to fifth transistors has a gate, a first terminal, and a second terminal; each of the sixth and seventh transistors has a gate, a back gate, a first terminal, and a second terminal; a first terminal of the first transistor is electrically connected to a first terminal of the second transistor and a first terminal of the third transistor; a second terminal of the third transistor is electrically connected to a first terminal of the fourth transistor and a first terminal of the sixth transistor; a second terminal of the fourth transistor electrically connected to a first terminal of the light emitting device and a first terminal of the fifth transistor; a second terminal of the light emitting device electrically connected to a common potential line; a gate of the third transistor is electrically connected to a second terminal of the sixth transistor, a first terminal of the seventh transistor, and a first terminal of the capacitive element; a second terminal of the fifth transistor and a second terminal of the seventh transistor are each electrically connected to an initialization line; a gate of the sixth transistor is electrically connected to a first gate line to which a first control signal is supplied; a back gate of the sixth transistor is electrically connected to a second gate line to which a second control signal is supplied; a gate of the seventh transistor is electrically connected to a third gate line to which a third control signal is supplied; a back gate of the seventh transistor is electrically connected to a fourth gate line to which a fourth control signal is supplied; the first control signal and the second control signal are signals of the same logic, the third control signal and the fourth control signal are signals of the same logic, a low-level potential of the second control signal and a low-level potential of the fourth control signal are different from a low-level potential of the first control signal and a low-level potential of the third control signal; Display device. 　 a first to seventh transistors, a capacitance element, and a light-emitting device; each of the first to fifth transistors has a gate, a first terminal, and a second terminal; each of the sixth and seventh transistors has a gate, a back gate, a first terminal, and a second terminal; a first terminal of the first transistor electrically connected to a data line; a second terminal of the first transistor electrically connected to a first terminal of the second transistor and a first terminal of the third transistor; a second terminal of the second transistor electrically connected to a current supply line; a second terminal of the third transistor is electrically connected to a first terminal of the fourth transistor and a first terminal of the sixth transistor; a second terminal of the fourth transistor electrically connected to a first terminal of the light emitting device and a first terminal of the fifth transistor; a second terminal of the fifth transistor is electrically connected to an initialization line; a second terminal of the light emitting device electrically connected to a common potential line; a gate of the third transistor is electrically connected to a second terminal of the sixth transistor, a first terminal of the seventh transistor, and a first terminal of the capacitive element; a second terminal of the capacitance element electrically connected to the current supply line; a second terminal of the seventh transistor is electrically connected to the initialization line; a gate of the sixth transistor is electrically connected to a first gate line to which a first control signal is supplied; a back gate of the sixth transistor is electrically connected to a second gate line to which a second control signal is supplied; a gate of the seventh transistor is electrically connected to a third gate line to which a third control signal is supplied; a back gate of the seventh transistor is electrically connected to a fourth gate line to which a fourth control signal is supplied; the first control signal and the second control signal are signals of the same logic, the third control signal and the fourth control signal are signals of the same logic, the potential of the initialization line is lower than the potential of the common potential line; a low-level potential of the second control signal and a low-level potential of the fourth control signal are equal to or lower than a potential of the initialization line; Display device. 　 a first to seventh transistors, a capacitance element, and a light-emitting device; each of the first to fifth transistors has a gate, a first terminal, and a second terminal; each of the sixth and seventh transistors has a gate, a back gate, a first terminal, and a second terminal; a first terminal of the first transistor electrically connected to a data line; a second terminal of the first transistor electrically connected to a first terminal of the second transistor and a first terminal of the third transistor; a second terminal of the second transistor electrically connected to a current supply line; a second terminal of the third transistor is electrically connected to a first terminal of the fourth transistor and a first terminal of the sixth transistor; a second terminal of the fourth transistor electrically connected to a first terminal of the light emitting device and a first terminal of the fifth transistor; a second terminal of the fifth transistor is electrically connected to an initialization line; a second terminal of the light emitting device electrically connected to a common potential line; a gate of the third transistor is electrically connected to a second terminal of the sixth transistor, a first terminal of the seventh transistor, and a first terminal of the capacitive element; a second terminal of the capacitance element electrically connected to the current supply line; a second terminal of the seventh transistor is electrically connected to the initialization line; a gate of the sixth transistor is electrically connected to a first gate line to which a first control signal is supplied; a back gate of the sixth transistor is electrically connected to a second gate line to which a second control signal is supplied; a gate of the seventh transistor is electrically connected to a third gate line to which a third control signal is supplied; a back gate of the seventh transistor is electrically connected to a fourth gate line to which a fourth control signal is supplied; the first control signal and the second control signal are signals of the same logic, the third control signal and the fourth control signal are signals of the same logic, the potential of the initialization line is lower than the potential of the common potential line; the potential of the initialization line is lower than the potential of the data line; a low-level potential of the second control signal and a low-level potential of the fourth control signal are equal to or lower than a potential of the initialization line; Display device. 　 In any one of claims 1 to 3, the first to fifth transistors are p-channel transistors, the sixth and seventh transistors are each an n-channel transistor; Display device. 　 In claim 4, the back gate of the n-channel transistor is provided opposite to the gate of the n-channel transistor across a channel formation region of the n-channel transistor; Display device. 　 In claim 4, the n-channel transistor has a first semiconductor layer; the first semiconductor layer comprises indium oxide; Display device. 　 In claim 4, the p-channel transistor has a second semiconductor layer; the second semiconductor layer comprises silicon; Display device. 　 In any one of claims 1 to 3, a high-level potential of the second control signal and a high-level potential of the fourth control signal are the same as a high-level potential of the first control signal and a high-level potential of the third control signal; Display device. 　 In any one of claims 1 to 3, a channel length of the third transistor is longer than a channel length of the first transistor, a channel length of the second transistor, a channel length of the fourth transistor, and a channel length of the fifth transistor; Display device.

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