Packet buffer latency mitigation in a network device

The network device mitigates packet latency by using a memory controller to buffer packet data based on congestion states, employing a fast 'early forward' scheme for uncongested interfaces, ensuring data availability at the egress processor and reducing transmission latency.

WO2025202999A1PCT designated stage Publication Date: 2025-10-02MARVELL ASIA PTE LTD
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Patent Information

Application Number
PCT/IB2025/053315
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-03-28
Filing Date
2025-03-28
Publication Date
2025-10-02

AI Technical Summary

Technical Problem

Network devices experience latency in packet transmission due to the temporary storage of packets in packet memory, particularly when network interfaces are not congested, as the time taken to issue and receive packet data from the memory adds unnecessary delay.

Method used

A network device employs a memory controller to buffer packet data based on congestion states of network interfaces, using a first buffering scheme for congested interfaces and a second, faster 'early forward' scheme for uncongested interfaces, where packet data is transmitted without waiting for a read request, reducing latency by storing data in both a shared buffer and an early forward queue.

Benefits of technology

This approach reduces or eliminates latency in packet transmission by ensuring packet data is available at the egress processor when ready to be transmitted, without requiring excessively large cache memory, and maintains efficient data transmission even in cases of internal congestion.

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Abstract

A network device includes a plurality of network interfaces and an ingress processor configured to process packets received by the network device to determine network interfaces, among the plurality of network interfaces, via which the packets are to be transmitted by the network device. The network device also includes a memory device configured to buffer packet data corresponding to the packets while the packets are being processed by the network device and a memory controller configured to select a buffering scheme for buffering a packet in the memory device based on a congestion state of a network interface via which the packet is to be transmitted. The buffering scheme is selected among a first buffering scheme having a first latency associated with buffering packet data and a second buffering scheme having a second latency, smaller than the first latency, associated with buffering packet data.
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Citation Information

Patent Citations

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  • Shared memory switch fabric system and method

    US9985912B1