Semiconductor light-receiving element, method for manufacturing semiconductor light-receiving element, optical-line-terminating device, multi-value intensity modulation transmission / reception device, digital coherent reception device, optical fiber radio system, spad sensor system, and lidar device

Abstract

A semiconductor light-receiving element (100) according to the present disclosure comprises: a substrate (1); a first mesa structure (30) having at least an n-type semiconductor layer (2, 3), a multiplication layer (4), a p-type electric field relaxation layer (5), a light absorption layer (6), and an i-type semiconductor layer (8) having a larger band gap than the light absorption layer (6), said layers being sequentially formed on the substrate (1); a second mesa structure (31) having at least a window layer (9) having a larger band gap than the light absorption layer (6), the second mesa structure (31) being formed on the first mesa structure (30); and a terrace part (40) comprising the outermost surface of the first mesa structure (30) exposed to the outer-peripheral side of the second mesa structure (31).

Description

Semiconductor photodetector, method of manufacturing semiconductor photodetector, optical line terminal, multilevel intensity modulation transmitter / receiver, digital coherent receiver, radio-on-fiber system, SPAD sensor system, and lidar device

[0001] The present disclosure relates to a semiconductor photodetector, a method for manufacturing a semiconductor photodetector, an optical line terminal, a multilevel intensity modulation transceiver, a digital coherent receiver, an optical fiber radio system, a SPAD sensor system, and a LIDAR device.

[0002] Along with the progress of digital transformation that utilizes digital information, there has been remarkable development of communication networks that mutually communicate digital information and data centers that store and process data. Optical communication is used for communication networks and communication within data centers. Optical communication has made remarkable progress in recent years in increasing speed and capacity. With the development of optical communication, photodiodes (PDs) and avalanche photodiodes (APDs) that can provide high receiving sensitivity are required as optical communication receivers.

[0003] Passive Optical Networks (PONs) are the primary method used in access networks that connect optical communication subscribers. PON systems began with G(E)-PON systems that transmit signals at 1-2 Gbps, and are expected to see an increase in 10G-EPON and XG-PON systems that transmit signals at 10 Gbps.

[0004] Furthermore, the International Telecommunication Union Telecommunication Standardization Sector (ITU-T) is studying the 50G-PON system, a next-generation high-speed PON system, and it is expected that 50 Gbps-class transmission will also be put into practical use in access networks in the future.

[0005] Patent No. 4609430 Patent No. 4985298 Patent No. 5025330 JP 11-354827 JP 3-050875 JP 2002-324911

[0006] Jiyuan Zheng, et al. , “Digital Alloy InAlAs Avalanche Photodiodes”, JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 36, NO. 17, SEPTEMBER 1, pp. 3580-3585, 2018

[0007] (1) Issues Related to the Multiplication Layer in APDs APDs, which are semiconductor photodetectors used in PON systems, have a device structure consisting of a light absorption layer (InGaAs), an electric field relaxation layer (InP or InAlAs), and a multiplication layer (InP or InAlAs). A high electric field of approximately 800 kV / cm is applied to the multiplication layer to multiply, or ionize, the electrons and holes generated in the light absorption layer. The electric field relaxation layer functions to weaken the electric field so that the high electric field of the multiplication layer is not applied to the light absorption layer. Incidentally, the ionization rate of electrons is expressed as α, and the ionization rate of holes as β.

[0008] In an APD, the greater the difference between the ionization rates of electrons and holes, the smaller the excess noise generated during multiplication and the higher the receiver sensitivity.Furthermore, the greater the difference between the ionization rates of electrons and holes, the shorter the multiplication time in the multiplication layer, resulting in a wider response band.

[0009] The ionization rate ratio k of electrons and holes is defined as k = β / α. When electrons are injected into the multiplication layer, the smaller the ionization rate ratio k, the better the performance of the APD. The multiplication layer of an APD for optical communication uses a compound semiconductor material such as InAlAs or InP.

[0010] When InAlAs is selected as the material for the multiplication layer, the difference between the ionization rates of electrons and holes is greater than when InP is used. In InP, the ionization rate of holes is greater than that of electrons, and the ionization rate of holes is approximately twice that of electrons. On the other hand, when InAlAs is selected as the material for the multiplication layer, the ionization rate of electrons is greater than that of holes, and the ionization rate of electrons is approximately five times that of holes. Therefore, since the receiver sensitivity is higher when InAlAs is used as the multiplication layer, InAlAs is more suitable than InP as the material for the multiplication layer of an APD.

[0011] As mentioned above, in a PON system, a wide response band and high receiving sensitivity are required for the APD, which is a semiconductor light receiving element. However, unlike a PD, an APD has a problem in that the time required for multiplication, that is, the multiplication time, increases as the multiplication factor increases, resulting in a decrease in the response band at high multiplication factors.

[0012] Although APDs with a multiplication layer made of InAlAs, which is used in optical communications, have a wider response band than APDs made of other semiconductor materials, the response band remains at approximately 20 GHz when the multiplication factor is 6 or more. In other words, there is a problem in that it is difficult to achieve the wide response band of 37.5 GHz or more required for 50G-PON systems when conventional APDs are used.

[0013] As mentioned above, APDs, which are semiconductor light-receiving elements used in optical communications, are required to operate over an even wider response band. Patent Document 5 describes an APD that uses a superlattice as a multiplication layer, but because each layer of the superlattice has a thickness of 5 to 10 nm, it acts as a quantum well that reflects the band gap of each layer. If the thickness of each stacked layer exceeds several nm, energy unevenness that reflects the band gap of each layer will occur, hindering the movement of carriers and reducing their movement speed.

[0014] In a 50G-PON system, the response bandwidth of the semiconductor light-emitting element and the semiconductor light-receiving element, as well as the optical output of the semiconductor light-emitting element and the receiving sensitivity of the semiconductor light-receiving element, are insufficient. For this reason, it is being considered to provide a digital bandwidth compensation circuit using a digital signal processor (DSP) after the APD in the optical network unit (ONU), i.e., the receiving device on the subscriber side.

[0015] Furthermore, in the optical line terminal (OLT), i.e., the receiving device on the central office side, a semiconductor optical amplifier (SOA) is required to compensate for the lack of receiving sensitivity of the semiconductor light receiving element, or an SOA must be integrated into the electro-absorption modulated laser diode (EML) on the transmitting side of the ONU to increase the optical output.

[0016] However, DSPs and SOAs consume a lot of power, which increases costs, and there are fears that the replacement of existing PON systems with 50G-PON systems will not progress.

[0017] In existing PON systems other than the next-generation high-speed PON system, increasing the number of branches of the optical signal output from the OLT is being considered to reduce costs. However, even in this case, it is necessary to integrate an SOA in the EML on the transmitting side of the OLT and ONU to increase the optical output, which causes problems such as increased power consumption of the transmitter and increased costs.

[0018] As described above, in order to compensate for the limitations of the receiving sensitivity and response bandwidth of semiconductor photodetectors, transceivers have been designed that incorporate expensive and power-hungry DSPs and SOAs into the ONU and OLT, but this results in problems such as increased power consumption and increased costs.

[0019] In order to solve the above-mentioned problems related to the multiplication layer in APDs, the application of a digital alloy structure to the multiplication layer, in which the ionization rate ratio k is significantly reduced compared to a random alloy structure, has been considered, as described in Non-Patent Document 1. However, there are problems that must be solved in order to apply a digital alloy structure multiplication layer to an APD having a highly reliable p-type impurity diffusion structure.

[0020] (2) Issues Related to the Formation of a P-Type Impurity Region in an APD with a P-Type Impurity Diffusion Structure Patent Document 1 and other publications describe an APD with a p-type impurity diffusion structure. In an APD with a p-type impurity diffusion structure, a convex p-type impurity diffusion region, i.e., a p-type region, is formed on the bottom side, concentrating the electric field in the light-receiving region and suppressing local multiplication (edge ​​breakdown) at the periphery of the light-receiving region. Because an APD with a p-type impurity diffusion structure does not experience edge breakdown, it has an excellent structure with low dark current and highly reliable device characteristics. In an APD with a p-type impurity diffusion structure, a p-type region is formed in an i-type InP window layer by Zn diffusion, and a pn junction is formed and a reverse bias is applied, so that an electric field is applied to the light absorption layer, the electric field buffer layer, and the multiplication layer. The applied electric field creates a depletion layer between the deepest part of the p-type region and the n-type semiconductor layer.

[0021] A necessary condition for a wide response band APD is that the transit time of carriers traveling through the depletion layer must be short. The 3-dB bandwidth ftr, determined by the transit time of carriers through the depletion layer in the light-absorbing layer, is expressed by the following equation (1): ftr = 3.5Vav / (2πW) (1). In equation (1), W is the thickness of the depletion layer formed in the light-absorbing layer, and Vav is the average saturated transit velocity of electrons and holes. The response band of the entire APD is determined by the transit time through the depletion layer formed in the light-absorbing layer, as described above, as well as the RC time constant, multiplication time, and the time it takes for carriers to diffuse through the p-type region in the light-absorbing layer. As can be seen from equation (1), ftr is inversely proportional to the thickness of the depletion layer. Therefore, to achieve a wide response band, it is necessary to thin the thickness of the depletion layer by converting part of the light-absorbing layer into a p-type region.

[0022] Therefore, it is necessary to perform thermal diffusion of p-type impurities such as Zn at high temperatures for a long period of time so that the deepest part of the p-type impurity diffusion region reaches the light absorption layer. However, if the Zn diffusion time at high temperatures is long, the dopants contained in the p-type InP field relaxation layer thermally diffuse into each layer in the vertical direction, and the required amount of field relaxation cannot be obtained. As a result, a high electric field is applied to the light absorption layer, causing tunnel breakdown and preventing multiplication. Alternatively, even if multiplication occurs, a high dark current flows. In particular, when the multiplication layer has a digital alloy structure, the thermal diffusion of the p-type impurities into the multiplication layer causes disordering of the digital alloy structure, resulting in an increase in multiplication noise.

[0023] In this way, if the thermal diffusion of p-type impurities is carried out for a long period of time in order to shorten the carrier transit time, and the deepest part of the p-type impurity diffusion region is formed inside the light absorption layer, problems such as a loss of multiplication, an increase in dark current, and an increase in multiplication noise may occur.

[0024] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor photodetector having excellent device characteristics such as operation over a wide response band, a method for manufacturing the same, and equipment using the semiconductor photodetector.

[0025] The semiconductor light-receiving element according to the present disclosure comprises: a substrate; a first mesa structure having at least an n-type semiconductor layer, a multiplication layer, a p-type electric field buffer layer, a light absorption layer, and an i-type semiconductor layer having a band gap larger than that of the light absorption layer, which are sequentially formed on the substrate; a second mesa structure formed on the first mesa structure and having at least a window layer having a band gap larger than that of the light absorption layer; and a terrace portion consisting of the outermost surface of the first mesa structure exposed on the outer periphery of the second mesa structure.

[0026] a selective diffusion mask formed of an insulating film having a substantially circular opening on a surface of the p-type contact layer; a p-type impurity diffusion region having a bottom extending from the opening to at least the interior of the light absorption layer; a removing step of the selective diffusion mask; a step of processing the p-type contact layer into a ring shape along an outer periphery of the light receiving region; a step of etching the outer periphery of the light receiving region until at least the i-type semiconductor layer is exposed on the surface, thereby forming a second mesa structure; and a step of etching a portion of the second mesa structure other than a predetermined region from the outer periphery.

[0027] The optical line terminal device according to the present disclosure comprises the above-mentioned semiconductor photodetector; an optical multiplexer / demultiplexer that inputs an optical signal to the semiconductor photodetector; an amplifier circuit that amplifies an electrical signal output from the semiconductor photodetector; a clock and data recovery circuit connected to the amplifier circuit that recovers clock data from the amplified electrical signal; and a forward error correction circuit connected to the clock and data recovery circuit that corrects errors in the clock data.

[0028] The multilevel intensity modulation transceiver according to the present disclosure includes the above-described semiconductor photodetector that receives an optical signal that has been intensity-modulated into multiple levels; an amplifier circuit that amplifies an electrical signal output from the semiconductor photodetector; an analog-to-digital conversion circuit that is connected to the amplifier circuit and converts the amplified electrical signal into a digital signal; and a digital signal processing circuit that is connected to the analog-to-digital conversion circuit and processes the digital signal.

[0029] The radio-on-fiber system according to the present disclosure includes: a light source that emits an analog-modulated optical signal; the above-described semiconductor photodetector that receives the analog-modulated optical signal; a transmission path that transmits the analog electrical signal output from the semiconductor photodetector to an antenna; and an antenna that is connected to the transmission path and emits the analog electrical signal as a radio wave signal.

[0030] The digital coherent receiving device according to the present disclosure comprises the semiconductor photodetector described above, a polarization separator that separates the polarizations of a polarization multiplexed optical signal whose intensity and phase are modulated, a 90-degree hybrid that splits and combines the optical signal output from the polarization separator, and a digital signal processing circuit that is connected to the 90-degree hybrid and processes digital signals.

[0031] A SPAD (Single Photon Avalanche Diode) sensor system according to the present disclosure includes: a SPAD sensor configured with the above-described semiconductor light-receiving element; a quenching circuit that repeatedly applies a voltage equal to or greater than a breakdown voltage and a voltage less than the breakdown voltage to the SPAD sensor; and a photoelectron measurement circuit that measures an electrical signal output from the SPAD sensor.

[0032] The LIDAR device according to the present disclosure comprises a light source that emits light in pulses, the above-mentioned semiconductor light receiving element that receives light that is emitted from the light source and reflected by an object, an amplifier circuit that amplifies the electrical signal output from the semiconductor light receiving element, and a ranging circuit that calculates distance based on the electrical signal amplified by the amplifier circuit.

[0033] According to the semiconductor light receiving element and the method for manufacturing a semiconductor light receiving element according to the present disclosure, since a terrace portion is provided, it is possible to obtain a semiconductor light receiving element and a method for manufacturing a semiconductor light receiving element that have excellent element characteristics such as operation over a wide response band.

[0034] According to the optical line terminal device, multi-level intensity modulation transceiver device, digital coherent receiver device, optical fiber radio system, SPAD sensor system, and LIDAR device of the present disclosure, the semiconductor photodetector element of the present disclosure is used as the semiconductor photodetector element, thereby achieving the effect of obtaining each device and system with excellent performance.

[0035] FIG. 6A is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to the first embodiment. FIG. 6B is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to the first embodiment, after epitaxial crystal growth. FIG. 6C is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to the first embodiment, after a p-type impurity diffusion step. FIG. 6D is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to the first embodiment, after a contact layer has been patterned. FIG. 6E is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to the first embodiment, after a window layer has been patterned. FIG. 6F is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to the first embodiment, after a mesa groove has been patterned, and FIG. 6G is a top view. FIG. 6G is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to the first embodiment, after a surface protective film has been formed and patterned. FIG. 6G is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to the first embodiment, after a surface electrode has been formed and patterned. 10A is a cross-sectional view showing the element structure of a back-illuminated APD as a comparative example of embodiment 1. FIG. 10A is a cross-sectional view after epitaxial crystal growth in a manufacturing method of a back-illuminated APD as an example of a semiconductor light-receiving element according to embodiment 1, and FIG. 10B is a cross-sectional view after epitaxial crystal growth in a manufacturing method of a back-illuminated APD as a comparative example. FIG. 11A is a cross-sectional view after a p-type impurity diffusion step in a manufacturing method of a back-illuminated APD as an example of a semiconductor light-receiving element according to embodiment 1, and FIG. 11B is a cross-sectional view after a p-type impurity diffusion step in a manufacturing method of a back-illuminated APD as a comparative example. FIG. 11B is a cross-sectional view showing the element structure of a back-illuminated APD as an example of a semiconductor light-receiving element according to embodiment 2. FIG. 14A to FIG. 14C are conceptual diagrams showing the ionization rates of electrons and holes. FIG. 14C is a diagram showing the layer thickness dependence of the ionization rate ratio and the tunnel current of the multiplication layer.16A to 16D are conceptual diagrams showing the ionization rates in the multiplication layer and the electric field relaxation layer, where FIG. 16A shows the ionization rate in the case of a random alloy structure multiplication layer, FIG. 16B shows the ionization rate in the case of a digital alloy structure multiplication layer, FIG. 16C shows the ionization rate in the case of a partially disordered digital alloy structure multiplication layer, and FIG. 16D shows the ionization rate in the case of a combination of a thick electric field relaxation layer and a digital alloy structure multiplication layer. It is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to a first modification of the second embodiment. It is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to a second modification of the second embodiment. It is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to a third modification of the second embodiment. It is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to a fourth modification of the second embodiment. It is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to a fifth modification of the second embodiment. 30A and 30B are conceptual diagrams illustrating received waveforms of a multi-level intensity modulation transmitting / receiving device according to a fifth embodiment. 31A and 31B are conceptual diagrams illustrating the operation of a PD at a high optical input. 31B are conceptual diagrams illustrating the operation of a PD at a high optical input. 31C are conceptual diagrams illustrating the operation of a PD at a high optical input. 31D are conceptual diagrams illustrating the operation of a PD at a high optical input. 31E are conceptual diagrams illustrating the operation of a PD at a high optical input. 31F are conceptual diagrams illustrating the operation of a PD at a high optical input. 31G are conceptual diagrams illustrating the operation of a PD at a high optical input. 31G are conceptual diagrams illustrating the operation of a PD at a high optical input. 31H are conceptual diagrams illustrating the operation of a PD at a high optical input. 31H are conceptual diagrams illustrating the operation of a PD at a high optical input. 10 is a diagram showing the residence time of electrons and holes for each material constituting a multiplication layer. FIG. 11 is a diagram showing the configuration of a radio-on-fiber system according to a sixth embodiment. FIG. 12 is a diagram showing the configuration of a radio-on-fiber system as a comparative example.37A is a diagram showing the configuration of a digital coherent receiving device according to embodiment 7. FIG. 37A is a conceptual diagram showing waveforms of a digital coherent receiving device as a comparative example, and FIG. 37B is a conceptual diagram showing waveforms of a digital coherent receiving device according to embodiment 7. FIG. 37B is a conceptual diagram showing waveforms of a digital coherent receiving device according to embodiment 7. FIG. 37A is a conceptual diagram showing waveforms of a digital coherent receiving device according to embodiment 7. ...A is a conceptual diagram showing waveforms of a digital coherent receiving device according to embodiment 7. FIG. 37B is a conceptual diagram showing waveforms of a digital coherent receiving device according to embodiment 7.

[0036] 1 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element 100 according to embodiment 1. In the following description, the upper side refers to the direction in which semiconductor layers are stacked from the surface of a semiconductor substrate, i.e., the stacking direction, and the lower side refers to the direction opposite to the stacking direction, in other words, the direction from the surface side on which the semiconductor layers are formed to the back side of the semiconductor substrate.

[0037] <Element Structure of Semiconductor Photodetector (APD) According to First Embodiment> A back-illuminated APD, which is an example of the semiconductor photodetector 100 according to the first embodiment, includes an Fe-doped InP substrate 1 and an Fe-doped InP substrate 1 having a carrier concentration of 5×10 17 ~8 x 10 18 cm -3 and an n-type InP conductive layer 2 having a thickness of 0.1 to 1.0 μm and a carrier concentration of 5×10 17 ~8 x 10 18 cm -3 and an n-type InAlAs conductive layer 3 having a layer thickness of 0.1 to 1.0 μm, an i-type InAlAs multiplication layer 4, and a carrier concentration of 1×10 16 ~5 x 10 18 cm -3The semiconductor device includes a p-type InAlAs field relaxation layer 5 having a thickness of 10 to 100 nm, an i-type InGaAs light absorption layer 6 having a thickness of 0.1 to 2.0 μm, an i-type InAlGaAs graded layer 7 having a thickness of 5 to 100 nm and in which the composition wavelength is gradually shortened, and an i-type InAlAs surface protection layer 8 having a thickness of 10 to 200 nm, and an n-type InP conductive layer 2 as a semiconductor layer exposed on the outer periphery, the first mesa structure 30 having a substantially circular surface in a top view, and a plurality of semiconductor layers having a carrier concentration of 5×10 17 ~8 x 10 18 cm -3 and a p-type InP window layer 9 having a thickness of 0.1 to 3.0 μm and a carrier concentration of 5×10 17 ~8 x 10 18 cm -3 a p-type InGaAs contact layer 10 having a ring shape along the outer periphery of a light-receiving region 60 having a thickness of 0.05 to 0.5 μm and a thickness of 0.05 to 0.5 μm, the p-type InGaAs contact layer 10 having a ring shape along the outer periphery of the light-receiving region 60 having a substantially circular shape in a top view; a second mesa structure 31 having a substantially circular surface in a top view; a p-type impurity diffusion region 20 provided in a part of the p-type InP window layer 9 and the i-type InGaAs light absorption layer 6 on the inner periphery side of the ring-shaped p-type InGaAs contact layer 10; a terrace portion 40 consisting of an outermost surface of the first mesa structure 30 exposed on the outer periphery side of the second mesa structure 31 and having a region with a width of 0.5 μm or more in the outer periphery direction; and a surface protection film 11 consisting of an insulating film covering the first mesa structure 30, the side portions of the first mesa structure 30, and the terrace portion 40. the p-type InP window layer 9 corresponding to the inner periphery of the ring-shaped p-type InGaAs contact layer 10, i.e., the substantially circular light-receiving region 60; an n-type electrode 50 formed on the surface of the n-type InP conductive layer 2 exposed as a semiconductor layer on the outer periphery of the first mesa structure 30; a p-type electrode 51 provided on the surface of the ring-shaped p-type InGaAs contact layer 10 and on the surface of the front-side antireflection coating 15; a back-side antireflection coating 16 provided on the back side of the Fe-doped InP substrate 1 at a position opposite to the p-type electrode 51; and a back-side electrode 52 provided on the outer periphery of the back-side antireflection coating 16 on the back side of the Fe-doped InP substrate 1.

[0038] In the present disclosure, i-type refers to undoped or an i-type semiconductor having a p-type impurity concentration or an n-type impurity concentration of 5×10 17 cm -3 This means the following cases:

[0039] As described above, the terrace portion 40 is made up of the outermost surface of the first mesa structure 30 exposed on the outer periphery side of the second mesa structure 31, and has a region with a width of 0.5 μm or more in the outer periphery direction. In the above-described configuration, the outermost surface of the first mesa structure 30 exposed on the outer periphery side is the upper surface of the i-type InAlAs surface protective layer 8. In the following description, the surface exposed as a semiconductor layer in the terrace portion 40 is referred to as a terrace surface 41. For example, in the above-described configuration, the upper surface of the i-type InAlAs surface protective layer 8, i.e., the upper surface, is the terrace surface 41. Note that the upper surface refers to, for example, the upper one of the two surfaces of the i-type InAlAs surface protective layer 8, i.e., the surface opposite to the Fe-doped InP substrate 1.

[0040] The p-type electrode 51 also functions as a reflective film that returns to the i-type InGaAs light absorption layer 6 the light 90 incident from the back surface side of the Fe-doped InP substrate 1 that has been transmitted to the front surface side without being absorbed by the i-type InGaAs light absorption layer 6.

[0041] The p-type InP window layer 9 may be formed of a p-type InAlAs layer, a p-type InAlGaAs layer, or a p-type InGaAsP layer instead of a p-type InP layer. The window layer may also be formed of a multi-layer structure in which two or more layers selected from the group consisting of p-type InP, p-type InAlAs, p-type InAlGaAs, and p-type InGaAsP are stacked. The i-type InAlAs surface protective layer 8 also functions as a gooding layer that reduces the band gap difference between the two layers above and below the i-type InAlAs surface protective layer 8.

[0042] An i-type InP layer may be used as the surface protective layer instead of the i-type InAlAs surface protective layer 8. Using the i-type InP layer as the surface protective layer makes it possible to prevent oxidation of the terrace surface 41 of the terrace portion 40, thereby achieving the effect of extending the life of the semiconductor light-receiving element.

[0043] When the i-type InP layer is used as the surface protective layer, the window layer may be a p-type InAlAs layer, which facilitates the formation of the terrace 40 by selective etching. When the i-type InP layer is used as the surface protective layer, an i-type InAlAs layer may be provided between the i-type InAlGaAs graded layer 7 and the i-type InP surface protective layer to reduce the band gap step between the i-type InAlGaAs graded layer 7 and the i-type InP surface protective layer.

[0044] Here, the graded layer is a layer for reducing the step between the valence band and the conduction band that occurs when semiconductor materials of different materials or different compositions are stacked.Specific examples of the graded layer include a layer composed of multiple layers having a band gap intermediate between the two stacked layers, a layer having a material composition that forms an intermediate energy step in the valence band and the conduction band even if it does not have an intermediate band gap, and a layer in which two stacked layers are alternately stacked at a short period of several nanometers or less.

[0045] The p-type InAlAs field relaxation layer 5 may have either a random alloy structure or a digital alloy structure. Alternatively, the field relaxation layer may be made of a p-type InP layer. A graded layer made of an i-type InAlGaAs layer or an i-type InGaAsP layer may be provided between the p-type InAlAs field relaxation layer 5 and the i-type InGaAs light absorption layer 6.

[0046] <Method of Manufacturing Semiconductor Light-Receiving Element According to First Embodiment> A method of manufacturing a back-illuminated APD, which is an example of the semiconductor light-receiving element 100 according to the first embodiment, will be described with reference to FIGS. 2 to 8 as needed.

[0047] First, on an Fe-doped InP substrate 1, an n-type InP conductive layer 2, an n-type InAlAs conductive layer 3, an i-type InAlAs multiplication layer 4, a p-type InAlAs field relaxation layer 5, an i-type InGaAs light absorption layer 6, an i-type InAlGaAs graded layer 7, an i-type InAlAs surface protection layer 8, a p-type InP window layer 9, and a p-type InGaAs contact layer 10 are epitaxially grown in this order from the Fe-doped InP substrate 1 side. Figure 2 is a cross-sectional view of the back-illuminated APD after each epitaxially grown layer in the manufacturing method thereof according to the first embodiment.

[0048] Examples of epitaxial crystal growth methods include metal organic vapor phase epitaxy (MOVPE) and molecular beam epitaxy (MBE).

[0049] As the n-type impurity (n-type dopant) of the epitaxial crystal growth layer, sulfur (S) or silicon (Si) is preferred. As the p-type impurity (p-type dopant), zinc (Zn), beryllium (Be), carbon (C), cadmium (Cd), and magnesium (Mg) are preferred. The crystal growth temperature during epitaxial crystal growth is preferably in the range of 450°C to 800°C in the case of MOVPE, and in the range of 500°C to 800°C in the case of MBE.

[0050] The wafer after epitaxial crystal growth of the back-illuminated APD according to the first embodiment is characterized in that an i-type InAlAs surface protection layer 8 is provided, and that the InP window layer and the InGaAs contact layer are p-type rather than i-type.

[0051] A selective diffusion mask 12 made of an insulating film such as a SiN film or a SiO2 film is formed on the surface of the p-type InGaAs contact layer 10, and an opening is provided in the portion that will become the light-receiving region 60. P-type impurities such as Zn, Cd, or Mg are thermally diffused into the semiconductor layer by vapor-phase diffusion or solid-phase diffusion, thereby forming the p-type impurity diffusion region 20. The diffusion temperature is set within a range of 400°C to 800°C. The thermal diffusion is controlled so that the deepest portion of the p-type impurity diffusion region 20 is located inside the i-type InGaAs light absorption layer 6. FIG. 3 is a cross-sectional view of the back-illuminated APD after the p-type impurity diffusion step in the manufacturing method for the first embodiment.

[0052] The depth of the p-type impurity diffusion into the i-type InGaAs light absorption layer 6 is controlled to 0.3 μm or less. If the p-type impurity diffusion is too deep into the i-type InGaAs light absorption layer 6, a problem occurs in that the light receiving sensitivity decreases due to the influence of carrier recombination in the p-type i-type InGaAs light absorption layer 6. Therefore, the optimum depth of the p-type impurity diffusion into the i-type InGaAs light absorption layer 6 is within the range of 0.05 to 0.3 μm.

[0053] In the back-illuminated APD according to the first embodiment, the p-type InP window layer 9 and the p-type InGaAs contact layer 10 are doped in advance with p-type impurities such as Zn, Be, C, Cd, or Mg during epitaxial crystal growth.

[0054] For example, as shown in FIG. 3 , when Zn is subjected to solid-phase diffusion into the Zn- or Be-doped p-type InGaAs contact layer 10 and the p-type InP window layer 9, the pre-doped Zn or Be starts thermal diffusion downward, i.e., toward the Fe-doped InP substrate 1, without waiting for the arrival of newly added Zn from the outside, and therefore the p-type impurity thermally diffuses into the i-type InGaAs light absorption layer 6 in a short time.

[0055] In particular, when Zn is thermally diffused into the p-type InGaAs contact layer 10 and the p-type InP window layer 9 that have been doped with Be in advance, inter-diffusion (or mutual diffusion) of Be and Zn occurs, i.e., the phenomenon occurs in which Be and Zn replace impurity atoms already present in the semiconductor layer in a short time. This inter-diffusion allows the atoms that serve as the diffusion source, i.e., Zn, to reach the deepest part of the p-type impurity diffusion region 20 in an extremely short time. Zn has a higher diffusion rate than Be, and therefore Zn inter-diffuses into the i-type InGaAs light absorption layer 6 in a short time, which significantly reduces the diffusion time.

[0056] On the other hand, it is preferable to maintain a thick depletion layer on the outer periphery of the light-receiving region 60, i.e., the region covered with the selective diffusion mask 12, by preventing as much p-type impurity as possible from entering the i-type InGaAs light absorption layer 6. Since vacancies are unlikely to occur in the region covered with the selective diffusion mask 12, the p-type impurity is unlikely to thermally diffuse into the i-type InGaAs light absorption layer 6.

[0057] In particular, when the pre-doped p-type impurity is Be, the diffusion rate of Be is lower than that of Zn as described above, and therefore interdiffusion of Be into the i-type InGaAs light absorption layer 6 is less likely to proceed, thereby maintaining a thick depletion layer. Therefore, a suitable combination of impurity species is to use Be as the p-type impurity doped in the epitaxial crystal growth of the p-type InGaAs contact layer 10 and the p-type InP window layer 9, and Zn as the p-type impurity thermally diffused in the subsequent p-type impurity diffusion step.

[0058] After the above-described p-type impurity diffusion step, the p-type InGaAs contact layer 10 is processed into a ring shape when viewed from above. Figure 4 is a cross-sectional view of the p-type InGaAs contact layer 10 after processing into a ring shape in the method for manufacturing a back-illuminated APD according to the first embodiment. The ring-shaped p-type InGaAs contact layer 10 is processed so that its inner diameter is approximately the same as or smaller than that of the p-type impurity diffusion region 20. On the other hand, the outer diameter of the ring-shaped p-type InGaAs contact layer 10 may be smaller or larger than that of the p-type impurity diffusion region 20.

[0059] Next, the p-type InP window layer 9 exposed on the outer peripheral surface of the ring-shaped p-type InGaAs contact layer 10 is removed by etching down to the surface of the i-type InAlAs surface protective layer 8. Figure 5 is a cross-sectional view of the back-illuminated APD according to the first embodiment after patterning the p-type InP window layer 9.

[0060] However, it is not always necessary to etch the p-type InP window layer 9 until it is completely removed. In other words, it is sufficient if the p-type InP window layer 9 can be mostly removed by etching, and the p-type window layer 9 may remain on the surface of the i-type InAlAs surface protective layer 8 as long as it has a thickness of about 100 nm. The reason for this is that if the partially remaining p-type InP window layer 9 is thin, the remaining p-type InP window layer 9 also becomes depleted when a voltage is applied to the APD, thereby functioning to alleviate the electric field in the terrace portion 40.

[0061] Furthermore, the etching depth may be set to about 100 nm from the lower surface of the i-type InAlAs surface protective layer 8 so that the etching surface reaches the inside of the i-type InAlGaAs graded layer 7 or the inside of the i-type InGaAs light absorption layer 6. The reason for this is that even if p-type impurities are thermally diffused downward from the p-type InP window layer 9 during the heat treatment for thermal diffusion, the electric field in the terrace portion 40 can be alleviated by removing the region into which the p-type impurities are thermally diffused in a subsequent process.

[0062] The p-type InP window layer 9 and the i-type InAlAs surface protective layer 8 may both be formed of InP layers. Alternatively, the p-type InP window layer 9 may be formed of a p-type InAlAs layer, and the i-type InAlAs surface protective layer 8 may be formed of an i-type InP layer. In the latter case, the window layers can be easily selectively etched.

[0063] By etching the p-type InP window layer 9 as described above, a second mesa structure 31 is formed, which has a substantially circular surface in top view, and which includes the p-type InP window layer 9 and the p-type InGaAs contact layer 10 that has a ring shape along the outer periphery of the light-receiving region 60 that has a substantially circular shape in top view, which are sequentially formed on the first mesa structure 30 described below.

[0064] A mesa groove 35 is formed by leaving a terrace portion 40 having a width of 1 μm or more in the circumferential direction on the outer periphery of the substantially circular second mesa structure 31, i.e., on the outer periphery of the etched p-type InP window layer 9, with the upper surface of the i-type InAlAs surface protective layer 8 as the outermost surface, i.e., terrace surface 41, and further etching the semiconductor layer on the outer periphery until the etched surface reaches the n-type InAlAs conductive layer 3 or the n-type InP conductive layer 2. The mesa groove 35 may be deep enough to physically separate the i-type InAlAs multiplication layer 4 and not to have its bottom etched to reach the Fe-doped InP substrate 1. Figures 6A and 6B are a cross-sectional view and a top view, respectively, of the mesa groove 35 after its bottom etched to reach the n-type InP conductive layer 2 in the method for manufacturing a back-illuminated APD according to the first embodiment.

[0065] The steps from patterning the p-type InGaAs contact layer 10 into a ring shape in Fig. 4 to forming the mesa groove in Fig. 6 may be performed in any order. For example, the p-type InP window layer 9 may be etched into a substantially circular shape in top view so that the etched surface reaches the i-type InAlAs surface protective layer 8, and then the p-type InGaAs contact layer 10 on the inner periphery may be etched away, leaving only the outer periphery of the substantially circular p-type InGaAs contact layer 10. Alternatively, the mesa groove 35 may be formed first, and then the p-type InP window layer 9 and the p-type InGaAs contact layer 10 may be patterned.

[0066] By etching the semiconductor layers on the outer periphery of the second mesa structure 31 and the terrace portion 40, a first mesa structure 30 is formed, which has an n-type InP conductive layer 2, an n-type InAlAs conductive layer 3, an i-type InAlAs multiplication layer 4, a p-type InAlAs field relaxation layer 5, an i-type InGaAs light absorption layer 6, an i-type InAlGaAs graded layer 7, and an i-type InAlAs surface protection layer 8, which are formed in this order on the Fe-doped InP substrate 1, with the n-type InP conductive layer 2 exposed on the outer periphery as a semiconductor layer and having a substantially circular surface in top view. In other words, the outermost surface of the first mesa structure 30 is exposed on the terrace portion 40 as a semiconductor layer.

[0067] After the first mesa structure 30 is formed on the wafer, a surface protection film 11 and a front-side antireflection film 15 made of SiN are deposited. Openings are formed in the surface protection film 11 formed on the surface of the ring-shaped p-type InGaAs contact layer 10 and on the surface of the n-type InP conductive layer 2 exposed at the bottom of the mesa groove 35 by the above-described etching. Instead of a SiN film, an insulating film made of an organic material such as a SiO film, a SiON film, a BCB (benzocyclobutene) film, or a polyimide may be used. Figure 7 is a cross-sectional view after the surface protection film 11 and the front-side antireflection film 15 made of SiN are deposited and the openings are patterned in the method for manufacturing a back-illuminated APD according to the first embodiment.

[0068] Next, a p-type electrode 51 is formed on the ring-shaped p-type InGaAs contact layer 10 and on the insulating film made of a SiN film of the light-receiving region 60, and an n-type electrode 50 is formed on the surface of the n-type InP conductive layer 2 exposed on the outer periphery of the first mesa structure 30. Fig. 8 is a cross-sectional view showing the device structure after the p-type electrode 51 and the n-type electrode 50 are formed in the method for manufacturing a back-illuminated APD according to the first embodiment.

[0069] The p-type electrode 51 and the n-type electrode 50 are formed from a combination of multiple metal films, such as Ti / Au, Ti / Pt / Au, Pt / Ti / Pt / Au, or Pt / Ti / Au / Ti / Pt / Au, from bottom to top. When a back-illuminated APD is mounted in a junction-down configuration, the p-type electrode 51 may be formed from multiple metal films, such as Ti / Au / Ti / Pt / Au, from bottom to top. Pt is inserted into some of the multiple metal films because it functions as a barrier metal that prevents the diffusion of solder material into the back-illuminated APD.

[0070] The reason why the Fe-doped InP substrate 1 is used as the semiconductor substrate in the back-illuminated APD, which is an example of the semiconductor light-receiving element 100 according to the first embodiment, is that if an n-type InP substrate is used in a back-illuminated APD, the optical absorption loss due to the n-type InP substrate becomes slightly large. However, there is no particular problem with the operation of the APD even if an n-type InP substrate is used instead of the Fe-doped InP substrate 1. When an n-type InP substrate is used in a back-illuminated APD, an n-type electrode may be provided on the back side of the n-type InP substrate, and the back electrode of the back-illuminated APD may be used as the n-type electrode.

[0071] <Operation of Semiconductor Light-Receiving Element According to First Embodiment> The operation of the back-illuminated APD, which is an example of the semiconductor light-receiving element 100 according to the first embodiment shown in FIG. 1, will be described below.

[0072] In the back-illuminated APD according to the first embodiment, the p-type InGaAs contact layer 10 and the p-type InP window layer 9 are doped with p-type impurities such as Zn and Be in advance during epitaxial crystal growth. For example, if solid-phase or vapor-phase diffusion of Zn is performed externally into the p-type InGaAs contact layer 10 and the p-type InP window layer 9, which are semiconductor layers doped with Be, the Be already contained as a p-type impurity begins to diffuse downward without waiting for the arrival of Zn by solid-phase or vapor-phase diffusion. The interdiffusion of Be and Zn allows Zn to reach the deepest part of the p-type impurity diffusion region 20 in an extremely short time. That is, the p-type impurities, i.e., Zn and Be, interdiffuse within the i-type InGaAs light absorption layer 6 in a short time.

[0073] The diffusion depth is (diffusion time) 0.5 Since the diffusion time is proportional to the diffusion depth, if the depth required for diffusion is halved, the diffusion time will be ¼, and therefore, it will be possible to thermally diffuse the p-type impurity into the i-type InGaAs light absorption layer 6 in a short time. By shortening the diffusion time, it will be possible to prevent problems such as an increase in dark current caused by the p-type impurity pre-contained in the p-type InAlAs electric field relaxation layer 5 diffusing into the i-type InGaAs light absorption layer 6.

[0074] In the back-illuminated APD according to the first embodiment, the inner periphery of the ring-shaped p-type InGaAs contact layer 10 functions as the light-receiving region 60. In the light-receiving region 60, electrons generated by light absorbed in the i-type InGaAs light absorption layer 6 travel to the i-type InAlAs multiplication layer 4 side and are multiplied.

[0075] The deepest part of the p-type impurity diffusion region 20 penetrates approximately 0.2 μm into the i-type InGaAs light absorption layer 6. Since the thickness of the i-type InGaAs light absorption layer 6 is approximately 0.6 μm in a 50 Gbps APD, the thickness of the depletion layer inside the i-type InGaAs light absorption layer 6 is approximately 0.4 μm. As shown in the above equation (1), the response bandwidth determined by the time it takes for light to travel through the depletion layer inside the i-type InGaAs light absorption layer 6 is inversely proportional to the thickness of the depletion layer, and therefore the APD according to the first embodiment has improved reception sensitivity over a wide response bandwidth.

[0076] On the other hand, the depletion layer below the lower surface of the p-type InP window layer 9 becomes a depletion layer below the p-type InGaAs contact layer 10, and therefore the thickness of the depletion layer increases. Since the capacitance of the pn junction of an APD is inversely proportional to the thickness of the depletion layer, the capacitance is reduced, and therefore the response band determined by the RC time constant is improved in the back-illuminated APD according to the first embodiment.

[0077] For example, if the total layer thickness from the lower surface of the p-type InP window layer 9 to the upper surface of the n-type InAlAs conductive layer 3, i.e., DL1 in FIG. 1, is 0.9 μm, and the total layer thickness from the deepest part of the p-type impurity diffusion region 20 to the upper surface of the n-type InAlAs conductive layer 3, i.e., DL2 in FIG. 1, is 0.6 μm, then the capacitance per unit area below the p-type InGaAs contact layer 10 will be ⅔ (=0.6 μm / 0.9 μm) of the capacitance per unit area of ​​the light-receiving region 60.

[0078] A comparison is made between a back-illuminated APD according to the first embodiment, in which p-type impurities are thermally diffused only to the inner periphery of the ring-shaped p-type InGaAs contact layer 10, and a back-illuminated APD of a comparative example, described later, in which p-type impurities are thermally diffused to the outer periphery of the p-type InGaAs contact layer 10, when the capacitance of the p-n junction is set to an APD for 50 Gbps. The capacitance Cpn of the p-n junction is expressed by the following equation (2): Cpn=εr·ε0·S / Wt (2)

[0079] In equation (2), εr is the relative permittivity, ε0 ​​is the dielectric constant of a vacuum (= 8.85 × 10 -18 F / μm), S represents the area of ​​the pn junction, and Wt represents the thickness of the depletion layer. The relative dielectric constant εr varies depending on the composition of the semiconductor material, but is approximately 13.5. In reality, the dielectric constant differs slightly for each semiconductor layer, but to simplify the calculations, the relative dielectric constant εr of all semiconductor layers is set to a uniform 13.5.

[0080] In order to reduce the capacity of a 50 Gbps APD, the diameter of the light receiving region, i.e., the inner periphery of the ring-shaped contact layer, must be reduced to about 10 μmΦ, and the diameter of the window layer, i.e., the outer periphery of the ring-shaped contact layer, must be reduced to about 16 μmΦ. The surface area of ​​a light receiving region with a diameter of 10 μmΦ is 78.5 μm. 2 , the surface area of ​​the window layer with a diameter of 16 μm is 201.0 μm 2 The surface area of ​​the window layer excluding the light receiving region, that is, the surface area of ​​the ring-shaped contact layer, is 122.5 μm 2 The pn junction capacitance Cpn of the APD according to the comparative example described later is calculated by the following formula (3): 13.5×8.85×10 -18 F / μm ×201.0μm 2 / 0.6 μm=40 fF (3)

[0081] On the other hand, the pn junction capacitance Cpn of the back-illuminated APD according to the first embodiment is calculated by the following equation (4): 13.5×8.85×10 -18 F / μm× (78.5μm 2 / 0.6 μm + 122.5 μm 2 / 0.9 μm) = 32 fF (4)

[0082] That is, while the pn junction capacitance Cpn of the back-illuminated APD of the comparative example is 40 fF, the pn junction capacitance Cpn of the back-illuminated APD according to the first embodiment is 32 fF, which is a reduction of 8 fF. That is, the back-illuminated APD according to the first embodiment can reduce the pn junction capacitance Cpn by 20% compared to the comparative example. Therefore, the bandwidth fcr (=1 / (2πCR)) determined by the capacitance C and the load resistance R is improved by 20%. For example, if the load resistance R is 50 Ω, the bandwidth fcr determined only by the pn junction capacitance Cpn in the back-illuminated APD according to the first embodiment is 100 GHz.

[0083] In addition, the response bandwidth of an APD is affected by factors other than the pn junction capacitance Cpn, such as the transit time and multiplication time of electrons and holes, parasitic capacitance, and element resistance. Therefore, in an APD for 50 Gbps, the response bandwidth determined by the pn junction capacitance Cpn and load resistance R must be approximately 100 GHz, which is about twice the transmission speed.

[0084] As described above, by reducing the thickness of the depletion layer in the light-receiving region where electrons and holes travel through the depletion layer and by increasing the thickness of the depletion layer below the p-type contact layer in the region where electrons and holes do not travel through the depletion layer, it is possible to reduce the pn junction capacitance Cpn of the APD, and as a result, the response bandwidth is improved.

[0085] The drawback of making the entire window layer p-type is that, during APD operation, an increased electric field is applied to the side surface of the first mesa structure 30. If a large electric field is applied to the side surfaces of the i-type InAlAs multiplication layer 4, the p-type InAlAs electric field buffer layer 5, and the i-type InGaAs light absorption layer 6 exposed on the side surface of the first mesa structure 30, the dark current may change over time, potentially damaging the reliability of the APD.

[0086] In the back-illuminated APD according to the first embodiment, the distance between the side surface of the second mesa structure 31 and the side surface of the first mesa structure 30 (hereinafter referred to as the terrace width Lt) is increased by providing a terrace portion 40 between the side surface of the second mesa structure 31 and the side surface of the first mesa structure 30. This reduces the electric field applied to the side surface of the first mesa structure 30, resulting in a highly reliable back-illuminated APD.

[0087] The lower limit of the terrace width Lt is preferably 1 μm or more, which facilitates the processing of the terrace portion 40 and reduces the electric field applied to the mesa groove 35. On the other hand, if the terrace width Lt is too long, i.e., if the area of ​​the terrace portion 40 is too large, the areas of the i-type InAlAs multiplication layer 4 and the i-type InGaAs light absorption layer 6 increase, resulting in a problem of increased dark current. Therefore, the upper limit of the terrace width Lt is preferably 300 μm or less. Furthermore, considering that the device resistance increases as the distance between the light-receiving region 60 and the n-type electrode 50 increases, the terrace width Lt is preferably 50 μm or less. In other words, it can be said that the terrace width Lt is preferably in the range of 1 μm to 50 μm.

[0088] Effect of First Embodiment As described above, the semiconductor light-receiving element according to the first embodiment has an element structure in which a second mesa structure and a terrace portion are provided on the first mesa structure, and a p-type impurity region is formed only in the light-receiving region. This reduces the pn junction capacitance and suppresses thermal diffusion of the p-type impurity in regions other than the light-receiving region, thereby providing the effect of providing a semiconductor light-receiving element that operates over a wide response band and has high reliability.

[0089] As described above, according to the method for manufacturing a semiconductor light-receiving element according to the first embodiment, the contact layer and the window layer are doped with p-type impurities in advance in the epitaxial crystal growth process, and the p-type impurities are selectively diffused into the light absorption layer only in the light-receiving region in the p-type impurity diffusion process after the epitaxial crystal growth. This reduces the time required for the p-type impurity diffusion. Furthermore, it also reduces the time required for the high-temperature heat treatment during the p-type impurity diffusion. As a result, it is possible to prevent the p-type impurities contained in the electric field buffer layer from thermally diffusing into the light absorption layer and the multiplication layer, thereby reducing dark current and enabling the easy manufacture of a semiconductor light-receiving element with high reception sensitivity.

[0090] Furthermore, doping the contact layer and window layer with p-type impurities in advance during the epitaxial crystal growth process, and then selectively diffusing the p-type impurities into the light absorption layer only in the light-receiving region during the p-type impurity diffusion process after epitaxial crystal growth, has the advantage that the thickness of the depletion layer formed below the ring-shaped p-type InGaAs contact layer can be made thicker than the thickness of the depletion layer formed in the light-receiving region on the inner side of the p-type InGaAs contact layer. This advantage makes it possible to reduce the pn junction capacitance, thereby achieving a semiconductor light-receiving element with a wide response band.

[0091] Comparative Example of First Embodiment Fig. 9 is a cross-sectional view showing the device structure of a back-illuminated APD, which is an example of a semiconductor photodetector 200 according to a comparative example of the first embodiment. The semiconductor photodetector 200 according to the comparative example is structurally different from the semiconductor photodetector 100 according to the first embodiment in that it does not have a second mesa structure, an i-type InAlAs surface protection layer, or a terrace portion, and in that the contact layer and window layer are not doped with p-type impurities in advance during the epitaxial crystal growth process.

[0092] <Element Structure of Semiconductor Photodetector (APD) According to Comparative Example of First Embodiment> A back-illuminated APD, which is an example of the semiconductor photodetector 200 according to the first embodiment, includes an Fe-doped InP substrate 1 and an Fe-doped InP substrate 1 having a carrier concentration of 5×10 17 ~8 x 10 18 cm -3 and an n-type InP conductive layer 2 having a thickness of 0.1 to 1.0 μm and a carrier concentration of 5×10 17 ~8 x 10 18 cm -3 and an n-type InAlAs conductive layer 3 having a layer thickness of 0.1 to 1.0 μm, an i-type InAlAs multiplication layer 4, and a carrier concentration of 1×10 16 ~5 x 10 18 cm -3The p-type InAlAs field relaxation layer 5 has a thickness of 10 to 100 nm, the i-type InGaAs light absorption layer 6 has a thickness of 0.1 to 2.0 μm, the i-type InAlGaAs graded layer 7 has a thickness of 5 to 100 nm and the composition wavelength is gradually shortened, the i-type InAlGaAs window layer 9a has a thickness of 0.1 to 3.0 μm and is undoped, and the i-type InP window layer 9b has a thickness of 0.05 to 0.5 μm and is undoped and has a substantially circular shape in top view. a p-type impurity diffusion region 20a provided in a part of the i-type InGaAs light absorption layer 6 and an i-type InP window layer 9a on the outer periphery of the ring-shaped i-type InGaAs contact layer 10a, the i-type InP window layer 9a being exposed as a semiconductor layer on the outer periphery of the ring-shaped i-type InGaAs contact layer 10a; a surface protective film 11 made of an insulating film covering the surface of the i-type InP window layer 9 a exposed on the outer periphery of the ring-shaped i-type InGaAs contact layer 10 a; a front-side antireflection film 15 made of a SiN film formed on the inner periphery of the ring-shaped i-type InGaAs contact layer 10 a, i.e., on the surface of the i-type InP window layer 9 a corresponding to the approximately circular light-receiving region 60; an n-type electrode 50 formed on the surface of the n-type InP conductive layer 2 exposed as a semiconductor layer on the outer periphery of the mesa structure 33; a p-type electrode 51 provided on the surface of the ring-shaped i-type InGaAs contact layer 10 a and on the surface of the front-side antireflection film 15; a back-side antireflection film 16 provided on the back side of the Fe-doped InP substrate 1 so as to face the p-type electrode 51;

[0093] FIG. 10A is a cross-sectional view of the semiconductor light-receiving element 100 according to the first embodiment, i.e., a back-illuminated APD, after epitaxial crystal growth in a manufacturing method thereof, and FIG. 10B is a cross-sectional view of the semiconductor light-receiving element 100 according to the first embodiment, after epitaxial crystal growth in a manufacturing method thereof in a back-illuminated APD according to a comparative example of the first embodiment.

[0094] As shown in FIG. 10B , in the back-illuminated APD according to the comparative example of the first embodiment, the wafer after epitaxial crystal growth is composed of, on an Fe-doped InP substrate 1, the following semiconductor layers in order from the Fe-doped InP substrate 1 side: an n-type InP conductive layer 2, an n-type InAlAs conductive layer 3, an i-type InAlAs multiplication layer 4, a p-type InAlAs field relaxation layer 5, an i-type InGaAs light absorption layer 6, an i-type InAlGaAs graded layer 7, an i-type InP window layer 9 a, and an i-type InGaAs contact layer 10 a.

[0095] 10A and 10B, the back-illuminated APD according to the comparative example of the first embodiment is structurally different from the back-illuminated APD according to the first embodiment in that the semiconductor layer stack structure does not include an i-type InAlAs surface protective layer, and the InP window layer 9 a and the InGaAs contact layer 10 a each have an i-type conductivity. That is, in the comparative example, the i-type InP window layer 9 a and the i-type InGaAs contact layer 10 a form i-type regions.

[0096] 11A is a cross-sectional view of a back-illuminated APD after a p-type impurity diffusion step in the method for manufacturing the back-illuminated APD according to the first embodiment, and FIG. 11B is a cross-sectional view of a back-illuminated APD after a p-type impurity diffusion step in the method for manufacturing the back-illuminated APD according to the comparative example.

[0097] 11B , it takes a long time for Zn to reach the i-type InGaAs light absorption layer 6 from the outermost surface of the semiconductor layer, and therefore Be, which is pre-contained as a p-type impurity in the p-type InAlAs electric field relaxation layer 5, thermally diffuses into the i-type InGaAs light absorption layer 6, resulting in a problem of increased dark current. In addition, Be also thermally diffuses toward the i-type InAlAs multiplication layer 4, partially converting the multiplication layer to p-type, which generates an electric field distribution within the multiplication layer, resulting in problems such as an increase in multiplication noise.

[0098] 11A according to the first embodiment, the diffusion time is short, so that the thermal diffusion of Be, which is pre-contained as a p-type impurity in the p-type InAlAs field buffer layer 5, is suppressed, and the p-type impurity in the p-type InAlAs field buffer layer 5 does not thermally diffuse. Therefore, problems such as an increase in dark current and a deterioration in multiplication noise in the back-illuminated APD do not occur.

[0099] Second Embodiment. <Features of the Semiconductor Photodetector (APD) According to the Second Embodiment> Figure 12 is a cross-sectional view showing the device structure of a back-illuminated APD, which is an example of a semiconductor photodetector 110 according to the second embodiment. The semiconductor photodetector 110 according to the second embodiment differs structurally from the semiconductor photodetector 100 according to the first embodiment in that the multiplication layer of the semiconductor photodetector 100 according to the first embodiment is an i-type InAlAs layer, i.e., has a random alloy structure, whereas the multiplication layer of the semiconductor photodetector 110 according to the second embodiment has an i-type InAs / AlAs digital alloy structure. In other words, the semiconductor photodetector 110 according to the second embodiment has a multiplication layer 4a with an i-type InAs / AlAs digital alloy structure.

[0100] As an example, the i-type InAs / AlAs digital alloy structure multiplication layer 4a is composed of semiconductor layers in which InAs layers (layer thickness: two atomic layers, approximately 0.6 nm) and AlAs layers (layer thickness: two atomic layers, approximately 0.6 nm) are alternately stacked in this order.

[0101] However, the thickness of each of the InAs layer and the AlAs layer may be in the range of 2 to 6 atomic layers. The reason for 6 atomic layers or less is that it is desirable that the stacked structure of the InAs layer and the AlAs layer does not function as a quantum well structure. In other words, the digital alloy structure is formed by alternately stacking two types of semiconductor layers, each made of a different semiconductor material, at a period of 2 to 6 atomic layers.

[0102] Furthermore, the number of atomic layers in each layer of the i-type InAs / AlAs digital alloy structure multiplication layer 4a is preferably between two and four atomic layers, with two atomic layers being optimal. The reason for this is that the thinner the atomic layer thickness of each layer, the greater the effect of reducing the ionization rate ratio k due to the digital alloy structure. Furthermore, when considering not only the performance as a semiconductor light-receiving element but also productivity, a layer thickness of between four and six atomic layers is also optimal, as this reduces the number of shutter switching times during crystal growth by MBE.

[0103] Considering the above factors, it can be said that the number of atomic layers in each layer of the i-type InAs / AlAs digital alloy structure multiplication layer 4a preferably ranges from 2 to 6. Similarly, from the viewpoint of productivity, the entire multiplication layer does not have to have an InAs / AlAs digital alloy structure; instead, a portion of the multiplication layer may have an InAs / AlAs digital alloy structure and the remainder may have an InAlAs random alloy structure.

[0104] The thickness of the i-type InAs / AlAs digital alloy structure multiplication layer 4a is suitably in the range of 40 nm to 170 nm, but may be 300 nm or less. For example, if the thickness of the i-type InAs / AlAs digital alloy structure multiplication layer 4a is 100 nm, the number of repetitions of the InAs layer (two atomic layers) / AlAs layer (two atomic layers) is 85.

[0105] The conductivity type of the i-type InAs / AlAs digital alloy structure multiplication layer 4a is i-type, and the carrier concentration is 1×10 17 cm -3 However, as the conductivity type of the InAs / AlAs digital alloy structure multiplication layer, the carrier concentration is 5×10 17 cm -3 It may be p-type or n-type as follows.

[0106] In addition to the multiplication layer having an InAs / AlAs digital alloy structure, for example, a digital alloy structure made of InAlAsSb, which is a material system containing antimony (Sb), can also be applied as the multiplication layer of the semiconductor light-receiving element of the present disclosure.

[0107] In the semiconductor light receiving element 110 according to the second embodiment, similarly to the first embodiment, the diffusion depth is (diffusion time) 0.5 Since the diffusion time is proportional to the thickness of the p-type impurity, if the depth required for thermal diffusion is halved, the diffusion time will be ¼, and therefore, it will be possible to thermally diffuse the p-type impurity into the i-type InGaAs light absorption layer 6 in a short time. By shortening the diffusion time, it will be possible to prevent problems such as an increase in dark current due to the thermal diffusion of the p-type impurity already contained in the p-type InAlAs electric field buffer layer 5 into the i-type InGaAs light absorption layer 6, and further, the thermal diffusion of the p-type impurity from the p-type InAlAs electric field buffer layer 5 toward the i-type InAs / AlAs digital alloy structure multiplication layer 4a, which will cause disorder in the digital alloy structure multiplication layer and worsen the multiplication noise.

[0108] In the semiconductor light-receiving element 110 according to the second embodiment, as in the first embodiment, the p-type impurity diffusion region 20 is provided only in the light-receiving region 60, which affects the carrier transit time, to deepen the p-type region. Therefore, the depth of the p-type region formed on the outer periphery of the second mesa structure 31, i.e., below the terrace portion 40, is 0.3 μm shallower than that of the light-receiving region 60. Therefore, even if the terrace width Lt is 0 μm, the distance between the p-type region and the i-type InAs / AlAs digital alloy structure multiplication layer 4a is 0.3 μm greater. As a result, in the back-illuminated APD according to the first embodiment, even if the terrace width Lt is 0 μm, i.e., no terrace portion 40 is provided, the thickness of the depletion layer below the p-type InGaAs contact layer 10 is 0.3 μm greater than that of the semiconductor light-receiving element 200, which is the comparative example, thereby achieving the effect of reducing capacitance.

[0109] The semiconductor light-receiving element 110 according to the second embodiment is characterized in that the multiplication layer has an i-type InAs / AlAs digital alloy structure. The following describes in detail the digital alloy structure multiplication layer, which is one of the structural features of the semiconductor light-receiving elements of the present disclosure, including the semiconductor light-receiving elements described above and below.

[0110] If a wideband APD of 37.5 GHz or more can be realized, next-generation high-speed PON systems can be realized without using DSPs and SOAs. In the case of PDs, where it is relatively easy to widen the response bandwidth, the response bandwidth is limited by: (1) the RC time constant (R is the element resistance, and C is the element capacitance) and (2) the carrier transit time (the time it takes for electrons or holes to transit through the depletion layer). In APDs, the response bandwidth is further limited by: (3) the multiplication time (the time it takes for electrons and holes to multiply in a chain reaction within the multiplication layer, which increases in proportion to the multiplication factor).

[0111] While a PD can achieve the above-mentioned 37.5 GHz bandwidth, an APD requires a multiplication time, making it difficult to achieve the desired bandwidth if the multiplication factor is increased. The multiplication time TM is expressed by the following equations (5) to (7): Multiplication time TM = multiplication factor M / GB product (5) GB product = 1 / (2πNkτav) (6) That is, multiplication time TM = 2πNkMτav (7)

[0112] Here, GB product is the product of the multiplication factor and the response bandwidth, k is the ionization rate ratio, N is a coefficient that is loosely dependent on the ionization rate ratio k, and τav is the average time it takes for electrons and holes to travel through the multiplication layer. Therefore, by reducing the ionization rate ratio k, it is possible to shorten the multiplication time TM. In particular, to realize a high-speed PON system, it is necessary to make the multiplication time TM approach zero, that is, to make the ionization rate ratio k approach zero.

[0113] In order to make the ionization rate ratio k zero, various compound semiconductors have been proposed as materials for the multiplication layer. Furthermore, in order to reduce the ionization rate ratio k, a digital alloy structure has been proposed in which semiconductor layers of different compositions are alternately stacked in a cycle of 1 to 6 atomic layers. However, even in the digital alloy structure, it has been difficult to make the ionization rate ratio k zero unless the structure is optimized. The digital alloy structure is described in Non-Patent Document 1.

[0114] Therefore, in order to reduce the ionization rate ratio k of the digital alloy structure, the inventors fabricated an APD with a digital alloy structure multiplication layer using a multiplication layer formed by alternately stacking two-atom InAs layers and two-atom AlAs layers, and analyzed the multiplication characteristics. As a result, they discovered that the distance that carriers travel through the multiplication layer to become ionized is longer than that of an APD with an InAlAs multiplication layer made of a normal bulk crystal, i.e., an InAlAs random alloy structure multiplication layer. The distance that carriers travel through the multiplication layer to become ionized is called the dead space.

[0115] Because the length of the dead space (hereinafter referred to as the dead space length) is longer for holes than for electrons, in the case of an InAlAs random alloy structure made of a typical bulk crystal, when the multiplication layer is thinned to a level of several tens of nanometers, the holes cannot be ionized, resulting in a decrease in the ionization rate ratio k. However, when the multiplication layer is thinned to a level of several tens of nanometers, a new problem arises: a higher electric field must be applied to the multiplication layer to obtain the desired multiplication factor, which increases leakage currents such as tunnel currents. In other words, an increase in tunnel current increases noise generated in the APD. On the other hand, the inventors' analysis discovered that, because the dead space is unusually large in the digital alloy structure compared to the random alloy structure, the ionization rate ratio k = 0 even when the multiplication layer is 100 nm or thick.

[0116] In other words, the inventors have discovered for the first time that by constructing the multiplication layer of an APD with a digital alloy structure, it is possible to achieve an ionization rate ratio k = 0 while suppressing the tunneling current. Specifically, they have found that in a multiplication layer having the digital alloy structure of the present disclosure, the ionization rate ratio k drops sharply at a layer thickness of 170 nm or less, and that the dead space effect is dramatically improved particularly when the multiplication layer thickness is in the range of 60 to 130 nm. In other words, the inventors have demonstrated that the ionization rate ratio k = 0, which was impossible to achieve with a multiplication layer having a random alloy structure or a multiplication layer having a thick digital alloy structure, can be achieved by applying a multiplication layer having the digital alloy structure of the present disclosure. At present, no research institute has reported that thinning the multiplication layer of an APD having a digital alloy structure multiplication layer is more effective in reducing the ionization rate ratio k than thinning the multiplication layer of an APD made of conventional materials.

[0117] The thickness of the i-type InAs / AlAs digital alloy structure multiplication layer 4a is within the range of 40 nm to 1000 nm. However, in order to increase the dead space effect in the i-type InAs / AlAs digital alloy structure multiplication layer 4a, the thickness of the i-type InAs / AlAs digital alloy structure multiplication layer 4a may be within the range of 40 nm to 170 nm. Furthermore, considering the typical degree of variation of 20% in layer thickness during fabrication of the semiconductor light receiving element 110, the thickness of the i-type InAs / AlAs digital alloy structure multiplication layer 4a is more preferably within the range of 50 nm to 140 nm.

[0118] The function of an APD having an i-type InAs / AlAs digital alloy multiplication layer will be described below. The inventors have found that the use of a digital alloy multiplication layer, as in the back-illuminated APD according to the second embodiment, enhances the dead space effect, i.e., the effect of reducing the ionization rate ratio k.

[0119] 13 is a graph (estimated values) showing the electric field dependence of the electron dead space in an InAlAs multiplication layer. As a result of analyzing the electron multiplication characteristics of the digital alloy structure multiplication layer, the inventors have found that the InAs / AlAs digital alloy structure multiplication layer of the present disclosure has a longer dead space than the conventional InAlAs random alloy structure multiplication layer, as shown in the graph of FIG.

[0120] 14A to 14C are conceptual diagrams showing the ionization rates of electrons and holes, respectively. FIG. 14A shows the case of electron ionization, FIG. 14B shows the case of hole ionization, and FIG. 14C shows the ionization rate when the multiplication layer is thinned. In a conventional InAlAs random alloy multiplication layer, as shown in the graph of FIG. 13, the dead space length is about 45 nm, so the thickness of the multiplication layer needs to be thinned to about 1.5 times the dead space (about 70 nm). However, thinning the multiplication layer to 70 nm increases the electric field in the multiplication layer, which leads to a rapid increase in tunnel current and an increase in noise.

[0121] On the other hand, in the i-type InAs / AlAs digital alloy structure multiplication layer 4a of the back-illuminated APD according to the second embodiment, as shown in the graph of FIG. 13, the reciprocal of the applied electric field is 1.47×10 -6 In the case of a dc voltage of 1.0 V, the dead space length is approximately 85 nm, and therefore the ionization rate ratio k can be made close to zero even if the thickness of the multiplication layer is approximately 1.5 times the dead space (approximately 130 nm). Therefore, the influence of the tunnel current is small in the back-illuminated APD according to the second embodiment.

[0122] In addition, in the multiplication layer with an InAs / AlAs digital alloy structure, the dead space is highly dependent on the applied electric field. For example, when the reciprocal of the applied electric field is 1.27×10 -6 In the case of a multiplication layer having a dead space length of about 50 nm, the thickness of the multiplication layer must be reduced to 75 nm, as shown in the graph of Fig. 13. In other words, the thickness of the multiplication layer having an InAs / AlAs digital alloy structure can be made thicker than that of the multiplication layer having an InAlAs random alloy structure.

[0123] Fig. 15 is a graph showing the layer thickness dependence of the ionization rate ratio and the tunnel current (experimental values ​​and literature values). The inventors fabricated APDs having an InAs / AlAs digital alloy structure multiplication layer and an InAlAs random alloy structure multiplication layer, measured the ionization rate ratio k, and further plotted the results in Fig. 15 together with the measurement results of Literatures 1 and 2 described in Fig. 15. Literatures 1 and 2 in Fig. 15 are as follows:

[0124] (1) Reference 1 Yuan Yuan, et al. , “Temperature dependence of the ionization coefficients of InAlAs and AlGaAs digital alloys”pp. 794, Vol. 6, No. 8 / August 2018 / Photonics Research (2) Literature 2 Wenyang Wang, et al. , “Characteristics of thin InAlAs digital alloy avalanche photodiodes” pp. 3841, Vol. 46, No. 16 / 15 August 2021 / Optics Letters

[0125] As shown in Figure 15, in an InAlAs random alloy multiplication layer, the effect of reducing the ionization rate ratio k due to dead space cannot be achieved unless the multiplication layer thickness is 80 nm or less. On the other hand, if the multiplication layer thickness is thinner than 80 nm, the tunneling current increases sharply, resulting in tunnel breakdown. When the multiplication layer thickness is around 60 nm, both the reduction in the ionization rate ratio k and the limitation of the tunneling current are barely achieved, but the thickness margin is only a few nanometers, making it extremely difficult to reliably manufacture APDs. Furthermore, the ionization rate ratio k is also large, at 0.12. In other words, with a conventional InAlAs random alloy multiplication layer, it is difficult to apply the effect of reducing the ionization rate ratio k by thinning the layer to APDs.

[0126] On the other hand, in the InAs / AlAs digital alloy structure multiplication layer of the present disclosure, as discovered by the inventors, the dead space is large, and therefore, as the multiplication layer is made thinner, the ionization rate ratio k starts to decrease to 0.1 or less at a layer thickness of 170 nm, as shown in Fig. 15. Here, the ionization rate ratio k is determined from the measured value of the multiplication noise, and is the minimum value of the ionization rate ratio in the multiplication factor range of 1 to 10. For the same ionization rate ratio k, the layer thickness of the InAs / AlAs digital alloy structure multiplication layer is more than twice as large as that of the InAlAs random alloy structure multiplication layer.

[0127] As shown in FIG. 15 , in an APD with a pn junction diameter of 20 μm, if the lower limit of the thickness of the multiplication layer at which the tunnel current becomes 1 μA is set to 40 nm, the layer thickness range of 40 nm to 170 nm is the optimum range for an InAs / AlAs digital alloy structure multiplication layer, and layer thicknesses within this range can be fabricated with sufficient reproducibility.

[0128] The thickness of the InAs / AlAs digital alloy structure multiplication layer, which can sufficiently reduce the ionization rate ratio k due to the dead space effect, is set to 1.47×10 -6 In the case of a thickness of 170 nm, the upper limit of the thickness of the InAs / AlAs digital alloy structure multiplication layer is approximately twice the dead space length. Therefore, considering that the dead space length is 85 nm as shown in FIG. 15, 170 nm, which is twice the dead space length, is a suitable value for the upper limit of the thickness of the InAs / AlAs digital alloy structure multiplication layer.

[0129] Furthermore, in order to control the ionization rate ratio k to 0.05 or less in an InAs / AlAs digital alloy structure multiplication layer, the thickness of the multiplication layer is preferably 150 nm or less, as shown in Figure 15. Furthermore, in order to achieve a tunnel current of 1 μA or less and an ionization rate ratio k of approximately zero, the thickness of the multiplication layer is optimally in the range of 60 nm to 130 nm. If a margin of 10 nm is set during the fabrication of an APD, the thickness of the multiplication layer is preferably set in the range of 70 nm to 120 nm.

[0130] Furthermore, as shown in Figure 13, the length of the dead space is preferably 50 nm to 90 nm. The ratio of the length of the dead space to the thickness of the multiplication layer is preferably 29% or more, calculated by dividing the minimum dead space length of 50 nm by the maximum multiplication layer thickness of 170 nm. As the ratio increases, the ionization rate ratio k decreases, but it cannot exceed 100%. This is because multiplication no longer occurs when the ionization rate ratio k exceeds 100%. Therefore, in principle, the ratio of the length of the dead space to the thickness of the multiplication layer is preferably 29% or more but less than 100%. Furthermore, since the thickness of the multiplication layer in this prototype was 120 nm, the experimentally confirmed optimal range was 42% (= 50 nm / 120 nm) to 75% (= 90 nm / 120 nm).

[0131] The inventors have considered why the ionization rate ratio k=0 could not be achieved with a conventional InAlAs random alloy structure multiplication layer, but the ionization rate ratio k=0 could be achieved with the InAs / AlAs digital alloy structure multiplication layer of the present disclosure.

[0132] If the electron dead space length is De and the hole dead space length is Dh, the conditions for achieving the ionization rate ratio k=0 are expressed by the following equations (8) and (9). Note that equation (8) represents the condition for the difference in dead space length, and equation (9) represents the condition for the tunnel current. Dhe=Dh-De>0 (8) Dh>Tmin (9)

[0133] Here, Dhe is the difference between the dead space lengths of holes and electrons. Tmin is the minimum thickness of the multiplication layer at which the tunnel current becomes small enough to not affect noise, and the thicker the multiplication layer, the more the tunnel current decreases. As shown in the conceptual diagram of Figure 14C, the condition for the difference in dead space length is set as shown in the above-mentioned formula (8) because when the layer thickness of the multiplication layer is equal to or smaller than the dead space length of holes, holes are no longer multiplied and the ionization rate ratio k = 0.

[0134] 13 and 15, in the case of an InAlAs random alloy structure multiplication layer, the values ​​at which the ionization rate ratio k starts to decrease as the multiplication layer is made thinner are De of about 40 nm and Dh of about 80 nm. When the pn junction diameter is 20 μm and the tunnel current is set to 100 nA or less, the minimum layer thickness Tmin is 90 nm. Therefore, the InAlAs random alloy structure does not satisfy the tunnel current condition, and it is impossible to achieve an ionization rate ratio k=0.

[0135] On the other hand, in the case of an InAs / AlAs digital alloy structure multiplication layer, the values ​​at which the ionization rate ratio k begins to decrease as the multiplication layer is made thinner are De of approximately 80 nm and Dh of approximately 170 nm, and when the pn junction diameter is 20 μm and the tunnel current is 100 nA or less, the minimum layer thickness Tmin = 90 nm, so there is a multiplication layer thickness that satisfies the condition that the ionization rate ratio k = 0. Note that the minimum layer thickness Tmin is the same for the InAs / AlAs digital alloy structure multiplication layer and the InAlAs random alloy structure multiplication layer because the band gaps of both are the same.

[0136] Specifically, the inventors found that in the case of a random alloy structure, De is about 40 nm and Dh is about 80 nm, whereas in the case of a digital alloy structure, De is about 80 nm and Dh is about 170 nm.

[0137] In the InAs / AlAs digital alloy structure multiplication layer, the difference in lattice constant between the InAs (lattice constant = 0.606 nm) and AlAs (lattice constant = 0.566 nm) that make up the superlattice is very large at 6.55%, which means that the dopants in the field relaxation layer, i.e., impurities, may diffuse into the InAs / AlAs digital alloy structure multiplication layer during the fabrication process, causing disorder within the multiplication layer.

[0138] 16A to 16D are conceptual diagrams showing the ionization rates in the multiplication layer and the electric field relaxation layer, where Fig. 16A is for an InAlAs random alloy structure multiplication layer, Fig. 16B is for an InAs / AlAs digital alloy structure multiplication layer, Fig. 16C is for a partially disordered InAs / AlAs digital alloy structure multiplication layer, and Fig. 16D is a conceptual diagram showing the ionization rates when a thick electric field relaxation layer and an InAs / AlAs digital alloy structure multiplication layer are combined. Compared to the InAlAs random alloy structure multiplication layer shown in Fig. 16A, the InAs / AlAs digital alloy structure multiplication layer shown in Fig. 16B has a longer dead space length, but due to dopant diffusion from the electric field relaxation layer, the partially disordered InAs / AlAs digital alloy structure multiplication layer has a shorter dead space length, as shown in Fig. 16C.

[0139] In order to avoid the influence of disordering in the InAs / AlAs digital alloy structure multiplication layer, the selection of the material and dopant of the field relaxation layer and the doping concentration are important. The impurity diffusion equation is expressed by the following equation (10): dN / dt=D(d 2 N / d 2 x)-F (10)

[0140] In equation (10), N is the impurity concentration, t is time, D is the diffusion constant, x is position, and F is the external force acting on the diffusion. Examples of materials for the field buffer layer include InP, an InAlAs random alloy structure, and an InAs / AlAs digital alloy structure. Examples of p-type dopants for the field buffer layer include Be and Zn. Considering the p-type dopant, a combination of a Be-doped p-type InP field buffer layer and an InAs / AlAs digital alloy structure multiplication layer is preferable. This is because Be has a small diffusion constant D and also forms a potential barrier between itself and the InAs / AlAs digital alloy structure multiplication layer. The potential barrier corresponds to F in equation (10).

[0141] When the thickness of the electric field relaxation layer varies, the carrier concentration of the electric field relaxation layer is set to 2×10 so that the variation in the amount of electric field relaxation, that is, the variation in the product of the layer thickness and the carrier concentration, does not increase. 18 cm-3 When InAlAs is used as the material for the field relaxation layer, Zn doping is optimal, and the carrier concentration is 2×10 18 cm -3 The optimum is 2 × 10 18 cm -3 When the impurity concentration is higher than 5×10, the inactive impurities increase and diffusion becomes more likely. 18 cm -3 The following is required:

[0142] The electric field relaxation amount ΔE is expressed by the following formula (11): ΔE=WqN / ε (11) In formula (11), W is the layer thickness of the electric field relaxation layer, q is the elementary charge, N is the carrier concentration of the electric field relaxation layer, and ε is the dielectric constant. When the electric field relaxation amount ΔE is constant, if the carrier concentration of the electric field relaxation layer is increased, the layer thickness of the electric field relaxation layer must be reduced in inverse proportion to the carrier concentration.

[0143] The carrier concentration N of the electric field relaxation layer is 5×10 18 cm -3 In order to prevent the dead space length from being shortened due to impurity diffusion into the multiplication layer, the carrier concentration of the field relaxation layer is set to 5×10 18 cm -3 The electric field relaxation layer must have a thickness of 10 nm or more.

[0144] On the other hand, as shown in Figure 16D, when the thickness of the electric field buffer layer becomes 1.5 times or more the dead space length of the electric field buffer layer, multiplication occurs in the electric field buffer layer. As shown in Figure 13, in the random alloy structure, the dead space length is 45 nm or less, so the layer thickness of the electric field buffer layer made of the random alloy structure needs to be 70 nm or less. On the other hand, in the InAs / AlAs digital alloy structure, the dead space length is 85 nm or less, so the layer thickness of the digital alloy structure electric field buffer layer needs to be 130 nm or less.

[0145] The lengths of the dead spaces shown in FIGS. 16A to 16D have the following relationship: dead space (FIG. 16A)<dead space (FIG. 16D)<dead space (FIG. 16C)<dead space (FIG. 16B).

[0146] <Effects of the Digital Alloy Structure Multiplication Layer of the Semiconductor Photodetector (APD) According to the Second Embodiment> First, the first effect of the semiconductor photodetector 110 according to the second embodiment will be quantitatively described below. The 3 dB bandwidth fc of a conventional APD is expressed by the following equation (12), where frc is the bandwidth limit due to the RC time constant, ftr is the bandwidth limited by the carrier transit time, and fm is the bandwidth limit due to the multiplication time. fc_APD=1 / ((1 / frc) 2 +(1 / ftr) 2 +(1 / fm) 2 ) 0.5 (12)

[0147] On the other hand, the 3 dB bandwidth fc of the APD having the InAs / AlAs digital alloy structure multiplication layer according to the first and second embodiments is limited only by the RC time constant and the carrier transit time according to the equations (7) and (12) because the ionization rate ratio k is close to zero, and therefore can be expressed by the following equation (13): fc_APD=1 / ((1 / frc) 2 +(1 / ftr) 2 ) 0.5 (13) In equation (13), the transit time ftr of the carriers includes the transit time in the light absorption layer plus the transit time in the multiplication layer.

[0148] Since the RC time constant is inversely proportional to the sum of the thicknesses of the light absorption layer and the multiplication layer, while the transit time is directly proportional, Equation (13) has a maximum value. That is, the maximum bandwidth occurs when frc = ftr. Substituting frc = ftr, Equation (13) can be expressed as the following Equation (14): fc = ftr / √2 (14)

[0149] The 3 dB bandwidth ftr determined by the transit time is expressed by the following equation (15): ftr=3.5Vav / (2πWt) (15)

[0150] In equation (15), Vav is the average saturated transit velocity of electrons and holes, and Wt is the total thickness of the light absorption layer and the multiplication layer. For example, in the case of InGaAs, Vav is 5.35×10 6 In addition, if the thickness of the multiplication layer is 100 nm and the thickness of the light absorption layer is 400 nm, Wt=500 nm.

[0151] Vav=5.35×10 6 When the wavelengths of the optical fibers are 1000 nm and 1000 GHz, and Wt=500 nm are substituted into equation (15), ftr=59.6 GHz is obtained. Furthermore, when the calculated ftr is substituted into equation (14), the 3 dB bandwidth of the APD having the InAs / AlAs digital alloy structure multiplication layer according to the second embodiment is 42.2 GHz. Therefore, it is clear from the above considerations that the APD having the InAs / AlAs digital alloy structure multiplication layer according to the second embodiment can satisfy the bandwidth of 37.5 GHz required for a 50G-PON system. In the description of the devices, systems, etc. described below, the APD having the InAs / AlAs digital alloy structure multiplication layer according to the second embodiment of the present disclosure will be referred to as the DA-APD of the present disclosure.

[0152] <Effects of Second Embodiment> As described above, the semiconductor photodetector according to the second embodiment further includes a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range, and therefore has the effect of providing a semiconductor photodetector that operates in a wider response band and has high reception sensitivity.

[0153] 17 is a cross-sectional view showing the device structure of a back-illuminated APD, which is an example of a semiconductor photodetector 120 according to Modification 1 of Embodiment 2. The semiconductor photodetector 120 according to Modification 1 of Embodiment 2 is structurally different from the semiconductor photodetector 110 according to Embodiment 2 in that, while the window layer of the semiconductor photodetector 110 according to Embodiment 2 is a p-type InP window layer 9, the window layer of the semiconductor photodetector 110 according to Embodiment 2 is composed of two layers, that is, an i-type InP first window layer 9b and a p-type InAlAs second window layer 9c, from the side of the i-type InAlAs surface protective layer 8.

[0154] In the configuration of the back-illuminated APD according to the first modification of the second embodiment, the semiconductor layers from the n-type InP conductive layer 2 to the i-type InAlAs surface protective layer 8 are the same as those in the back-illuminated APD according to the second embodiment, and therefore, the description thereof will be omitted.

[0155] In the back-illuminated APD according to the first modification of the second embodiment, an i-type InP first window layer 9b having a thickness of 0.1 to 1 μm and a carrier concentration of 5×10 17 ~8 x 10 18 cm -3 and a p-type InAlAs second window layer 9c having a thickness of 0.1 to 2.0 μm. 17 ~8 x 10 18 cm -3 and a p-type InGaAs contact layer 10 having a ring shape along the outer periphery of the light receiving region 60 having a thickness of 0.05 to 0.5 μm and a substantially circular shape in top view.

[0156] As in the back-illuminated APD according to the second embodiment, the i-type InAlAs surface protective layer 8 may be an i-type InP layer, the first window layer may be an InAlAs layer, and the second window layer may be a p-type InP layer.

[0157] <Function of the Semiconductor Photodetector (APD) According to Modification 1 of Embodiment 2> The back-illuminated APD according to Modification 1 of Embodiment 2 has the same functions and effects as the back-illuminated APD according to Embodiment 2. As described above, the back-illuminated APD according to Modification 1 of Embodiment 2 has the i-type InP first window layer 9b, and therefore the thickness of the depletion layer below the ring-shaped p-type InGaAs contact layer 10 is increased by the thickness of the i-type InP first window layer 9b. When the thickness of the i-type InP first window layer 9b is 0.3 μm, Equation (4) becomes Equation (16) below.

[0158] 13.5 x 8.85 x 10 -18 F / μm×(78.5μm 2 / 0.6μm +122.5μm 2 / (0.9 μm+0.3 μm))=28 fF (16)

[0159] The pn junction capacitance Cpn of the back-illuminated APD according to the first modification of the second embodiment, calculated from equation (4), is 32 fF. This reduces the pn junction capacitance Cpn of the back-illuminated APD according to the first modification of the second embodiment, calculated from equation (16), to 28 fF. This reduces the RC time constant in the back-illuminated APD according to the first modification of the second embodiment. Meanwhile, the thickness of the depletion layer in the light-receiving region 60 in the back-illuminated APD according to the first modification of the second embodiment remains unchanged, so the carrier transit time does not increase. As a result, the response bandwidth of the entire APD is improved, i.e., a wider response bandwidth is obtained.

[0160] <Effects of Modification 1 of Second Embodiment> As described above, according to the semiconductor photodetector of Modification 1 of Second Embodiment, the window layer is formed of two layers, that is, the i-type InP first window layer and the p-type InAlAs second window layer. This reduces the pn junction capacitance, thereby achieving the effect of providing a semiconductor photodetector that operates over a wider response band and has high reliability.

[0161] 18 is a cross-sectional view showing the device structure of a back-illuminated APD, which is an example of a semiconductor photodetector 130 according to Modification 2 of Embodiment 2. The semiconductor photodetector 130 according to Modification 2 of Embodiment 2 is structurally different from the semiconductor photodetector 110 according to Embodiment 2 in that, in the semiconductor photodetector 110 according to Embodiment 2, the upper surface of the i-type InAlAs surface protective layer 8 immediately below the p-type InP window layer 9 serves as the terrace surface 41 of the terrace portion 40, and this i-type InAlAs surface protective layer 8 relaxes the electric field applied to the side surface portion of the i-type InAs / AlAs digital alloy structure multiplication layer 4a exposed to the mesa groove 35, whereas in the semiconductor photodetector 130 according to Modification 2 of Embodiment 2, the upper surface of the p-type InAlAs electric field relaxation layer 5 immediately below the i-type InGaAs light absorption layer 6 serves as the terrace surface 41a of the terrace portion 40a. That is, the outer periphery of the p-type InGaAs contact layer 10 having a ring shape when viewed from above is etched down to the p-type InAlAs electric field buffer layer 5 so that the terrace surface 41 a is formed on the upper surface of the p-type InAlAs electric field buffer layer 5 .

[0162] In the back-illuminated APD according to the second embodiment, the i-type InAlAs surface protective layer 8 formed between the i-type InAlGaAs graded layer 7 and the p-type InP window layer 9 functions as both a surface protective layer and a graded layer. On the other hand, in the back-illuminated APD according to the second modification of the second embodiment, the i-type InAlAs layer formed between the i-type InAlGaAs graded layer 7 and the p-type InP window layer 9 functions solely as the i-type InAlAs graded layer 8a.

[0163] The p-type InAlAs field buffer layer 5 may have either a random alloy structure or a digital alloy structure. The p-type field buffer layer may also be composed of a p-type InP layer. A graded layer made of an i-type InAlGaAs layer or an i-type InGaAsP layer may be provided between the p-type InAlAs field buffer layer 5 and the i-type InGaAs light absorption layer 6.

[0164] The terrace surface 41 a of the terrace portion 40 a may be formed by the upper surface of the p-type InAlAs electric field buffer layer 5, or may be formed by an intermediate surface of the p-type InAlAs electric field buffer layer 5 or an intermediate surface of the i-type InAs / AlAs digital alloy structure multiplication layer 4 a.

[0165] When a graded layer is provided between the p-type InAlAs field buffer layer 5 and the i-type InGaAs light absorption layer 6, the terrace surface 41a of the terrace portion 40a may be formed by the upper surface or an intermediate surface of the graded layer. Furthermore, even if the terrace surface 41a is formed by the i-type InGaAs light absorption layer 6 remaining on the p-type InAlAs field buffer layer 5 with a thickness of 100 nm or less, there is no problem because the electric field is relaxed by the terrace portion 40a. That is, in the back-illuminated APD according to the second modification of the second embodiment, the terrace surface 41a may be formed on the upper surface of the p-type InAlAs field buffer layer 5 or within a range of 100 nm in thickness vertically from the upper surface of the p-type InAlAs field buffer layer 5.

[0166] <Functions and Effects of the Semiconductor Photodetector (APD) According to Modification 2 of Second Embodiment> In the back-illuminated APD according to the second embodiment, as shown in FIG. 12 , the i-type InGaAs light absorption layer 6 is present below the terrace surface 41 a. However, in the back-illuminated APD according to Modification 2 of Second Embodiment, as shown in FIG. 18 , the i-type InGaAs light absorption layer 6 is not present below the terrace surface 41 a. The i-type InGaAs light absorption layer 6, which has a small band gap, causes dark current. However, in the back-illuminated APD according to Modification 2 of Second Embodiment, the semiconductor layers other than the light-receiving region 60 and the p-type InGaAs contact layer 10 are removed by etching down to the top surface of the p-type InAlAs field relaxation layer 5. As a result, the area of ​​the i-type InGaAs light absorption layer 6 is reduced, which has the effect of reducing dark current.

[0167] 12 , in the back-illuminated APD according to the second embodiment, when incident light 90 is incident on an Fe-doped InP substrate 1 having a thickness of 100 μm or more, the light beam spreads as the light propagates through the Fe-doped InP substrate 1, and the light is also absorbed in the i-type InGaAs light absorption layer 6 outside the light-receiving region 60, generating electrons and holes. The electrons and holes generated in the terrace portion 40 outside the light-receiving region 60, for example, have a long distance to the p-type region, which increases their travel time, potentially resulting in a deterioration in frequency response. Therefore, in the case of a back-illuminated APD, care must be taken to prevent the light beam from spreading and the optical axis of the light from shifting from the light-receiving region.

[0168] On the other hand, in the back-illuminated APD according to the second modification of the second embodiment, the i-type InGaAs light absorption layer 6 below the terrace 40a is removed to reduce light absorption outside the light-receiving region 60, so that the incident light spreads toward the terrace 40a and is not absorbed even when it is incident on the terrace 40a. In other words, even if the beam of incident light 90 spreads inside the back-illuminated APD, the response band does not deteriorate.

[0169] By thermally diffusing the p-type impurity only into the light-receiving region 60, the p-type impurity diffusion region 20 is made deeper, while the p-type region below the ring-shaped p-type InGaAs contact layer 10 remains shallow. This reduces the electric field applied to the side surface of the i-type InGaAs light absorption layer 6, resulting in a highly reliable back-illuminated APD.

[0170] Furthermore, the side surface of the i-type InAs / AlAs digital alloy structure multiplication layer 4a on the mesa groove 35 side, to which a high electric field is applied, is located further outward than the terrace portion 40a and is farther away from the p-type InP window layer 9. As a result, the electric field applied to the side surface of the i-type InAs / AlAs digital alloy structure multiplication layer 4a during APD operation is reduced, resulting in a highly reliable back-illuminated APD.

[0171] The lower limit of the terrace width Lt is preferably 1 μm or more, which facilitates the processing of the terrace portion 40a and reduces the electric field applied to the side surface exposed in the mesa groove 35. On the other hand, if the terrace width Lt is too long, i.e., if the area of ​​the terrace portion 40a is too large, the area of ​​the i-type InAs / AlAs digital alloy structure multiplication layer 4a increases, resulting in a problem of increased dark current. Therefore, the upper limit of the terrace width Lt is preferably 300 μm or less. Furthermore, considering that the device resistance increases as the distance between the light-receiving region 60 and the n-type electrode 50 increases, a terrace width Lt of 50 μm or less is more preferable. Therefore, it can be said that the terrace width Lt is preferably in the range of 1 μm to 50 μm.

[0172] When a SiN or SiO2 film is formed on a semiconductor layer by chemical vapor deposition (CVD) using a source gas containing hydrogen, hydrogen is incorporated into the semiconductor layer and combines with impurities (dopants) and vacancies. When the impurities combine with hydrogen, the impurities are inactivated, resulting in a decrease in carrier concentration. This phenomenon is called hydrogen passivation. Heat, light, or plasma is used to efficiently induce the film formation reaction, and plasma-enhanced chemical vapor deposition (PECVD) is commonly used. In plasma-enhanced CVD, hydrogen passivation is particularly likely to occur due to the high reaction energy. If the upper surface or an intermediate surface of the electric field buffer layer made of a p-type InAlAs layer or a p-type InP layer is used as the terrace surface 41a, hydrogen passivation, which occurs when the insulating surface protective film 11 is formed by plasma-enhanced CVD, reduces the activation rate of p-type impurities such as Zn and Be contained in the p-type electric field buffer layer 5, thereby reducing the carrier concentration of the p-type impurities in the p-type electric field buffer layer 5 located below the terrace portion 40a. In other words, a hydrogen passivation region 45 is formed within the p-type electric field buffer layer 5 located below the terrace portion 40a. As a result of the formation of the hydrogen passivation region 45, the electric field concentration in the multiplication layer located below the terrace portion 40a is alleviated, and edge breakdown, i.e., local multiplication in the side surface exposed to the mesa groove 35, does not occur. This results in low noise characteristics that are unique to the digital alloy structure multiplication layer.

[0173] <Effects of Modification 2 of Second Embodiment> As described above, according to the semiconductor light-receiving element of Modification 2 of Second Embodiment, the upper surface of the p-type electric field relaxation layer is the terrace surface of the terrace portion, and therefore the electric field applied to the side surface portion of the i-type InGaAs light absorption layer is kept small, thereby achieving the effect of realizing a semiconductor light-receiving element that has low dark current, low noise, and high reliability, and whose response band does not deteriorate even if the incident light beam spreads inside the semiconductor light-receiving element.

[0174] 19 is a cross-sectional view showing the device structure of a back-illuminated APD, which is an example of a semiconductor photodetector 140 according to the third modification of the second embodiment. The semiconductor photodetector 140 according to the third modification of the second embodiment is structurally different from the semiconductor photodetector 130 according to the second modification of the second embodiment in that, in the semiconductor photodetector 130 according to the second modification of the second embodiment, the i-type InAlGaAs graded layer 7 and the i-type InGaAs light absorption layer 6 below the p-type InP window layer 9 both have i-type conductivity, whereas in the semiconductor photodetector 140 according to the third modification of the second embodiment, the p-type InAlGaAs graded layer 7 a and the upper part of the InGaAs light absorption layer are p-type. That is, the InGaAs light absorption layer is composed of two layers, that is, an i-type InGaAs first light absorption layer 6 a and a p-type InGaAs second light absorption layer 6 b from the side in contact with the p-type InAlAs electric field buffer layer 5 .

[0175] The i-type InGaAs first light absorption layer 6a is provided on the upper side thereof with a carrier concentration of 5×10 17 ~8 x 10 18 cm -3 A p-type InGaAs second optical absorption layer 6b having a thickness of 0.4 μm or less is formed, and a p-type InAlGaAs graded layer 7a having a thickness of 5 to 100 nm and a composition wavelength that gradually shortens, and a p-type InAlAs graded layer 7b having a thickness of 10 to 200 nm are formed above the p-type InGaAs second optical absorption layer 6b. The p-type InP window layer 9 and the subsequent semiconductor layers above the p-type InAlAs graded layer 7b are the same as those in the semiconductor photodetector 130 according to the second modification of the second embodiment.

[0176] Here, when the upper part of the light absorption layer is a p-type semiconductor layer, that is, when the p-type InGaAs second light absorption layer 6 b is provided, holes tend to flow more easily from the p-type InGaAs second light absorption layer 6 b to the p-type InP window layer 9, and therefore the p-type InAlGaAs graded layer 7 a and the p-type InAlAs graded layer 7 b are not necessarily required.

[0177] <Functions and Effects of Semiconductor Photodetector (APD) According to Modification 3 of Second Embodiment> In the semiconductor photodetector 140 according to Modification 3 of Second Embodiment, the entire light absorption layer is p-type up to the p-type InGaAs second light absorption layer 6b, which is located at the upper side, and therefore the diffusion time is further shortened. Therefore, it is possible to prevent an increase in dark current due to thermal diffusion of p-type impurities contained in the p-type InAlAs field buffer layer 5 and a deterioration in multiplication noise due to disordering of the i-type InAs / AlAs digital alloy structure multiplication layer 4a caused by the thermal diffusion of p-type impurities.

[0178] Variation 4 of Second Embodiment <Features of Semiconductor Photodetector (APD) According to Variation 4 of Second Embodiment> Figure 20 is a cross-sectional view showing the device structure of a back-illuminated APD, which is an example of a semiconductor photodetector 150 according to Variation 4 of Second Embodiment. The semiconductor photodetector 150 according to Variation 4 of Second Embodiment is structurally different from the semiconductor photodetector 140 according to Variation 3 of Second Embodiment shown in Figure 19 in that, while the semiconductor photodetector 140 according to Variation 3 of Second Embodiment has a p-type InAlAs layer as the p-type electric field buffer layer and is provided with a p-type impurity diffusion region 20, the semiconductor photodetector 150 according to Variation 4 of Second Embodiment has a p-type InP layer as the p-type electric field buffer layer and is not provided with a p-type impurity diffusion region.

[0179] When the electric field relaxation layer is formed of a p-type InP layer, examples of p-type impurities that may be pre-doped into the p-type InP layer include Zn, C, Be, and Mg. In the fourth modification of the second embodiment, as described above, no p-type impurity diffusion region is provided on the inner periphery of the p-type InGaAs contact layer 10. Therefore, the boundary between the i-type region and the p-type region within the InGaAs optical absorption layer, which is formed of two layers, i.e., the i-type InGaAs first optical absorption layer 6 a and the p-type InGaAs second optical absorption layer 6 b, i.e., the interface where the i-type InGaAs first optical absorption layer 6 a and the p-type InGaAs second optical absorption layer 6 b meet, is uniform in the horizontal direction, i.e., in the direction parallel to the surface of the Fe-doped InP substrate 1.

[0180] <Functions and Effects of Semiconductor Photodiode (APD) According to Modification 4 of Embodiment 2> When forming insulating films such as SiN and SiO films in a p-type InP layer, a phenomenon occurs in which hydrogen is incorporated into the semiconductor layer during processing such as plasma processing in an atmosphere containing hydrogen. When hydrogen is incorporated into the p-type semiconductor layer, the hydrogen inactivates the p-type impurities. This phenomenon is called hydrogen passivation.

[0181] Hydrogen passivation inactivates p-type impurities contained in the p-type InP field buffer layer 5a, thereby reducing the carrier concentration of the p-type InP field buffer layer 5a. In the p-type InP field buffer layer 5a exposed on the outer periphery of the terrace portion 40, hydrogen passivation easily reduces the carrier concentration. That is, a hydrogen passivation region 45a is formed inside the p-type InP field buffer layer 5a located below the terrace portion 40a. Furthermore, a reduced carrier concentration region is formed inside the i-type InAs / AlAs digital alloy structure multiplication layer 4a located below the hydrogen passivation region 45a.

[0182] In the hydrogen passivation region 45a, which is a portion of the p-type InP field relaxation layer 5a where the carrier concentration is reduced, i.e., in a region where the amount of field relaxation is reduced, multiplication is less likely to occur in the i-type InAs / AlAs digital alloy structure multiplication layer 4a in contact with the hydrogen passivation region 45a, thereby achieving the effect of suppressing edge breakdown at the side portions of the i-type InAs / AlAs digital alloy structure multiplication layer 4a.

[0183] The hydrogen introduced into the semiconductor layer due to hydrogen passivation generated by the formation of the insulating film is desorbed and reduced during the high-temperature heat treatment process after the formation of the insulating film. In actual measurements, the hydrogen concentration in the p-type InP layer was 2×10 17 ~1 x 10 18 cm -3 It was found that the carrier concentration in the p-type InP field relaxation layer 5a before hydrogen passivation occurred was 5×10 17 ~2 x 10 18 cm -3 Therefore, 2 × 10 17 ~1 x 10 18cm -3 The carrier concentration of the p-type InP field buffer layer 5a is reduced by about half by incorporating hydrogen at a concentration of 1000 kJ / cm into the p-type InP field buffer layer 5a. Therefore, the formation of the hydrogen passivation region 45a can reduce the carrier concentration of the p-type InP field buffer layer 5a located below the terrace portion 40, thereby achieving an effect of significantly suppressing edge breakdown.

[0184] Hydrogen is also incorporated into the semiconductor layer during epitaxial crystal growth. However, in the case where hydrogen passivation does not occur in a semiconductor material lattice-matched to an InP substrate, the hydrogen concentration is 5×10 16 cm -3 or less, and the p-type InP field relaxation layer 5a has a thickness of 5×10 17 ~2 x 10 18 cm -3 is one order of magnitude smaller than the carrier concentration of 5×10 17 ~2 x 10 18 cm -3 It is believed that the effect of hydrogen passivation is exhibited if hydrogen exists in the p-type InP field buffer layer 5a at a concentration on the same order as that of the p-type InP field buffer layer 5a. Therefore, the hydrogen concentration taken into the p-type InP field buffer layer 5a exposed to the terrace portion 40, i.e., the hydrogen concentration in the hydrogen passivation region 45a, is 2×10 17 ~1 x 10 18 cm -3 The range of is preferably:

[0185] In the p-type InP field relaxation layer 5a, the carrier concentration due to the p-type impurity is 5×10 17 ~2 x 10 18 cm -3 The optimum thickness of the electric field relaxation layer in this case will be described. The electric field relaxation amount is expressed as elementary charge × carrier concentration × layer thickness of multiplication layer / (relative dielectric constant · dielectric constant of vacuum). In order to obtain the electric field relaxation amount of 700 kV / cm required for the electric field relaxation layer, if the relative dielectric constant of the electric field relaxation layer is 13, the carrier concentration due to the p-type impurity should be 5 × 10 17 cm -3 In this case, the thickness of the electric field relaxation layer is 100 nm, and the carrier concentration is 2×10 18cm -3 Therefore, in the p-type InP field buffer layer 5a, the carrier concentration due to the p-type impurity is 5×10 17 ~2 x 10 18 cm -3 In this range, the layer thickness is preferably in the range of 25 to 100 nm.

[0186] For example, in Patent Document 6, the thickness of the electric field buffer layer at the outer periphery is thinned by etching to reduce the amount of electric field buffering on the outer periphery of the electric field buffer layer. On the other hand, in Modification 4 of Embodiment 2, simply forming a surface protective film 11 made of, for example, a SiN film on the terrace surface 41 of the terrace portion 40 reduces the amount of electric field buffering in the terrace portion 40 through the hydrogen passivation effect, thereby suppressing excess noise due to edge breakdown. As described above, Modification 4 of Embodiment 2 simplifies the manufacturing process of the structure for suppressing edge breakdown, and furthermore, since etching of the electric field buffer layer, which is difficult to control, is not performed, variation in device characteristics is also reduced. Furthermore, Modification 4 of Embodiment 2 does not perform high-temperature thermal diffusion of p-type impurities, so disordering of the digital alloy structure multiplication layer does not occur, and therefore, an APD with low noise characteristics can be easily realized.

[0187] In addition, in Modifications 2, 3, and 5 (described later) of Embodiment 2, the electric field buffer layer is formed of a p-type InP layer, thereby achieving the same effect as in Modification 4 of Embodiment 2. As in Modification 4 of Embodiment 2, the preferred ranges of the carrier concentration due to p-type impurities and the layer thickness of the electric field buffer layer are as follows: the carrier concentration due to p-type impurities is 5×10 17 ~2 x 10 18 cm -3 and the layer thickness is in the range of 25 to 100 nm.

[0188] 21 is a cross-sectional view showing the device structure of a back-illuminated APD, which is an example of a semiconductor photodetector 160 according to the fifth modification of the second embodiment. The semiconductor photodetector 160 according to the fifth modification of the second embodiment is characterized in that it has two terraces: a first terrace 42a having the p-type InAlAs electric field relaxation layer 5 below the i-type InGaAs light absorption layer 6 as its outermost surface, and a second terrace 42b having the i-type InAlAs surface protective layer 8 below the p-type InP window layer 9 as its outermost surface.

[0189] The semiconductor light-receiving element 160 according to the fifth modification of the second embodiment includes an Fe-doped InP substrate 1, a first mesa structure 30 having an n-type InP conductive layer 2, an n-type InAlAs conductive layer 3, an i-type InAs / AlAs digital alloy structure multiplication layer 4a, and a p-type InAlAs field relaxation layer 5, which are sequentially formed on the Fe-doped InP substrate 1, an i-type InGaAs light absorption layer 6, a p-type InAlGaAs graded layer 7a, and a p-type InAlGaAs light absorption layer 7b are formed on the first mesa structure 30. , an i-type InAlAs surface protection layer 8, a first terrace portion 42a consisting of the outermost surface of the first mesa structure 30 exposed on the outer periphery of the second mesa structure 31, a third mesa structure 32 formed on the second mesa structure 31 and having a p-type InP window layer 9 having a band gap larger than that of the i-type InGaAs light absorption layer 6, and a second terrace portion 42b consisting of the outermost surface of the second mesa structure 31 exposed on the outer periphery of the third mesa structure 32.

[0190] As an example of a manufacturing method for the semiconductor light-receiving element 160 according to the fifth modification of the second embodiment, there is a manufacturing method in which the p-type InP window layer 9 in the second embodiment is etched to form the second terrace portion 42b as shown in Fig. 5, and then the i-type InAlAs surface protective layer 8, the p-type InAlGaAs graded layer 7a, and the i-type InGaAs light absorption layer 6 are removed by etching to form the first terrace portion 42a as shown in Fig. 22. After the first terrace portion 42a is formed, a mesa groove 35 is formed whose etched surface reaches the n-type InP conductive layer 2, and a surface protective film 11, an n-type electrode 50, a p-type electrode 51, and a backside antireflection film 16 are formed in the same manner as in the second embodiment.

[0191] The terrace width Lt suitable for both the first terrace portion 42a and the second terrace portion 42b is preferably 1 μm or greater, which facilitates processing and reduces the electric field applied to the mesa groove 35. On the other hand, if the terrace width Lt is too wide, the areas of the i-type InGaAs light absorption layer 6 and the i-type InAs / AlAs digital alloy structure multiplication layer 4a increase, resulting in an increase in dark current. Taking the above into consideration, the combined terrace width Lt of the first terrace portion 42a and the second terrace portion 42b is preferably 300 μm or less. Furthermore, considering that an increase in the distance between the light-receiving region 60 and the n-type electrode 50 increases the device resistance, a combined terrace width Lt of 50 μm or less is preferable. From the above, it can be said that the terrace width Lt of both the first terrace portion 42a and the second terrace portion 42b is preferably within the range of 1 μm to 50 μm.

[0192] <Functions and Effects of the Semiconductor Photodetector (APD) According to Modification 5 of Second Embodiment> When a large electric field is applied to the exposed side surfaces of the i-type InAs / AlAs digital alloy structure multiplication layer 4 a, the p-type InAlAs electric field reduction layer 5, and the i-type InGaAs light absorption layer 6, the dark current changes over time, resulting in a problem of impaired reliability. Therefore, in the semiconductor photodetector 160 according to Modification 5 of Second Embodiment, by providing the second terrace 42 b in addition to the first terrace 42 a, the distance from the p-type InP window layer 9 to the exposed side surfaces of the i-type InGaAs light absorption layer 6 can be increased, thereby reducing the electric field applied to the side surfaces of the i-type InGaAs light absorption layer 6.

[0193] Furthermore, as in the second modification of the second embodiment, the first terrace 42 a relieves electric field concentration on the side surface of the i-type InAs / AlAs digital alloy structure multiplication layer 4 a, thereby preventing edge breakdown, i.e., local multiplication on the side surface, and thus achieving the effect of stably achieving low noise, which is characteristic of a digital alloy structure multiplication layer. As described above, by forming the first terrace 42 a and the second terrace 42 b, it is possible to realize a highly reliable APD in which dark current and multiplication noise are stable over a long period of time.

[0194] Third Embodiment <Features of Semiconductor Photodetector (APD) According to Third Embodiment> Fig. 23 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor photodetector 170 according to the third embodiment. The difference from the semiconductor photodetector 110 according to the second embodiment shown in Fig. 12 is that the semiconductor photodetector 110 according to the second embodiment is a back-illuminated APD in which light is incident from the back side of the semiconductor substrate, whereas the semiconductor photodetector 170 according to the third embodiment is a front-illuminated APD in which light is incident from the front side of the semiconductor substrate.

[0195] The front-illuminated APD, which is an example of the semiconductor light-receiving element 170 according to the third embodiment, includes an n-type InP substrate 1a and a semiconductor layer having a carrier concentration of 5×10 17 ~8 x 10 18 cm -3 and an n-type InAlAs conductive layer 3 having a layer thickness of 0.1 to 1.0 μm, an i-type InAs / AlAs digital alloy structure multiplication layer 4a, and a carrier concentration of 1×10 16 ~5 x 10 18 cm -3 The semiconductor device includes a p-type InAlAs field relaxation layer 5 having a thickness of 10 to 100 nm, an i-type InGaAs light absorption layer 6 having a thickness of 0.1 to 2.0 μm, an i-type InAlGaAs graded layer 7 having a thickness of 5 to 100 nm and in which the composition wavelength is gradually shortened, and an i-type InAlAs surface protection layer 8 having a thickness of 10 to 200 nm, and an n-type InP substrate 1a is exposed on the outer periphery as a semiconductor layer. The first mesa structure 30 has a substantially circular surface when viewed from above, and a plurality of semiconductor layers having a carrier concentration of 5×10 17 ~8 x 10 18 cm -3 and a p-type InP window layer 9 having a thickness of 0.1 to 3.0 μm and a carrier concentration of 5×10 17 ~8 x 10 18 cm -3a p-type InGaAs contact layer 10 having a ring shape along the outer periphery of a light-receiving region 60 having a thickness of 0.05 to 0.5 μm and a thickness of 0.05 to 0.5 μm, the p-type InGaAs contact layer 10 having a ring shape along the outer periphery of the light-receiving region 60 having a substantially circular shape in a top view, a second mesa structure 31 having a substantially circular surface in a top view, a p-type impurity diffusion region 20 provided in a part of the p-type InP window layer 9 and the i-type InGaAs light absorption layer 6 on the inner periphery side of the ring-shaped p-type InGaAs contact layer 10, a terrace portion 40 consisting of the first mesa structure 30 exposed on the outer periphery side of the second mesa structure 31 and having a terrace surface 41 having a width of 1.0 μm or more in the outer periphery direction, and a rib a front-side antireflection coating 15 made of a SiN film formed on the inner periphery of the ring-shaped p-type InGaAs contact layer 10, i.e., on the surface of the p-type InP window layer 9 corresponding to the approximately circular light-receiving region 60; a mesa groove 35 extending to the outer periphery of the first mesa structure 30 and reaching the n-type InP substrate 1a; a light-shielding metal film 66 made of a metal film covering the terrace surface 41 of the terrace portion 40 and the side surface of the first mesa structure 30; a p-type electrode 51a provided on the front surface of the ring-shaped p-type InGaAs contact layer 10; and an n-type electrode 50a provided on the back surface of the n-type InP substrate 1a.

[0196] The light-shielding metal film 66 is made of the same material as the p-type electrode 51 a, such as Ti / Au or Ti / Pt / Au, from the contact surface side. As described above, the p-type impurity diffusion region 20 is provided on the inner periphery side of the ring-shaped p-type InGaAs contact layer 10 so as to reach the i-type InGaAs light absorption layer 6.

[0197] Here, the i-type means undoped, or p-type or n-type with a carrier concentration of 5×10 17 cm -3 The semiconductor light-receiving element 110 according to the second embodiment uses an Fe-doped InP substrate 1, so the n-type electrode 50 needs to be formed on the front side of the Fe-doped InP substrate 1. On the other hand, the semiconductor light-receiving element 170 according to the third embodiment uses an n-type InP substrate 1a as shown in FIG. 23 , so the n-type electrode 50a can be formed on the back side of the n-type InP substrate 1a.

[0198] <Functions and Effects of Semiconductor Photodetector (APD) According to Third Embodiment> In the case of a back-illuminated APD, which is an example of the semiconductor photodetector 110 according to the second embodiment, after light is incident on the Fe-doped InP substrate 1 having a layer thickness of 100 μm or more, the light beam spreads and enters the i-type InGaAs light absorption layer 6 other than the light-receiving region 60, and light is absorbed even in the region other than the light-receiving region 60, generating electrons and holes.

[0199] In areas other than the light-receiving region 60, such as the terrace portion 40 and the area below the p-type InGaAs contact layer 10, the depletion layer is thick, so the time it takes for generated carriers such as electrons and holes to travel is long. Therefore, in the case of a back-illuminated APD, it is necessary to prevent the light beam from spreading and the optical axis from shifting from the light-receiving region 60.

[0200] On the other hand, in the front-illuminated APD according to the third embodiment, the light-shielding metal film 66 is disposed outside the light-receiving region 60, such as the terrace 40, so that even if incident light is incident on the terrace 40, it is not absorbed by the i-type InGaAs light absorption layer 6. Furthermore, because the surface of the ring-shaped p-type InGaAs contact layer 10 is covered with the p-type electrode 51, light is also not incident on the i-type InGaAs light absorption layer 6 located below the p-type InGaAs contact layer 10. As a result, even if the light beam spreads or the optical axis shifts inside the front-illuminated APD, carrier components with a slow response speed are not generated, and therefore, a semiconductor photodetector (APD) with a wide response band can be obtained.

[0201] 24 is a configuration diagram showing an optical line terminal (OLT) 260 of a 50G-PON system according to embodiment 3. The optical line terminal 260 includes an FEC (Forward Error Correction) 261, a driver amplifier 262, a light source 263, a WDM (Wavelength Division Multiplexing) 264, a CDR (Clock Data Recovery) 265 which is a clock and data recovery circuit, a limiting amplifier 266, a burst TIA 267, and a DA-APD 268 of the present disclosure.

[0202] The DA-APD in the present disclosure refers to an APD in which the multiplication layer has an InAs / AlAs digital alloy structure, as explained in the second embodiment, the first to fifth modifications of the second embodiment, and the third embodiment.

[0203] 25 is a configuration diagram illustrating an optical network unit (ONU) of a 50G-PON system according to embodiment 4. The optical network unit 270 includes a WDM 271, a light source 272, a driver amplifier 273, an FEC 274, a DA-APD 275 of the present disclosure, a TIA 276, a limiting amplifier 277, and a CDR 278.

[0204] 26 is a configuration diagram showing an optical line terminal (OLT) 250a of a 50G-PON system as a comparative example. The optical line terminal 250a as a comparative example includes a forward error correction (FEC) circuit (FEC) 251, a driver amplifier 252, a light source 253, a wavelength division multiplexing (WDM) circuit (WDM) 254, a digital signal processing circuit (DSP) 255, an analog-to-digital converter (ADC) 256, an analog-to-digital conversion circuit (ADC), a burst TIA 257, and a conventional APD 258.

[0205] As shown in the optical line terminal 250a of a 50G-PON system as a comparative example in Figure 26, the 50G-PON system as a comparative example requires digital bandwidth compensation, i.e., a DSP 255. On the other hand, in a 50G-PON system using the DA-APD of the present disclosure, digital bandwidth compensation is not required. In other words, as shown in the optical line terminal (ONU) of a 50G-PON system according to embodiment 4 as shown in Figure 25, by using the DA-APD of the present disclosure, a wide response bandwidth and high receiving sensitivity are possible, which enables the DSP circuit to be simplified, power consumption to be reduced, and the output power of the SOA to be reduced.

[0206] In order to increase the number of branches in a PON system and eliminate the need for an SOA, it is necessary to improve the S / N ratio of the receiver and increase the receiving sensitivity. For example, if an optical demultiplexer is added to increase the number of branches from the current level, the amount of light will be halved, so the S / N ratio must be improved by at least 3 dB. The S / N ratio of a receiver using an APD is expressed by the following equation (17): S / N ratio = Iph 2 ・M 2 / (2q(Iph+Id)M 2 ・F・B +4Kb・T・Ft・B / Rt) (17)

[0207] In equation (17), I is the photocurrent of the APD, M is the multiplication factor, q is the unit charge, I is the dark current to be multiplied, F is the excess noise factor of the APD, B is the bandwidth, K is the Boltzmann constant, T is the absolute temperature, F is the noise figure of the amplifier, and R is the input resistance. The left term of the denominator represents the shot noise of the APD, and the right term of the denominator represents the thermal noise of the amplifier.

[0208] To simplify equation (17), we assume that Id is sufficiently smaller than Iph, and that the APD shot noise term and the amplifier thermal noise term are equal when the multiplication factor is set to maximize the S / N ratio. If we replace the amplifier thermal noise term with the APD shot noise term, the S / N ratio can be expressed by the following equation (18): S / N ratio=Iph / (4q F B) (18)

[0209] The excess noise factor F is given by the following equation (19): F = M(1-(1-k) ((M-1) 2 / M 2 )) (19)

[0210] In the case of a conventional InAlAs random alloy multiplication layer, thinning it to the point where the dead space effect appears (approximately 70 nm) increases the tunneling current and worsens noise, as mentioned above. To minimize the tunneling current, the pn junction diameter must be reduced to a few microns or less, but this requires strict alignment precision when focusing light onto the APD. While reducing the noise to a certain extent is possible with a random alloy multiplication layer by thinning the multiplication layer in this way, although it is inferior to the noise of a digital alloy multiplication layer, the small diameter of the pn junction creates limitations in terms of productivity, etc. For this reason, systems are designed with the ionization rate ratio k set to 0.2 for a non-thinned InAlAs multiplication layer. When the ionization rate ratio k = 0.2 and the multiplication factor is 12x, the excess noise factor F = 3.9.

[0211] On the other hand, in the 50G-PON system according to the fourth embodiment, an APD with an InAs / AlAs digital alloy structure multiplication layer, i.e., the DA-APD of the present disclosure, is used as the semiconductor light-receiving element. In the case of the InAs / AlAs digital alloy structure multiplication layer of the present disclosure, the dead space effect functions even with a layer thickness of 100 nm or more, making it possible to apply it to an APD. In this case, the ionization rate ratio k = 0, and when the multiplication factor is 12 times, the excess noise factor F = 1.9. Therefore, the excess noise is approximately half that of a conventional APD. As a result, the DA-APD of the present disclosure improves the S / N ratio by 3 dB.

[0212] Generally, in a 50G-PON system, inserting one stage of a 2-stage demultiplexer to increase the number of branches increases the loss by 3 dB. Therefore, by applying the DA-APD of the present disclosure as a semiconductor photodetector, it becomes possible to insert one more stage of demultiplexer into the 50G-PON system.

[0213] 27 is a diagram illustrating a configuration of an optical line terminal (OLT) of a 50G-PON system according to embodiment 4. An optical line terminal 260a of the 50G-PON system includes an FEC 261, a driver amplifier 262, a light source 263, a WDM 264, a DSP 265a, an ADC 266a, a burst TIA 267, and a DA-APD 268 of the present disclosure.

[0214] 28 is a diagram illustrating a configuration of an optical network unit (ONU) of a 50G-PON system according to embodiment 4. The optical network unit 260b of the 50G-PON system includes an FEC 261, a driver amplifier 262, a light source 263, a WDM 264, a DSP 265a, an ADC 266a, a TIA 267a, and a DA-APD 268 of the present disclosure.

[0215] The effects of the semiconductor photodetector according to the present disclosure will now be further explained. Among the DA-APDs disclosed herein, APDs having an InAs / AlAs digital alloy structure multiplication layer can achieve a multiplication time of approximately zero in equation (7) by controlling the layer thickness of the multiplication layer within a preset range and setting the ionization rate ratio k to zero. As a result, the response bandwidth of the APD does not deteriorate even when the multiplication factor is increased. In other words, in the DA-APD disclosed herein, the response bandwidth is limited only by the RC time constant and carrier transit time, as in conventional PDs. This makes it possible to widen the response bandwidth required for 50G-PON systems, enabling reception without digital bandwidth compensation by a DSP.

[0216] Furthermore, when the ionization rate ratio k approaches zero, excess noise that deteriorates receiver sensitivity is suppressed, eliminating the need for SOA amplification of the optical signal. Furthermore, even in PON systems other than 50G-PON systems, it becomes possible to achieve a higher number of branches than before. As a result, PON systems can be made lower cost and more energy-efficient.

[0217] <Effects of Fourth Embodiment> As described above, according to the optical line terminal of the fourth embodiment, the DA-APD of the present disclosure is used as the semiconductor photodetector, and therefore an optical line terminal that can increase the transmission distance of optical signals and reduce power consumption can be obtained.

[0218] Embodiment 5 Fig. 29 is a diagram showing the configuration of a multi-level intensity modulation transmitting / receiving apparatus 300 according to embodiment 5. Also, Fig. 30A and Fig. 30B are conceptual diagrams showing expected received waveforms in the multi-level intensity modulation transmitting / receiving apparatus 300 according to embodiment 4.

[0219] The multilevel intensity modulation transmitting / receiving device 300 is a multilevel intensity modulation transmitting / receiving device that uses PAM (Pulse Amplitude Modulation), which is a multilevel intensity modulation method. In the transmitting section, a digital signal generated by a DSP 301 is converted to an analog signal by a DAC 302a, amplified by a driver amplifier 303, and driven by a light source 304 consisting of a DFB laser or EML to emit an optical signal to an optical fiber cable 310.

[0220] On the other hand, in the receiving section, the light passes through the optical fiber cable 310 and the optical system and enters the DA-APD 305, which is the semiconductor light receiving element of the present disclosure, where the optical signal is converted into a current and multiplied. After being amplified in the Linear-TIA 306, the light is converted into a digital signal in the ADC 302b and signal processing is performed by the DSP 301.

[0221] <Functions and Effects of the Multilevel Intensity Modulation Transmitter / Receiver According to the Fifth Embodiment> In the PAM-based multilevel intensity modulation transmitter / receiver 300, not only binary signals of 1 and 0 such as NRZ (None Return to Zero) and RZ (Return to Zero) are required to be received, but also, for example, four values ​​of different optical signal intensities in PAM4 (Pulse Amplitude Modulation-4). An assumed example of a PAM4 received waveform is shown in the conceptual diagram of FIG. 30A. To determine whether the received waveform in PAM4 is good or bad, an index called TDECQ (Transmitter Dispersion and Eye Closure Quaternary) is used. TDECQ is calculated using the following equation (20): TDECQ(dB)=10・log(OMA / (6・Qt・R)) (20)

[0222] In equation (20), the optical modulation amplitude (OMA) is the total amplitude from level 0 to level 3, Qt is a value dependent on the SER (Symbol Error Rate) defined by the IEEE (Institute of Electrical and Electronics Engineers), and R is the additional noise value required to achieve the SER value. TDECQ (dB) is defined as, for example, 3 dB or less. To reduce TDECQ (dB), it is necessary that: (1) the eye opening at each level is uniform, and (2) the noise at each level is low.

[0223] In order to ensure uniform eye openings at each of the four levels of optical signal intensity, the semiconductor photodetector must have excellent linearity. Here, good linearity of a semiconductor photodetector means that the photocurrent Iph increases in proportion to the optical input power Pin. In other words, even if the optical input power Pin changes, the semiconductor photodetector has good linearity if Iph / Pin is constant.

[0224] Furthermore, PAM requires a good dynamic range because it must receive signals ranging from low to high intensity. In other words, even if the optical input power Pin increases, a good dynamic range can be achieved if the decrease in Iph / Pin is small. As shown in the received waveform in the conceptual diagram of Figure 30B for explanation, if the linearity and dynamic range deteriorate, the eye opening formed between level 2 and level 3 deteriorates.

[0225] In the case of PDs and APDs, the linearity deteriorates when the photocurrent increases with increasing optical input, which causes an increase in the number of holes and electrons traveling in the multiplication layer and the light absorption layer, changing the electric field distribution in the multiplication layer and the light absorption layer. This phenomenon is called the space charge effect.

[0226] The inventors have studied a model for the degradation of APD linearity. Figures 31A and 31B are conceptual diagrams explaining the operation of a PD when a high optical input is applied. As shown in Figure 31A, when the optical input increases and the photocurrent increases, a space charge effect occurs, as if a voltage drop occurs due to series resistance and no voltage is applied to the pn junction. This voltage drop reduces the multiplication factor. This is because the generated electrons and holes affect the electric field distribution, as shown in Figure 31B. The series resistance Rli that degrades the linearity of an APD is expressed by the following equation (21): Rli = Rsc + Rd + Rlo (21)

[0227] In equation (21), Rsc is the resistance due to the space charge effect, Rd is the element resistance, and Rlo is the load resistance. Rd and the load resistance are usually several tens of Ω, but Rsc can be several hundreds of Ω or more.

[0228] The inventors have found that, assuming that the time it takes for electrons and holes generated by light absorption to pass through the depletion layer is Td, Rsc can be expressed by the following equation (22): Rsc=W·Td / (2εS) (22) In equation (22), W is the thickness of the depletion layer, ε is the dielectric constant, and S is the pn junction area. The resistance Rsc due to the space charge effect is proportional to the time Td it takes for electrons and holes to pass through the depletion layer. Therefore, if the traveling speed of electrons and holes is increased to reduce Td, it is possible to reduce the resistance Rsc.

[0229] In the DA-APD disclosed herein, the multiplication time is short, so the response band does not deteriorate even when used at a high multiplication factor. Therefore, even if the amount of light absorbed by the optical absorption layer is small, operating at a high multiplication factor can increase the receiver sensitivity, making it possible to thin the optical absorption layer, which in turn reduces the resistance Rsc. As a result, the eye opening becomes uniform, so that TDECQ satisfies the specified value. Furthermore, it becomes possible to increase the transmission distance and reduce the drive current of the transmitting laser.

[0230] The use of the DA-APD of the present disclosure will be described below. First, the operation of an APD at high light input will be described. FIG. 32 is a conceptual diagram illustrating the operation of an APD at high light input. When a large number of electrons and holes are generated in the multiplication layer, the electric field in the multiplication layer of the APD changes, that is, the so-called space charge effect occurs. The occurrence of this space charge effect reduces the multiplication factor of the APD and deteriorates its linearity. As described above, the deterioration of the linearity of an APD is caused by the series resistance Rsc, so it is necessary to reduce the residence time Tdm of electrons and holes in the depletion layer. In particular, as the multiplication factor increases, the residence time Tdm in the multiplication layer increases. Tdm is the same as the so-called multiplication time, and is expressed by the following equation (23). Residence time Tdm = multiplication time = 2πNkMτav (23)

[0231] In equation (23), N is the Emmons coefficient (which is loosely dependent on the ionization rate ratio k), M is the multiplication factor, and τav is the average time it takes for electrons and holes to travel through the multiplication layer. The one-way transit time for carriers to traverse the multiplication layer is excluded from the residence time Tdm. N is 0.55, 0.83, 1.1, and 2.0 when the ionization rate ratio k=0.5 (InP), 0.2 (InAlAs), 0.1 (Si), and 0 to 0.001 (InAs / AlAs digital alloy structure), respectively.

[0232] Figure 33 shows the estimated residence time Tdm of electrons and holes for each material constituting the multiplication layer. In the InAs / AlAs digital alloy structure multiplication layer, the residence time Tdm within the multiplication layer is dramatically reduced. In other words, electrons and holes are quickly discharged from the multiplication layer, suppressing the space charge effect in the multiplication layer, resulting in improved linearity and dynamic range in the InAs / AlAs digital alloy structure multiplication layer.

[0233] As a result, while the eye opening of PAM4 was non-uniform with a conventional APD as shown in the conceptual diagram of Fig. 30B, the eye opening is uniform with the DA-APD of the present disclosure as shown in the conceptual diagram of Fig. 30A, making it possible for TDECQ to satisfy the specified value. Therefore, when the DA-APD of the present disclosure is used, an APD can be used even in a PAM transceiver, which makes it possible to increase the transmission distance of optical signals and reduce the drive current of the transmitting laser.

[0234] <Effects of Fifth Embodiment> As described above, the multi-level intensity modulation transceiver according to the fifth embodiment uses the DA-APD of the present disclosure as the semiconductor light-receiving element, and therefore has the effect of providing a multi-level intensity modulation transceiver that can increase the transmission distance of optical signals and reduce power consumption.

[0235] Sixth Embodiment Fig. 34 is a schematic diagram showing the configuration of a radio-on-fiber (RoF) system 400 according to a sixth embodiment. Fig. 35 is a schematic diagram showing the configuration of a radio-on-fiber system 450, which is a comparative example. The radio-on-fiber system 400 includes a light source 401, a transmission path 402 such as an optical fiber cable, a DA-APD 403 according to the present disclosure, and an antenna 404.

[0236] In a radio-on-fiber system 400 according to the sixth embodiment, an analog electrical amplitude signal is input to a light source 401 such as an LD and converted into an optical amplitude signal. The converted optical amplitude signal is transmitted through an optical fiber cable, i.e., a transmission line 402. The transmitted optical amplitude signal is multiplied and converted into an electrical amplitude signal using a DA-APD 403 according to the present disclosure. The converted electrical amplitude signal is transmitted to an antenna 404 and radiated as a radio wave signal.

[0237] The radio-on-fiber system 400 according to the sixth embodiment can efficiently supply signals to an antenna 404 that is located at a distance from an electrical signal source. Furthermore, since no analog-to-digital or digital-to-analog conversion is performed during transmission, the system has the advantages of a simple configuration and low power consumption.

[0238] <Functions and Effects of the Radio-on-Fiber System According to the Sixth Embodiment> In the radio-on-fiber system 450 of the comparative example shown in FIG. 35, if the signal is attenuated during transmission through the optical fiber cable, the signal cannot be amplified by the PD 406, and therefore there is a problem that a sufficient radio signal cannot be emitted from the antenna.

[0239] Furthermore, when a conventional APD is used, as shown in the conceptual diagrams of Figures 31A and 31B, an increase in the number of electrons and holes in the multiplication layer changes the electric field distribution, resulting in saturation of the multiplication factor and an inability to ensure a sufficient dynamic range. This not only results in an insufficient amplitude of the electrical signal, but also in distortion of the analog signal. As a result, it is difficult to apply a conventional APD to a radio-on-fiber system 450 such as the comparative example.

[0240] On the other hand, the DA-APD of the present disclosure used in the radio-on-fiber system 400 according to the sixth embodiment has a short multiplication time, so the response bandwidth does not deteriorate even when used at a high multiplication factor. Therefore, even if the amount of light absorbed by the optical absorption layer is small, operating at a high multiplication factor can increase the receiving sensitivity, making it possible to thin the optical absorption layer, which in turn reduces the resistance Rsc. As a result, a response with good linearity can be obtained over a wide dynamic range, and a large current amplitude can be obtained. Thus, the radio-on-fiber system 400 is configured using the DA-APD of the present disclosure, making it possible to output a strong radio wave signal with good linearity even over a long optical transmission distance.

[0241] Furthermore, in the DA-APD 403 of the present disclosure, as shown in FIG. 33, the residence time Tdm of electrons and holes in the multiplication layer is short, thereby suppressing changes in the electric field distribution in the multiplication layer. As a result, a response with excellent linearity can be obtained over a wide dynamic range. In other words, since the DA-APD 403 of the present disclosure multiplies the signal, the original signal can be reproduced and a large current amplitude can be obtained.

[0242] The DA-APD403 of the present disclosure can be used with a multiplication factor in the range of 1.2 to 10. However, since a larger multiplication factor causes signal distortion, it is desirable to use a multiplication factor in the range of 1.2 to 5. Furthermore, considering the loss of the optical fiber and the fact that the quantum efficiency of the APD is not 100% but about 80%, it is optimal to use a multiplication factor of 2 to 3 to compensate for such loss.

[0243] Effect of Sixth Embodiment As described above, according to the radio-on-fiber system of the sixth embodiment, the DA-APD of the present disclosure is used to configure the radio-on-fiber system, which has the effect of providing a radio-on-fiber system that can output a strong radio wave signal even if the optical transmission distance is long.

[0244] 36 is a schematic diagram showing the configuration of a digital coherent receiving apparatus 500 according to embodiment 7. The digital coherent receiving apparatus 500 according to embodiment 7 is characterized in that it uses the DA-APD 505a of the present disclosure.

[0245] In digital coherent communications, optical signals modulated in both phase and intensity are polarization-multiplexed and transmitted through optical fibers. In a digital coherent receiving device 500, an optical signal input from an optical fiber cable 501 is first polarization-separated by a polarization separator 502. After polarization separation, each polarized signal light is input to a 90-degree hybrid device 503a and a 90-degree hybrid device 503b, respectively. Meanwhile, a laser light locally emitted from a semiconductor laser 504 is separated into two signals with a phase shift of 90 degrees from each other.

[0246] The signal light and laser light are multiplexed, and the signal light is further separated into orthogonal components (I, Q) and output. The four optical signals, i.e., the orthogonal I and Q components for each polarization, total four optical signals, are incident on four balanced detectors 505 arranged in 90-degree hybrid devices 503a, 503b, each of which is made up of two DA-APDs 505a of the present disclosure connected in series. The electrical signals output from the balanced detectors 505 are input to the DSP 506. The digital coherent receiving device 500 according to the seventh embodiment has the above configuration.

[0247] <Function of the digital coherent receiving device according to embodiment 7> Figure 37A is a conceptual diagram for explaining the waveform expected in a digital coherent receiving device which is a comparative example, and Figure 37B is a conceptual diagram for explaining the waveform expected in a digital coherent receiving device according to embodiment 7.

[0248] Conventional balanced detectors use PDs as semiconductor light-receiving elements for receiving signal light. On the other hand, the DA-APD 505a disclosed herein can multiply signals, thereby enabling the local oscillation to be suppressed. Furthermore, when a conventional APD is used, as shown in the conceptual diagram of FIG. 32 , an increase in the number of electrons and holes in the multiplication layer changes the electric field distribution, resulting in saturation of the multiplication factor and an inability to ensure a sufficient dynamic range. This not only results in insufficient electrical signal amplitude, but also in distortion of the analog signal. As a result, as shown in the conceptual diagram of FIG. 37A , in the comparative example, the interval between waveforms A1 and B1 becomes narrow, distorting the intensity signal of the constellation waveform, making it difficult to apply an APD.

[0249] On the other hand, in the DA-APD of the present disclosure used in the digital coherent receiving device 500 according to the seventh embodiment, the multiplication time is short, and therefore the response band does not deteriorate even when used at a high multiplication factor. Therefore, even if the amount of light absorbed by the light absorption layer is small, operation at a high multiplication factor can increase the reception sensitivity, which makes it possible to make the light absorption layer thinner. The thinning of the light absorption layer makes it less susceptible to the influence of resistance Rsc due to the space charge effect, and therefore a constellation waveform with excellent linearity can be obtained over a wide dynamic range.

[0250] Furthermore, in the DA-APD 505a of the present disclosure, as shown in Figure 33, the residence time Tdm of electrons and holes in the multiplication layer is short, thereby suppressing changes in the electric field distribution in the multiplication layer. As a result, as shown in the conceptual diagram of Figure 37B, when the DA-APD 505a of the present disclosure is used, the interval between waveform A and waveform B is widened, and a constellation waveform with excellent linearity over a wide dynamic range is obtained. In other words, even if a signal is multiplied by an APD, the original signal can be reproduced, and a large current amplitude can be obtained.

[0251] The multiplication factor of the DA-APD 505a of the present disclosure can be used within a range of 1.2 to 10. However, as the multiplication factor increases, the signal becomes distorted, so it is desirable to use a multiplication factor within a range of 1.2 to 5.

[0252] <Effects of Seventh Embodiment> As described above, according to the digital coherent receiving device of the seventh embodiment, the DA-APD of the present disclosure is applied as a semiconductor photodetector that receives an optical signal, and therefore it is possible to reduce the drive current of the local light (laser), that is, to reduce the power consumption of the digital coherent receiving device.

[0253] 38 is a schematic diagram showing the configuration of a SPAD sensor system according to embodiment 8. A SPAD sensor system 600 includes a photoelectron measurement circuit 601, a SPAD sensor 602 including a DA-APD according to the present disclosure, and a quenching circuit 603.

[0254] SPADs can be used not only to count photons but also as highly sensitive light-receiving elements. However, they require constant cycling from the Quenching voltage (described below) to the Geiger mode voltage (described below) (B). The cycling cycle is on the order of nanoseconds to microseconds. If the cycling cycle between the Quenching voltage (A) and the Geiger mode voltage (B) can be shortened, the response speed of the SPAD can be increased.

[0255] In other words, when the DA-APD of the present disclosure is used in a SPAD, it becomes possible to switch between A: Quenching voltage and B: Geiger mode voltage, which have a high response speed, and it is possible to improve the response band of the SPAD sensor 602.

[0256] Furthermore, when the DA-APD 505a of the present disclosure is used in the SPAD sensor system 600, photons incident on the SPAD sensor system 600 are absorbed in the light absorption layer of the SPAD sensor 602 made of the DA-APD of the present disclosure, generating pairs of electrons and holes, and the electrons flow into the multiplication layer. An electric field approximately 10% higher than the avalanche breakdown electric field is applied to the multiplication layer.

[0257] This state is called the Geiger mode. In the Geiger mode, electrons are 6 The generated electrons flow as a current and are passed through the photoelectron measurement circuit 601. If the current generated by one photon is known in advance, it is possible to count the number of photons incident on the SPAD sensor system 600.

[0258] FIG. 39A is a conceptual diagram showing the expected multiplication characteristics of a SAPD sensor system according to a comparative example, and FIG. 39B is a conceptual diagram showing the expected multiplication characteristics of a SAPD sensor system according to embodiment 8. Continuous application of an electric field equal to or greater than the avalanche breakdown electric field to the multiplication layer causes excessive current to flow. Therefore, after photons are detected, the voltage applied to the SPAD sensor 602 is quickly reduced to weaken the electric field in the multiplication layer. This is called quenching. As shown in the comparison of the multiplication characteristics of the SPAD sensor shown in the conceptual diagrams of FIGS. 39A and 39B , the voltage is reduced from B: Geiger-mode voltage to A: quenching voltage to stop chain multiplication. Then, the voltage is increased again from A: quenching voltage to B: Geiger-mode voltage, enabling high-sensitivity reception of incident photons.

[0259] The quenching circuit 603 that controls the voltage is classified into a passive circuit and an active circuit. In a passive circuit, when a current flows due to photons incident on the SPAD sensor 602, a voltage drop occurs in a resistor connected in series to the SPAD sensor 602, resulting in a decrease in the voltage applied to the SPAD sensor 602. In other words, the quenching circuit 603 operates to repeatedly apply a voltage equal to or greater than the breakdown voltage and a voltage less than the breakdown voltage to the SPAD sensor 602.

[0260] <Functions and Effects of the SPAD Sensor System According to the Eighth Embodiment> The SPAD sensor system 600 according to the eighth embodiment can be used not only to count the number of photons but also as a highly sensitive semiconductor light-receiving element. However, it is necessary to constantly repeat the process from B: Geiger-mode voltage to A: quenching voltage. The repetition period is on the order of nanoseconds to microseconds. If the difference between A: quenching voltage and B: Geiger-mode voltage can be reduced, the repetition period can be shortened, thereby enabling the response speed of the SPAD sensor system 600 to be increased.

[0261] The passive quenching circuit 603 makes it possible to reduce the resistance value connected in series to the SPAD sensor 602, thereby increasing the response speed of the SPAD sensor 602. Furthermore, the active quenching circuit 603 reduces the voltage amplitude, making it possible to simplify the drive circuit and save power, and also to widen the response band.

[0262] In the DA-APD of the present disclosure, the multiplication time is short, so the response band does not deteriorate even when used at a high multiplication factor. Therefore, even if the amount of light absorbed in the light absorption layer is small, operating at a high multiplication factor can increase the receiving sensitivity, making it possible to make the light absorption layer thinner. Reducing the thickness of the light absorption layer reduces the resistance Rsc, and therefore the breakdown voltage. When the DA-APD of the present disclosure is used in a SPAD, the difference between the quenching voltage and the Geiger mode voltage, i.e., the applied voltage difference, can be reduced, making it possible to improve the response band and simplify the quenching circuit and reduce power consumption.

[0263] The effect of using the InAs / AlAs digital alloy structure of the present disclosure as a multiplication layer will be described below. In the InAs / AlAs digital alloy structure multiplication layer of the present disclosure, as shown in the conceptual diagrams of FIGS. 14A and 14B , the dead space length is long, so multiplication does not occur at low electric fields. However, as the electric field increases, the dead space length shortens, causing a rapid increase in the multiplication factor, leading to breakdown. In APDs with InAlAs random alloy structure multiplication layers and APDs with thick InAs / AlAs digital alloy structure multiplication layers, if the breakdown voltage is defined as the voltage at which the dark current exceeds 10 μA, the multiplication factor at 90% of the breakdown voltage exceeds 10 times. On the other hand, in the InAs / AlAs digital alloy structure multiplication layer of the present disclosure, the multiplication factor at 90% of the breakdown voltage is 10 times or less.

[0264] The voltage required for breakdown depends on the device structure, such as the thickness of the light absorption layer and the carrier concentration of the electric field buffer layer, so here we verify the effect using the quantifiable electric field of the multiplication layer. Note that above the reach-through voltage (up to 12 V), the voltage applied to the SPAD sensor 602 and the electric field of the multiplication layer are proportional.

[0265] 40 is a diagram showing the calculated difference between the quenching electric field and the Geiger mode electric field for each material constituting the multiplication layer. It can be seen that in the InAs / AlAs digital alloy structure multiplication layer of the present disclosure, the difference between the quenching electric field and the Geiger mode electric field of each multiplication layer is 170 kV / cm, which is exceptionally low. The electric field is 120 kV / cm lower than that of an InAs / AlAs digital alloy structure multiplication layer having a superlattice structure similar to the InAs / AlAs digital alloy structure multiplication layer of the present disclosure but a layer thickness of 200 nm or more that has not been thinned.

[0266] <Effects of Eighth Embodiment> As described above, according to the SPAD sensor system of the eighth embodiment, the DA-APD of the present disclosure is used in the SPAD sensor, and therefore the difference between the quenching electric field and the Geiger mode electric field, that is, the applied voltage difference, can be reduced, thereby achieving the effect of obtaining a SPAD sensor system that enables an improvement in the response band, simplification of the quenching circuit, and power saving.

[0267] Ninth Embodiment Fig. 41 is a diagram showing the configuration of a LiDAR (Light Detection and Ranging) device according to a ninth embodiment. Fig. 42A is a conceptual diagram showing a received waveform expected at the APD of a LiDAR device as a comparative example, and Fig. 42B is a conceptual diagram showing a received waveform expected at the APD of a LiDAR device 700 according to the ninth embodiment.

[0268] A LIDAR device 700 according to the ninth embodiment includes a light source 701, a DA-APD 702 according to the present disclosure, a TIA 703, and a distance measurement circuit 704. The light source 701 emits pulsed light (hereinafter referred to as pulsed light) or frequency-modulated light.

[0269] In the LIDAR device 700 according to the ninth embodiment, the distance to the object 705 is calculated by measuring the time it takes for pulsed light emitted from a light source to hit the object 705 and return to the semiconductor light-receiving element. An LD or the like is used as the light source 701. To measure long distances, the light output of the LD needs to be increased, but an upper limit is set for the amount of light emitted from the LD for eye safety reasons. Therefore, the receiving sensitivity of the semiconductor light-receiving element needs to be increased. Therefore, in the LIDAR device 700 according to the ninth embodiment, the DA-APD 702 according to the present disclosure is used as the semiconductor light-receiving element with a high multiplication factor.

[0270] The detected optical pulse is multiplied by the DA-APD 702 of the present disclosure and converted into a current pulse. It is then amplified by the TIA 703 and input to the distance measurement circuit 704, and as shown in the conceptual diagrams of Figures 42A and 42B, the time when the intensity of the pulse signal exceeds a preset discrimination line is determined to be the arrival time. The timing at which the optical pulse is emitted from the light source 701 is input as a signal to the distance measurement circuit 704, and the distance to the object 705 can be calculated by multiplying the time difference between them by the speed of light and dividing the result by 2. Another method that can be used is to emit frequency-modulated light and calculate the distance from the frequency difference between the emitted wave and the returning reflected wave.

[0271] <Functions and Effects of the LIDAR Device According to Embodiment 9> Because the reflectivity of the object 705 is not necessarily high and the reflection direction varies, it is necessary to detect weak light using an APD. With a conventional APD, as shown in the conceptual diagram of FIG. 42A , when a voltage is set to achieve high multiplication and the APD is operated, the multiplication time becomes long, and the current pulse width output from the APD becomes wide. Furthermore, the tunnel current increases, making it difficult to distinguish between light pulses. Even with a method of calculating distance from the frequency difference between the emitted wave and the reflected wave, frequency discrimination becomes difficult.

[0272] On the other hand, the DA-APD of the present disclosure used in the LIDAR device 700 according to the ninth embodiment can obtain high sensitivity even when the light receiving sensitivity of a conventional APD is insufficient. As a result, not only can it measure the distance to a distant object 705, but it can also reduce the optical output of the light source 701, thereby saving power and improving safety for the eyes.

[0273] Furthermore, with the DA-APD 505a of the present disclosure, even at a high multiplication factor of 20 or more, the tunnel current does not increase as described in the explanation of FIG. 15, making it easy to identify weak light. Furthermore, as shown in FIG. 33, the residence time in the multiplication layer is short, and therefore, as shown in the conceptual diagram of FIG. 42B, a current pulse with a high peak intensity is obtained, resulting in high identification sensitivity. As a result, not only is it possible to measure the distance to a distant object, but the optical output of the light source can be reduced, thereby saving power and further improving safety for the eyes.

[0274] Effect of Ninth Embodiment As described above, according to the LIDAR device of the ninth embodiment, the reflected light from an object is received by the DA-APD of the present disclosure, which has the effect of enabling distance measurement of a distant object, enabling power consumption of the light source to be reduced, and further providing a LIDAR device that is highly safe for the eyes.

[0275] Although the present disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to application to a particular embodiment, but may be applied to the embodiments alone or in various combinations.

[0276] Therefore, countless variations not illustrated are conceivable within the scope of the technology of the present disclosure, including, for example, cases where at least one component is modified, added, or omitted, and even cases where at least one component is extracted and combined with a component of another embodiment.

[0277] 1 Fe-doped InP substrate, 2 n-type InP conductive layer, 3 n-type InAlAs conductive layer, 4 i-type InAlAs multiplication layer, 4a i-type InAs / AlAs digital alloy structure multiplication layer, 5 p-type InAlAs electric field relaxation layer, 5a p-type InP electric field relaxation layer, 6 i-type InGaAs light absorption layer, 6a i-type InGaAs first light absorption layer, 6b p-type InGaAs second light absorption layer, 7 i-type InAlGaAs graded layer, 7a p-type InAlGaAs graded layer, 8 i-type InAlAs surface protection layer, 8a i-type InAlAs graded layer, 9 p-type InP window layer, 9a i-type InP window layer, 9b i-type InP first window layer, 9c p-type InAlAs second window layer, 10 p-type InGaAs contact layer, 10a i-type InGaAs contact layer, 11 surface protection film, 12 selective diffusion mask, 15 front-side anti-reflection film, 16 back-side anti-reflection film, 20, 20a p-type impurity diffusion region, 30 first mesa structure, 31 second mesa structure, 32 third mesa structure, 33 mesa structure, 35 mesa groove, 40, 40a terrace portion, 41, 41a terrace surface, 42a first terrace portion, 42b second terrace portion, 45, 45a hydrogen passivation region, 50, 50a n-type electrode, 51, 51a p-type electrode, 52 back electrode, 60 light-receiving region, 66 light-shielding metal film, 100, 110, 120, 130, 140, 150, 160, 170, 200 Semiconductor photodetector, 250a, 260, 260a, 260b, 270 Optical line terminal, 251, 261, 274 FEC, 252, 262, 273, 303 Driver amplifier, 253, 263, 272, 304, 401, 701 Light source, 254, 264, 271 WDM, 255, 265a, 301, 506 DSP, 256, 266a, 302b ADC, 258 APD, 257, 267 Burst TIA, 265, 278 CDR, 266, 277 Limiting amplifier, 267a, 276, 703 TIA, 268, 275, 305, 403, 505a, 702 DA-APD, 300 Multilevel intensity modulation transmitting / receiving device, 302a DAC, 310, 501 Optical fiber cable, 306 Linear-TIA, 400, 450 Radio-on-fiber system, 402 Transmission path, 404 Antenna, 406 PD, 500 Digital coherent receiving device, 501 Optical fiber cable, 502 Polarization separator, 503a,503b 90-degree hybrid device, 504 semiconductor laser, 505 balanced detector, 600 SPAD sensor system, 601 photoelectric measurement circuit, 602 SPAD sensor, 603 quenching circuit, 700 lidar device, 704 ranging circuit, 705 object,

Claims

1. A semiconductor light-receiving element comprising: a substrate; a first mesa structure having at least an n-type semiconductor layer, a multiplication layer, a p-type electric field buffer layer, a light absorption layer, and an i-type semiconductor layer having a band gap larger than that of the light absorption layer, which are formed in this order on the substrate; a second mesa structure formed on the first mesa structure and having at least a window layer having a band gap larger than that of the light absorption layer; and a terrace portion consisting of the outermost surface of the first mesa structure exposed on the outer periphery of the second mesa structure.

2. The semiconductor photodetector according to claim 1, wherein the window layer is composed of two layers, an i-type first window layer and a p-type second window layer, from the side in contact with the first mesa structure.

3. A semiconductor light-receiving element comprising: a substrate; a first mesa structure having at least an n-type semiconductor layer, a multiplication layer, and an electric field relaxation layer formed in this order on the substrate; a second mesa structure formed on the first mesa structure and having at least a light absorption layer and a window layer having a band gap larger than that of the light absorption layer; and a terrace portion consisting of the outermost surface of the first mesa structure exposed on the outer periphery of the second mesa structure.

4. The semiconductor light-receiving element according to claim 3, wherein the light-absorbing layer is composed of two layers, an i-type first light-absorbing layer and a p-type second light-absorbing layer, from the side in contact with the first mesa structure.

5. The semiconductor light-receiving element according to claim 3 or 4, wherein the electric field relaxation layer is made of a p-type InAlAs layer.

6. The semiconductor photodetector according to claim 3 or 4, wherein the electric field relaxation layer is made of a p-type InP layer.

7. A semiconductor light-receiving element comprising: a substrate; a first mesa structure having at least an n-type semiconductor layer, a multiplication layer, and a p-type electric field buffer layer formed in this order on the substrate; a second mesa structure formed on the first mesa structure and having at least a light absorption layer and an i-type surface protection layer; a first terrace portion consisting of the outermost surface of the first mesa structure exposed on the outer periphery of the second mesa structure; a third mesa structure formed on the second mesa structure and having at least a window layer having a band gap larger than that of the light absorption layer; and a second terrace portion consisting of the outermost surface of the second mesa structure exposed on the outer periphery of the third mesa structure.

8. The semiconductor light-receiving element according to claim 7, wherein the second mesa structure further comprises an i-type semiconductor layer on the light-absorbing layer, the i-type semiconductor layer having a band gap larger than that of the light-absorbing layer.

9. The semiconductor light-receiving element according to any one of claims 1, 3 to 8, further comprising: p-type impurity diffusion regions provided in the window layer and in a portion of the light absorption layer.

10. The semiconductor light-receiving element according to claim 9, wherein the thickness of said p-type impurity diffusion region within said light absorption layer is 0.1 μm or more and 0.3 μm or less.

11. The semiconductor light-receiving element according to claim 9 or 10, wherein the p-type impurity contained in said p-type impurity diffusion region is any one of zinc, cadmium, magnesium, and beryllium.

12. The semiconductor light-receiving element according to any one of claims 1, 3 to 7, wherein the conductivity type of the window layer is p-type.

13. The semiconductor light-receiving element according to any one of claims 1 to 12, wherein the multiplication layer has a digital alloy structure.

14. The semiconductor photodetector according to claim 13, wherein the digital alloy structure is a structure in which InAs layers and AlAs layers are alternately stacked.

15. A semiconductor light-receiving element according to any one of claims 1 to 6, further comprising a surface protection film made of an insulating film that covers at least the side portions of the first mesa structure, the side portions of the second mesa structure, and the surface of the terrace portion.

16. A semiconductor light-receiving element according to claim 15, further comprising a light-shielding metal film provided on at least the surface of the surface protection film covering the terrace portion and the surface protection film covering the side portion of the first mesa structure.

17. A semiconductor light-receiving element according to any one of claims 1 to 6, wherein a hydrogen passivation region is formed inside the semiconductor layer in contact with the underside of the terrace portion.

18. The hydrogen concentration in the hydrogen passivation region is 2×10 17 cm -3 1x10 or more 18 cm -3 18. The semiconductor light-receiving element according to claim 17, wherein the range is as follows:

19. A method for manufacturing a semiconductor light-receiving element, comprising the steps of: epitaxially growing on a substrate at least an n-type semiconductor layer, a multiplication layer, a p-type electric field buffer layer, a light-absorbing layer, an i-type semiconductor layer having a band gap larger than that of the light-absorbing layer, a window layer having a band gap larger than that of the light-absorbing layer, and a p-type contact layer; forming a selective diffusion mask made of an insulating film having a substantially circular opening on the surface of the p-type contact layer; forming a p-type impurity diffusion region whose bottom extends from the opening to at least the interior of the light-absorbing layer; removing the selective diffusion mask; processing the p-type contact layer into a ring shape that follows the outer periphery of the light-receiving region; forming a second mesa structure by etching the outer periphery of the light-receiving region until at least the i-type semiconductor layer is exposed on the surface; and forming a first mesa structure by etching from the outer periphery of the second mesa structure except for a predetermined region.

20. The method for manufacturing a semiconductor light-receiving element according to claim 19, wherein the p-type impurity diffusion region is formed by a vapor phase diffusion method or a solid phase diffusion method.

21. An optical line termination device comprising: a semiconductor photodetector according to any one of claims 1 to 20; an optical multiplexer / demultiplexer that inputs an optical signal to said semiconductor photodetector; an amplifier circuit that amplifies an electrical signal output from said semiconductor photodetector; a clock and data recovery circuit connected to said amplifier circuit that recovers clock data from the amplified electrical signal; and a forward error correction circuit connected to said clock and data recovery circuit that corrects errors in the clock data.

22. An optical line termination device comprising: a semiconductor photodetector according to any one of claims 1 to 20; an optical multiplexer / demultiplexer that inputs an optical signal to the semiconductor photodetector; an amplifier circuit that amplifies an electrical signal output from the semiconductor photodetector; an analog / digital conversion circuit connected to the amplifier circuit that converts the amplified electrical signal into a digital signal; a digital signal processing circuit connected to the analog / digital conversion circuit that processes the digital signal; and a forward error correction circuit connected to the digital signal processing circuit that corrects errors in the digital signal.

23. A multi-level intensity modulation transmitting / receiving device comprising: a semiconductor photodetector according to any one of claims 1 to 20, which receives a multi-level intensity modulated optical signal; an amplifier circuit which amplifies an electrical signal output from the semiconductor photodetector; an analog / digital conversion circuit connected to the amplifier circuit, which converts the amplified electrical signal into a digital signal; and a digital signal processing circuit connected to the analog / digital conversion circuit, which processes the digital signal.

24. A radio-on-fiber system comprising: a light source that emits an analog-modulated optical signal; a semiconductor photodetector according to any one of claims 1 to 20 that receives the analog-modulated optical signal; a transmission path that transmits the analog electrical signal output from the semiconductor photodetector to an antenna; and an antenna connected to the transmission path that radiates the analog electrical signal as a radio wave signal.

25. A digital coherent receiving device comprising: a semiconductor photodetector according to any one of claims 1 to 20; a polarization separator that separates the polarizations of a polarization multiplexed optical signal whose intensity and phase are modulated; a 90-degree hybrid that splits and combines the optical signals output from the polarization separator; and a digital signal processing circuit connected to the 90-degree hybrid that processes digital signals.

26. A SPAD sensor system comprising: a SPAD sensor constructed using a semiconductor light-receiving element according to any one of claims 1 to 20; a quenching circuit that repeatedly applies a voltage equal to or greater than the breakdown voltage and a voltage less than the breakdown voltage to the SPAD sensor; and an optoelectronic measurement circuit that measures the electrical signal output from the SPAD sensor.

27. A lidar device comprising: a light source that emits pulsed light or frequency-modulated light; a semiconductor light-receiving element according to any one of claims 1 to 20 that receives light that is emitted from the light source and reflected by an object; an amplifier circuit that amplifies the electrical signal output from the semiconductor light-receiving element; and a distance measuring circuit that calculates distance based on the electrical signal amplified by the amplifier circuit.

Images