Semiconductor module

Abstract

According to the embodiments, a semiconductor module (2) comprises a plurality of semiconductor chips (3), a busbar (51), and a stress relaxation part (53). The plurality of semiconductor chips (3) are provided on a substrate (7). The busbar (51) is provided on the semiconductor chips and electrically connects the semiconductor chips. The busbar (51) is formed from a plurality of small busbar parts (52). The stress relaxation part (53) is provided between adjacent small busbar parts (52) at at least one location, electrically connects the small busbar parts (52), and alleviates thermal stress that occurs between the small busbar parts.

Description

Semiconductor Module

[0001] The disclosed embodiments relate to a semiconductor module.

[0002] A semiconductor module used in a power conversion device includes multiple semiconductor chips mounted on a substrate and bus bars that electrically connect the multiple semiconductor chips. Because such a semiconductor module handles high voltages and currents, it generates heat during operation.

[0003] When the busbars in a semiconductor module thermally expand due to heat generation, stress caused by thermal strain concentrates at the ends of the lead terminals joined to the main electrodes within the sealing body, which can become the starting point for damage. Therefore, a semiconductor module has been proposed in which the ends of the busbars are bent to relieve the thermal stress in the busbars (see, for example, Japanese Patent Application Laid-Open No. 2018-93244).

[0004] Japan Publication No. 2018-93244

[0005] However, since the thermal stress of the busbar affects not only the ends of the busbar but the entire busbar, it can be one of the causes of the electrical connection between the semiconductor chip and the substrate. Therefore, it may be difficult to sufficiently relieve the thermal stress of the busbar by simply bending the ends of the busbar, as in the technique described in Patent Document 1.

[0006] One aspect of the embodiment has been made in view of the above, and aims to provide a semiconductor module that can improve the thermal stress relaxation performance of a bus bar.

[0007] A semiconductor module according to one aspect of the embodiment includes a plurality of semiconductor chips, a bus bar, and a stress relief portion. The plurality of semiconductor chips are provided on a substrate. The bus bar is disposed on the semiconductor chips and electrically connects the semiconductor chips to each other. The bus bar is composed of a plurality of small bus bar portions. The stress relief portion is provided between at least one or more adjacent small bus bar portions, electrically connecting the small bus bar portions to each other and easing thermal stress generated between the small bus bar portions.

[0008] In the semiconductor module according to the embodiment, the thermal stress of the bus bar is absorbed by the stress absorbing portion, thereby improving the thermal stress absorbing performance of the bus bar.

[0009] FIG. 1 is a diagram illustrating an example of a circuit configuration of an inverter circuit according to an embodiment. FIG. 2 is an explanatory side cross-sectional view of an inverter circuit according to a first embodiment. FIG. 3 is an explanatory side cross-sectional view illustrating an example of a configuration of a busbar according to a second embodiment. FIG. 4 is an explanatory side cross-sectional view illustrating an example of a configuration of a busbar according to a third embodiment. FIG. 5 is an explanatory side cross-sectional view illustrating an example of a configuration of a busbar according to a fourth embodiment. FIG. 6 is an explanatory side cross-sectional view illustrating an example of a configuration of a busbar according to a fifth embodiment. FIG. 7 is an explanatory side cross-sectional view of an inverter circuit according to a sixth embodiment. FIG. 8 is an explanatory side cross-sectional view illustrating an example of a configuration of a busbar according to a seventh embodiment. FIG. 9 is an explanatory side cross-sectional view illustrating an example of a configuration of a busbar according to an eighth embodiment. FIG. 10 is an explanatory side cross-sectional view of an inverter circuit according to a ninth embodiment. FIG. 11 is an explanatory side cross-sectional view of an inverter circuit according to a comparative example. FIG. 12 is an explanatory side cross-sectional view of an inverter circuit according to a tenth embodiment.

[0010] Hereinafter, a detailed description will be given of a semiconductor module according to the present disclosure (hereinafter referred to as an "embodiment") with reference to the drawings. Note that the present disclosure is not limited to the embodiment. Furthermore, the embodiments can be appropriately combined as long as the processing content is not contradictory. Furthermore, in the following embodiments, components that perform the same function are assigned the same reference numerals, and redundant description will be omitted.

[0011] Furthermore, in the embodiments described below, expressions such as "constant," "orthogonal," "vertical," or "parallel" may be used, but these expressions do not necessarily mean "constant," "orthogonal," "vertical," or "parallel" in the strict sense. In other words, the expressions described above allow for deviations due to, for example, manufacturing precision, installation precision, etc. It is sufficient to use "constant," "orthogonal," "vertical," or "parallel" to the extent that the effects of the invention are achieved.

[0012] 1. Example of Circuit Configuration of Inverter Circuit According to Embodiment An example of the circuit configuration of an inverter circuit according to an embodiment will be described with reference to Fig. 1. Fig. 1 is a diagram showing an example of the circuit configuration of an inverter circuit 2 according to an embodiment.

[0013] The inverter circuit 2 according to the embodiment constitutes, for example, a part of a power conversion device that converts DC power supplied from a DC power supply 10 into AC power. The inverter circuit 2 includes a plurality of semiconductor chips provided on a substrate. Note that Fig. 1 shows an example in which the entire inverter circuit 2 is modularized. That is, in the example shown in Fig. 1, the entire inverter circuit 2 corresponds to the semiconductor module according to the embodiment.

[0014] 1, the inverter circuit 2 includes a first switching unit 21 and a second switching unit 22. The number of switching units included in the inverter circuit 2 is not limited to two.

[0015] The first switching unit 21 includes a first transistor 3 and a first diode 30. The first transistor 3 and the first diode 30 may be provided on separate semiconductor chips. The first transistor 3 is, for example, a power metal oxide semiconductor field effect transistor (MOSFET). The first transistor 3 may also be an insulated gate bipolar transistor (IGBT) or a gate turn-off (GTO) thyristor. The first diode 30 is connected in anti-parallel to the first transistor 3. The first diode 30 is a freewheeling diode for protecting the first transistor 3.

[0016] When the first transistor 3 is a power MOSFET, the first diode 30 may be a body diode built into the first transistor 3. In this case, the first diode 30 is the same semiconductor chip as the first transistor 3. Note that the semiconductor module according to the embodiment may be one in which the first transistor 3 and the first diode 30 are modularized.

[0017] The second switching unit 22 includes a second transistor 4 and a second diode 40. The second transistor 4 and the second diode 40 may be provided on separate semiconductor chips. The second transistor 4 may be, for example, a power MOSFET. The second transistor 4 may also be an IGBT or a GTO thyristor. The second diode 40 is connected in anti-parallel to the second transistor 4. The second diode 40 may be a freewheeling diode for protecting the second transistor 4.

[0018] When the second transistor 4 is a power MOSFET, the second diode 40 may be a body diode built into the second transistor 4. In this case, the second diode 40 is the same semiconductor chip as the second transistor 4. Note that the semiconductor module according to the embodiment may be one in which the second transistor 4 and the second diode 40 are modularized.

[0019] The first transistor 3 is an element that functions as a low-side transistor in the power conversion circuit. If the first transistor 3 is a MOSFET, the source 32 is connected to a wiring on the substrate that is connected to the negative electrode of the DC power supply 10. The drain 33 of the first transistor 3 is connected to a wiring on the substrate that is connected to the source 42 of the second transistor 4. The wiring that connects the drain 33 of the first transistor 3 and the source 42 of the second transistor 4 is connected to the output node 5. The first transistor 3 is controlled to be turned on and off by a control voltage applied to the gate 31.

[0020] The second transistor 4 is an element that functions as a high-side transistor in the power conversion circuit. If the second transistor 4 is a MOSFET, its source 42 is connected to a wiring on the substrate that is connected to the drain 33 of the first transistor 3. The drain 43 of the second transistor 4 is connected to a wiring on the substrate that is connected to the positive electrode of the DC power supply 10. The second transistor 4 is controlled to be turned on and off by a control voltage applied to its gate 41.

[0021] In the inverter circuit 2 configured as above, the first transistor 3 and the second transistor 4 are alternately turned on in accordance with the control voltages applied to the gate 31 of the first transistor 3 and the gate 41 of the second transistor 4 .

[0022] As a result, the inverter circuit 2 converts DC power input from the DC power supply 10 into AC power and outputs it to a load such as a motor from the output terminal 11 via the output node 5. When two inverter circuits 2 are connected in parallel, single-phase AC power can be generated, and when three inverter circuits 2 are connected in parallel, three-phase AC power can be generated.

[0023] 2. Example of Side End Surface Structure of Inverter Circuit According to First Embodiment FIG. 2 is an explanatory side cross-sectional view of the inverter circuit 2 according to the first embodiment. As shown in FIG. 2, the inverter circuit 2 according to the first embodiment includes a substrate 7, a plurality of first transistors 3, and a bus bar 51. While the plurality of transistors are shown as first transistors 3 in FIG. 2, they may be second transistors 4 or a combination of the first transistors 3 and the second transistors 4. The substrate 7 has a three-layer structure in which a first conductive layer 71 serving as a base plate, a ceramic layer 72 serving as an insulating layer, and a second conductive layer 73 on which a wiring pattern is formed are sequentially stacked. The first conductive layer 71 and the second conductive layer 73 are made of, for example, copper.

[0024] The plurality of first transistors 3 are provided on the substrate 7 via connection pads 81. The bus bar 51 has connection pads 81 provided on each of the first transistors 3, electrically connecting the plurality of first transistors 3. At least a portion of the connection pads 81 includes a bonding material such as solder, sintered metal, or a conductive adhesive.

[0025] The left end of the bus bar 51 is fixed to a module housing (not shown). The bus bar 51 is made up of a plurality of small bus bar portions 52. Each small bus bar portion 52 is made of, for example, a copper plate. The bus bar 51 also includes a stress relief portion 53. The stress relief portion 53 is provided between at least one or more adjacent small bus bar portions 52.

[0026] The stress relief portions 53 are made of a material that is conductive and softer than the small busbar portions 52. The stress relief portions 53 are made of, for example, solder, sintered metal, or a conductive adhesive. As a result, the stress relief portions 53 electrically connect the small busbar portions 52 to each other and can relieve thermal stress generated between the small busbar portions 52.

[0027] In other words, even if the small busbar portions 52 thermally expand due to heat generated by switching the first transistor 3 and the second transistor 4, the stress relief portions 53 can absorb the thermal stress of the small busbar portions 52, thereby alleviating the thermal stress generated between the small busbar portions 52.

[0028] Furthermore, the inverter circuit 2 includes a plurality of legs 54. The legs 54 are located between the bus bar 51 and the substrate 7. For example, the legs 54 are located between the small bus bar portion 52 and the substrate 7. The legs 54 support the bus bar 51. This allows the inverter circuit 2 to prevent the bus bar 51 from tilting from a state parallel to the substrate 7 even if the connection pad 81 is softened due to heat generated by the first transistor 3 or the second transistor 4. Therefore, the inverter circuit 2 can prevent poor connection between the bus bar 51 and the connection pad 81 due to tilting of the bus bar 51.

[0029] The legs 54 may be integral with the small busbar portions 52, or may be separate from the small busbar portions 52. When the legs 54 are integral with the small busbar portions 52, they are conductive and are therefore provided so as to be positioned between the ceramic layer 72 on the substrate 7 and the small busbar portions 52. This allows the inverter circuit 2 to have a reduced number of components.

[0030] Furthermore, when the leg portions 54 are separate from the small busbar portions 52, they may be made of an insulator. In this case, the contact position between the leg portions 54 and the substrate 7 may be the ceramic layer 72 or the second conductive layer 73. This improves the flexibility of the positions at which the leg portions 54 are provided in the inverter circuit 2. Note that the configuration of the busbar 51 shown in FIG. 2 is one example. Next, other configuration examples of the busbar 51 will be described.

[0031] [3. Configuration Examples of Busbars] Fig. 3 is a cross-sectional side view illustrating a configuration example of a busbar according to a second embodiment. Fig. 4 is a cross-sectional side view illustrating a configuration example of a busbar according to a third embodiment. Fig. 5 is a cross-sectional side view illustrating a configuration example of a busbar according to a fourth embodiment. Fig. 6 is a cross-sectional side view illustrating a configuration example of a busbar according to a fifth embodiment. Fig. 7 is a cross-sectional side view illustrating an inverter circuit according to a sixth embodiment. Fig. 8 is a cross-sectional side view illustrating a configuration example of a busbar according to a seventh embodiment. Fig. 9 is a cross-sectional side view illustrating a configuration example of a busbar according to an eighth embodiment. Fig. 10 is a cross-sectional side view illustrating an inverter circuit according to a ninth embodiment.

[0032] As shown in Figures 3 to 6, the busbars 51 according to the second to fifth embodiments differ from the busbar 51 according to the first embodiment in the shape of the ends of the small busbar portions 52 adjacent to each other across the stress relief portion 53, and in the shape of the stress relief portion 53 that follows the shape of the ends of the small busbar portions 52.

[0033] As shown in Figures 3 to 6, at least one adjacent small busbar portion 52 in the busbar 51 according to the second to fifth embodiments partially overlaps with each other via a stress relief portion 53 when viewed from the normal direction of the substrate 7.

[0034] As a result, the busbar 51 can support one of the adjacent small busbar portions 52 from below by the other small busbar portion 52 that is located below the first small busbar portion 52 via the stress relief portion 53.

[0035] Therefore, the busbar 51 according to the second to fifth embodiments can prevent the busbar 51 from tilting from a state parallel to the substrate 7 even if the connection pad 81 is softened due to heat generated by the first transistor 3 or the second transistor 4 or due to heating treatment during mounting.

[0036] Specifically, as shown in FIG. 3 , at least one adjacent small busbar portion 52 according to the second embodiment has an L-shaped notch 91 at its end, which is fitted together via a stress relief portion 53 in a side cross section.

[0037] 4, at least one or more adjacent small busbar portions 52 according to the third embodiment have an inclined portion 92 at their ends that vertically overlap with each other via a stress relief portion 53. As shown in FIG. 5, at least one or more adjacent small busbar portions 52 according to the fourth embodiment have an end portion of one small busbar portion 52 that has a protrusion 93. The other small busbar portion 52 according to the fourth embodiment has an end portion that has a recess 94 into which the protrusion 93 fits.

[0038] As shown in FIG. 6 , at least one adjacent small busbar portion 52 according to the fifth embodiment has one small busbar portion 52 that includes a convex portion 93 and the other small busbar portion 52 that includes a concave portion 94, similar to the small busbar portions 52 according to the fourth embodiment.

[0039] However, the convex portion 93 of one small busbar portion 52 according to the fifth embodiment is wedge-shaped in side cross section. The concave portion 94 of the other small busbar portion 52 has a shape that narrows toward the back. The busbar 51 according to the second to fifth embodiments can prevent the busbar 51 from tilting from a state parallel to the substrate 7, even if the connection pad 81 is softened by heat generated by the first transistor 3 or the second transistor 4 or by heating during mounting.

[0040] According to the configuration shown in FIGS. 3 to 6, i.e., the configuration in which the end of one small busbar portion 52 supports the end of the other small busbar portion 52 from below, as shown in FIG. 7, the inverter circuit 2 according to the sixth embodiment can suppress tilting of the busbars 51 even if the number of legs 54 is reduced.

[0041] As shown in FIGS. 8 and 9 , the busbars 51 according to the seventh and eighth embodiments include leaf springs 55, 56 that function as stress relief portions 53 between at least one or more adjacent small busbar portions 52.

[0042] Specifically, as shown in Fig. 8, the leaf spring 55 according to the seventh embodiment is a leaf spring 55 having a U-shape in side cross section. Also, as shown in Fig. 9, the leaf spring 56 according to the eighth embodiment is a leaf spring 56 having a zigzag shape in side cross section. According to the busbars 51 according to the seventh and eighth embodiments, thermal stress due to thermal expansion of the small busbar portions 52 can be alleviated by the elastic deformation of the leaf springs 55, 56.

[0043] Furthermore, the leaf springs 55, 56 according to the seventh and eighth embodiments may be integral with the small busbar portion 52, or may be separate from the small busbar portion 52. When the leaf springs 55, 56 and the small busbar portion 52 are integral with each other, the busbar 51 can be manufactured by, for example, shaping a single copper plate using a mold, which simplifies the manufacturing process.

[0044] In this case, busbar 51 is formed so that the thickness of leaf springs 55, 56 is thinner than that of small busbar portion 52. This makes leaf springs 55, 56 of busbar 51 more susceptible to elastic deformation than small busbar portion 52, improving the ability to alleviate thermal stress caused by thermal expansion of small busbar portion 52.

[0045] Furthermore, when the leaf springs 55, 56 and the small busbar portions 52 are separate bodies, the leaf springs 55, 56 are typically made of a conductive material that is softer than the small busbar portions 52. This makes the leaf springs 55, 56 of the busbar 51 more susceptible to elastic deformation than the small busbar portions 52, improving the ability to alleviate thermal stress caused by thermal expansion of the small busbar portions 52. Note that when the leaf springs 55, 56 and the small busbar portions 52 are separate bodies, the leaf springs 55, 56 and the small busbar portions 52 may be fixed together by welding or the like, or by fasteners such as screws.

[0046] Also, as shown in FIG. 10 , in the inverter circuit 2 according to the ninth embodiment, of the multiple legs 54 provided on the bus bar 51, at least one leg 54 has its tip connected to an electrically isolated floating node pattern 57 on the substrate 7.

[0047] A control pin 58 for detecting the state of the bus bar 51 is provided at a location on the floating node pattern 57 different from the location to which the leg 54 is connected. The control pin 58 is, for example, a voltage detection terminal for a separately provided controller to monitor the voltage of the bus bar 51. Alternatively, when the bus bar 51 is connected to the source of the first transistor 3, the control pin 58 is connected to the source terminal of a separately provided gate driver circuit.

[0048] In this way, in the inverter circuit 2 of the ninth embodiment, the leg 54 whose tip is connected to the floating node pattern 57 can be used both to support the bus bar 51 and to connect the bus bar 51 to the control pin 58.

[0049] Furthermore, in the inverter circuit 2 according to the ninth embodiment, the control pin 58 is provided at a position different from the current path, so that it is possible to detect the voltage of the bus bar 51 while minimizing the influence of wiring inductance. Furthermore, in the inverter circuit 2 according to the ninth embodiment, a floating node can be formed at any position on the substrate 7, so that it is possible to improve the degree of freedom in the layout of the control pin 58.

[0050] In the above-described inverter circuit 2, the potential of the output node 5 fluctuates at high frequency in accordance with the switching of the first transistor 3 and the second transistor 4. Therefore, if the output node 5 has stray capacitance, charging and discharging of the stray capacitance may occur, which may cause noise. In particular, if a node (such as a heat sink) grounded to earth potential is present close to the output node 5, the stray capacitance between them may cause common mode noise. For this reason, it is preferable that the stray capacitance between the output node 5 and earth potential is small.

[0051] Next, the cross-sectional structure and stray capacitance of a general semiconductor module according to a comparative example will be described, and then the cross-sectional structure and stray capacitance of the inverter circuit 2 according to the tenth embodiment will be described.

[0052] 11 is a side cross-sectional view of an inverter circuit 20 according to a comparative example. As shown in FIG. 11 , the general inverter circuit 20 according to the comparative example has a first switching unit 21 and a second switching unit 22 provided on a substrate 7. The first switching unit 21 includes a first transistor 3. The second switching unit 22 includes a second transistor 4.

[0053] The substrate 7 has a three-layer structure in which a first conductive layer 71 serving as a base plate, a ceramic layer 72 serving as an insulating layer, and a second conductive layer 73 on which a wiring pattern is formed are sequentially stacked. The first conductive layer 71 and the second conductive layer 73 are made of, for example, copper. The first transistor 3 and the second transistor 4 have the same structure.

[0054] For example, the first transistor 3 has a gate 31 and a source 32 on one main surface side, and a drain 33 on the other main surface side. A connection pad 81 is provided for each of the gate 31, the source 32, and the drain 33. The connection pad 81 is, for example, solder.

[0055] Similarly, the second transistor 4 has a gate 41 and a source 42 on one main surface side, and a drain 43 on the other main surface side. Connection pads 81 are provided to the gate 41, the source 42, and the drain 43, respectively.

[0056] 11 , the first transistor 3 is provided on the substrate 7 so that the connection pad 81 of the drain 33 abuts the output node 5 of the second conductive layer 73. The second transistor 4 is provided on the substrate 7 so that the connection pad 81 of the drain 43 abuts the second conductive layer 73.

[0057] The source 32 of the first transistor 3 and the wiring pattern of the second conductive layer 73 are connected by a bonding wire 82. The drain 33 of the first transistor 3 and the source 42 of the second transistor 4 are also connected by a bonding wire 82. A bus bar may be used instead of a bonding wire for connection.

[0058] In this configuration, the output node 5 and the first conductive layer 71 (base plate) form a pair of electrodes to form a stray capacitance 6. In this case, the distance D1 between the pair of electrodes is the same as the thickness of the ceramic layer 72 and is relatively small. Therefore, the stray capacitance 6 of the inverter circuit 20 according to the comparative example becomes large.

[0059] Therefore, the inverter circuit 2 of the tenth embodiment described next is configured so that the distance D2 between a pair of electrodes that forms the floating capacitance 6 is wider than that of the inverter circuit 20 of the comparative example, thereby reducing the floating capacitance 6.

[0060] 12 is a side cross-sectional explanatory view of an inverter circuit 2 according to a tenth embodiment. As shown in FIG. 12, the inverter circuit 2 according to the tenth embodiment has a first switching unit 21 and a second switching unit 22 provided on a substrate 7. The first switching unit 21 includes a first transistor 3. The second switching unit 22 includes a second transistor 4.

[0061] The first transistor 3 and the second transistor 4 according to the tenth embodiment are the same elements as the first transistor 3 and the second transistor 4 according to the comparative example. However, the first transistor 3 and the second transistor 4 according to the tenth embodiment are provided on the substrate 7 with their front and backs facing inversely to each other.

[0062] 12 , the first transistor 3 according to the tenth embodiment is flip-chip mounted on the substrate 7 so that its front and back face faces in the opposite direction to the first transistor 3 according to the comparative example. The second transistor 4 according to the tenth embodiment is mounted on the substrate 7 so that its front and back face faces in the same direction as the second transistor 4 according to the comparative example.

[0063] Specifically, the first transistor 3 according to the tenth embodiment is provided on the substrate 7 so that the connection pads 81 of the gate 31 and the source 32 abut against the wiring pattern of the second conductive layer 73. The second transistor 4 according to the tenth embodiment is provided on the substrate 7 so that the connection pad 81 of the drain 43 abuts against the second conductive layer 73, similar to the second transistor 4 of the comparative example.

[0064] The connection pad 81 of the drain 33 of the first transistor 3 according to the tenth embodiment and the connection pad 81 of the source 42 of the second transistor 4 according to the tenth embodiment are connected by a bus bar 51 that serves as the output node 5. The bus bar 51 includes a stress relief portion 53. The stress relief portion 53 is provided between at least one or more adjacent small bus bar portions 52. Fig. 12 shows an example in which the structure of the first embodiment is applied to the stress relief portion 53, but a configuration following any of the second to eighth embodiments may also be used.

[0065] Furthermore, the inverter circuit 2 according to the tenth embodiment includes a columnar connection portion 50 that extends from the underside of the bus bar 51 to the connection pad 81 of the first switching unit 21 and the connection pad 81 of the second switching unit 22, electrically connecting the bus bar 51 and the connection pad 81.

[0066] In this configuration, the output node 5 (bus bar 51) and the first conductive layer 71 form a pair of electrodes to form a floating capacitance 6. The distance D2 between the pair of electrodes is equal to the total thickness of the ceramic layer 72, the second conductive layer 73, the connection pad 81, the first transistor 3 (second transistor 4), and the connection portion 50.

[0067] That is, the distance D2 between the pair of electrodes of the stray capacitance 6 according to the tenth embodiment is greater than the distance D1 between the pair of electrodes of the stray capacitance 6 according to the comparative example. As a result, the inverter circuit 2 according to the tenth embodiment has a smaller stray capacitance 6 than the inverter circuit 20 according to the comparative example, and common node noise can be reduced.

[0068] In the inverter circuit 2 according to the tenth embodiment, even if the connection portion 50 is not provided, the distance D2 between the pair of electrodes of the stray capacitance 6 is larger than the distance D1 between the pair of electrodes of the stray capacitance 6 according to the comparative example. Therefore, even if the connection portion 50 is not provided, the stray capacitance 6 of the inverter circuit 2 according to the tenth embodiment is smaller than that of the inverter circuit 20 according to the comparative example, and common node noise can be reduced.

[0069] [6. Supplementary Notes] The present technology may have the following configurations. (1) A semiconductor module including: a plurality of semiconductor chips provided on a substrate; and a bus bar provided on the semiconductor chips and electrically connecting the semiconductor chips to each other, the bus bar being composed of a plurality of small busbar portions and including a stress relief portion provided between at least one or more adjacent small busbar portions to electrically connect the small busbar portions to each other and to relieve thermal stress generated between the small busbar portions. (2) The semiconductor module according to (1), wherein at least one or more adjacent small busbar portions partially overlap with each other via the stress relief portion when viewed from a normal direction of the substrate. (3) The semiconductor module according to (2), wherein at least one or more adjacent small busbar portions include an L-shaped cutout portion at an end thereof that fits with each other via the stress relief portion. (4) The semiconductor module according to (2), wherein at least one or more adjacent small busbar portions have an inclined portion at their end that vertically overlaps with the stress relief portion interposed therebetween. (5) The semiconductor module according to (2), wherein at least one or more adjacent small busbar portions have a convex portion at their end, and the other small busbar portion has a concave portion at their end into which the convex portion fits. (6) The semiconductor module according to (5), wherein the convex portion is wedge-shaped in side cross section, and the concave portion has a shape that narrows toward the back. (7) The semiconductor module according to any one of (1) to (6), wherein the stress relief portion is solder, sintered metal, or conductive adhesive. (8) The semiconductor module according to (1), wherein the stress relief portion is a leaf spring. (9) The semiconductor module according to (1) or (8), wherein the small busbar portion and the stress relief portion are integral. (10) The semiconductor module according to (1) or (8), wherein the small busbar portion and the stress relaxation portion are separate bodies. (11) The semiconductor module according to any one of (1) to (10), further comprising: a leg portion positioned between the busbar and the substrate and supporting the busbar.(12) The semiconductor module according to (11), wherein tips of the legs are connected to an electrically isolated floating node pattern on the substrate, and a control pin for detecting a state of the bus bar is provided at a location on the floating node pattern different from the location to which the legs are connected. (13) The semiconductor module according to any one of (1) to (12), wherein a columnar connection portion extends from a lower surface of the bus bar to a connection pad of the semiconductor chip and electrically connects the bus bar to the connection pad. (14) The semiconductor module according to any one of (1) to (13), wherein one semiconductor chip of a pair of semiconductor chips electrically connected by the bus bar includes a low-side transistor having a source connected to wiring on the substrate that is connected to the negative electrode of a power supply and a drain connected to the bus bar, and the other semiconductor chip includes a high-side transistor having a source connected to the bus bar and a drain connected to wiring on the substrate that is connected to the positive electrode of the power supply.

[0070] Further advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described above. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

[0071] 2, 20 Inverter circuit 3 First transistor 4 Second transistor 5 Output node 6 Floating capacitance 7 Substrate 10 DC power supply 11 Output terminal 21 First switching section 22 Second switching section 30 First diode 31, 41 Gate 32, 42 Source 33, 43 Drain 40 Second diode 50 Connection section 51 Bus bar 52 Small bus bar section 53 Stress relief section 54 Leg section 55, 56 Leaf spring 57 Floating node pattern 58 Control pin 71 First conductive layer 72 Ceramic layer 73 Second conductive layer 81 Connection pad 82 Bonding wire 92 Sloped section 93 Convex section 94 Concave section

Claims

1. A semiconductor module comprising: a plurality of semiconductor chips mounted on a substrate; and a bus bar mounted on the semiconductor chips to electrically connect the semiconductor chips together, the bus bar being composed of a plurality of small bus bar portions and having a stress relief portion disposed between at least one or more adjacent small bus bar portions to electrically connect the small bus bar portions together and to relieve thermal stress generated between the small bus bar portions.

2. The semiconductor module according to claim 1, wherein at least one adjacent small busbar portion partially overlaps with the stress relaxation portion interposed therebetween when viewed from the normal direction of the substrate.

3. A semiconductor module according to claim 2, wherein at least one or more adjacent small busbar portions have an L-shaped cutout portion at their ends that fits together via the stress relief portion.

4. The semiconductor module according to claim 2, wherein at least one or more adjacent small busbar portions have an inclined portion at an end thereof that vertically overlaps with the stress relaxation portion interposed therebetween.

5. The semiconductor module according to claim 2, wherein at least one or more adjacent small busbar portions have a convex portion at an end, and the other small busbar portion has a concave portion at an end into which the convex portion is fitted.

6. The semiconductor module according to claim 5, wherein the convex portion has a wedge shape in a side cross section, and the concave portion has a shape that narrows toward the back.

7. The semiconductor module according to any one of claims 1 to 6, wherein the stress relaxation portion is made of solder, sintered metal, or conductive adhesive.

8. The semiconductor module according to claim 1, wherein the stress relief portion is a leaf spring.

9. The semiconductor module according to claim 1, wherein the small busbar portion and the stress relaxation portion are integral.

10. The semiconductor module according to claim 1, wherein the small busbar portion and the stress relaxation portion are separate bodies.

11. The semiconductor module according to any one of claims 1 to 6, further comprising legs positioned between the bus bars and the substrate to support the bus bars.

12. The semiconductor module according to claim 11, wherein the tips of the legs are connected to an electrically isolated floating node pattern on the substrate, and a control pin for detecting the state of the bus bar is provided at a location on the floating node pattern different from the location where the legs are connected.

13. The semiconductor module according to any one of claims 1 to 6, further comprising columnar connection portions extending from the lower surface of the bus bar to the connection pads of the semiconductor chip, electrically connecting the bus bar and the connection pads.

14. A semiconductor module according to any one of claims 1 to 6, wherein one of the pair of semiconductor chips electrically connected by the bus bar comprises a low-side transistor whose source is connected to a wiring on the substrate that is connected to the negative electrode of the power supply and whose drain is connected to the bus bar, and the other semiconductor chip comprises a high-side transistor whose source is connected to the bus bar and whose drain is connected to a wiring on the substrate that is connected to the positive electrode of the power supply.

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