Semiconductor device and communication device

Abstract

Provided is a semiconductor device comprising: a compound semiconductor layer; an insulating layer stacked on the compound semiconductor layer; and a gate electrode stacked on the insulating layer so as to fill an opening provided in the insulating layer. A first metal layer, which forms a Schottky junction with the compound semiconductor layer, and a second metal layer, which suppresses metal diffusion from the gate electrode, are stacked on the compound semiconductor layer located beneath the opening.

Description

Semiconductor device and communication device

[0001] The present disclosure relates to a semiconductor device and a communication device.

[0002] HEMT (High Electron Mobility Transistor) devices, which are heterogeneous field-effect transistors (FETs) made of gallium nitride (GaN)-based wide-gap semiconductor materials, are capable of low resistance, high-speed, and high-voltage operation, and are therefore expected to be applied to RF (Radio Frequency) devices such as power devices and switches in 5G high-speed communication systems.

[0003] JP 2023-136148 A JP 2013-258368 A

[0004] A HEMT device with a Schottky gate structure has an insulating layer stacked on a compound semiconductor layer and a gate electrode that contacts the compound semiconductor layer through an opening in the insulating layer. When annealing is performed during manufacturing, metal (e.g., gold (Au) or the like) diffuses from the gate electrode and segregates on the surface of the compound semiconductor layer 110, which increases the off-leakage of the HEMT device and causes a fluctuation in the threshold voltage (Vth) during device operation.

[0005] Therefore, the present disclosure proposes a semiconductor device and a communication device that can suppress the diffusion of metal from the gate electrode to the surface of the compound semiconductor layer, thereby avoiding an increase in off-leakage and fluctuations in the threshold voltage (Vth) during device operation.

[0006] According to the present disclosure, there is provided a semiconductor device comprising: a compound semiconductor layer; an insulating layer stacked on the compound semiconductor layer; and a gate electrode stacked on the insulating layer so as to fill an opening provided in the insulating layer, wherein a first metal layer forming a Schottky junction with the compound semiconductor layer and a second metal layer suppressing diffusion of metal from the gate electrode are stacked on the compound semiconductor layer located below the opening.

[0007] Furthermore, according to the present disclosure, there is provided a communication device equipped with a semiconductor device, the semiconductor device including a compound semiconductor layer, an insulating layer stacked on the compound semiconductor layer, and a gate electrode stacked on the insulating layer so as to fill an opening provided in the insulating layer, and on the compound semiconductor layer located below the opening, a first metal layer forming a Schottky junction with the compound semiconductor layer and a second metal layer suppressing diffusion of metal from the gate electrode are stacked.

[0008] 1 is a cross-sectional view of a HEMT device 10a according to a comparative example; FIG. 2 is a cross-sectional view of a HEMT device 10b according to a comparative example; FIG. 3 is a cross-sectional view of a HEMT device 10 according to an embodiment of the present disclosure; FIG. 4 is a cross-sectional view of a HEMT device 10 according to a first modified example of an embodiment of the present disclosure; FIG. 5 is a cross-sectional view of a HEMT device 10 according to a second modified example of an embodiment of the present disclosure; FIG. 6 is a cross-sectional view for explaining a method for manufacturing a HEMT device 10 according to an embodiment of the present disclosure; and FIG. 7 is an explanatory view for explaining an application example of a HEMT device 10 according to an embodiment of the present disclosure.

[0009] Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted. Furthermore, in this specification and the drawings, multiple components having substantially the same or similar functional configurations may be distinguished by adding different letters after the same reference numeral. However, when there is no particular need to distinguish between multiple components having substantially the same or similar functional configurations, only the same reference numerals will be used.

[0010] The drawings referred to in the following description are for explaining and facilitating understanding of one embodiment of the present disclosure, and for the sake of clarity, the shapes, dimensions, ratios, etc. shown in the drawings may differ from the actual ones. Furthermore, the design of the devices shown in the drawings can be modified as appropriate, taking into consideration the following description and known technologies.

[0011] The description will be given in the following order: 1. Background 2. Embodiment 2.1 Detailed structure 2.2 Modified example 2.3 Manufacturing method 3. Summary 4. Application example 5. Supplementary information

[0012] <<1. Background>> First, the background that led the inventors to create the embodiments of the present disclosure will be described with reference to Figures 1 and 2. Figures 1 and 2 are cross-sectional views of HEMT devices 10a and 10b according to comparative examples, and the lower part of each figure shows an enlarged view of a main portion of the HEMT devices 10a and 10b shown in the upper part of each figure. Note that the comparative examples refer to the HEMT devices 10a and 10b that the inventors had studied extensively before creating the embodiments of the present disclosure.

[0013] GaN, a wide-gap semiconductor material, has characteristics such as a high breakdown voltage, high-temperature operation, and a high saturated drift velocity. Furthermore, the two-dimensional electron gas (2DEG) layer generated at a GaN-based heterojunction has high mobility and a high sheet electron density. Due to these characteristics, a GaN HEMT, which is one type of GaN-based heterojunction FET, is capable of low resistance, high-speed, and high-voltage operation, and is therefore expected to be applied to RF devices such as power devices and switches in 5G high-speed communication systems. In particular, GaN HEMTs are expected to be applied to power amplifiers (hereinafter referred to as PAs) in which characteristics such as power density, power-added efficiency, and output power (Pout) are important in the millimeter-wave band, where spatial attenuation is large.

[0014] The 2DEG layer is a layer in which electrons are distributed two-dimensionally. Specifically, polarization within the crystal, which is one of the characteristics of Group III nitrides, results in a sheet-like electron distribution at the heterojunction interface. This sheet-like layer resulting from electron distribution is called the 2DEG layer, and the 2DEG layer functions as a channel for the HEMT device.

[0015] As shown in FIG. 1 , the HEMT device 10a according to the comparative example is, for example, a device having a Schottky gate structure. Specifically, as shown in FIG. 1 , the HEMT device 10a according to the comparative example 1 includes a compound semiconductor layer 110 stacked on a semiconductor substrate 100. The compound semiconductor layer 110 is a stack of multiple layers including a heterojunction, and includes a 2DEG layer that functions as a channel. The HEMT device 10a also includes an insulating layer 130 stacked on the compound semiconductor layer 110. In the HEMT device 10a, an opening 130a is provided in the insulating layer 130, and a gate electrode 150 is provided on the insulating layer 130 so as to contact the compound semiconductor layer 110 via a Schottky metal film 152 in the opening 130a. The Schottky metal film 152 can form a Schottky junction with the compound semiconductor layer 110.

[0016] In such a HEMT device 10a, a gold (Au) film is typically used as the gate electrode 150, and a nickel (Ni) film is typically used as the Schottky metal film 152. During the manufacture of the HEMT device 10a, annealing causes gold to diffuse from the gate electrode 150 into the Schottky metal film 152. In the comparative example, as shown in the enlarged view of a main portion in FIG. 1 , the Schottky metal film 152 is provided to cover the side surface of the opening 130a, and therefore, there may be areas (low-quality regions) on the side surface where the Schottky metal film 152 has poor coverage. In such areas, for example, voids 160 are formed, and Au further diffuses into the compound semiconductor layer 110 through the voids 160. As a result, in the comparative example, Au diffused from the gate electrode 150 segregates on the surface of the compound semiconductor layer 110, resulting in an increase in off-leakage current of the HEMT device 10a and a fluctuation in the threshold voltage (Vth) during device operation.

[0017] Therefore, in order to prevent such Au diffusion, a comparative example HEMT device 10b structure as shown in FIG. 2 was investigated. As shown in FIG. 2, the comparative example HEMT device 10b includes a compound semiconductor layer 110 stacked on a semiconductor substrate 100 and an insulating layer 130 stacked on the compound semiconductor layer 110. Furthermore, in the HEMT device 10b, an opening 130a is provided in the insulating layer 130, and within the opening 130a, not only a Schottky metal film 152 but also a barrier metal film 154 is provided to prevent the diffusion of metal (e.g., Au) from the gate electrode 150. In the HEMT device 10b, the gate electrode 150 is also provided on the insulating layer 130 so as to be in contact with the compound semiconductor layer 110 via the Schottky metal film 152 and the barrier metal film 154 within the opening 130a. The barrier metal film 154 is made of, for example, platinum (Pt) or palladium (Pd). That is, in the HEMT device 10 b according to the comparative example shown in FIG. 2, a barrier metal film 154 is provided at the lower end of the gate electrode 150 to suppress diffusion of Au from the gate electrode 150 .

[0018] However, even in the comparative example of FIG. 2 , as shown in the enlarged view of a main portion of the comparative example of FIG. 2 , the Schottky metal film 152 and the barrier metal film 154 are provided to cover the side surfaces of the opening 130 a. Therefore, the side surfaces may have portions (low-film-quality regions) where the coverage of the Schottky metal film 152 and the barrier metal film 154 is poor. Therefore, even in the comparative example of FIG. 2 , Au diffuses from the gate electrode 150 through voids 160 and the like generated in the portions with poor coverage, and segregates onto the surface of the compound semiconductor layer 110. As a result, even in the comparative example of FIG. 2 , this leads to an increase in off-leakage current of the HEMT device 10 b and a fluctuation in the threshold voltage (Vth) during device operation.

[0019] In order to prevent the above-described poor coverage, it is possible to form the opening 130a so that the area of ​​the opening 130a increases (expands) upward. This facilitates film deposition within the opening 130a, improving the coverage of the Schottky metal film 152 and the barrier metal film 154. However, in the miniaturized HEMT devices 10a and 10b, forming such an opening 130a involves an increase in the width of the opening 130a, which may limit design margins and make stable mass production difficult.

[0020] In view of the above-described circumstances, the present inventors have conceived the following embodiments of the present disclosure. Specifically, if the Schottky metal film 152 and the barrier metal film 154 are formed as flat layers extending over the compound semiconductor layer 110 rather than along the sidewall of the opening 130a, their coverage can be easily improved. Furthermore, if the Schottky metal film 152 and the barrier metal film 154 are formed as films that do not have areas with poor coverage (low-quality regions) that include voids 160, diffusion from the gate electrode 150 to the surface of the compound semiconductor layer 110 can be suppressed. Based on this idea, the present inventors have conceived the HEMT device 10 of forming the Schottky metal film 152 and the barrier metal film 154 as flat layers extending over the compound semiconductor layer 110 located below the opening 130a. According to such an embodiment of the present disclosure, it is possible to prevent metal (e.g., Au) from diffusing from the gate electrode 150 to the surface of the compound semiconductor layer 110, thereby preventing an increase in off-leakage and fluctuations in the threshold voltage (Vth) during device operation. Hereinafter, details of the embodiment of the present disclosure created by the present inventors will be sequentially described.

[0021] <<2. Embodiment>> <2.1 Detailed Structure> First, a detailed structure of a HEMT device (semiconductor device) 10 according to an embodiment of the present disclosure will be described with reference to Fig. 3. Fig. 3 is a cross-sectional view of the structure of the HEMT device 10 according to this embodiment, and more specifically, corresponds to a cross section of the HEMT device 10 cut along the stacking direction (cross-sectional view). The lower part of Fig. 3 shows an enlarged view of a main part of the HEMT device 10 shown in the upper part of Fig. 3.

[0022] As shown in FIG. 3 , the HEMT device 10 according to this embodiment includes a compound semiconductor layer 110 stacked on a semiconductor substrate 100 and an insulating layer 130 having an opening 130a stacked on the compound semiconductor layer 110. In this embodiment, a Schottky metal film (first metal layer) 152 that forms a Schottky junction with the compound semiconductor layer 110 and a barrier metal film (second metal layer) 154 that suppresses metal diffusion from the gate electrode 150 are stacked in a region on the compound semiconductor layer 110 below the opening 130a. In this embodiment, the Schottky metal film 152 and the barrier metal film 154 are flat layers that extend over the compound semiconductor layer 110. Furthermore, in this embodiment, an adhesion film (third metal layer) 156 is provided so as to cover the sidewall of the opening 130a, the periphery of the opening 130a on the top surface of the insulating layer 130, and a portion of the top surface of the barrier metal film 154 exposed from the opening 130a. The adhesion film 156 has a function of adhering the gate electrode 150 to the barrier metal film 154. Also in this embodiment, the gate electrode 150 is provided on the insulating layer 130 so as to fill the opening 130a.

[0023] In this embodiment, the Schottky metal film 152 and the barrier metal film 154 are formed as flat layers extending over the compound semiconductor layer 110 located below the opening 130a, making it easy to form films with high coverage. Therefore, the barrier metal film 154 does not have any areas with poor coverage (low-quality regions) such as voids 160, or has few such areas, so that the entire film can suppress diffusion of metal (e.g., Au) from the gate electrode 150. In addition, because the barrier metal film 154 is stacked as a flat layer on the Schottky metal film 152, it also has high coverage with the Schottky metal film 152, and can suppress diffusion of metal from the gate electrode 150 into the Schottky metal film 152. Furthermore, the Schottky metal film 152 does not have any areas with poor coverage (low-quality regions) such as voids 160, or has few such areas, so that diffusion of metal from the gate electrode 150 can be suppressed. Therefore, according to this embodiment, the Schottky metal film 152 and the barrier metal film 154 suppress the diffusion of metal from the gate electrode 150 to the surface of the compound semiconductor layer 110, thereby making it possible to avoid an increase in off-leakage and fluctuations in the threshold voltage (Vth) during device operation.

[0024] Furthermore, in this embodiment, the Schottky metal film 152 and the barrier metal film 154 are provided so as to cover a portion of the upper surface of the compound semiconductor layer 110 located below the opening 130a. Therefore, according to this embodiment, damage to the compound semiconductor layer 110 due to etching can be suppressed when the opening 130a is formed. Details of this will be described later.

[0025] Furthermore, in this embodiment, by providing the adhesion film 156, the gate electrode 150 and the barrier metal film 154 can be more closely adhered to each other, and therefore the barrier metal film 154 can better suppress the diffusion of metal from the gate electrode 150.

[0026] More specifically, as shown in the enlarged view of Fig. 3 , in this embodiment, it is preferable that the length Lb of the barrier metal film 154 in the plane of the compound semiconductor layer 110 be longer than the width d of the opening 130a. Furthermore, in the example shown in Fig. 3 , the length Lb of the barrier metal film 154 and the length Ls of the Schottky metal film 152 in the plane of the compound semiconductor layer 110 are the same. Therefore, in the example of Fig. 3 , the length Ls of the Schottky metal film 152 in the plane of the compound semiconductor layer 110 is longer than the width d of the opening 130a. Furthermore, in this embodiment, it is preferable that the film thicknesses of the Schottky metal film 152 and the barrier metal film 154 be approximately several tens of nanometers.

[0027] In this embodiment, by making the length Lb of the barrier metal film 154 in the plane of the compound semiconductor layer 110 longer than the width d of the opening 130a, the diffusion of metal Au from the gate electrode 150 embedded in the opening 130a can be effectively suppressed.

[0028] Furthermore, in this embodiment, in a cross section (cross-sectional view) of the HEMT device 10 cut along the stacking direction, the opening 130a preferably has a tapered shape such that the opening widens (expands in diameter) toward the upper surface of the insulating layer 130. In this embodiment, by forming the opening 130a in this shape, the coverage of the adhesion film 156 is improved. As a result, according to this embodiment, the gate electrode 150 and the barrier metal film 154 can be more reliably adhered to each other.

[0029] In this embodiment, the compound semiconductor layer 110 mainly includes, for example, a buffer layer provided on the semiconductor substrate 100, a channel layer (first compound semiconductor layer) that forms a 2DEG layer provided on the buffer layer, and a barrier layer (second compound semiconductor layer) that is provided on the channel layer and forms a heterojunction with the channel layer. That is, the barrier layer is made of a compound semiconductor different from that of the channel layer. In this embodiment, although not shown, a source and a drain are provided on either side of the gate electrode 150, sandwiching the stack of the compound semiconductor layer 110 and the insulating layer 130.

[0030] Furthermore, the details of each layer of the HEMT device 10 according to this embodiment will be explained in order.

[0031] The semiconductor substrate 100 is made of a semiconductor material and can be formed from, for example, a ternary or quaternary compound semiconductor material such as a III-V group compound semiconductor material. More specifically, it is made of, for example, a semi-insulating single-crystal GaN substrate. In this embodiment, the semiconductor substrate 100 may be a substrate whose lattice constant is different from that of the channel layer by controlling the lattice constant with a buffer layer, which will be described later. Specifically, silicon carbide (SiC), sapphire, silicon (Si) substrates, etc. can be used as the semiconductor substrate 100. The use of a Si substrate has the advantage that it is inexpensive and can be large-diameter.

[0032] As described above, the compound semiconductor layer 110 includes, for example, a buffer layer stacked on the semiconductor substrate 100, a channel layer forming a 2DEG layer on the buffer layer, and a barrier layer heterojunctioned on the channel layer. Each layer of the compound semiconductor layer 110 will be described in detail below.

[0033] The buffer layer is composed of, for example, a compound semiconductor epitaxially grown on the semiconductor substrate 100. When the lattice constants of the semiconductor substrate 100 and the channel layer are different, controlling the lattice constant with the buffer layer improves the crystalline state of the channel layer and can control warpage of the entire compound semiconductor layer. For example, when the semiconductor substrate 100 is made of single-crystal silicon and the channel layer is made of GaN, the buffer layer can be made of, for example, aluminum nitride (AlN), AlGaN, GaN, or the like. Furthermore, the buffer layer does not necessarily have to be a single layer, but may be a stack of different layers. Furthermore, when the buffer layer is made of a ternary or quaternary compound semiconductor, the buffer layer may have a composition that gradually changes along its thickness.

[0034] The channel layer is a region where carriers accumulate due to polarization with the barrier layer, which will be described later. Such a channel layer is made of a compound semiconductor in which carriers are likely to accumulate due to polarization. The channel layer is made of, for example, a group III nitride containing at least one of indium (In), gallium (Ga), and aluminum (Al). An example of the channel layer is a GaN epitaxially grown layer. The channel layer may also be a u (undoped)-GaN layer to which no impurities are added. This suppresses impurity scattering of carriers in the channel layer, enabling carrier movement with high mobility.

[0035] The barrier layer is formed using a compound semiconductor in which polarization with the channel layer generates two-dimensional electron (2DEG) gas in the channel layer (heterojunction interface), accumulating carriers. Such a barrier layer may be made of, for example, a Group III nitride containing at least one of indium (In), gallium (Ga), and aluminum (Al). Specifically, an epitaxially grown layer of Al1-x-yGaxInyN (0≦x<1, 0≦y<1) may be used. The barrier layer may also be u-Al1-x-yGaxInyN, which does not contain any impurities. This suppresses impurity scattering of carriers in the channel layer, enabling high-mobility carrier movement. The barrier layer does not necessarily have to be a single layer, but may be a stack of different layers, such as an Al1-x-yGaxInyN layer with different compositions. Alternatively, the barrier layer may have a composition that gradually changes along its thickness.

[0036] In this embodiment, a cap film (not shown) may be provided on the upper surface of the barrier layer to protect the barrier layer from oxidation and thermal processes. The cap film may be made of, for example, GaN or silicon nitride (Si ３ N ４ ) and is made of a nitride film containing at least one of gallium, indium, aluminum, and silicon.

[0037] In this embodiment, a back barrier layer may be provided between the channel layer and the buffer layer. The back barrier layer is made of a semiconductor having a wider energy gap than the channel layer. Examples of the back barrier layer include an epitaxially grown layer of Al1-x-yGaxInyN (0≦x<1, 0≦y<1) or u-Al1-x-yGaxInyN. The back barrier layer does not necessarily have to be a single layer, but may be a stack of different layers, for example, an Al1-x-yGaxInyN layer having different compositions. Alternatively, the back barrier layer may have a composition that gradually changes along the thickness of the layer.

[0038] In this embodiment, a spacer layer may be provided between the barrier layer and the channel layer. The spacer layer may be made of, for example, a compound semiconductor material having a larger polarization than the barrier layer, and may improve the mobility of electrons in the 2DEG formed in the channel layer. For example, when the barrier layer and the channel layer are the above-mentioned AlGaInN / GaN combination, the spacer layer may be made of, for example, AlN. Alternatively, the spacer layer may be made of InGaN, AlGaN, or the like.

[0039] Furthermore, it is preferable that the insulating layer 130 has insulating properties relative to the barrier layer and has the property of not deteriorating the device characteristics by forming a good interface with the barrier layer. Specifically, the insulating layer 130 is, for example, a single layer film or a multilayer film made of an oxide or a nitride. In more detail, the insulating layer 130 is, for example, a film made of aluminum oxide (Al ２ O ３ ), hafnium oxide (HfO ２ ), silicon oxide (SiO ２ ), silicon nitride (Si ３ N ４ ) or the like, which contains at least one of Si, Al, and Hf.

[0040] The gate electrode 150 is, for example, a single-layer film or a multi-layer film containing gold (Au). More specifically, the gate electrode 150 may be, for example, a multi-layer film in which nickel (Ni) and gold (Au) are stacked. Furthermore, in order to reduce gate impedance, the gate electrode 150 is generally formed in a T-gate shape.

[0041] The Schottky metal film 152 is a film that forms a Schottky junction with the compound semiconductor layer 110, and is formed of, for example, a single layer film or a multilayer film containing nickel (Ni).

[0042] The barrier metal film 154 is a film that prevents diffusion of a metal (e.g., Au) from the gate electrode 150. In detail, the barrier metal film 154 is formed of a single layer film or a multilayer film that includes at least one of titanium (Ti), palladium (Pd), platinum (Pt), molybdenum (Mo), tungsten (W), and chromium (Cr).

[0043] The adhesion film 156 is a film that functions to adhere the gate electrode 150 and the barrier metal film 154. The adhesion film 156 is formed of a single layer film or a multilayer film containing at least one of chromium (Cr), titanium (Ti), molybdenum (Mo), nickel (Ni), palladium (Pd), and platinum (Pt), for example.

[0044] As described above, in this embodiment, the Schottky metal film 152 and the barrier metal film 154 are formed as flat layers extending over the compound semiconductor layer 110 located below the opening 130 a, which facilitates the formation of films with high coverage. Therefore, in this embodiment, the Schottky metal film 152 and the barrier metal film 154 do not have any areas with poor coverage (low-quality regions) that include voids 160, or have few such areas. Therefore, according to this embodiment, the Schottky metal film 152 and the barrier metal film 154 suppress the diffusion of metal (e.g., Au) from the gate electrode 150 to the surface of the compound semiconductor layer 110, thereby preventing an increase in off-leakage current and a fluctuation in the threshold voltage (Vth) during device operation.

[0045] Furthermore, by applying the HEMT device 10 with reduced off-leakage according to this embodiment to wireless communication devices (e.g., mobile base stations, mobile terminals, etc.) as described below, it is possible to achieve high efficiency and low power consumption.

[0046] 3, the structure of the HEMT device 10 can be modified into various structures as described below. For example, in this embodiment, the adhesion film 156 may not be provided, or the top surface of the gate electrode 150 may be flat without any recesses.

[0047] 2.2 Modifications Next, the HEMT device 10 according to each modification of the embodiment of the present disclosure will be described with reference to Fig. 4 and Fig. 5. Fig. 4 and Fig. 5 are cross-sectional views of the HEMT device 10 according to each modification of the embodiment, and more specifically, correspond to a cross section of the HEMT device 10 cut along the stacking direction (cross-sectional view). The lower part of each figure shows an enlarged view of a main part of the HEMT device 10 shown in the upper part of each figure.

[0048] (Variation 1) In Variation 1, as in the present embodiment, as shown in FIG. 4 , the length Lb of the barrier metal film 154 in the plane of the compound semiconductor layer 110 is longer than the width d of the opening 130a. In Variation 1, by making the length Lb of the barrier metal film 154 longer than the width d of the opening 130a, diffusion of metal (e.g., Au) from the gate electrode 150 embedded in the opening 130a can be effectively suppressed. However, in Variation 1, unlike the present embodiment, the length Lb of the barrier metal film 154 in the plane of the compound semiconductor layer 110 is longer than the length Ls of the Schottky metal film 152. In other words, the length Ls of the Schottky metal film 152 is shorter than the length Lb of the barrier metal film 154. In Variation 1, the Schottky metal film 152 and the barrier metal film 154 are formed as flat layers extending over the compound semiconductor layer 110 below the opening 130a, and therefore can be easily formed as films with high coverage. Therefore, also in the present modification 1, the Schottky metal film 152 and the barrier metal film 154 do not have any areas (low-film-quality regions) with poor coverage such as those containing voids 160, or have few such areas with poor coverage. Therefore, according to the present modification 1, the Schottky metal film 152 and the barrier metal film 154 suppress the diffusion of metal from the gate electrode 150 to the surface of the compound semiconductor layer 110, thereby making it possible to avoid an increase in off-leakage and fluctuations in the threshold voltage (Vth) during device operation.

[0049] (Variation 2) In Variation 2, as in the present embodiment, as shown in FIG. 5 , the length Lb of the barrier metal film 154 in the plane of the compound semiconductor layer 110 is longer than the width d of the opening 130a. Similarly to Variation 1, by making the length Lb of the barrier metal film 154 longer than the width d of the opening 130a, it is possible to suppress diffusion of metal (e.g., Au) from the gate electrode 150 embedded in the opening 130a to the surface of the compound semiconductor layer 110. However, in Variation 2, unlike the present embodiment, the length Lb of the barrier metal film 154 in the plane of the compound semiconductor layer 110 is shorter than the length Ls of the Schottky metal film 152. In other words, the length Ls of the Schottky metal film 152 is longer than the length Lb of the barrier metal film 154. Also in Variation 2, the Schottky metal film 152 and the barrier metal film 154 are formed as flat layers extending over the compound semiconductor layer 110 below the opening 130a, and therefore can be easily formed as films with high coverage. Therefore, also in the present modification 2, the Schottky metal film 152 and the barrier metal film 154 do not have any areas (low-film-quality regions) with poor coverage such as those containing voids 160, or have few such areas with poor coverage. Therefore, according to the present modification 2, the Schottky metal film 152 and the barrier metal film 154 suppress the diffusion of metal from the gate electrode 150 to the surface of the compound semiconductor layer 110, thereby making it possible to avoid an increase in off-leakage and fluctuations in the threshold voltage (Vth) during device operation.

[0050] In the modified example of the present disclosure, the HEMT device 10 is not limited to the forms shown in FIGS. 4 and 5, and can be further modified into various forms.

[0051] 2.3 Manufacturing Method Next, a method for manufacturing the HEMT device 10 according to this embodiment will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view illustrating the method for manufacturing the HEMT device according to this embodiment, and more specifically, is a cross-sectional view at each manufacturing stage corresponding to Fig. 3.

[0052] First, as shown on the left side of FIG. 6 , a compound semiconductor layer 110 is stacked on a semiconductor substrate 100. Furthermore, a Schottky metal film 152 and a barrier metal film 154 are sequentially stacked on the compound semiconductor layer 110 in a region where the gate electrode 150 is to be formed, i.e., a region where the opening 130 a in the insulating layer 130 is to be formed. At this time, in order to stack the Schottky metal film 152 and the barrier metal film 154 on the compound semiconductor layer 110 in the region where the opening 130 a is to be formed, for example, existing film formation techniques, mask formation techniques, etching techniques such as wet etching, etc. can be used. In this embodiment, the Schottky metal film 152 and the barrier metal film 154 are formed as a stack of flat films extending on the compound semiconductor layer 110, and therefore can be easily formed as films with high coverage.

[0053] Next, as shown in the second from the left in FIG. 6 , an insulating layer 130 is stacked on the compound semiconductor layer 110 and the barrier metal film 154 using an existing film formation technique such as a CVD (Chemical Vapor Deposition) method or an ALD (Atomic Layer Deposition) method.

[0054] 6 , the insulating layer 130 is etched by, for example, reactive ion etching (RIE) or the like until a portion of the upper surface of the barrier metal film 154 is exposed, thereby forming an opening 130a. In this embodiment, the Schottky metal film 152 and the barrier metal film 154 that cover a portion of the upper surface of the compound semiconductor layer 110 can suppress damage to the compound semiconductor layer 110 due to etching.

[0055] Next, a lift-off resist or the like is formed and patterned, and then an adhesion film 156 and a gate electrode 150 are formed according to the pattern provided in the resist, and the lift-off resist and excess metal are removed by a lift-off process. In this way, the HEMT device 10 according to this embodiment can be fabricated, as shown on the right side of FIG.

[0056] In this manner, the HEMT device 10 according to this embodiment can be fabricated. As described above, in this embodiment, the HEMT device 10 according to this embodiment can be fabricated without significantly changing the conventional manufacturing process.

[0057] <<3. Summary>> As described above, in the embodiment of the present disclosure, the Schottky metal film 152 and the barrier metal film 154 are formed as flat layers extending over the compound semiconductor layer 110 located below the opening 130a, which facilitates the formation of films with high coverage. Therefore, in this embodiment, the Schottky metal film 152 and the barrier metal film 154 do not have any areas with poor coverage (low-quality regions) that include the voids 160, or have few such areas. Therefore, according to this embodiment, the Schottky metal film 152 and the barrier metal film 154 suppress diffusion of metal (e.g., Au) from the gate electrode 150 to the surface of the compound semiconductor layer 110, thereby preventing an increase in off-leakage current and a fluctuation in the threshold voltage (Vth) during device operation.

[0058] Although the HEMT device 10 according to each embodiment of the present disclosure is a GaN-based compound semiconductor, the present disclosure is not limited to this and may be, for example, a compound semiconductor such as GaAs, or a semiconductor using a Si substrate, etc.

[0059] Furthermore, the materials, film thicknesses, film formation methods, and film formation conditions of each layer in the above-described embodiments are not limited to those described above and can be changed as appropriate. That is, in this embodiment, the semiconductor device can be manufactured using techniques, devices, and conditions that are commonly used in the manufacture of semiconductor devices.

[0060] Examples of the above-mentioned techniques include physical vapor deposition (PVD), CVD, and ALD. Examples of PVD include vacuum deposition, electron beam (EB) deposition, various sputtering methods (magnetron sputtering, RF (radio frequency)-direct current (DC) combined bias sputtering, electron cyclotron resonance (ECR) sputtering, facing target sputtering, and high frequency sputtering), ion plating, laser ablation, molecular beam epitaxy (MBE), and laser transfer. Examples of CVD methods include plasma CVD, thermal CVD, metal organic (MO) CVD, and photo-CVD. Other methods include electroplating, electroless plating, spin coating, dipping, casting, microcontact printing, drop casting, various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing, stamping, spraying, and various coating methods such as air doctor coater, blade coater, rod coater, knife coater, squeeze coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, cast coater, spray coater, slit orifice coater, and calendar coater. Examples of patterning methods include shadow masking, laser transfer, chemical etching such as electron beam lithography and photolithography, and physical etching using ultraviolet light or laser. Additionally, examples of planarization techniques include CMP (Chemical Mechanical Polishing), laser planarization, and reflow.

[0061] <<4. Application Examples>> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be applied to a communication device. Therefore, as an example of application of the technology according to the present disclosure, a wireless communication device (communication device) 500 will be described with reference to FIG. 7 . FIG. 7 is an explanatory diagram illustrating an application example of the HEMT device 10 according to each embodiment of the present disclosure.

[0062] The wireless communication device 500 shown in FIG. 7 is a mobile phone system having multiple functions, such as voice and data communication and LAN (Local Area Network) connection. For example, the wireless communication device 500 includes an antenna (ANT) 510, an antenna switch circuit 520, a high-frequency integrated circuit (RF IC) 530, a baseband unit 540, a high-power amplifier (HPA) 550, and an output unit 560 including an audio output unit (MIC), a data output unit (DT), and an interface (IF) unit. The interface (IF) unit can connect to devices that perform wireless communication, such as wireless LAN and Bluetooth (registered trademark). The high-frequency integrated circuit (RF IC) 530 and the baseband unit 540 are connected via an internal bus.

[0063] During transmission, a transmission signal output from the baseband unit 540 is output to the antenna 510 via the radio frequency integrated circuit RF IC 530, the high power amplifier 550, and the antenna switch circuit 520. During reception, a reception signal received by the antenna 510 is input to the baseband unit 540 via the antenna switch circuit 520 and the radio frequency integrated circuit RF IC 530. The baseband unit 540 processes the input signal and outputs it from the output unit 560 to an external device or the like.

[0064] For example, the technology of the present disclosure can be applied to an antenna switch circuit 520, a radio frequency integrated circuit (RF IC) 530, a high power amplifier 550, and the like. The effects of the technology of the present disclosure are particularly pronounced in wireless communication devices whose communication frequencies are in the UHF (Ultra High Frequency) band or higher. That is, by using a HEMT device 10 according to an embodiment of the present disclosure, in which off-leakage is reduced, as an antenna switch circuit 520, a radio frequency integrated circuit (RF IC) 530, a high power amplifier 550, and the like, it is possible to achieve high efficiency and low power consumption in the wireless communication device 500. In particular, when the wireless communication device 500 is applied to a mobile communication terminal, the high efficiency and low power consumption can extend battery life and improve portability.

[0065] The above describes an example configuration of the wireless communication device 500. Each of the above components may be configured using general-purpose components, or may be configured using hardware specialized for the function of each component. Such a configuration may be changed as appropriate depending on the technical level at the time of implementation.

[0066] <<5. Supplementary Information>> Although preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person skilled in the art of the present disclosure can conceive of various modified or altered examples within the scope of the technical idea described in the claims, and it is understood that these also naturally fall within the technical scope of the present disclosure.

[0067] Furthermore, the effects described herein are merely descriptive or exemplary and are not limiting. In other words, the technology according to the present disclosure may achieve other effects that will be apparent to those skilled in the art from the description of this specification, in addition to or in place of the above-described effects.

[0068] The present technology can also be configured as follows: (1) A semiconductor device comprising: a compound semiconductor layer; an insulating layer stacked on the compound semiconductor layer; and a gate electrode stacked on the insulating layer so as to fill an opening provided in the insulating layer, wherein a first metal layer forming a Schottky junction with the compound semiconductor layer and a second metal layer suppressing metal diffusion from the gate electrode are stacked on the compound semiconductor layer located below the opening. (2) The semiconductor device according to (1), wherein the length of the second metal layer in the plane of the compound semiconductor layer is longer than the width of the opening. (3) The semiconductor device according to (2), wherein the lengths of the first and second metal layers are the same. (4) The semiconductor device according to (2), wherein the length of the first metal layer is shorter than the length of the second metal layer. (5) The semiconductor device according to (2), wherein the length of the first metal layer is longer than the length of the second metal layer. (6) The semiconductor device according to any one of (1) to (5), wherein the first and second metal layers are flat layers extending over the compound semiconductor layer. (7) The semiconductor device according to any one of (1) to (6), further comprising a third metal layer covering the periphery of the opening on the upper surface of the insulating layer and the side surfaces of the opening, thereby adhering the gate electrode to the insulating layer. (8) The semiconductor device according to any one of (1) to (7), wherein the first metal layer is a single-layer film or a multi-layer film containing nickel. (9) The semiconductor device according to any one of (1) to (8), wherein the second metal layer is a single-layer film or a multi-layer film containing at least one of titanium, palladium, platinum, molybdenum, tungsten, and chromium. (10) The semiconductor device according to (7), wherein the third metal layer is a single-layer film or a multi-layer film containing at least one of chromium, titanium, molybdenum, nickel, palladium, and platinum. (11) The semiconductor device according to any one of (1) to (10) above, wherein the gate electrode is a single layer film or a multilayer film containing gold. (12) The semiconductor device according to any one of (1) to (11) above, wherein the insulating layer is a single layer film or a multilayer film.(13) The semiconductor device according to (12) above, wherein the insulating layer includes an oxide film or a nitride film containing at least one of silicon, aluminum, and hafnium. (14) The semiconductor device according to any one of (1) to (13) above, wherein, in a cross section of the semiconductor device cut along the stacking direction, the opening has a tapered shape widening toward an upper surface of the insulating layer. (15) The semiconductor device according to any one of (1) to (14) above, wherein the compound semiconductor layer includes: a first compound semiconductor layer; and a second compound semiconductor layer stacked on the first compound semiconductor layer and made of a compound semiconductor different from that of the first compound semiconductor layer. (16) The semiconductor device according to (15) above, wherein the first and second compound semiconductor layers are made of a Group III nitride containing at least one of gallium, indium, and aluminum. (17) The semiconductor device according to (15) or (16), wherein the compound semiconductor layer further has a cap film laminated on the second compound semiconductor layer, and the cap film is made of a nitride film containing at least one of gallium, indium, aluminum, and silicon. (18) A communication device equipped with a semiconductor device, wherein the semiconductor device comprises: a compound semiconductor layer, an insulating layer laminated on the compound semiconductor layer, and a gate electrode laminated on the insulating layer so as to fill an opening provided in the insulating layer, and a first metal layer forming a Schottky junction with the compound semiconductor layer and a second metal layer suppressing diffusion of metal from the gate electrode are laminated on the compound semiconductor layer located below the opening.

[0069] 10, 10a, 10b HEMT device 100 Semiconductor substrate 110 Compound semiconductor layer 130 Insulating layer 130a Opening 150 Gate electrode 152 Schottky metal film 154 Barrier metal film 156 Adhesion film 160 Void 500 Wireless communication device 510 Antenna 520 Antenna switch circuit 530 RF IC 540 Baseband section 550 High power amplifier 560 Output section

Claims

1. A semiconductor device comprising: a compound semiconductor layer; an insulating layer laminated on the compound semiconductor layer; and a gate electrode laminated on the insulating layer so as to fill an opening provided in the insulating layer, wherein a first metal layer that forms a Schottky junction with the compound semiconductor layer and a second metal layer that suppresses metal diffusion from the gate electrode are laminated on the compound semiconductor layer located below the opening.

2. The semiconductor device according to claim 1, wherein the length of said second metal layer in the plane of said compound semiconductor layer is longer than the width of said opening.

3. The semiconductor device according to claim 2, wherein the lengths of said first and second metal layers are the same.

4. The semiconductor device according to claim 2, wherein the length of said first metal layer is shorter than the length of said second metal layer.

5. The semiconductor device according to claim 2, wherein the length of said first metal layer is longer than the length of said second metal layer.

6. The semiconductor device according to claim 1, wherein said first and second metal layers are planar layers extending over said compound semiconductor layer.

7. The semiconductor device according to claim 1, further comprising a third metal layer covering the periphery of the opening on the top surface of the insulating layer and the side surfaces of the opening, thereby adhering the gate electrode to the insulating layer.

8. The semiconductor device according to claim 1, wherein the first metal layer is a single-layer film or a multi-layer film containing nickel.

9. The semiconductor device according to claim 1, wherein the second metal layer is a single layer or a multilayer film containing at least one of titanium, palladium, platinum, molybdenum, tungsten, and chromium.

10. The semiconductor device according to claim 7, wherein the third metal layer is a single layer or a multilayer film containing at least one of chromium, titanium, molybdenum, nickel, palladium, and platinum.

11. The semiconductor device according to claim 1, wherein the gate electrode is a single-layer film or a multi-layer film containing gold.

12. The semiconductor device according to claim 1, wherein the insulating layer is a single-layer film or a multi-layer film.

13. The semiconductor device according to claim 12, wherein the insulating layer includes an oxide film or a nitride film containing at least one of silicon, aluminum, and hafnium.

14. The semiconductor device according to claim 1, wherein, in a cross section of the semiconductor device cut along the stacking direction, the opening has a tapered shape widening toward the upper surface of the insulating layer.

15. The semiconductor device according to claim 1, wherein the compound semiconductor layer comprises: a first compound semiconductor layer; and a second compound semiconductor layer stacked on the first compound semiconductor layer and made of a compound semiconductor different from that of the first compound semiconductor layer.

16. The semiconductor device according to claim 15, wherein the first and second compound semiconductor layers are made of a Group III nitride containing at least one of gallium, indium, and aluminum.

17. The semiconductor device according to claim 15, wherein the compound semiconductor layer further has a cap film stacked on the second compound semiconductor layer, and the cap film is made of a nitride film containing at least one of gallium, indium, aluminum, and silicon.

18. A communication device equipped with a semiconductor device, the semiconductor device comprising: a compound semiconductor layer; an insulating layer laminated on the compound semiconductor layer; and a gate electrode laminated on the insulating layer so as to fill an opening provided in the insulating layer, and a first metal layer forming a Schottky junction with the compound semiconductor layer and a second metal layer suppressing diffusion of metal from the gate electrode are laminated on the compound semiconductor layer located below the opening.

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