Semiconductor device, method for manufacturing semiconductor device, and communication device

Abstract

The present invention provides a semiconductor device which has a layered structure comprising a first compound semiconductor layer, a second compound semiconductor layer that is superposed on the first compound semiconductor layer and is formed of a compound semiconductor which is different from that of the first compound semiconductor layer, an insulating layer that is superposed on the second compound semiconductor layer, and a gate electrode that is superposed on the insulating layer and is in contact with the second compound semiconductor layer through an opening provided in the insulating layer. In a cross-section obtained by cutting the semiconductor device along the stacking direction, the wall surface of the opening has two or more level differences.

Description

Semiconductor device, semiconductor device manufacturing method, and communication device

[0001] The present disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, and a communication device.

[0002] HEMT (High Electron Mobility Transistor) devices, which are heterogeneous field-effect transistors (FETs) made of gallium nitride (GaN)-based wide-gap semiconductor materials, are capable of low resistance, high-speed, and high-voltage operation, and are therefore expected to be applied to RF (Radio Frequency) devices such as power devices and switches in 5G high-speed communication systems.

[0003] JP 2013-77620 A

[0004] In HEMT devices (semiconductor devices), large parasitic capacitance can occur in the gate electrode, making it difficult to improve the gain of the HEMT device. Various methods have been investigated to avoid the occurrence of large parasitic capacitance, but these methods require special equipment and film formation conditions, resulting in increased manufacturing costs and time. Furthermore, these methods also pose problems with the stability of the mass-production process.

[0005] Therefore, the present disclosure proposes a semiconductor device, a method for manufacturing a semiconductor device, and a communication device that can be mass-produced using a highly stable process while avoiding the generation of large parasitic capacitance and suppressing a significant increase in manufacturing costs and manufacturing time.

[0006] According to the present disclosure, there is provided a semiconductor device having a stacked structure including: a first compound semiconductor layer; a second compound semiconductor layer stacked on the first compound semiconductor layer and made of a compound semiconductor different from that of the first compound semiconductor layer; an insulating layer stacked on the second compound semiconductor layer; and a gate electrode stacked on the insulating layer and in contact with the second compound semiconductor layer through an opening provided in the insulating layer, wherein a wall surface of the opening has two or more steps in a cross section of the semiconductor device cut along the stacking direction.

[0007] Furthermore, according to the present disclosure, there is provided a method for manufacturing a semiconductor device, including: stacking a second compound semiconductor layer on a first compound semiconductor layer, the second compound semiconductor layer being made of a compound semiconductor different from that of the first compound semiconductor layer; stacking an insulating layer having an opening on the second compound semiconductor layer; and forming a gate electrode on the insulating layer so as to be in contact with the second compound semiconductor layer through the opening, wherein the opening is formed so that a wall surface of the opening has two or more steps in a cross section of the insulating layer cut along a film thickness direction.

[0008] Furthermore, according to the present disclosure, there is provided a communication device equipped with a semiconductor device, wherein the semiconductor device has a stacked structure including a first compound semiconductor layer, a second compound semiconductor layer stacked on the first compound semiconductor layer and made of a compound semiconductor different from the first compound semiconductor layer, an insulating layer stacked on the second compound semiconductor layer, and a gate electrode stacked on the insulating layer and in contact with the second compound semiconductor layer through an opening provided in the insulating layer, and in a cross section of the semiconductor device cut along the stacking direction, a wall surface of the opening has two or more steps.

[0009] FIG. 1 is a cross-sectional view of a HEMT device 10a according to a comparative example; FIG. 2 is a cross-sectional view of a HEMT device 10 according to an embodiment of the present disclosure; FIG. 3 is a cross-sectional view (part 1) for explaining a method for manufacturing the HEMT device 10 according to an embodiment of the present disclosure; FIG. 4 is a cross-sectional view (part 2) for explaining a method for manufacturing the HEMT device 10 according to an embodiment of the present disclosure; FIG. 5 is a cross-sectional view of a main part of a HEMT device 10 according to a first modification of an embodiment of the present disclosure; FIG. 6 is a cross-sectional view of a main part of a HEMT device 10 according to a second modification of an embodiment of the present disclosure; FIG. 7 is a cross-sectional view of a main part of a HEMT device 10 according to a third modification of an embodiment of the present disclosure; FIG. 8 is a cross-sectional view of a main part of a HEMT device 10 according to a fourth modification of an embodiment of the present disclosure; FIG. 9 is a cross-sectional view of a main part of a HEMT device 10 according to a fifth modification of an embodiment of the present disclosure; FIG. 10 is a cross-sectional view of a main part of a HEMT device 10 according to a sixth modification of an embodiment of the present disclosure; FIG. 11 is a cross-sectional view of a main part of a HEMT device 10 according to a seventh modification of an embodiment of the present disclosure; and FIG. 12 is an explanatory diagram for explaining an application example of the HEMT device 10 according to an embodiment of the present disclosure.

[0010] Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted. Furthermore, in this specification and the drawings, multiple components having substantially the same or similar functional configurations may be distinguished by adding different letters after the same reference numeral. However, when there is no particular need to distinguish between multiple components having substantially the same or similar functional configurations, only the same reference numerals will be used.

[0011] The drawings referred to in the following description are for explaining and facilitating understanding of one embodiment of the present disclosure, and for the sake of clarity, the shapes, dimensions, ratios, etc. shown in the drawings may differ from the actual ones. Furthermore, the design of the devices shown in the drawings can be modified as appropriate, taking into consideration the following description and known technologies.

[0012] The description will be given in the following order: 1. Background 2. Embodiment 2.1 Detailed structure 2.2 Manufacturing method 2.3 Modification 3. Summary 4. Application example 5. Supplementary information

[0013] <<1. Background>> First, the background that led the inventors to create the embodiments of the present disclosure will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view of a HEMT device 10a according to a comparative example. Note that the comparative example here refers to the HEMT device 10a that the inventors had studied extensively before creating the embodiments of the present disclosure.

[0014] GaN, a wide-gap semiconductor material, has characteristics such as a high breakdown voltage, high-temperature operation, and a high saturated drift velocity. Furthermore, the two-dimensional electron gas (2DEG) layer generated at a GaN-based heterojunction has high mobility and a high sheet electron density. Due to these characteristics, a GaN HEMT, which is one type of GaN-based heterojunction FET, is capable of low resistance, high-speed, and high-voltage operation, and is therefore expected to be applied to RF devices such as power devices and switches in 5G high-speed communication systems. In particular, GaN HEMTs are expected to be applied to power amplifiers (hereinafter referred to as PAs) in which characteristics such as power density, power-added efficiency, and output power (Pout) are important in the millimeter-wave band, where spatial attenuation is large.

[0015] The 2DEG layer is a layer in which electrons are distributed two-dimensionally. Specifically, polarization within the crystal, which is one of the characteristics of Group III nitrides, results in a sheet-like electron distribution at the heterojunction interface. This sheet-like layer resulting from electron distribution is called the 2DEG layer, and the 2DEG layer functions as a channel for the HEMT device.

[0016] Specifically, as shown in FIG. 1 , the HEMT device 10a according to the comparative example has a Schottky gate structure. Furthermore, as shown in FIG. 1 , in the HEMT device 10a according to the comparative example, a buffer layer 110 is stacked on a substrate 100, and a channel layer 112 forming a 2DEG layer 114 is stacked on the buffer layer 110. Furthermore, in the HEMT device 10a according to the comparative example, a barrier layer 120 is heterojunctioned on the channel layer 112 via a spacer layer 116. Furthermore, in the comparative example, an insulating layer 130 is stacked on the barrier layer 120, and a gate electrode 152 is stacked on the insulating layer 130, and the gate electrode 152 is in contact with the barrier layer 120 through an opening provided in the insulating layer 130. Furthermore, in the comparative example, a source 150 and a drain 154 are formed on either side of the stack of the channel layer 112, the spacer layer 116, the barrier layer 120, and the insulating layer 130.

[0017] When the gate electrode 152 is fabricated by a metal lift-off process, the gate electrode 152 may be formed to have a main body portion and a skirt-shaped peripheral portion 152a surrounding the main body portion, as shown in FIG. 1. The peripheral portion 152a extends over the insulating layer 130, causing large parasitic capacitance between the peripheral portion 152a and the source 150 (specifically, the 2DEG layer 114 on the source 150 side) and between the peripheral portion 152a and the drain 154 (specifically, the 2DEG layer 114 on the drain 154 side). Due to such large parasitic capacitance, it was difficult to improve the gain of the HEMT device 10a according to the comparative example.

[0018] Various means have been proposed to suppress the formation of such a tapered outer peripheral portion 152a, but these have required special equipment and film-forming conditions, which not only increase manufacturing costs and manufacturing time but also pose problems with the stability of the process during mass production, making them unrealistic means.

[0019] In view of these circumstances, the present inventors have come up with a HEMT device structure that avoids the generation of large parasitic capacitance between the outer peripheral portion 152 a of the gate electrode 152 and the source 150, and between the outer peripheral portion 152 a and the drain 154, while suppressing a significant increase in manufacturing cost and manufacturing time, and achieving high process stability during mass production. That is, the HEMT device 10 according to an embodiment of the present disclosure created by the present inventors avoids the generation of large parasitic capacitance, while suppressing a significant increase in manufacturing cost and manufacturing time, and achieving high process stability during mass production. As a result, the embodiment of the present disclosure can improve the gain of the HEMT device 10, thereby promoting the reduction of power consumption of the HEMT device 10 and, for example, extending the operating time of an electronic device equipped with the HEMT device 10. The following describes the details of the embodiment of the present disclosure created by the present inventors.

[0020] <<2. Embodiment>> <2.1 Detailed Structure> First, a detailed structure of a HEMT device (semiconductor device) 10 according to an embodiment of the present disclosure will be described with reference to Fig. 2. Fig. 2 is a cross-sectional view of the structure of the HEMT device 10 according to this embodiment, and more specifically, corresponds to a cross section of the HEMT device 10 cut along the stacking direction (cross-sectional view).

[0021] The HEMT device 10 according to this embodiment has a Schottky gate structure. Specifically, as shown in FIG. 2 , in the HEMT device 10 according to this embodiment, a buffer layer 110 is stacked on a substrate 100, and a channel layer (first compound semiconductor layer) 112 forming a 2DEG layer 114 is stacked on the buffer layer 110. In addition, in the HEMT device 10 according to this embodiment, a barrier layer (second compound semiconductor layer) 120 is heterojunctioned on the channel layer 112 via a spacer layer 116. Furthermore, in this embodiment, an insulating layer 130 is stacked on the barrier layer 120, and a gate electrode 152 is stacked on the insulating layer 130. In this embodiment, the insulating layer 130 has an opening that exposes a portion of the top surface of the barrier layer 120, and the gate electrode 152 contacts the barrier layer 120 through the opening. Additionally, in this embodiment, the source 150 and the drain 154 are formed so as to sandwich the stack of the channel layer 112, the spacer layer 116, the barrier layer 120, and the insulating layer 130. Although not shown in the drawings, a source electrode and a drain electrode electrically connected to the source 150 and the drain 154 may be provided on the source 150 and the drain 154. In the following description, the stack from the substrate 100 to the barrier layer 120 is also referred to as a compound semiconductor layer.

[0022] Furthermore, in this embodiment, unlike the comparative example, the wall surface of the opening in the insulating layer 130 has multiple steps. Note that, in this embodiment, the wall surface of the opening in the insulating layer 130 may have two or more steps, and may have three or more steps. For example, in this embodiment, as shown in FIG. 2 , the wall surface of the opening in the insulating layer 130 has a step (second step) 130a located on the barrier layer 120 side and a step (first step) 130b located on the upper side of the insulating layer 130. In other words, for example, in this embodiment, as shown in FIG. 2 , the opening in the insulating layer 130 is composed of a first opening (corresponding to step 130b in FIG. 2 ) that penetrates the insulating layer 130 from the upper side to partway through the film thickness of the insulating layer 130, and a second opening (corresponding to step 130a in FIG. 2 ) that penetrates the insulating layer 130 from partway through the film thickness of the insulating layer 130 to the top surface of the barrier layer 120. In this embodiment, the first opening and the second opening are connected to form a single opening, and the first opening has a larger opening area than the second opening (the first opening has a larger diameter than the second opening).

[0023] In the comparative example, as shown in FIG. 1 , the gate electrode 152 has a main body (electrode portion) and a skirt-shaped peripheral portion 152a that surrounds the main body. Because the peripheral portion 152a is positioned to extend above the insulating layer 130, a large parasitic capacitance occurs between the peripheral portion 152a and the source 150 or the drain 154. However, in this embodiment, as shown in FIG. 2 , the presence of a step 130b divides the peripheral portion into the peripheral portions 152a and 152b. In this embodiment, although the peripheral portion 152a is positioned on the upper surface of the step 130a of the insulating layer 130, its area is narrowed by the division by the step 130b, and therefore a large parasitic capacitance does not occur between the peripheral portion 152a and the source 150 (specifically, the 2DEG layer 114 on the source 150 side) or between the peripheral portion 152a and the drain 154 (specifically, the 2DEG layer 114 on the drain 154 side). Furthermore, in this embodiment, the outer peripheral portion 152b, which is located outside the outer peripheral portion 152a when viewed from the main body of the gate electrode 152, is separated from the main body by the step 130b, and therefore does not significantly affect operation. That is, in this embodiment, by providing multiple steps 130a, 130b on the wall surface of the opening of the insulating layer 130, the step 130b separates the skirt-shaped outer peripheral portion 152a surrounding the main body of the gate electrode 152. Therefore, according to this embodiment, the area of ​​the outer peripheral portion 152a located on the upper surface of the step 130a of the insulating layer 130 is reduced, thereby preventing large parasitic capacitance from occurring between the outer peripheral portion 152a and the source 150 and between the outer peripheral portion 152a and the drain 154. As a result, according to this embodiment, the parasitic capacitance is reduced, improving the gain of the HEMT device 10 and ultimately reducing the power consumption of the HEMT device 10.

[0024] Furthermore, each layer will be described in detail in turn.

[0025] The substrate 100 is made of a semiconductor material and can be formed from a ternary or quaternary compound semiconductor material, such as a III-V group compound semiconductor material. More specifically, the substrate 100 can be made of, for example, a semi-insulating single-crystal GaN substrate. The substrate 100 may have a different lattice constant from that of the channel layer 112 by controlling the lattice constant with a buffer layer 110, which will be described later. Specifically, silicon carbide (SiC), sapphire, silicon (Si) substrates, etc. can be used as the substrate 100. The use of a Si substrate has the advantage that it is inexpensive and can be large-diameter.

[0026] The buffer layer 110 is composed of, for example, a compound semiconductor epitaxially grown on the substrate 100. When the lattice constants of the substrate 100 and the channel layer 112 are different, controlling the lattice constant with the buffer layer 110 can improve the crystalline state of the channel layer 112 and control the warpage of each layer. For example, when the substrate 100 is composed of single-crystal silicon and the channel layer 112 is composed of GaN, the buffer layer 110 can be made of, for example, aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), or the like. The buffer layer 110 does not necessarily have to be a single layer, but may be a stack of different layers. Furthermore, when the buffer layer 110 is composed of a ternary or quaternary compound semiconductor, the buffer layer 110 may have a composition that gradually changes along its thickness.

[0027] In this embodiment, a back barrier layer (not shown) may be provided between the channel layer 112 and the buffer layer 110. The back barrier layer is made of a semiconductor having a wider energy gap than the channel layer 112. An example of the back barrier layer is Al １－ｘ－ｙ Ga ｘ In ｙ N (0≦x<1, 0≦y<1), u-Al １－ｘ－ｙ Ga ｘ In ｙAn epitaxially grown layer of N can be used. The back barrier layer does not necessarily have to be a single layer, but may be a laminate of different layers. For example, １－ｘ－ｙ Ga ｘ In ｙ The N layer may be a stack of layers with different compositions, or the back barrier layer may have a composition that gradually changes along the thickness.

[0028] The channel layer 112 is a region where carriers accumulate due to polarization with the barrier layer 120, which will be described later. Such a channel layer 112 is made of a compound semiconductor in which carriers are likely to accumulate due to polarization, for example, a group III nitride containing at least one of indium (In), gallium (Ga), and aluminum (Al). In particular, the channel layer 112 may be, for example, an epitaxially grown layer of GaN. Alternatively, the channel layer 112 may be a u (undoped)-GaN layer to which no impurities are added. This suppresses impurity scattering of carriers in the channel layer 112, enabling carrier movement with high mobility.

[0029] The barrier layer 120 is made of a compound semiconductor in which polarization with the channel layer 112 generates two-dimensional electron gas in the channel layer 112 (heterojunction interface), and carriers accumulate. The barrier layer 120 is made of a compound semiconductor different from that of the channel layer 112, and is made of, for example, a group III nitride containing at least one of indium, gallium, and aluminum, and specifically, for example, Al １－ｘ－ｙ Ga ｘ In ｙ The barrier layer 120 can be an epitaxially grown layer of u-AlN (0≦x<1, 0≦y<1). １－ｘ－ｙ Ga ｘ In ｙ N. This can suppress impurity scattering of carriers in the channel layer 112, thereby realizing high carrier mobility. The barrier layer 120 does not necessarily have to be a single layer, but may be a stack of different layers. For example, Al １－ｘ－ｙ Ga ｘ Inｙ The barrier layer 120 may be an N layer, and may be a stack of layers with different compositions. Alternatively, the barrier layer 120 may have a composition that gradually changes along the thickness of the layer. Furthermore, a cap layer (not shown) may be provided on the upper surface of the barrier layer 120 to protect it from oxidation processes and thermal processes. For example, the cap layer may be made of GaN or silicon nitride (Si ｘ N ｙ )

[0030] 2 , a spacer layer 116 may be provided between the barrier layer 120 and the channel layer 112. The spacer layer 116 is made of, for example, a compound semiconductor material having a larger polarization than the barrier layer 120, and can improve the mobility of electrons in the 2DEG formed in the channel layer 112. For example, when the barrier layer 120 and the channel layer 112 are made of the above-mentioned AlGaInN / GaN combination, the spacer layer 116 may be made of, for example, AlN. Alternatively, the spacer layer 116 may be made of InGaN, AlGaN, or the like.

[0031] Furthermore, it is preferable that the insulating layer 130 has insulating properties relative to the barrier layer 120 and has the property of not deteriorating the device characteristics by forming a good interface with the barrier layer 120. Specifically, the insulating layer 130 is made of an oxide or nitride containing, for example, Si, Al, Hf, etc. In more detail, the insulating layer 130 is made of, for example, aluminum oxide (Al ２ O ３ ), hafnium oxide (HfO ２ ), silicon oxide (SiO ２ ), silicon nitride (Si ３ N ４ ) etc.

[0032] The gate electrode 152 may have a laminated structure in which, for example, nickel (Ni) and gold (Au) are laminated. Furthermore, in order to reduce gate impedance, the gate electrode 152 generally has a T-gate shape. In this embodiment, a barrier metal (not shown), such as titanium (Ti), may be formed to cover the surface of the gate electrode 152 in order to suppress metal diffusion.

[0033] The source 150 and the drain 154 are each composed of, for example, a high-concentration N-type (N+) region and an ohmic electrode that can form an ohmic junction with the region. The ohmic electrode is preferably one that can connect to the high-concentration N-type region with low resistance, and is formed, for example, of a single-layer film or a multilayer film of a metal with a low work function, such as Ti, Al, Ni, or Au. Although not shown in the figures in this embodiment, a source electrode and a drain electrode that are electrically connected to the source 150 and the drain 154 may be provided on the source 150 and the drain 154. These electrodes may be formed, for example, of a material such as copper (Cu) or Al.

[0034] As described above, in this embodiment, by providing a plurality of steps 130a, 130b on the wall surface of the opening of the insulating layer 130, the steps 130b divide the skirt-shaped outer peripheral portion 152a surrounding the main body of the gate electrode 152. Therefore, according to this embodiment, the area of ​​the outer peripheral portion 152a located on the upper surface of the steps 130a of the insulating layer 130 is narrowed, and it is possible to prevent large parasitic capacitance from occurring between the outer peripheral portion 152a and the source 150 and between the outer peripheral portion 152a and the drain 154. As a result, according to this embodiment, the parasitic capacitance is reduced, and the gain of the HEMT device 10 can be improved, which in turn reduces the power consumption of the HEMT device 10 and, for example, increases the operating time of an electronic device equipped with the HEMT device 10.

[0035] In this embodiment, the structure of the HEMT device 10 is not limited to the structure shown in FIG. 2, but can be modified into various structures as will be described later.

[0036] 2.2 Manufacturing Method Next, an example of a manufacturing method for the HEMT device 10 according to this embodiment will be described with reference to Figures 3A and 3B. Figures 3A and 3B are cross-sectional views illustrating the manufacturing method for the HEMT device 10 according to this embodiment, and in detail, each figure shows a cross section of the HEMT device 10 cut along the stacking direction at each manufacturing stage.

[0037] First, a buffer layer 110, a channel layer 112, a spacer layer 116, a barrier layer 120, and an insulating layer 130 are sequentially stacked on a GaN substrate 100. Next, a high-concentration N-type (N+) region is formed in the region that will become the source 150 and the drain 154. Specifically, the source 150 and the drain 154 are formed by, for example, forming ohmic electrodes (not shown) on both sides of the region where the gate electrode 152 will be formed, followed by annealing or the like. Furthermore, a high-concentration N-type region is formed on the substrate side by, for example, selective ion implantation. This can reduce contact resistance. Alternatively, instead of ion implantation, the source 150 and the drain 154 may be formed by selective crystal regrowth on the substrate. In this case, the regrown layer may be, for example, n (N-type)-In. １－ｘ Ga ｘ In this embodiment, the high concentration N-type regions that become the source 150 and the drain 154 do not necessarily have to be a single layer, but may be a stack of different layers. For example, １－ｘ Ga ｘ The N (0≦x<1) layer may be a stack of layers with different compositions. Alternatively, the heavily doped N-type region may have a composition that gradually changes along the thickness of the film. Furthermore, Si, germanium (Ge), etc., can be used as an N-type dopant (impurity). In this way, the configuration shown on the left side of FIG. 3A can be obtained.

[0038] Next, as shown in the center of Fig. 3A, resist 200 is applied onto insulating layer 130, and openings 200a are formed in resist 200 by exposure. Then, as shown on the right side of Fig. 3A, insulating layer 130 is etched according to openings 200a in resist 200. The step formed in insulating layer 130 by this etching becomes step 130b that divides outer periphery 152a of gate electrode 152.

[0039] Next, a resist 202 is applied onto the insulating layer 130, and the resist 202 is patterned by exposure according to the shape of the lower portion of the gate electrode 152. At this time, an opening 202a is formed in the resist 202. Furthermore, the insulating layer 130 is etched until a portion of the surface of the barrier layer 120 is exposed, thereby forming an opening for contact between the gate electrode 152 and the barrier layer 120. In this embodiment, a step 130a is formed in the insulating layer 130 at this time. That is, in this embodiment, the wall surface of the opening in the insulating layer 130 is formed so as to have two steps 130a, 130b. In this way, the configuration shown on the left side of FIG. 3B can be obtained.

[0040] Next, as shown in the center of Fig. 3B, a lift-off resist 210 and a resist 204 are formed and patterned, and then the gate electrode 152 is formed according to an opening 204a formed in the resist 204. Furthermore, the lift-off resist 210, the resist 204, and excess metal are removed by a lift-off process, thereby fabricating the HEMT device 10 according to this embodiment, as shown on the right side of Fig. 3B.

[0041] As described above, the HEMT device 10 according to this embodiment can be manufactured using existing equipment and film-forming conditions without requiring special equipment or film-forming conditions. Therefore, according to this embodiment, it is possible to suppress a significant increase in manufacturing cost and manufacturing time, and a highly stable mass-production process can be used.

[0042] 4A to 4G are cross-sectional views of a main portion of the HEMT device 10 according to each of the modifications of the embodiment of the present disclosure, and more specifically, show the main portion of a cross section of the HEMT device 10 taken along the stacking direction.

[0043] 4A, the gate electrode 152 may have a tapered shape that widens downward. That is, in this modification, depending on the manufacturing conditions of the gate electrode 152, the gate electrode 152 may have a tapered shape as shown in FIG.

[0044] 4B , the insulating layer 130 may be made up of two insulating layers 132 and 134. In particular, the step (second step) 130a of the insulating layer 130 is made up of the insulating layer (second insulating film) 132, and the step (first step) 130b of the insulating layer 130 is made up of the insulating layer (first insulating film) 134. The insulating layers 132 and 134 are made of different materials, and the densities and refractive indices of the materials are different from each other.

[0045] More specifically, in this modification, the insulating layer 132 and the insulating layer 134 may be made of different materials. ３ N ４ and the insulating layer 134 is formed of SiO ２ In this modification, by forming the insulating layer 132 and the insulating layer 134 from different materials in this way, the manufacturing means and conditions can be optimized for each material, thereby making it possible to form the two steps 130 a and 130 b with the desired shapes with high precision.

[0046] In addition, in this modification, the insulating layer 132 and the insulating layer 134 are not limited to being formed of different materials. For example, the insulating layer 132 and the insulating layer 134 may be formed of Si. ３ N ４ Alternatively, the insulating layer 132 and the insulating layer 134 may be formed of the same material, such as a material having a different density from the insulating layer 132. In this case, it is preferable that the insulating layer 132 and the insulating layer 134 have different densities. In particular, in this modification, the insulating layer 134 may have a lower density than the insulating layer 132, for example. Alternatively, in this modification, the insulating layer 134 may have a higher density than the insulating layer 132, for example. In this modification, the etching rates of the insulating layer 132 and the insulating layer 134 are different, so that the two steps 130a and 130b can be formed with high precision in a single process.

[0047] Furthermore, in this modification, for example, the insulating layer 132 and the insulating layer 134 are made of Si ３ N ４Alternatively, the insulating layer 132 and the insulating layer 134 may be formed of the same material, such as a material having a refractive index different from that of the insulating layer 132. In this case, it is preferable that the insulating layer 132 and the insulating layer 134 have different refractive indices. In particular, in this modification, the insulating layer 132 may have a higher refractive index than the insulating layer 134, for example. Alternatively, in this modification, the insulating layer 132 may have a lower refractive index than the insulating layer 134, for example. In this modification, the etching rates of the insulating layer 132 and the insulating layer 134 are different, so that the two steps 130a and 130b can be formed with high precision in a single process.

[0048] (Variation 3) In this embodiment, the step 130b of the insulating layer 130 is not limited to being provided both between the gate electrode 152 and the source 150 and between the gate electrode 152 and the drain 154. In this variation, for example, as shown in Variation 3 of FIG. 4C , the step 130b of the insulating layer 130 may be provided only on the drain 154 side. The gain of the HEMT device 10 is significantly affected by parasitic capacitance occurring on the drain 154 side. Therefore, in this variation, in order to reduce the parasitic capacitance on the drain 154 side, which is significantly affected, the step 130b may be provided only between the gate electrode 152 and the drain 154. In this variation, the step 130b of the insulating layer 130 may be provided only on the source 150 side.

[0049] (Variation 4) As shown in Variation 4 of FIG. 4D , the side surface 130c of the step 130b of the insulating layer 130 may be oblique, in other words, overhanging. Specifically, in this variation, the opening of the insulating layer 130 comprises two communicating openings, a first and a second opening. The first opening (corresponding to the step 130b) penetrates the insulating layer 130 from the upper side to partway through its thickness, and the second opening (corresponding to the step 130a) penetrates the insulating layer 130 from partway through its thickness to the top surface of the barrier layer 120. In this variation, the first opening has a larger opening area than the second opening, and the first opening itself has a tapered shape in which the opening area increases downward (toward the lower side of the insulating layer 130) (i.e., the diameter increases downward). According to this modification, by forming the first opening so that its diameter increases downward, in other words, so that its diameter decreases upward, it is possible to narrow the area where the gate electrode 152 is stacked on the upper surface of the step 130a exposed from the first opening. Therefore, according to this modification, the area of ​​the outer periphery 152a of the gate electrode 152 located on the upper surface of the step 130a of the insulating layer 130 is narrowed, and it is possible to prevent large parasitic capacitance from occurring between the outer periphery 152a and the source 150 and between the outer periphery 152a and the drain 154.

[0050] (Variation 5) As shown in Variation 5 of FIG. 4E , the insulating layer 130 may be formed from a stack (laminated film) of multiple insulating layers (insulating films) 136, 138, and 140. Specifically, in this variation, the opening in the insulating layer 130 is composed of three interconnected openings: a first, a second, and a third. In this case, the third opening penetrates the insulating layer 140, the first opening penetrates the insulating layer 138, and the second opening (corresponding to the step 130 a) penetrates the insulating layer 136. In this variation, the first opening penetrating the insulating layer 138 has a larger opening area than the second opening penetrating the insulating layer 136. Furthermore, in this variation, the third opening penetrating the insulating layer 140 has a smaller opening area than the first opening penetrating the insulating layer 138 (the sides of the first and third openings overhang). According to this modification, the third opening that penetrates the insulating layer 140 has a smaller opening area than the first opening that penetrates the insulating layer 138. In other words, the area over which the gate electrode 152 is stacked on the upper surface of the step 130a exposed from the first opening can be narrowed. Therefore, according to this modification, the area of ​​the outer periphery 152a of the gate electrode 152 located on the upper surface of the step 130a of the insulating layer 130 is narrowed, and it is possible to prevent large parasitic capacitance from occurring between the outer periphery 152a and the source 150 and between the outer periphery 152a and the drain 154.

[0051] In this modification, the insulating layers 136, 138, and 140 are preferably made of different materials, or have different densities and refractive indices. This allows for accurate formation of steps. Furthermore, this allows for accurate formation of multiple steps in a single process. Furthermore, in this modification, the insulating layer 130 is not limited to being formed from three insulating layers, but may be formed from four or more insulating layers.

[0052] (Variation 6) Furthermore, as shown in Variation 6 of FIG. 4F , the side surface 130d of the step 130b of the insulating layer 130 may be oblique. Specifically, in this variation, the opening of the insulating layer 130 is composed of two communicating openings, a first and a second opening. The first opening (corresponding to the step 130b) penetrates the insulating layer 130 from the upper side to partway through its thickness, and the second opening (corresponding to the step 130a) penetrates the insulating layer 130 from partway through its thickness to the top surface of the barrier layer 120. In this variation, the first opening has a larger opening area than the second opening, and the first opening itself has a tapered shape in which the opening area narrows downward (toward the lower side of the insulating layer 130) (i.e., the diameter decreases downward). According to this modification, depending on the processing conditions for the first opening, the first opening may have a tapered shape in which the opening area narrows downward.

[0053] (Variation 7) Furthermore, when forming the gate electrode 152, the gate electrode 152 is stacked on the insulating layer 130 while filling the opening in the insulating layer 130. Therefore, as shown in Variation 7 of FIG. 4G, the upper surface of the gate electrode 152 may have a recess 152c.

[0054] In the embodiments and modifications of the present disclosure, the HEMT device 10 is not limited to the forms shown in FIGS. 4A to 4G, but can be modified into various forms.

[0055] <<3. Summary>> As described above, in the embodiment of the present disclosure, by providing multiple steps 130a, 130b on the wall surface of the opening of the insulating layer 130, the steps 130b separate the skirt-shaped outer peripheral portion 152a surrounding the main body of the gate electrode 152. Therefore, according to this embodiment, the area of ​​the outer peripheral portion 152a located on the upper surface of the steps 130a of the insulating layer 130 is narrowed, and it is possible to avoid large parasitic capacitance between the outer peripheral portion 152a and the source 150 and between the outer peripheral portion 152a and the drain 154. As a result, according to this embodiment, the parasitic capacitance is reduced, and the gain of the HEMT device 10 can be improved. This in turn reduces the power consumption of the HEMT device 10 and extends the operating time of, for example, an electronic device equipped with the HEMT device 10. Furthermore, this embodiment does not require special equipment or film formation conditions and can be manufactured using existing equipment and film formation conditions. This prevents a significant increase in manufacturing cost and manufacturing time and allows for the use of a highly stable mass production process.

[0056] Although the HEMT device 10 according to each embodiment of the present disclosure is a GaN-based compound semiconductor, the present disclosure is not limited to this and may be, for example, a compound semiconductor such as GaAs, or a semiconductor using a Si substrate, etc.

[0057] Furthermore, the materials, film thicknesses, film formation methods, and film formation conditions of each layer in the above-described embodiments of the present disclosure are not limited to those described above and can be changed as appropriate. That is, in this embodiment, the semiconductor device can be manufactured using techniques, devices, and conditions that are commonly used in the manufacture of semiconductor devices.

[0058] Examples of the above-mentioned method include a physical vapor deposition (PVD) method, a chemical vapor deposition (CVD) method, and an atomic layer deposition (ALD) method. Examples of PVD methods include vacuum deposition, EB (electron beam) deposition, various sputtering methods (magnetron sputtering, RF (radio frequency)-DC (direct current) combined bias sputtering, ECR (electron cyclotron resonance) sputtering, facing target sputtering, high frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE), and laser transfer. Examples of CVD methods include plasma CVD, thermal CVD, metal organic (MO) CVD, and photo CVD. Other methods include electroplating, electroless plating, spin coating, dipping, casting, microcontact printing, drop casting, various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing, stamping, spraying, and various coating methods such as air doctor coater, blade coater, rod coater, knife coater, squeeze coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, cast coater, spray coater, slit orifice coater, and calendar coater. Furthermore, patterning methods include chemical etching such as shadow mask, laser transfer, and photolithography, and physical etching using ultraviolet light or laser. Additionally, planarization techniques include CMP (Chemical Mechanical Polishing), laser planarization, and reflow.

[0059] <<4. Application Examples>> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be applied to a communication device. Therefore, as an example of application of the technology according to the present disclosure, a wireless communication device (communication device) 500 will be described with reference to FIG. 5 . FIG. 5 is an explanatory diagram illustrating an application example of the HEMT device 10 according to an embodiment of the present disclosure.

[0060] The wireless communication device 500 shown in FIG. 5 is a mobile phone system having multiple functions, such as voice and data communication and LAN (Local Area Network) connection. For example, the wireless communication device 500 includes an antenna (ANT) 510, an antenna switch circuit 520, a radio frequency integrated circuit (RF IC (Radio Frequency Integrated Circuit)) 530, a baseband unit 540, a high power amplifier (HPA) 550, and an output unit 560 including an audio output unit (MIC), a data output unit (DT), and an interface (IF) unit. The interface (IF) unit can connect to a device that performs wireless communication, such as a wireless LAN or Bluetooth (registered trademark). The radio frequency integrated circuit RF IC 530 and the baseband unit 540 are connected via an internal bus.

[0061] During transmission, a transmission signal output from the baseband unit 540 is output to the antenna 510 via the radio frequency integrated circuit RF IC 530, the high power amplifier 550, and the antenna switch circuit 520. During reception, a reception signal received by the antenna 510 is input to the baseband unit 540 via the antenna switch circuit 520 and the radio frequency integrated circuit RF IC 530. The baseband unit 540 processes the input signal and outputs it from the output unit 560 to an external device or the like.

[0062] For example, the technology of the present disclosure can be applied to an antenna switch circuit 520, a radio frequency integrated circuit (RF IC) 530, a high power amplifier 550, and the like. The effects of the technology of the present disclosure are particularly pronounced in wireless communication devices whose communication frequencies are in the UHF (Ultra High Frequency) band or higher. That is, by using a HEMT device 10 according to an embodiment of the present disclosure, which has excellent high efficiency characteristics, as an antenna switch circuit 520, a radio frequency integrated circuit (RF IC) 530, a high power amplifier 550, and the like, it is possible to achieve high efficiency and low power consumption in communication processing in the wireless communication device 500. In particular, when the wireless communication device 500 is applied to a mobile communication terminal, the high efficiency and low power consumption of the HEMT device 10 can extend the battery life of the wireless communication device 500 and improve portability.

[0063] The above describes an example configuration of the wireless communication device 500. Each of the above components may be configured using general-purpose components, or may be configured using hardware specialized for the function of each component. Such a configuration may be changed as appropriate depending on the technical level at the time of implementation.

[0064] <<5. Supplementary Information>> Although preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person skilled in the art of the present disclosure can conceive of various modified or altered examples within the scope of the technical idea described in the claims, and it is understood that these also naturally fall within the technical scope of the present disclosure.

[0065] Furthermore, the effects described herein are merely descriptive or exemplary and are not limiting. In other words, the technology according to the present disclosure may achieve other effects that will be apparent to those skilled in the art from the description of this specification, in addition to or in place of the above-described effects.

[0066] The present technology can also be configured as follows. (1) A semiconductor device having a stacked structure including: a first compound semiconductor layer; a second compound semiconductor layer stacked on the first compound semiconductor layer and made of a compound semiconductor different from the first compound semiconductor layer; an insulating layer stacked on the second compound semiconductor layer; and a gate electrode stacked on the insulating layer and in contact with the second compound semiconductor layer through an opening provided in the insulating layer, wherein a wall surface of the opening has two or more steps in a cross section of the semiconductor device cut along the stacking direction. (2) The semiconductor device according to (1), wherein the opening has: a first step located above the insulating layer; and a second step located on the second compound semiconductor layer side. (3) The semiconductor device according to (2), wherein the gate electrode includes an electrode portion and an outer periphery surrounding the electrode portion, and the outer periphery is divided by the first step. (4) The semiconductor device according to (2) or (3), wherein the first step is made of a first insulating film, and the second step is made of a second insulating film. (5) The semiconductor device according to (4), wherein the first insulating film is made of a material different from that of the second insulating film. (6) The semiconductor device according to (4), wherein the first insulating film is made of a material having a different density from that of the second insulating film. (7) The semiconductor device according to (6), wherein the first insulating film has a lower density than that of the second insulating film. (8) The semiconductor device according to (4), wherein the first insulating film is made of a material having a different refractive index than that of the second insulating film. (9) The semiconductor device according to (8), wherein the first and second insulating films are made of silicon nitride. (10) The semiconductor device according to (2), wherein the first step is made of a stacked film in which a plurality of insulating films are stacked, and wherein, in the cross section, a side surface of the stacked film included in the opening has an overhanging shape. (11) The semiconductor device according to (2), further comprising a source and a drain provided to sandwich the stacked structure. (12) The opening has the first step between the gate electrode and the drain.(13) The semiconductor device according to (1) above, wherein the opening includes: a first opening penetrating the insulating layer from an upper side of the insulating layer to partway through its thickness; and a second opening penetrating the insulating layer from partway through its thickness to the surface of the second compound semiconductor layer, the first opening and the second opening being connected to each other, and the first opening having a larger opening area than the second opening. (14) The semiconductor device according to (13) above, wherein the first opening has a tapered shape in the cross section. (15) The semiconductor device according to (14) above, wherein the first opening has a tapered shape that widens toward the lower side of the insulating layer in the cross section. (16) The semiconductor device according to any one of (1) to (8) above, wherein the insulating layer is made of an oxide or nitride containing at least one of silicon, aluminum, and hafnium. (17) The semiconductor device according to any one of (1) to (16) above, wherein the stacked structure includes a spacer layer between the first compound semiconductor layer and the second compound semiconductor layer. (18) The semiconductor device according to any one of (1) to (17) above, wherein the first and second compound semiconductor layers are made of a Group III nitride containing at least one of gallium, indium, and aluminum. (19) A method for manufacturing a semiconductor device, comprising: stacking a second compound semiconductor layer made of a compound semiconductor different from that of the first compound semiconductor layer on the first compound semiconductor layer, stacking an insulating layer having an opening on the second compound semiconductor layer, and forming a gate electrode on the insulating layer so as to be in contact with the second compound semiconductor layer through the opening, wherein the opening is formed so that a wall surface of the opening has two or more steps in a cross section of the insulating layer cut along a film thickness direction.(20) A communication device equipped with a semiconductor device, wherein the semiconductor device has a stacked structure including: a first compound semiconductor layer; a second compound semiconductor layer stacked on the first compound semiconductor layer and made of a compound semiconductor different from that of the first compound semiconductor layer; an insulating layer stacked on the second compound semiconductor layer; and a gate electrode stacked on the insulating layer and in contact with the second compound semiconductor layer through an opening provided in the insulating layer, and wherein a wall surface of the opening has two or more steps in a cross section of the semiconductor device cut along the stacking direction.

[0067] 10, 10a HEMT device 100 Substrate 110 Buffer layer 112 Channel layer 114 2DEG layer 116 Spacer layer 120 Barrier layer 130, 132, 134, 136, 138, 140 Insulating layer 130a, 130b Step 130c, 130d Side surface 150 Source 152 Gate electrode 152a, 152b Outer periphery 152c Recess 154 Drain 200, 202, 204 Resist 200a, 202a, 204a Opening 210 Lift-off resist 500 Wireless communication device 510 Antenna 520 Antenna switch circuit 530 Radio frequency integrated circuit (RF IC) 540 Baseband section 550 High power amplifier 560 Output section

Claims

1. A semiconductor device having a layered structure including: a first compound semiconductor layer; a second compound semiconductor layer stacked on the first compound semiconductor layer and made of a compound semiconductor different from that of the first compound semiconductor layer; an insulating layer stacked on the second compound semiconductor layer; and a gate electrode stacked on the insulating layer and in contact with the second compound semiconductor layer through an opening provided in the insulating layer, wherein, in a cross section of the semiconductor device cut along the stacking direction, the wall surface of the opening has two or more steps.

2. The semiconductor device according to claim 1, wherein the opening has a first step located above the insulating layer and a second step located on the second compound semiconductor layer side.

3. The semiconductor device according to claim 2, wherein the gate electrode comprises an electrode portion and an outer periphery surrounding the electrode portion, and the outer periphery is divided by the first step.

4. The semiconductor device according to claim 2, wherein the first step is made of a first insulating film, and the second step is made of a second insulating film.

5. The semiconductor device according to claim 4, wherein the first insulating film is formed from a material different from that of the second insulating film.

6. The semiconductor device according to claim 4, wherein the first insulating film is formed from a material having a density different from that of the second insulating film.

7. The semiconductor device according to claim 6, wherein the first insulating film has a lower density than the second insulating film.

8. The semiconductor device according to claim 4, wherein the first insulating film is made of a material having a refractive index different from that of the second insulating film.

9. The semiconductor device according to claim 8, wherein the first and second insulating films are made of silicon nitride.

10. The semiconductor device according to claim 2, wherein the first step is made of a laminated film in which a plurality of insulating films are stacked, and in the cross section, the side surface of the laminated film included in the opening has an overhanging shape.

11. The semiconductor device according to claim 2, further comprising a source and a drain provided so as to sandwich the laminated structure.

12. The semiconductor device according to claim 11, wherein the opening has the first step between the gate electrode and the drain.

13. The semiconductor device according to claim 1, wherein the opening includes: a first opening penetrating the insulating layer from the upper side of the insulating layer to partway through its thickness; and a second opening penetrating the insulating layer from partway through its thickness to the surface of the second compound semiconductor layer; the first opening and the second opening are connected; and the first opening has a larger opening area than the second opening.

14. The semiconductor device according to claim 13, wherein said first opening has a tapered shape in said cross section.

15. The semiconductor device according to claim 14, wherein the first opening has a tapered cross section that widens toward the lower side of the insulating layer.

16. The semiconductor device according to claim 1, wherein the insulating layer is made of an oxide or nitride containing at least one of silicon, aluminum, and hafnium.

17. The semiconductor device according to claim 1, wherein the laminated structure has a spacer layer between the first compound semiconductor layer and the second compound semiconductor layer.

18. The semiconductor device according to claim 1, wherein the first and second compound semiconductor layers are made of a Group III nitride containing at least one of gallium, indium, and aluminum.

19. A method for manufacturing a semiconductor device, comprising: stacking a second compound semiconductor layer on a first compound semiconductor layer, the second compound semiconductor layer being made of a compound semiconductor different from that of the first compound semiconductor layer; stacking an insulating layer having an opening on the second compound semiconductor layer; and forming a gate electrode on the insulating layer, the gate electrode being in contact with the second compound semiconductor layer through the opening, wherein the opening is formed so that a wall surface of the opening has two or more steps in a cross section of the insulating layer cut along the film thickness direction.

20. A communication device equipped with a semiconductor device, wherein the semiconductor device has a layered structure including: a first compound semiconductor layer; a second compound semiconductor layer stacked on the first compound semiconductor layer and made of a compound semiconductor different from that of the first compound semiconductor layer; an insulating layer stacked on the second compound semiconductor layer; and a gate electrode stacked on the insulating layer and in contact with the second compound semiconductor layer through an opening provided in the insulating layer, and wherein, in a cross section of the semiconductor device cut along the stacking direction, the wall surface of the opening has two or more steps.

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