Methods & architectures of edge coated glass substrates

Abstract

An example method of manufacturing a glass substrate includes placing a glass panel on a temporary carrier film, cutting the glass panel in pieces in a first cutting operation, encapsulating a first surface of the glass pieces with a polymer dielectric, removing the temporary carrier film to expose a second surface of glass pieces, encapsulating the second surface of glass pieces with the polymer dielectric, applying a pressure or a temperature to the polymer dielectric, curing the polymer dielectric, forming a plurality of build-up layers on each of the glass pieces, where each build-up layer comprises a polymer layer and a metal layer, mounting an electronic component on the plurality of build-up layers of each of the glass pieces, and separating the glass pieces into individual glass substrates in a second cutting operation.

Description

METHODS & ARCHITECTURES OF EDGE COATED GLASS SUBSTRATESCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. provisional patent application No. 63 / 571,782, filed on March 29, 2024, and titled “METHODS & ARCHITECTURES OF EDGE COATED GLASS SUBSTRATES,” the disclosure of which is expressly incorporated herein by reference in its entirety.BACKGROUND

[0002] Semiconductor devices are electronic components that use semiconductor materials. Common semiconductor devices include integrated circuits and transistors. To protect electronic components like semiconductor devices, a package is commonly used. A common form of packaging is a substrate. Substrates can provide a structural base for packaging parts, and / or an electrical connections to parts. Glass and organic materials can be used as substrates, and build-up layers can be added to the substrates to add electrical connections. Improvements to substrates, and methods of manufacturing substrates, can improve the performance of electrical components by improving their packaging.SUMMARY

[0003] Disclosed herein is a method of edge-coating glass substrates and substrates produced therefrom, which can, in some implementations, improve the reliability and manufacturability of glass substrates for electronics. In an example implementation of the method, the glass panel is diced into the desired substrate size on a temporary carrier, and the diced glass pieces are then covered with polymer dielectric on both sides, leading to the formation of a composite panel with multiple small glass pieces in a polymer matrix. The composite panel is then used to form build-up layers for a device. After completion of all processing steps, the individual glass pieces can be diced such that the cut width is smaller than the initial cut width so that there can remain a polymer coating around the edges of the glass pieces. The polymer coating around glass edges can provide protection against the cracking of glass substrates during or after fabrication or during the operational lifetime.

[0004] In some aspects, implementations of the present disclosure include a method of manufacturing a glass substrate, the method including: placing a glass panel or wafer on a temporary carrier film; cutting the glass panel or wafer in pieces in a first cutting operation;encapsulating a first surface of the glass pieces with a polymer dielectric; removing the temporary carrier film to expose a second surface of glass pieces; encapsulating the second surface of glass pieces with the polymer dielectric, thereby forming a structure of glass pieces sandwiched between polymer dielectric layers on the first surface and second surface; applying a pressure or a temperature to the polymer dielectric; curing the polymer dielectric; forming a plurality of build-up layers on each of the glass pieces, wherein each build-up layer includes a polymer layer and a metal layer; mounting an electronic component on the plurality of buildup layers of each of the glass pieces; and separating the glass pieces into individual glass substrates in a second cutting operation.

[0005] In some aspects, implementations of the present disclosure include a method, wherein the first cutting operation defines a first width, and the second cutting operation defines a second width, and the first width is larger than the second width.

[0006] In some aspects, implementations of the present disclosure include a method, wherein the glass panel has one or a combination of through glass vias, metal pattern, metallized through glass vias or polymer coating.

[0007] In some aspects, implementations of the present disclosure include a method, wherein the glass panel and glass pieces have a thickness from 1 micrometer to 5000 micrometers.

[0008] In some aspects, implementations of the present disclosure include a method, wherein the glass substrate has a ratio of total thickness of build-up layers to the thickness of glass equal to or greater than 0.5.

[0009] In some aspects, implementations of the present disclosure include a method, wherein the glass substrate has a total thickness of build-up layers greater than or equal to 80 micrometers.

[0010] In some aspects, implementations of the present disclosure include a method, wherein a total thickness of polymer dielectric layers on either side of the glass pieces is greater than or equal to 60 micrometers.

[0011] In some aspects, implementations of the present disclosure include a method, wherein the polymer dielectric and the polymer layers include a single type of polymer dielectric.

[0012] In some aspects, implementations of the present disclosure include a method, wherein the glass substrate has excessive polymer dielectric at an edge of the glass substrate extending beyond the edge of each of the glass pieces by 1 micrometer to 500 micrometer.

[0013] In some aspects, implementations of the present disclosure include a method, wherein the pressure is between 0.1 MPa and 10 MPa.

[0014] In some aspects, implementations of the present disclosure include a method, wherein the temperature is between 70 to 300 degrees Celsius.

[0015] In some aspects, implementations of the present disclosure include a method, wherein where polymer layers are partially or completely removed to achieve thickness uniformity.

[0016] In some aspects, implementations of the present disclosure include an electronic device including: a glass piece including a first side and a second side, wherein the first side and the second side are encapsulated by a polymer dielectric at least one build-up layer formed on the glass piece; and an electronic component formed on the at least one build-up layer.

[0017] In some aspects, implementations of the present disclosure include an electronic device, wherein the glass piece includes an excess polymer dielectric edge extending beyond the edge of the glass piece by 1 micrometer to 500 micrometer.

[0018] In some aspects, implementations of the present disclosure include an electronic device or claim 14, wherein the glass piece includes at least one crack filled by a portion of the polymer dielectric.

[0019] In some aspects, implementations of the present disclosure include an electronic device, wherein the electronic component is a chiplet.

[0020] In some aspects, implementations of the present disclosure include an electronic device, wherein the at least one build-up layer or polymer dielectric define a rounded edge.

[0021] In some aspects, implementations of the present disclosure include an electronic device, wherein the electronic device is a component of a high-frequency system, radiofrequency system, 5G system, millimeter-wave system or 6G system.

[0022] In some aspects, implementations of the present disclosure include an electronic device, wherein the glass piece further includes a cavity defining a cavity surface, and wherein the polymer dielectric covers a portion of the cavity surface.

[0023] In some aspects, implementations of the present disclosure include a semiconductor substrate or interposer including: a glass core including at least one cut surface and an edge, wherein the at least one cut surface includes a crack or microcrack; a polymer material partially or completely occupying the cracks or microcracks, wherein the polymer material extends beyond the edge of the glass core and is configured as a barrier to prevent cracking of the glass core.

[0024] In some aspects, implementations of the present disclosure include a semiconductor substrate or interposer, having multiple metal and polymer layers forming a plurality of redistribution layers.

[0025] In some aspects, implementations of the present disclosure include a semiconductor substrate or interposer, wherein the redistribution layers are thicker than the glass core.

[0026] In some aspects, implementations of the present disclosure include a semiconductor device including: semiconductor substrate or interposer, chips or chiplets connected to the substrate, the substrate connected to a printed circuit board.

[0027] In some aspects, implementations of the present disclosure include a high- frequency or radio-frequency or 5G or millimeter-wave or 6G system including: semiconductor substrate or interposer, antenna structures, passive structures, waveguides.

[0028] In some aspects, implementations of the present disclosure include a method of edge coating a glass substrate, the method including: a) applying a carrier / dicing film to a first side of a glass panel; b) cutting the glass panel into a plurality of glass substrates, wherein a first side of the plurality of glass substrates remains attached to the carrier / dicing film; c) applying a first polymer to a second side of the plurality of glass substrates, wherein the first polymer at least partially fills cuts between glass substrates; d) removing the carrier / dicing film and applying a second polymer to the first side of the plurality of glass substrates, wherein the second polymer at least partially fills cuts between glass substrates; e) optionally forming one or more build-up layers on the first side and / or the second side of the plurality of glass substrates; and f) cutting the polymer between each of the plurality of glass substrates, thereby forming a plurality of edge-coated glass substrates.

[0029] In some aspects, implementations of the present disclosure include a method, further including assembling a chip on each of the plurality of glass substrates either before or after step f). In some aspects, implementations of the present disclosure include a method, further including planarizing one or both sides of the plurality of glass substrates after step c) and / or after step d).

[0030] In some aspects, implementations of the present disclosure include an edge-coated glass substrate formed by the methods described herein.

[0031] Other systems, methods, features and / or advantages will be or may become apparent to one with skill in the art upon examination of the following drawings and detailed descriptions. It is intended that all such additional systems, methods, features and / or advantages be included within this description and be protected by the accompanying claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The skilled person in the art will understand that the drawings described below are for illustration purposes only.

[0033] FIG. 1 illustrates an example method of fabricating glass substrates and electronics including glass substrates, according to implementations of the present disclosure.

[0034] FIG. 2 illustrates an example glass substrate, build-up layers, and electronic components, according to implementations of the present disclosure.

[0035] FIGS. 3 A and 3B illustrate a example glass substrates including a crack and a rounded edge, according to implementations of the present disclosure.

[0036] FIG. 4 illustrates an example glass substrate including any number of build-up layers, according to implementations of the present disclosure.

[0037] FIG. 5 illustrates an example process for edge coating glass substrates, in accordance with an example implementation of the present disclosure.

[0038] FIG. 6 illustrates an example magnified view of a diced substrate resulting from the method illustrated in FIG. 5.

[0039] FIG. 7 illustrates a dicing step that can optionally be performed after chip assembly, according to implementations of the present disclosure.

[0040] FIG. 8 illustrates an example process for a glass substrate with cavities, according to implementations of the present disclosure.

[0041] FIG. 9 illustrates an example topography after applying process steps according to implementations of the present disclosure.

[0042] FIG. 10 illustrates an example of planarization that can be applied to achieve thickness uniformity, according to implementations of the present disclosure.DETAILED DESCRIPTION

[0043] It is appreciated that certain features of the disclosure, which are, for clarity, described in the context of separate aspects, can also be provided in combination with a single aspect. Conversely, various features of the disclosure, which are, for brevity, described in the context of a single aspect, can also be provided separately or in any suitable subcombination. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present disclosure.

[0044] Some references, which may include various patents, patent applications, and publications, are cited in a reference list and discussed in the disclosure provided herein. The citation and / or discussion of such references is provided merely to clarify the description of the present disclosure and is not an admission that any such reference is “prior art” to any aspects of the present disclosure described herein. In terms of notation, “[n]” corresponds to the nlhreference in the list. All references cited and discussed in this specification are incorporated herein by reference in their entirety and to the same extent as if each reference was individually incorporated by reference.DEFINITIONS

[0045] In this specification and in the claims that follow, reference will be made to a number of terms, which shall be defined to have the following meanings:

[0046] As used herein, “comprising” is to be interpreted as specifying the presence of the stated features, integers, steps, or components as referred to, but does not preclude the presence or addition of one or more features, integers, steps, or components, or groups thereof. Moreover, each of the terms “by”, “comprising,” “comprises”, “comprised of,” “including,” “includes,” “included,” “involving,” “involves,” “involved,” and “such as” are used in their open, non-limiting sense and may be used interchangeably. Further, the term “comprising” is intended to include examples and aspects encompassed by the terms “consisting essentially of’ and “consisting of.” Similarly, the term “consisting essentially of’ is intended to include examples encompassed by the term “consisting of.

[0047] As used in the specification and the appended claims, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a compound”, “a composition”, or “a cancer”, includes, but is not limited to, two or more such compounds, compositions, or cancers, and the like.

[0048] It should be noted that ratios, concentrations, amounts, and other numerical data can be expressed herein in a range format. It can be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint. It is also understood that there are a number of values disclosed herein, and that each value is also herein disclosed as “about” that particular value in addition to the value itself. For example, if the value “10” is disclosed, then “about 10” is also disclosed. Ranges can be expressed herein as from “about” one particular value, and / or to “about” another particular value. Similarly, when values are expressed as approximations, by use of the antecedent “about,” it can be understood that the particular value forms a further aspect. For example, if the value “about 10” is disclosed, then “10” is also disclosed.

[0049] When a range is expressed, a further aspect includes from the one particular value and / or to the other particular value. For example, where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the disclosure, e.g. the phrase “x to y” includes the range from ‘x’ to ‘y’ as well as the range greater than ‘x’ and less than ‘y’. The range can also be expressed as an upper limit, e.g. ‘about x, y, z, or less’ and should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of ‘less than x’, less than y’, and ‘less than z’. Likewise, the phrase ‘about x, y, z, or greater’ should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of ‘greater than x’, greater than y’, and ‘greater than z’. In addition, the phrase “about ‘x’ to ‘y’”, where ‘x’ and ‘y’ are numerical values, includes “about ‘x’ to about ‘y’”.

[0050] It is to be understood that such a range format is used for convenience and brevity, and thus, should be interpreted in a flexible manner to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited. To illustrate, a numerical range of “about 0.1% to 5%” should be interpreted to include not only the explicitly recited values of about 0.1% to about 5%, but also include individual values (e.g., about 1%, about 2%, about 3%, and about 4%) and the subranges (e.g., about 0.5% to about 1.1%; about 5% to about 2.4%; about 0.5% to about 3.2%, and about 0.5% to about 4.4%, and other possible sub-ranges) within the indicated range.

[0051] As used herein, the terms “about,” “approximate,” “at or about,” and “substantially” mean that the amount or value in question can be the exact value or a value that provides equivalent results or effects as recited in the claims or taught herein. That is, it is understood that amounts, sizes, formulations, parameters, and other quantities and characteristics are not and need not be exact, but can be approximate and / or larger or smaller, as desired, reflecting tolerances, conversion factors, rounding off, measurement error and the like, and other factors known to those of skill in the art such that equivalent results or effects are obtained. In some circumstances, the value that provides equivalent results or effects cannot be reasonably determined. In such cases, it is generally understood, as used herein, that “about” and “at or about” mean the nominal value indicated ±10% variation unless otherwise indicated or inferred. In general, an amount, size, formulation, parameter or other quantity or characteristic is “about,” “approximate,” or “at or about” whether or not expressly stated to be such. It is understood that where “about,” “approximate,” or “at or about” is used before a quantitativevalue, the parameter also includes the specific quantitative value itself, unless specifically stated otherwise.

[0052] As used herein, the terms “optional” or “optionally” mean that the subsequently described event or circumstance can or cannot occur, and that the description includes instances where said event or circumstance occurs and instances where it does not.

[0053] With reference to FIG. 1, an example method of manufacturing a glass substrate is shown according to implementations of the present disclosure.

[0054] At step 102, the method includes placing a glass panel or wafer on a temporary carrier film. Optionally, the glass panel or wafer can include features for conducting electricity, including glass vias, metal patterning, metallized through-glass vias, etc. Alternatively or additionally, the glass panel can include a polymer coating.

[0055] At step 104, the method includes cutting the glass panel or wafer in pieces in a first cutting operation.

[0056] At step 106, the method includes encapsulating a first surface of the glass pieces with a polymer dielectric;

[0057] At step 108, the method includes removing the temporary carrier film to expose a second surface of glass pieces;

[0058] At step 110, the method includes encapsulating the second surface of glass pieces with the polymer dielectric, thereby forming a structure of glass pieces sandwiched between polymer dielectric layers on the first surface and second surface. Optionally, the dielectric used to encapsulate the second surface at step 110 can be the same as the polymer dielectric used to encapsulate the first surface at step 106. Alternatively or additionally, the dielectric used to encapsulate the second surface at step 110 can be the different from the polymer dielectric used to encapsulate the first surface at step 106. Non-limiting examples of types of polymer dielectric that can be used in step 106 and 110 include: Ajinomoto Build-up Film (ABF), BCB, epoxy, polymer composite film, silica filled polymers, polymer with fillers, polyimide, polybenzoxazoles (PBO).

[0059] At step 112, applying a pressure or a temperature to the polymer dielectric. Optionally, the temperature can be between 70-300 degrees Celsius. Alternatively or additionally, the pressure can be between .1 MPa and 10 MPa.

[0060] At step 114, the method includes curing the polymer dielectric.

[0061] At step 116, the method includes forming a plurality of build-up layers on each of the glass pieces. As used herein, a “buildup” layer is a each build-up layer comprises a polymer layer and a metal layer.

[0062] At step 118, the method includes mounting an electronic component on the plurality of build-up layers of each of the glass pieces.

[0063] At step 120, the method includes separating the glass pieces into individual glass substrates in a second cutting operation. The second cutting operation can be narrower than the first cutting operation, so that only the first cutting operation contacts the glass pieces. In other words, the first cutting operation can define a first width, and the second cutting operation can define a second width, where the first width is larger than the second width.

[0064] The first cutting operation performed at step 104 and second cutting operation performed at step 120 can be configured to leave an edge of excess polymer dielectric at the edge of the glass substrate that extends outwards from the glass substrate. For example, the edge of excess polymer dielectric can extend a distance of 1 micrometer to 500 micrometers, in some implementations. Alternatively or additionally, the first cutting operation performed at step 104 and second cutting operation performed at step 120 can be configured to leave an edge of excess polymer dielectric that extends from: 1 micrometer to 5000 micrometers.

[0065] Optionally, the method can include planarizing any of the polymer layers. As used herein, “planarizing” can refer to the process of partially or completely removing a layer to achieve thickness uniformity or flatness of the layer (e.g., flatness relative to the substrate or other layers).

[0066] It should be understood that the order of steps shown in FIG. 1 is intended as a nonlimiting example, and that the steps of the example implementations described herein can be performed in different orders. As additional non-limiting examples, in some implementations, step 118 can be performed after step 120, so that the electronic component(s) are mounted on the substrates after the glass pieces are separated in the second cutting operation. As yet another additional non-limiting example, a microchip can be assembled on the substrate before or after the second cutting operation at step 120. As a still additional non-limiting example, planarizing can be performed on the glass pieces before or after applying the polymer layer at steps 106 and 110.

[0067] FIG. 2 illustrates a side-view of a glass substrate 200 during fabrication steps described with reference to FIG.l. As shown in FIG. 2, the glass panel or wafer 202 can be placed on a temporary carrier / dicing film 204. The glass panel or wafer 202 can be part of a larger piece of glass (e.g., a larger glass panel). The larger glass panel and / or glass panel or wafer 202 can optionally have a thickness in the range from 1 micrometer to 500 micrometers.

[0068] Still with reference to FIG. 2, a fist cut 212a can separate the glass panel or wafer 202 from the larger glass panel (not shown). The first polymer dielectric layer 206 canencapsulate at least part of the glass panel or wafer 202, and the temporary carrier / dicing film 204 can be removed. A second polymer dielectric layer 207 can encapsulate the surface where the temporary carrier / dicing film is removed from. A second cut 212b can trim the excess polymer dielectric and separate the glass substrate 200 from other glass substrates formed from the same larger glass piece.

[0069] FIG. 2 further shows the thickness of the first polymer dielectric 214a and second polymer dielectric 214b. The thickness of the first polymer dielectric 214a and / or second polymer dielectric 214b can each be greater than or equal to 60 micrometers in some implementations of the present disclosure. One or more build-up layer(s) 208 can be formed on the first polymer dielectric layer 206 or second polymer dielectric layer 207. The build-up layer(s) 208 can be used to connect one or more electronic components 210a, 210b that can be mounted to the build-up layer(s) 208.

[0070] FIG. 3A illustrates a side-view of a glass substrate fabricated according to the methods described herein. As shown in FIG. 3A, the glass substrate can optionally include a crack 304 formed during a cutting step. The first polymer dielectric layer 206 and / or second polymer dielectric layer 207 can optionally fill the crack 304 partially or completely, which can protect the cracked surface and can prevent future cracking. Optionally, the crack 304 can be a microcrack (a crack that is only visible on microscopic scales). FIG. 3B illustrates an additional example of glass substrates with cracks filled by polymers, according to implementations of the present disclosure. Alternatively or additionally, as shown in FIG. 3, first polymer dielectric layer 206 and / or second polymer dielectric layer 207 can include at least one rounded edge 302. Alternatively or additionally, buildup layers can also define rounded edges in some implementations of the present disclosure.

[0071] With reference to FIG. 4, an example substrate with build-up layers is shown according to implementations of the present disclosure.

[0072] As shown in FIG. 4, any number of build-up layers can be used, illustrated as the first build-up layer 402 through the nth build-up layer 404, where n can be any integer. Example numbers of build-up layers that can be used include: 1 to 50 layers. In common terminology, the build up layer stack-up may be 4+2+4, 5+2+5, 10+2+10 or 25+2+25 for a symmetric stack- up. An asymmetric stack-up may be 3+2+1, 5+2+1, or 5+2+3. Where the first and third numbers denote the number of build-up layers on either side of substrate core, whereas the middle number denotes the number of metal layers on the substrate core.

[0073] FIG. 4 further shows the total thickness of build-up layers 406 (i.e., the total thickness of all build-up layers one through “n”). FIG. 4 also shows the thickness of the glasspanel or wafer 408. Optionally, the total thickness of build-up layers 406 is greater than or equal to 80 micrometers.

[0074] In some implementations of the present disclosure, the total thickness of build-up layers 406 is less than 50% of the thickness of the glass panel or wafer 408 (i.e., the thickness ratio of build-up layers to glass is less than .5).

[0075] The present disclosure contemplates that the substrates described herein can be used as substrates for any type of electronic component, and components of any electronic systems. For example, the electronic components described herein can be microchips, active and passive devices, chiplets, etc.

[0076] Example systems that can be made using implementations of the present disclosure include high frequency systems, radio-frequency systems, 5G systems, millimeter-wave systems, 6G systems. These kinds of systems can be implemented using the substrates described herein to fabricate electronics that are operably coupled to antenna structures, passive structures, and / or waveguides, for example.

[0077] For example, implementations of the present disclosure can include interposer. An interposer has high-density wiring whereas a substrate has coarser or low-density wiring conventionally. The implementations of the present disclosure may apply to either an interposer or a substrate wherein multiple build-up layers or redistribution layers are present.EXAMPLE METHOD AND DEVICE

[0078] FIGS. 5-10 illustrate example methods and devices according to implementations of the present disclosure. The examples shown in FIGS. 5-10 illustrate how implementations of the present disclosure can overcome limitations of traditional organic substrate cores. Contemporary device packaging, one approach is to use organic substrate cores like FR4 PCB laminates or BT epoxy PCB board (Bismaleimide-triazine resin-based copper clad laminate PCB), onto which thin organic build-up layers are applied to create wiring layers. However, the limitations of organic packaging for future mobile and high-performance needs are evident, and implementations of the present disclosure can overcome these limitations for these and other applications. For example, there is a need for thinner packages in mobile applications, but thinner packages can exacerbate warpage problems (both before and after assembly. Additionally, organic substrates can pose challenges in fine-pitch multilayer wiring and I / O’s for high-performance computing applications due to mis-registration of vias from layer to layer.

[0079] In particular, implementations of the present disclosure can improve the performance of Glass, a promising candidate for microelectronic packaging substrate. Glasscan have excellent electrical and high-temperature properties, low-cost potential, high modulus, tailorable CTE, smooth lithography surface, and a high glass transition temperature.

[0080] Despite its advantages, glass is susceptible to cracking under stress, especially during fabrication processes where copper and polymer deposition cause stress due to CTE mismatch. The susceptibility of glass to cracking has limited its consideration as a substrate. For example, the "free edge" effect during dicing and the impact of temperature excursions further contribute to the risk of cracking with glass substrates. Previous solutions have focused on optimizing the dicing process, improving interfacial adhesion, and reducing RDL (redistribution layer) thickness.

[0081] The exemplary processes for edge coating and dielectric pullback can improve the reliability of glass substrates by preventing failure due to cracking. Existing methods of applying coatings to glass substrates are manual, and are therefore limited to small-scale production. [1] [2]. Implementations of the present disclosure include methods of applying coatings to glass substrates that can be automated for high volume manufacturing.

[0082] The methods described herein further overcome limitations of existing methods that cut the glass pieces first and then cover them using an overmold compound. In such an approach, the glass panel is cut first, and then the individual glass pieces are placed on an encapsulating or overmold layer. This requires additional steps and complicates the process since the individual glass pieces need to be moved and placed onto the overmold or encapsulating layer. Moreover, conventional overmold and encapsulating may not have mechanical or electrical properties suitable for high-frequency applications.

[0083] Moreover, in example implementation described herein, the polymer coating thickness can be controlled more accurately by controlling the cut widths during dicing. The polymer dielectrics used in this invention can be polymer dielectrics used for redistribution layers or build-up layers, ensuring their suitability for high-frequency applications. The placement of glass and alignment of the subsequent build-up layers is also important. In this invention, the flow of the polymer are controlled to form grooves between the glass pieces. The grooves help in the further processing, alignment, and final dicing of the glass substrates.

[0084] The example implementations of the present disclosure can overcome these and other limitations of existing coatings, surface treatments, and other techniques for manufacturing glass substrates.

[0085] FIG. 5 shows an example process for edge coating of glass substrates in accordance with the present disclosure. A glass panel can be attached to a temporary carrier tape, dicing tape, or thermal / UV release tape. The carrier film can have an adhesive coating configured toadhere the glass panel to the carrier film. The adhesive coating can be releasable, such as by thermal or UV.

[0086] In the example shown in FIG. 5, the glass panel can be diced using mechanical, laser, or stealth dicing techniques. Dicing can be performed at the periphery of individual substrates or at locations where dicing streets would normally be located. The cuts can be made all the way through the glass panel or partially through, depending on the method of dicing. Dicing can optionally be done by mechanical sawing, laser cutting, or stealth dicing, as nonlimiting examples. Mechanical dicing can involve cutting or sawing using a rotating blade commonly used for wafer and panel dicing in semiconductor substrate manufacturing. Laser dicing can involve localized irradiation to cause local melting and vaporization of the underlying material. Stealth dicing may involve creating defects in the substrate in the dicing regions, followed by the application of an external force to separate the individual pieces. The example method can further include expanding the underlying carrier to apply a uniform tension in the peripheral direction. Scribing and breaking can also be used for the singulation of the glass pieces from the glass panel. FIG. 6 shows a magnified view of an example diced substrate.

[0087] The diced glass panel can optionally be cleaned to remove the debris formed due to cutting. The diced edges can be polished to make the edges smoother and to reduce the crack length.

[0088] The top surface of the diced panel can be coated / deposited / applied with polymer dielectric such that the diced regions can be partially or completely filled with polymer dielectric that flows into the spaces / trenches during application. The polymer application can be optimized to fill in the defects / cracks created during dicing. The polymer can cover the edges of the panel due to the flow of the polymer while application. The polymer coating can be on both sides of the glass. With both sides coated with additional build-up layers on both sides, chips or devices can be mounted on both sides.

[0089] In some implementations, one-sided polymer coating can be done. One-sided polymer can present advantages over conventional techniques which can require build-up layers on both sides to balance the stresses due to polymer and copper.

[0090] Dicing can create defects / cracks in the vicinity of the cuts. The polymer coating can be applied to partially or completely fill the dicing streets or the trenches created by dicing. The flow of the polymer into spaces / trenches can be caused by heating and / or pressure during the application of the polymer. In the example shown in FIGS. 5-6, the thickness of the polymer can be in the range of 1 micrometer to 500 micrometers. Optionally, the polymer thickness canbe larger than the glass panels, which can ensure complete filling of the trenches. Optionally, the temperature during the example polymer application can range from 70 to 300 degrees Celsius. Pressure values can range from 0.1 MPa to 10 MPa. Heating and pressure can optionally be applied simultaneously to achieve minimum melting viscosity of the polymer, typically in the range of 1000 to 100,000 Poise and between the temperature range of 70 to 300 degrees Celsius. For example, ABF GX92 has a minimum melt viscosity of 3700 Poise around 131 degree Celsius. Similarly other ABFs have minimum melt viscosity in the range 1000- 4000 Poise in the temperature range 120-140 degree Celsius. Optimization can be done by adjusting the temperature and pressure to have maximum flowability or minimum viscosity of the polymer.

[0091] Optionally, temporary carrier / thermal-release / UV-release tape can be released to make the bottom side of the glass panel available for processing. The release process can optionally involve applying UV, heat, and / or a certain temperature range.

[0092] The released side of the glass panel can be coated with polymer dielectric such that the polymer dielectric flows into the diced regions and fills up the trenches. Heat and / or pressure can be applied for the polymer to completely flow into the diced regions and cracks at the edges of the glass pieces. The polymer used in this step can be a different polymer and a different thickness. The polymer layers can be strong and / or thick enough to hold the pieces together. As such, the polymer may have an elastic modulus between 1 GPa to 50 GPa and / or a tensile strength between 10 MPa to 500 MPa. Optionally, the polymer dielectric on both sides of the diced can be thermal / UV cured for improved mechanical stability.

[0093] Using the substrate fabricated in FIGS. 5 and 6, additional build-up layers can be formed on the substrate. The first polymer dielectric can be used as a first layer on which the additional build-up layers can be formed. Vias can be formed in the polymer using laser, plasma, or photolithography.

[0094] Vias in substrates can be formed using laser drilling with the help of CO2, excimer, solid-state, UV, IR, nanosecond, picosecond, or femtosecond lasers. Optionally, vias in the polymer (e.g., vias formed in build-up layers) can connect to the existing metalized vias in the glass. Alternatively or additionally, vias can be formed through the polymer and glass at the time and then filled with metal. The vias can be completely filled or partially filled with metal. The aspect ratio of vias in polymer and / or glass can be in the range of 1 to 200.

[0095] After completion of build-up layers, dicing can be performed on top of the previous cuts. Dicing can be done over the grooves formed due to thinner stack up in the dicing streets.

[0096] The width of the dicing street or the width of the cut can be selected such that the first cut has a larger width than the second cut. This can create an excessive polymer coating around the edges of the diced panel. The excessive polymer coating can extend beyond the boundaries of the glass pieces. The excessive polymer layer can act as an edge coating, preventing the cracking of glass substrate. As a non-limiting example, the first cut can be 10 micrometers to 1000 micrometers in width. The second cut can be smaller than the first cut, ranging from 10 micrometers to 1000 micrometers. Optionally, the width of the first cut can optionally be zero (e.g., in implementations using stealth dicing). However, the separation between the individual glass pieces after dicing can be in the range of 10 micrometers to 1000 micrometers. Optionally, the second dicing step can also use stealth dicing. Optionally, wider cuts can be formed by using a wider blade or by doing multiple cuts using a thin blade (e.g., the same or different blade as the narrower cut).

[0097] The second dicing step can be done on a completely packaged system after assembly of chips, chiplets, devices, components or a combination thereof. In some case, the chips and devices are attached to the substrate by appropriate bonding techniques. The bonded chips and devices can also be attached with an overmold. The second dicing step can be performed on completely packaged substrates. The chips can be attached using solder, copper micropillars, copper-copper bonding, or hybrid bonding. An example of dicing after chip assembly is shown in FIG. 7.

[0098] As non-limiting examples, the polymer dielectrics described herein can be gap-fill polymer, overmold compound, liquid dielectric, and / or laminate films (alone or in combination). These are different types of polymers used in packaging. These polymer types have different properties with respect to mechanical, electrical, and thermal properties and filler content. It should be understood that the type of polymer dielectrics can be performed based on the application, for example, 5G, RF, data centers, Al chips, etc.

[0099] The glass panel can include through vias and / or through / blind cavities distributed over the panel area. The vias in the build-up layer can be connected to the vias in the glass. The alignment can be done by having alignment structures on the glass panel. Or the existing vias in glass can be used for alignment. The vias in glass and polymer can be formed after the polymer application after the first dicing step. The vias formed in this step can serve as alignment guides for aligning all subsequent layers. FIG. 8 shows an example process for forming glass substrates with cavities.

[0100] In some implementations of the present disclosure, a large glass panel can be separated into multiple glass pieces. The glass pieces can be covered in a polymer dielectric onall sides of the glass pieces including the top and bottom surfaces and at the edges. Build-up layers can be formed on the glass pieces covered in the polymer. After the completion of the substrate with multiple build-up layers, the individual glass substrates can be separated or singulated.

[0101] In some implementations of the present disclosure, a large glass panel can be diced into smaller glass pieces on an adhesive carrier film. A polymer dielectric can be applied to the diced glass pieces on the first surface. The temporary carrier can be de -bonded. The de-bonded side can be applied with a polymer layer. Pressure and heat can be applied to fill up the spaces between the individual glass pieces with polymer. The polymer layers can be cured with heat or UV radiation. A composite panel, including glass pieces covered with polymer, can be formed. Multiple redistribution layers, including polymer and metal (typically copper), can be formed to complete the substrate. Chips can optionally be attached after the completion of the substrate. The completed substrates, with or without assembled chips, can be singulated or diced over the same dicing streets that were formed in the initial dicing step. The cut width in this second dicing step can be smaller than the first dicing step. This can be done to leave a layer of polymer coating on the edges of the substrates extending beyond the area of the glass cores.As yet additional example features, The cut width in the ‘first cutting step’ can be larger than the cut width in the ‘second cutting step’. The large glass panel can have either through vias, cavities, through vias filled with metal, metal layer, polymer layer, or any combination thereof. The glass panel can have a thickness in the range of 1 micrometer to 500 micrometers. The glass substrate can have the ratio of a total thickness of build-up layers to the thickness of glass equal to or greater than 0.2. The glass substrate can have a total thickness of build-up layers greater than or equal to 80 micrometers. The glass substrate can have a total thickness of polymer layers on either side of the glass greater than or equal to 60 micrometers. The large glass panel can have a width dimension between 100 millimeters and 1000 millimeters, a length dimension between 100 millimeters and 1000 millimeters, and a thickness dimension between 1 micrometer and 1000 millimeters.

[0102] The polymer dielectric used for covering the glass panel and for forming build-up layers can be the same polymer. The glass substrate can have excessive polymer dielectric coating on the side of a glass or at the edge of the substrate extending beyond the edge of the individual glass piece by 1 micrometer to 500 micrometers. A rectangular glass substrate can have its size ranging from 1 millimeter to 500 millimeters on a side. A semiconductor substrate or interposer can have the glass core cut from a larger glass panel. The glass core can havecracks or microcracks at the edges, sides, or on any of its surfaces due to the cutting process. The polymer can occupy the cracks partially or completely, thus preventing crack propagation and preventing failure. The polymer coating can extend beyond the edge of the glass core, forming a barrier against further cracking of glass.

[0103] The semiconductor substrate can have multiple metal and polymer layers forming the redistribution layers. Chips or chiplets or devices or components can be connected on the substrate before the final dicing or cutting process. For certain applications such as radiofrequency or 5G or 6G applications, a thicker polymer dielectric can be beneficial to attend to certain performance characteristics such as gain, losses, or power efficiency. The semiconductor substrate can have the thickness of build-up layers or polymer layers on either side of the glass core thicker than the glass core thickness. A semiconductor substrate used for high-frequency or radio-frequency, 5G, millimeter-wave, or 6G applications can comprise of antenna structures, passive structures, waveguides, or a combination thereof.

[0104] The glass panel or substrate can have a through cavity for embedding components. The edges or sides of the cavity can be coated with the polymer dielectric during the application steps. The edges of diced or cut glass pieces and the edges of the cavity can be coated at the same time. The initial glass panel can have multiple cavities with a variety of sizes. Pressure, heat and thickness of polymer can be optimized during application.

[0105] The panel including glass pieces covered with polymer dielectric can have a non- uniform topography. The topography can include trenches or grooves at the location of the first dicing streets. An example topography after various process steps is shown in FIG. 10. The polymer coating or edge coating can be continuous, where the first build-up layer on either side of the glass extends beyond the glass core to form a continuous polymer coating. The polymer layer of build-up layer can be rounded at the edges of the glass core.

[0106] The overall thickness can be smaller in the dicing streets than at the middle of the glass substrate or average thickness over the glass substrate. The total thickness in the dicing streets can be approximately equal to the thickness of the polymer layers.

[0107] The polymer filled in the spaces between the individual glass pieces can form groove-like structures due to the absence of a glass core in those areas. These grooves can be used as alignment marks for processing and as dicing streets for the second dicing step.

[0108] Planarization can be done after polymer application to minimize the thickness variation or to make the surface substantially flat. FIG. 10 shows an example of planarization.

[0109] The polymer dielectric can optionally be a dry -film polymers with or without filler used in traditional build-up layers, such as Ajinomoto build-up films (ABF), polyimide, benzocyclobutene, and epoxy. The glass edges can be partially covered with polymer in the first polymer application step. The remaining glass edges can be again partially covered during the second polymer application step. The glass edges can be partially covered or completely covered after the polymer application steps.

[0110] In one aspect, provided is a method of manufacturing a glass substrate, the method comprising: placing a large glass panel or wafer on a temporary carrier film, cutting the large glass panel or wafer into smaller pieces in the ‘first cutting step’, covering the first surface of glass pieces with a polymer dielectric without removing the glass pieces from the temporary carrier film, separating the glass pieces from the carrier film to expose the second surface of the glass pieces, covering the second surface of glass pieces with a polymer dielectric, forming a structure of glass pieces sandwiched between polymer dielectric layers on first surface and second surface, applying pressure and / or heat to increase the flowability of polymer dielectric, curing the polymer dielectric by applying heat or radiation, forming build-up layers with multiple layers of polymer and metal, assembling chips / chiplets / devices / components on buildup layers, separating the assembly of chips / devices, build-up layers, and glass pieces into individual glass substrates in the ‘second cutting step’.

[0111] In some aspects, the cut width in the ‘first cutting step’ can be larger than the cut width in the ‘second cutting step’.

[0112] In some aspects, the glass panel can include one or a combination of through glass vias, metal pattern, metalized through glass vias, or polymer coating.

[0113] In some aspects, the glass panel can have a thickness in the range of 1 micrometer to 500 micrometers.

[0114] In some aspects, the glass substrate can have a ratio of a total thickness of build-up layers to the thickness of glass equal to or greater than 0.5.

[0115] In some aspects, the glass substrate can have a total thickness of build-up layers greater than or equal to 80 micrometers.

[0116] In some aspects, the glass substrate can have a total thickness of polymer dielectric layers on either side of glass greater than or equal to 60 micrometers.

[0117] In some aspects, the same polymer dielectric can be used for covering the glass panel and for forming more than one buildup layers.

[0118] In some aspects, the glass substrate can have excessive polymer dielectric at the edge of the completed substrate extending beyond the edge of the individual glass piece by 1 micrometer to 500 micrometer.

[0119] In another aspect, provided is a rectangular glass substrate having a size ranging from 1 millimeter to 500 millimeters on a side.

[0120] In yet another aspect, provided is a semiconductor substrate or interposer comprising: a glass core cut from a larger glass panel, glass core having cracks or microcracks in the regions where it was cut, a polymer material occupying the cracks partially or completely, the polymer material extending beyond the edge of the glass core forming a barrier against further cracking of glass.

[0121] In some aspects, the semiconductor substrate can include multiple metal and polymer layers forming the redistribution layers.

[0122] In some aspects, the semiconductor substrate can have a thickness of redistribution layers on either side of glass core thicker than the glass core thickness.

[0123] In another aspect, provided is a semiconductor device comprising: any of the disclosed semiconductor substrates, chips or chiplets connected to the substrate, and a printed circuit board connected to the substrate.

[0124] In yet another aspect, provided is a semiconductor substrate used for high-frequency or radio-frequency, 5G, millimeter-wave, or 6G applications comprising: antenna structures, passive structures, and / or waveguides.

[0125] In yet another aspect, provided is a glass substrate including one or more through cavities where the cavities are coated while applying a polymer to cover the edges of the cavities.

[0126] In yet another aspect, provided is a glass substrate including polymer coating on all sides with a rounded profile around the edges.

[0127] In yet another aspect, provided is a panel substrate including multiple glass pieces covered with polymer coating, including a separation between the individual pieces filled with polymer, with the polymer in the spaces having a smaller thickness thus forming a groove-like structure.

[0128] In yet another aspect, provided is a method of forming a glass panel substrate, where polymer layers are partially or completely removed to achieve thickness uniformity.

[0129] The following patents, applications and publications as listed below and throughout this document are hereby incorporated by reference in their entirety herein.Reference list[1] Process Innovations to Prevent Glass Substrate Fracture From RDL Stress and Singulation Defects, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 16, NO. 4, DECEMBER 2016[2] New structure of microelectronic packages with edge protection by coating, US20160111380A1[3] Embedded glass core patch, W02023049540A, US20230085646A1.

Claims

What is claimed is:

1. A method of manufacturing a glass substrate, the method comprising: placing a glass panel or wafer on a temporary carrier film; cutting the glass panel or wafer in pieces in a first cutting operation; encapsulating a first surface of the glass pieces with a polymer dielectric; removing the temporary carrier film to expose a second surface of glass pieces; encapsulating the second surface of glass pieces with the polymer dielectric, thereby forming a structure of glass pieces sandwiched between polymer dielectric layers on the first surface and second surface; applying a pressure or a temperature to the polymer dielectric; curing the polymer dielectric; forming a plurality of build-up layers on each of the glass pieces, wherein each buildup layer comprises a polymer layer and a metal layer; mounting an electronic component on the plurality of build-up layers of each of the glass pieces; and separating the glass pieces into individual glass substrates in a second cutting operation.

2. The method of claim 1, wherein the first cutting operation defines a first width, and the second cutting operation defines a second width, and the first width is larger than the second width.

3. The method of claim 1 or 2, wherein the glass panel has one or a combination of through glass vias, metal pattern, metallized through glass vias or polymer coating.

4. The method of any one of claims 1-3, wherein the glass panel and glass pieces have a thickness from 1 micrometer to 500 micrometers.

5. The method of any one of claims 1-4, wherein the glass substrate has a ratio of total thickness of build-up layers to the thickness of glass equal to or greater than 0.5.

6. The method of any one of claims 1-5, wherein the glass substrate has a total thickness of build-up layers greater than or equal to 80 micrometers.

7. The method of any one of claims 1-6, wherein a total thickness of polymer dielectric layers on either side of the glass pieces is greater than or equal to 60 micrometers.

8. The method of any one of claims 1-7, wherein the polymer dielectric and the polymer layers comprise a single type of polymer dielectric.

9. The method of any one of claims 1-8, wherein the glass substrate has excessive polymer dielectric at an edge of the glass substrate extending beyond the edge of each of the glass pieces by 1 micrometer to 500 micrometer.

10. The method of any one of claims 1-9, wherein the pressure is between 0.1 MPa and 10 MPa.

11. The method of any one of claims 1-10, wherein the temperature is between 70 to 300 degrees Celsius.

12. The method of any one of claims 1-11, wherein polymer layers are partially or completely removed or planarized to achieve thickness uniformity.

13. An electronic device comprising: a glass piece comprising a first side and a second side, wherein the first side and the second side are encapsulated by a polymer dielectric at least one build-up layer formed on the glass piece; and an electronic component formed on the at least one build-up layer.

14. The electronic device of claim 13, wherein the glass piece comprises an excess polymer dielectric edge extending beyond the edge of the glass piece by 1 micrometer to 500 micrometer.

15. The electronic device of claim 13 or claim 14, wherein the glass piece comprises at least one crack filled by a portion of the polymer dielectric.

16. The electronic device of any one of claims 13-15, wherein the electronic component is a chiplet.

17. The electronic device of any one of claims 13-16, wherein the at least one build-up layer or polymer dielectric define at least one rounded edge.

18. The electronic device of any one of claims 13-17, wherein the electronic device is a component of a high-frequency system, radio-frequency system, 5G system, millimeter-wave system or 6G system.

19. The electronic device of any one of claims 13-18, wherein the glass piece further comprises a cavity defining a cavity surface, and wherein the polymer dielectric covers a portion of the cavity surface.

20. A semiconductor substrate or interposer comprising: a glass core comprising at least one cut surface and an edge, wherein the at least one cut surface comprises a crack or microcrack; a polymer material partially or completely occupying the cracks or microcracks, wherein the polymer material extends beyond the edge of the glass core and is configured as a barrier to prevent cracking of the glass core.

21. The semiconductor substrate or interposer of claim 20, having multiple metal and polymer layers forming a plurality of redistribution layers.

22. The semiconductor substrate or interposer of claim 21, wherein the redistribution layers are thicker than the glass core.

23. A semiconductor device comprising: semiconductor substrate or interposer of claim 20, chips or chiplets connected to the substrate, the substrate connected to a printed circuit board.

24. A high-frequency or radio-frequency or 5G or millimeter-wave or 6G system comprising: semiconductor substrate or interposer of claim 20, antenna structures, passive structures, waveguides.

25. A method of edge coating a glass substrate, the method comprising: a) applying a carrier / dicing film to a first side of a glass panel; b) cutting the glass panel into a plurality of glass substrates, wherein a first side of the plurality of glass substrates remains attached to the carrier / dicing film; c) applying a first polymer to a second side of the plurality of glass substrates, wherein the first polymer at least partially fills cuts between glass substrates;d) removing the carrier / dicing film and applying a second polymer to the first side of the plurality of glass substrates, wherein the second polymer at least partially fills cuts between glass substrates; e) optionally forming one or more build-up layers on the first side and / or the second side of the plurality of glass substrates; and f) cutting the polymer between each of the plurality of glass substrates, thereby forming a plurality of edge-coated glass substrates.

26. The method of claim 25, further comprising assembling a chip on each of the plurality of glass substrates either before or after step f).

27. The method of claim 25 or claim 26, further comprising planarizing one or both sides of the plurality of glass substrates after step c) and / or after step d).

28. An edge-coated glass substrate formed by the method of any one of claims 25-27.

Images