Pixel driving circuit, display panel, and display device

Abstract

The present disclosure relates to the technical field of display, and provides a pixel driving circuit, a display panel, and a display device. The pixel driving circuit comprises: at least one driving circuit, a data writing circuit, a compensation circuit, and a redundant circuit. The driving circuit comprises a control signal end and two current transmission ends; the two current transmission ends comprise a first current transmission end and a second current transmission end; the driving circuit is used for forming a driving current between the two current transmission ends on the basis of a signal of the control signal end; and the at least one driving circuit comprises a first driving circuit. The data writing circuit is connected to the first current transmission end of the first driving circuit and a data signal end; and the data writing circuit is used for responding to a control signal to transmit a signal of the data signal end to the first current transmission end of the first driving circuit. The compensation circuit is connected to the second current transmission end and control signal end of the first driving circuit, and a first gate driving signal end; and the compensation circuit is used for responding to a signal of the first gate driving signal end to turn on the control signal end and second current transmission end of the first driving circuit. The redundant circuit comprises a redundant compensation circuit; the redundant compensation circuit is connected between a control signal end and one current transmission end of one driving circuit; and the redundant compensation circuit is used for responding to a control signal to turn on the control signal end and current transmission end which are connected to the redundant compensation circuit. The pixel driving circuit facilitates repair.

Description

Pixel driving circuit, display panel, display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit, a display panel, and a display device. Background Art

[0002] In the related art, the gate of the second transistor in the pixel driving circuit is prone to leak electricity to the gate of the driving transistor, thereby causing abnormal display of the display panel.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] According to one aspect of the present disclosure, a pixel driving circuit is provided, wherein the pixel driving circuit includes:

[0006] at least one driving circuit, the driving circuit comprising a control signal terminal and two current transmission terminals, the two current transmission terminals comprising a first current transmission terminal and a second current transmission terminal, the driving circuit being configured to generate a driving current between the two current transmission terminals according to a signal from the control signal terminal, the at least one driving circuit comprising a first driving circuit;

[0007] a data writing circuit connected to the first current transmission terminal and the data signal terminal of the first driving circuit, the data writing circuit being configured to respond to a control signal to transmit a signal from the data signal terminal to the first current transmission terminal of the first driving circuit;

[0008] a compensation circuit connected to the second current transmission terminal, the control signal terminal, and the first gate drive signal terminal of the first drive circuit, the compensation circuit being configured to conduct the control signal terminal and the second current transmission terminal of the first drive circuit in response to a signal at the first gate drive signal terminal;

[0009] A redundant circuit, comprising a redundant compensation circuit, wherein the redundant compensation circuit is connected between a control signal terminal and a current transmission terminal of the driving circuit, and the redundant compensation circuit is used to respond to a control signal to conduct the control signal terminal and the current transmission terminal connected thereto.

[0010] In an exemplary embodiment of the present disclosure, the redundant compensation circuit is connected to the control signal terminal and the second current transmission terminal of the first driving circuit, and the redundant compensation circuit is used to respond to a control signal to turn on the control signal terminal and the second current transmission terminal of the first driving circuit.

[0011] In an exemplary embodiment of the present disclosure, the redundancy compensation circuit is connected to the control signal terminal and the first current transmission terminal of the first driving circuit, and the redundancy compensation circuit is configured to conduct the control signal terminal and the first current transmission terminal of the first driving circuit in response to a control signal;

[0012] The redundant circuit further includes:

[0013] The redundant data writing circuit is connected to the second current transmission end and the data signal end of the first driving circuit, and is used to respond to a control signal to transmit the data signal of the data signal end to the second current transmission end of the first driving circuit.

[0014] In an exemplary embodiment of the present disclosure, at least one driving circuit includes a second driving circuit;

[0015] The redundant compensation circuit is connected to a control signal terminal and a current transmission terminal of the second driving circuit, and is used for responding to a control signal to conduct the control signal terminal and the current transmission terminal of the second driving circuit.

[0016] In an exemplary embodiment of the present disclosure, the first current transmission terminal of the first driving circuit is connected to the first current transmission terminal of the second driving circuit;

[0017] The redundancy compensation circuit is connected to the control signal terminal and the second current transmission terminal of the second driving circuit, and is used for responding to a control signal to conduct the control signal terminal and the second current transmission terminal of the second driving circuit.

[0018] In an exemplary embodiment of the present disclosure, the pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit further includes:

[0019] a light-emitting control circuit connected to a first power supply terminal, a first current transmission terminal of the first driving circuit, a second current transmission terminal of the first driving circuit, an enable signal terminal, and a first electrode of the light-emitting unit, the light-emitting control circuit being configured to connect the first power supply terminal and the first current transmission terminal of the first driving circuit in response to a signal from the enable signal terminal, and to connect the second current transmission terminal of the first driving circuit and the first electrode of the light-emitting unit in response to a signal from the enable signal terminal;

[0020] a first reset circuit, the first reset circuit being connected to the second current transmission terminal of the first driving circuit, the first initial signal terminal, and the first reset signal terminal, the first reset circuit being configured to respond to a signal at the first reset signal terminal to transmit a signal at the first initial signal terminal to the second current transmission terminal of the first driving circuit;

[0021] a second reset circuit connected to the first electrode of the light-emitting unit, the second initial signal terminal, and the second reset signal terminal, the second reset circuit being configured to respond to a signal at the second reset signal terminal to transmit a signal at the second initial signal terminal to the first electrode of the light-emitting unit;

[0022] a storage circuit connected between the control signal terminal of the first driving circuit and the first power supply terminal;

[0023] The redundant circuit further includes:

[0024] a redundant light-emitting control circuit connected to a first power supply terminal, a first current transmission terminal of the second driving circuit, a second current transmission terminal of the second driving circuit, and a first electrode of the light-emitting unit, the redundant light-emitting control circuit being configured to connect the first power supply terminal to the first current transmission terminal of the second driving circuit, and connect the second current transmission terminal of the second driving circuit to the first electrode of the light-emitting unit in response to a control signal;

[0025] A redundant first reset circuit is connected to the second current transmission end and the first initial signal end of the second driving circuit, and the first reset circuit is used to respond to a control signal to transmit the signal of the first initial signal end to the second current transmission end of the second driving circuit.

[0026] The redundant storage circuit is connected between the control signal terminal of the second driving circuit and the first power supply terminal.

[0027] In an exemplary embodiment of the present disclosure, the pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit further includes:

[0028] a light-emitting control circuit connected to a first power supply terminal, a first current transmission terminal of the first driving circuit, a second current transmission terminal of the first driving circuit, an enable signal terminal, and a first electrode of the light-emitting unit, the light-emitting control circuit being configured to connect the first power supply terminal and the first current transmission terminal of the first driving circuit in response to a signal from the enable signal terminal, and to connect the second current transmission terminal of the first driving circuit and the first electrode of the light-emitting unit in response to a signal from the enable signal terminal;

[0029] a second reset circuit connected to the first electrode of the light-emitting unit, the second initial signal terminal, and the second reset signal terminal, the second reset circuit being configured to respond to a signal at the second reset signal terminal to transmit a signal at the second initial signal terminal to the first electrode of the light-emitting unit;

[0030] a third reset circuit, connected to the first current transmission terminal, the third initial signal terminal, and the second reset signal terminal of the first driving circuit, the third reset circuit being configured to respond to a signal from the second reset signal terminal to transmit a signal from the third initial signal terminal to the first current transmission terminal of the first driving circuit;

[0031] The storage circuit is connected between the control signal terminal of the first driving circuit and the first power supply terminal.

[0032] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes:

[0033] A first reset circuit, wherein the first reset circuit is connected to the control signal terminal, the first initial signal terminal, and the first reset signal terminal of the first driving circuit, and the first reset circuit is used to respond to the signal of the first reset signal terminal to transmit the signal of the first initial signal terminal to the control signal terminal of the first driving circuit.

[0034] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes:

[0035] A first reset circuit, wherein the first reset circuit is connected to the second current transmission end, the first initial signal end, and the first reset signal end of the first drive circuit, and the first reset circuit is used to respond to the signal of the first reset signal end to transmit the signal of the first initial signal end to the second current transmission end of the first drive circuit.

[0036] In an exemplary embodiment of the present disclosure, the first driving circuit includes:

[0037] a first driving transistor, wherein a gate of the first driving transistor forms a control signal terminal of the first driving circuit, a first electrode of the first driving transistor forms a first current transmission terminal of the first driving circuit, and a second electrode of the first driving transistor forms a second current transmission terminal of the first driving circuit;

[0038] The data writing circuit includes:

[0039] a fourth transistor, wherein a first electrode of the fourth transistor is connected to the data signal terminal, a second electrode of the fourth transistor is connected to the first electrode of the first driving transistor, and a gate of the fourth transistor is connected to a second gate driving signal terminal;

[0040] The compensation circuit comprises:

[0041] A second transistor, wherein a first electrode of the second transistor is connected to the gate of the first driving transistor, a second electrode of the second transistor is connected to the second electrode of the first driving transistor, and a gate of the second transistor is connected to the first gate driving signal terminal.

[0042] In an exemplary embodiment of the present disclosure, the redundancy compensation circuit includes:

[0043] A redundant second transistor, wherein a first electrode of the redundant second transistor is connected to the control signal terminal of the first driving circuit, and a second electrode of the redundant second transistor is connected to the second current transmission terminal of the first driving circuit.

[0044] In an exemplary embodiment of the present disclosure, the redundancy compensation circuit includes:

[0045] a redundant second transistor, wherein a first electrode of the redundant second transistor is connected to the control signal terminal of the first driving circuit, and a second electrode of the redundant second transistor is connected to the first current transmission terminal of the first driving circuit;

[0046] The redundant data writing circuit includes:

[0047] A redundant fourth transistor, wherein a first electrode of the redundant fourth transistor is connected to the data signal end, and a second electrode of the redundant fourth transistor is connected to the second current transmission end of the first driving circuit.

[0048] In an exemplary embodiment of the present disclosure, the second driving circuit includes:

[0049] a second driving transistor, wherein the gate of the second driving transistor forms a control signal terminal of the second driving current, the first electrode of the second driving transistor forms a first current transmission terminal of the second driving circuit, and the second electrode of the second driving transistor forms a second current transmission terminal of the second driving circuit;

[0050] The redundancy compensation circuit includes:

[0051] a redundant second transistor, wherein a first electrode of the redundant second transistor is connected to the gate of the second driving transistor, and a second electrode of the redundant second transistor is connected to the second electrode of the second driving transistor;

[0052] In an exemplary embodiment of the present disclosure, the light emitting control circuit includes:

[0053] a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power supply terminal, a second electrode of the fifth transistor is connected to the first current transmission terminal of the first driving circuit, and a gate of the fifth transistor is connected to the enable signal terminal;

[0054] a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second current transmission terminal of the first driving circuit, a second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, and a gate of the sixth transistor is connected to the enable signal terminal;

[0055] The first reset circuit includes:

[0056] a first transistor, wherein a first electrode of the first transistor is connected to the first initial signal terminal, a second electrode is connected to the second current transmission terminal of the first driving circuit, and a gate is connected to the first reset signal terminal;

[0057] The second reset circuit includes:

[0058] a seventh transistor, wherein a first electrode of the seventh transistor is connected to the second initial signal terminal, a second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, and a gate of the seventh transistor is connected to the second reset signal terminal;

[0059] The storage circuit includes:

[0060] a capacitor, wherein a first electrode of the capacitor is connected to the control signal terminal of the first driving circuit, and a second electrode of the capacitor is connected to the first power supply terminal;

[0061] The redundant light emitting control circuit includes:

[0062] a redundant fifth transistor, wherein a first electrode of the redundant fifth transistor is connected to the first power supply terminal, and a second electrode of the redundant fifth transistor is connected to the first current transmission terminal of the second driving circuit;

[0063] a redundant sixth transistor, wherein a first electrode of the redundant sixth transistor is connected to the second current transmission end of the second driving circuit, and a second electrode of the redundant sixth transistor is connected to the first electrode of the light-emitting unit;

[0064] The redundant first reset circuit includes:

[0065] a redundant first transistor, wherein a first electrode of the redundant first transistor is connected to the first initial signal terminal, and a second electrode of the redundant first transistor is connected to the second current transmission terminal of the second driving circuit;

[0066] The redundant storage circuit comprises:

[0067] A redundant capacitor, wherein a first electrode of the redundant capacitor is connected to the control signal terminal of the second driving circuit, and a second electrode of the redundant capacitor is connected to the first power supply terminal.

[0068] In an exemplary embodiment of the present disclosure, the light emitting control circuit includes:

[0069] a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power supply terminal, a second electrode of the fifth transistor is connected to the first current transmission terminal of the first driving circuit, and a gate of the fifth transistor is connected to the enable signal terminal;

[0070] a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second current transmission terminal of the first driving circuit, a second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, and a gate of the sixth transistor is connected to the enable signal terminal;

[0071] The second reset circuit includes:

[0072] a seventh transistor, wherein a first electrode of the seventh transistor is connected to the second initial signal terminal, a second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, and a gate of the seventh transistor is connected to the second reset signal terminal;

[0073] The third reset circuit includes:

[0074] an eighth transistor, wherein a first electrode of the eighth transistor is connected to the third initial signal terminal, a second electrode of the eighth transistor is connected to the first current transmission terminal of the first driving circuit, and a gate of the eighth transistor is connected to the second reset signal terminal;

[0075] The storage circuit includes:

[0076] A capacitor, wherein a first electrode of the capacitor is connected to the control signal terminal of the first driving circuit, and a second electrode of the capacitor is connected to the first power supply terminal.

[0077] In an exemplary embodiment of the present disclosure, the first reset circuit includes:

[0078] A first transistor, wherein a first electrode of the first transistor is connected to the first initial signal terminal, a second electrode is connected to the control signal terminal of the first driving circuit, and a gate is connected to the first reset signal terminal.

[0079] In an exemplary embodiment of the present disclosure, the first reset circuit includes:

[0080] A first transistor, wherein a first electrode of the first transistor is connected to the first initial signal terminal, a second electrode is connected to the second current transmission terminal of the first driving circuit, and a gate is connected to the first reset signal terminal.

[0081] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes the above-mentioned pixel driving circuit.

[0082] In an exemplary embodiment of the present disclosure, in at least part of the pixel driving circuit, the connection between the channel region of the transistor in the compensation circuit and the control signal terminal of the first driving circuit is interrupted.

[0083] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes a pixel driving circuit, and the pixel driving circuit includes:

[0084] a first driving transistor;

[0085] a fourth transistor, a first electrode of which is connected to the data line, and a second electrode of which is connected to the first electrode of the first driving transistor;

[0086] a second transistor, a first electrode of which is connected to the gate of the first driving transistor, and a second electrode of which is connected to the second electrode of the first driving transistor;

[0087] A redundant second transistor has a first electrode connected to the gate of the first driving transistor, and the redundant second transistor is used to write a compensation voltage into the gate of the first driving transistor.

[0088] In an exemplary embodiment of the present disclosure, the second electrode of the redundant second transistor is connected to the second electrode of the first driving transistor, and the display panel further includes:

[0089] substrate;

[0090] a first active layer located on one side of the base substrate, the first active layer comprising a third active portion and a fourth active portion, the third active portion being used to form a channel region of the first driving transistor, and the fourth active portion being used to form a channel region of the fourth transistor;

[0091] a first gate layer, located on a side of the first active layer facing away from the base substrate, the first gate layer comprising a first conductive portion and a second gate line, an orthographic projection of the first conductive portion on the base substrate overlapping an orthographic projection of the third active portion on the base substrate, the first conductive portion being used to form a gate of the first driving transistor, an orthographic projection of the second gate line on the base substrate extending along the first direction and covering an orthographic projection of the fourth active portion on the base substrate, and a portion of the second gate line being used to form a gate of the fourth transistor;

[0092] a second active layer, located on a side of the first gate layer facing away from the base substrate, the second active layer comprising a second active portion and a redundant second active portion, the second active portion being used to form a channel region of the second transistor, and the redundant second active portion being used to form a channel region of the redundant second transistor;

[0093] A third gate layer is located on a side of the second active layer facing away from the base substrate, the third gate layer includes a first gate line and a redundant first gate line, the orthographic projection of the first gate line on the base substrate extends along the first direction and covers the orthographic projection of the second active portion on the base substrate, a partial structure of the first gate line is used to form a top gate of the second transistor, the orthographic projection of the redundant first gate line on the base substrate extends along the first direction and covers the orthographic projection of the redundant second active portion on the base substrate, and a partial structure of the redundant first gate line is used to form a top gate of the redundant second transistor.

[0094] In an exemplary embodiment of the present disclosure, in the same pixel driving circuit:

[0095] The orthographic projection of the first gate line on the substrate is located between the orthographic projection of the second gate line on the substrate and the orthographic projection of the first conductive portion on the substrate, and the orthographic projection of the redundant first gate line on the substrate is located between the orthographic projection of the second gate line on the substrate and the orthographic projection of the first gate line on the substrate.

[0096] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, a second electrode is connected to a second electrode of the first driving transistor, and a gate is connected to a first reset signal line;

[0097] The orthographic projection of the first reset signal line on the base substrate extends along the first direction;

[0098] In the same pixel driving circuit: the orthographic projection of the redundant first gate line on the substrate is located between the orthographic projection of the first reset signal line on the substrate and the orthographic projection of the first gate line on the substrate, and the orthographic projection of the second gate line on the substrate is located between the orthographic projection of the first gate line on the substrate and the orthographic projection of the redundant first gate line on the substrate.

[0099] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a fifth transistor, a first electrode of the fifth transistor being connected to the first power line, and a second electrode of the fifth transistor being connected to the first electrode of the first driving transistor;

[0100] The first active layer further includes a fifth active portion, wherein the fifth active portion is used to form a channel region of the fifth transistor;

[0101] In the first direction of the same pixel driving circuit, an orthographic projection of the redundant second active portion on the base substrate is located between an orthographic projection of the second active portion on the base substrate and an orthographic projection of the fifth active portion on the base substrate.

[0102] In an exemplary embodiment of the present disclosure, the display panel further includes a light emitting unit, and the pixel driving circuit further includes a first transistor and a sixth transistor;

[0103] The first electrode of the first transistor is connected to the first initial signal line, the second electrode is connected to the second electrode of the first driving transistor, and the gate is connected to the first reset signal line;

[0104] The first electrode of the sixth transistor is connected to the second electrode of the first driving transistor, and the second electrode is connected to the first electrode of the light emitting unit;

[0105] The second active layer further comprises:

[0106] a twentieth active portion connected to a side of the second active portion away from the redundant second active portion;

[0107] a twenty-first active portion connected to a side of the redundant second active portion away from the second active portion;

[0108] The first active layer further comprises:

[0109] a first active portion, wherein the first active portion is used to form a channel region of the first transistor;

[0110] a seventeenth active portion connected to one side of the first active portion;

[0111] a ninth active portion connected between the third active portion and the sixth active portion;

[0112] The display panel further includes:

[0113] The first source-drain layer is located on a side of the third gate layer away from the base substrate, and the first source-drain layer includes a first bridge portion, which is connected to the 20th active portion, the 21st active portion, the 17th active portion, and the 9th active portion through vias respectively.

[0114] In an exemplary embodiment of the present disclosure, the second electrode of the redundant second transistor is connected to the first electrode of the first driving transistor, and the pixel driving circuit further includes:

[0115] A redundant fourth transistor has a first electrode connected to the data signal terminal and a second electrode connected to the second electrode of the first driving transistor.

[0116] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0117] substrate;

[0118] a first active layer located on one side of the base substrate, the first active layer comprising a third active portion, a fourth active portion, and a redundant fourth active portion, the third active portion being used to form a channel region of the first driving transistor, the fourth active portion being used to form a channel region of the fourth transistor, and the redundant fourth active portion being used to form a channel region of the redundant fourth transistor;

[0119] a first gate layer, located on a side of the first active layer facing away from the base substrate, the first gate layer comprising a first conductive portion, a second gate line, and a redundant second gate line segment, the orthographic projection of the first conductive portion on the base substrate overlapping the orthographic projection of the third active portion on the base substrate, the first conductive portion being used to form the gate of the first driving transistor, the orthographic projection of the second gate line on the base substrate extending along a first direction and covering the orthographic projection of the fourth active portion on the base substrate, a partial structure of the second gate line being used to form the gate of the fourth transistor, the orthographic projection of the redundant second gate line segment on the base substrate covering the orthographic projection of the redundant fourth active portion on the base substrate, and a partial structure of the redundant second gate line segment being used to form the gate of the redundant fourth transistor;

[0120] a second active layer, located on a side of the first gate layer facing away from the base substrate, the second active layer comprising a second active portion and a redundant second active portion, the second active portion being used to form a channel region of the second transistor, and the redundant second active portion being used to form a channel region of the redundant second transistor;

[0121] A third gate layer is located on a side of the second active layer facing away from the base substrate, the third gate layer includes a first gate line and a redundant first gate line, the orthographic projection of the first gate line on the base substrate extends along the first direction and covers the orthographic projection of the second active portion on the base substrate, a partial structure of the first gate line is used to form a top gate of the second transistor, the orthographic projection of the redundant first gate line on the base substrate extends along the first direction and covers the orthographic projection of the redundant second active portion on the base substrate, and a partial structure of the redundant first gate line is used to form a top gate of the redundant second transistor.

[0122] In an exemplary embodiment of the present disclosure, in the same pixel driving circuit:

[0123] The orthographic projection of the first gate line on the substrate is located between the orthographic projection of the second gate line on the substrate and the orthographic projection of the first conductive portion on the substrate, the orthographic projection of the redundant first gate line on the substrate is located between the orthographic projection of the second gate line on the substrate and the orthographic projection of the first gate line on the substrate, and the orthographic projection of the redundant second gate line segment on the substrate is located on a side of the orthographic projection of the second gate line on the substrate away from the orthographic projection of the first gate line on the substrate.

[0124] In an exemplary embodiment of the present disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit further includes a sixth transistor, wherein a first electrode of the sixth transistor is connected to a second electrode of the first driving transistor, and a second electrode is connected to a first electrode of the light-emitting unit;

[0125] The first active layer further comprises:

[0126] a sixth active portion, the sixth active portion being configured to form a channel region of the sixth transistor;

[0127] In the first direction of the same pixel driving circuit:

[0128] The orthographic projection of the redundant second active portion on the substrate is located between the orthographic projection of the second active portion on the substrate and the orthographic projection of the fourth active portion on the substrate, and the orthographic projection of the redundant fourth active portion on the substrate is located between the orthographic projection of the fourth active portion on the substrate and the orthographic projection of the sixth active portion on the substrate.

[0129] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, a second electrode is connected to a second electrode of the first driving transistor, and a gate is connected to a first reset signal line;

[0130] The first active layer further includes a first active portion, and the first active portion is used to form a channel region of the first transistor;

[0131] The redundant fourth active portion is connected to the fourth active portion, the third active portion, and the first active portion in the same layer.

[0132] In an exemplary embodiment of the present disclosure, a length direction of the channel region of the redundant fourth transistor is a first direction.

[0133] In an exemplary embodiment of the present disclosure, an orthographic projection of the redundant fourth active portion on the base substrate extends along a second direction, and the second direction intersects the first direction;

[0134] The display panel includes a plurality of the redundant fourth active portions, wherein orthographic projections of the plurality of the redundant fourth active portions on the base substrate are distributed along the first direction, and the display panel further includes:

[0135] A redundant second gate connection line is provided, wherein the redundant second gate connection line is connected to a plurality of the redundant fourth active portions distributed in the first direction through via holes.

[0136] In an exemplary embodiment of the present disclosure, the second active layer further includes:

[0137] a twenty-first active portion, connected to a side of the redundant second active portion away from the second active portion, wherein a size of an orthographic projection of the twenty-first active portion on the base substrate in the first direction is larger than a size of an orthographic projection of the redundant second active portion on the base substrate in the first direction;

[0138] An orthographic projection of the twenty-first active portion on the base substrate overlaps with an orthographic projection of the second gate line on the base substrate.

[0139] According to one aspect of the present disclosure, a display device is provided, wherein the display device includes the above-mentioned display panel.

[0140] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0141] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0142] FIG1 is a schematic structural diagram of an exemplary embodiment of a pixel driving circuit disclosed herein;

[0143] FIG2 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in FIG1 ;

[0144] FIG3 is a schematic structural diagram of an exemplary embodiment of a pixel driving circuit disclosed herein;

[0145] FIG4 is a timing diagram of each node in an exemplary embodiment of the pixel driving circuit shown in FIG3 ;

[0146] FIG5 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit disclosed herein;

[0147] FIG6 is a timing diagram of each node in an exemplary embodiment of the pixel driving circuit shown in FIG5 ;

[0148] FIG7 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit disclosed herein;

[0149] FIG8 is a timing diagram of each node in an exemplary embodiment of the pixel driving circuit shown in FIG7 ;

[0150] FIG9 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit disclosed herein;

[0151] FIG10 is a timing diagram of each node in an exemplary embodiment of the pixel driving circuit shown in FIG9 ;

[0152] FIG11 is a timing diagram of each node in an exemplary embodiment of the pixel driving circuit shown in FIG9 ;

[0153] FIG12 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0154] FIG13 is a structural diagram of the shielding layer in FIG12 ;

[0155] FIG14 is a structural diagram of the first active layer in FIG12;

[0156] FIG15 is a structural layout diagram of the first gate layer in FIG12;

[0157] FIG16 is a structural layout diagram of the second gate layer in FIG12 ;

[0158] FIG17 is a structural diagram of the second active layer in FIG12;

[0159] FIG18 is a structural layout diagram of the third gate layer in FIG12;

[0160] FIG19 is a structural diagram of the first source and drain layer in FIG12 ;

[0161] FIG20 is a structural diagram of the second source and drain layer in FIG12;

[0162] FIG21 is a structural layout diagram of the shielding layer and the first active layer in FIG12;

[0163] FIG22 is a structural layout diagram of the shielding layer, the first active layer, and the first gate layer in FIG12 ;

[0164] FIG23 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, and the second gate layer in FIG12 ;

[0165] FIG24 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in FIG12 ;

[0166] FIG25 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in FIG12 ;

[0167] FIG26 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source and drain layer in FIG12 ;

[0168] FIG27 is a partial cross-sectional view of the display panel shown in FIG12 taken along dotted line AA;

[0169] FIG28 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0170] FIG29 is a structural diagram of the shielding layer in FIG28;

[0171] FIG30 is a structural layout diagram of the first active layer in FIG28;

[0172] FIG31 is a structural layout diagram of the first gate layer in FIG28;

[0173] FIG32 is a structural layout diagram of the second gate layer in FIG28;

[0174] FIG33 is a structural layout diagram of the second active layer in FIG28;

[0175] FIG34 is a structural layout diagram of the third gate layer in FIG28;

[0176] FIG35 is a structural layout diagram of the first source and drain layer in FIG28;

[0177] FIG36 is a structural layout diagram of the second source and drain layer in FIG28;

[0178] FIG37 is a structural layout diagram of the shielding layer and the first active layer in FIG28;

[0179] FIG38 is a structural layout diagram of the shielding layer, the first active layer, and the first gate layer in FIG28 ;

[0180] FIG39 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, and the second gate layer in FIG28;

[0181] FIG40 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in FIG28 ;

[0182] FIG41 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in FIG28 ;

[0183] FIG42 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source and drain layer in FIG28 ;

[0184] FIG43 is a partial cross-sectional view of the display panel shown in FIG28 taken along dotted line BB;

[0185] FIG44 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit disclosed herein;

[0186] FIG45 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0187] FIG46 is a structural diagram of the shielding layer in FIG45 ;

[0188] FIG47 is a structural layout diagram of the first active layer in FIG45;

[0189] FIG48 is a structural layout diagram of the first gate layer in FIG45 ;

[0190] FIG49 is a structural layout diagram of the second gate layer in FIG45;

[0191] FIG50 is a structural layout diagram of the second active layer in FIG45;

[0192] FIG51 is a structural layout diagram of the third gate layer in FIG45;

[0193] FIG52 is a structural layout diagram of the first source and drain layer in FIG45;

[0194] FIG53 is a structural layout diagram of the second source and drain layer in FIG45;

[0195] FIG54 is a structural layout diagram of the shielding layer and the first active layer in FIG45;

[0196] FIG55 is a structural layout diagram of the shielding layer, the first active layer, and the first gate layer in FIG45 ;

[0197] FIG56 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, and the second gate layer in FIG45 ;

[0198] FIG57 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in FIG45 ;

[0199] FIG58 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in FIG45 ;

[0200] FIG59 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source and drain layer in FIG45 ;

[0201] FIG60 is a partial cross-sectional view of the display panel shown in FIG45 taken along the dotted line DD. DETAILED DESCRIPTION

[0202] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0203] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0204] This exemplary embodiment also provides a pixel driving circuit, as shown in Figures 1 and 2. Figure 1 is a structural schematic diagram of an exemplary embodiment of the pixel driving circuit disclosed herein, and Figure 2 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in Figure 1.

[0205] The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. A first electrode of the fourth transistor T4 is connected to the data signal terminal Da, a second electrode of the fourth transistor T4 is connected to the first electrode of the driving transistor T3, and a gate of the fourth transistor T4 is connected to the second gate driving signal terminal G2; a first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, a second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3, and a gate of the fifth transistor T5 is connected to the enable signal terminal EM; a gate of the driving transistor T3 is connected to a node N; a first electrode of the second transistor T2 is connected to the node N, a second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3, and a gate of the second transistor T2 is connected to the first gate driving signal terminal G1; a first electrode of the sixth transistor T6 is connected to the first power supply terminal VDD, a second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3, and a gate of the fifth transistor T5 is connected to the enable signal terminal EM; a gate of the driving transistor T3 is connected to a node N; a first electrode of the second transistor T2 is connected to the node N, a second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3, and a gate of the second transistor T2 is connected to the first gate driving signal terminal G1; The pixel driving circuit is connected to the second electrode of the driving transistor T3, the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7, the gate of the sixth transistor T6 is connected to the enable signal terminal EM, the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate of the seventh transistor T7 is connected to the second reset signal terminal Re2; the first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, the second electrode of the first transistor T1 is connected to the second electrode of the driving transistor T3, and the gate of the first transistor T1 is connected to the first reset signal terminal Re1; the first electrode of the eighth transistor T8 is connected to the third initial signal terminal Vinit3, the second electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor T3, and the gate of the eighth transistor T8 is connected to the second reset signal terminal Re2; the first electrode of the capacitor C is connected to the node N, and the second electrode of the capacitor C is connected to the first power supply terminal VDD. This pixel driving circuit can be used to drive a light-emitting unit OLED. The first electrode of the light-emitting unit OLED can be connected to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting unit can be connected to the second power supply terminal VSS. The first electrode of the light-emitting unit can be the anode of the light-emitting unit, and the second electrode of the light-emitting unit can be the cathode of the light-emitting unit. The second transistor T2 may be an N-type transistor, for example, an N-type metal oxide transistor. N-type transistors have a relatively low leakage current, thereby preventing leakage of power from the node N through the second transistor T2 during the light-emitting phase. Meanwhile, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-type transistors, for example, P-type low-temperature polysilicon transistors. P-type transistors have a relatively high carrier mobility, thereby facilitating the realization of display panels with high resolution, high response speed, high pixel density, and high aperture ratio.The first initial signal terminal, the second initial signal terminal, and the third initial signal terminal can output the same or different voltage signals according to actual conditions.

[0206] As shown in Figure 2, where G1 represents the timing of the first gate drive signal terminal G1, G2 represents the timing of the second gate drive signal terminal G2, Re2 represents the timing of the second reset signal terminal Re2, Re1 represents the timing of the first reset signal terminal Re1, and EM represents the timing of the enable signal terminal EM, a driving cycle of the pixel driving circuit may include a first reset phase t1, a second reset phase t2, a data writing phase t3, a third reset phase t4, and a light-emitting phase t5.

[0207] During the first reset phase t1, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit OLED, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3 to improve the hysteresis problem of the driving transistor T3. During the second reset phase t2, the first gate drive signal terminal G1 outputs a high-level signal, the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 and the second transistor T2 are turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the node N through the first transistor T1 and the second transistor T2. During the data writing phase t3, the second gate drive signal terminal G2 outputs a low-level signal, the first gate drive signal terminal G1 outputs a high-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da writes the compensation voltage Vdata+Vth to the node N through the fourth transistor T4 and the second transistor T2, where Vdata is the voltage of the data signal on the data signal terminal and Vth is the threshold voltage of the driving transistor T3. During the third reset phase t4, the second reset signal terminal RE2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit OLED, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3. During the light-emitting phase t5, the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata + Vth stored in the capacitor C. The output current formula of the driving transistor is as follows:

[0208] I=(μWCox / 2L)(Vgs-Vth) 2

[0209] Where I is the output current of the driver transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the gate-source voltage difference of the driver transistor, and Vth is the threshold voltage of the driver transistor. The output current of the driver transistor in the above pixel driving circuit is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0210] In the related art, the gate of the second transistor T2 is prone to leakage to its source and drain. As shown in Figure 1, during the display phase, the low-level signal at the gate of the second transistor T2 is prone to leakage to node N, resulting in bright spots on the display panel. In particular, when the second transistor is an N-type transistor, the gate insulating layer between the channel region and the gate of the second transistor is relatively thin. The gate insulating layer in the second transistor is easily affected by foreign particles and has a certain degree of conductivity, which causes the gate of the second transistor T2 to leak to its source and drain.

[0211] Based on this, this exemplary embodiment provides a pixel driving circuit, as shown in Figure 3, which is a schematic structural diagram of an exemplary embodiment of the pixel driving circuit disclosed herein. The pixel driving circuit includes: at least one driving circuit, a data writing circuit 121, a compensation circuit 131, and a redundancy circuit. The driving circuit includes a control signal terminal and two current transmission terminals, the two current transmission terminals including a first current transmission terminal and a second current transmission terminal. The driving circuit is used to form a driving current between the two current transmission terminals according to the signal of the control signal terminal. At least one driving circuit includes a first driving circuit 111; a data writing circuit 121 is connected to the first current transmission terminal, the data signal terminal Da, and the second gate driving signal terminal G2 of the first driving circuit 111. The data writing circuit 121 is used to respond to the signal of the second gate driving signal terminal G2 to transmit the signal of the data signal terminal Da to the first current transmission terminal of the first driving circuit 111; a compensation circuit 131 is connected to the second current transmission terminal, the control signal terminal, and the first gate driving signal terminal G1 of the first driving circuit 111. The compensation circuit 131 is used to respond to the signal of the first gate driving signal terminal G1 to conduct the control signal terminal and the second current transmission terminal of the first driving circuit 111; the redundant circuit includes a redundant compensation circuit 132. The redundant compensation circuit 132 is connected between the control signal terminal and the current transmission terminal of one driving circuit. The redundant compensation circuit 132 is used to respond to a control signal to conduct the control signal terminal and the current transmission terminal connected thereto.

[0212] In this exemplary embodiment, when the display panel undergoes AOI (Automated Optical Inspection), if foreign particles are found between the gate and source / drain electrodes of the transistor in compensation circuit 131, the connection between the transistor channel region in compensation circuit 131 and the control signal terminal in the first driver circuit can be disconnected, and threshold compensation of the driver circuit can be achieved through redundant compensation circuit 132. This configuration allows for quick and easy repair of bright spots in the display panel.

[0213] In this exemplary embodiment, as shown in FIG3 , a redundancy compensation circuit 132 is connected to the control signal terminal and the second current transmission terminal of the first driver circuit 111. The redundancy compensation circuit 132 is configured to respond to a signal from the redundant first gate drive signal terminal G1S to conduct the control signal terminal and the second current transmission terminal of the first driver circuit 111. The redundancy compensation circuit 132 can implement threshold compensation for the first driver circuit 111.

[0214] In this exemplary embodiment, as shown in FIG3 , the first driving circuit 111 includes: a first driving transistor T31, wherein the gate of the first driving transistor T31 forms the control signal terminal of the first driving circuit, the first electrode of the first driving transistor T31 forms the first current transmission terminal of the first driving circuit 111, and the second electrode of the first driving transistor T31 forms the second current transmission terminal of the first driving circuit 111; the data writing circuit 121 includes: a fourth transistor T4, wherein the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the first driving transistor T31, and the gate is connected to the second gate driving signal terminal G2; the compensation circuit 131 includes: a second transistor T2, wherein the first electrode of the second transistor T2 is connected to the gate of the first driving transistor T31, the second electrode is connected to the second electrode of the first driving transistor T31, and the gate is connected to the first gate driving signal terminal G1; and the redundant compensation circuit 132 includes: a redundant second transistor T2S, wherein the first electrode of the redundant second transistor T2S is connected to the control signal terminal of the first driving circuit 111, and the second electrode is connected to the second current transmission terminal of the first driving circuit 111.

[0215] In this exemplary embodiment, the redundancy compensation circuit 132 is configured to respond to the redundant first gate drive signal terminal G1S to conduct the control signal terminal and the second current transmission terminal of the first drive circuit 111. Accordingly, the gate of the redundant second transistor T2S is connected to the redundant first gate drive signal terminal G1S. The signal timings at the redundant first gate drive signal terminal G1S and the first gate drive signal terminal G1 can be identical. It should be understood that in other exemplary embodiments, the timings at the redundant first gate drive signal terminal G1S and the first gate drive signal terminal G1 can also be different. Accordingly, the signal timings at the second gate drive signal terminal G2, the first reset signal terminal Re1, the second reset signal terminal Re2, and the enable signal terminal EM may also need to be adjusted accordingly. Furthermore, when the second transistor is functioning properly, the redundant second transistor T2S and the second transistor T2 can be driven simultaneously or alternatively.

[0216] In this exemplary embodiment, as shown in FIG3 , the pixel driving circuit is used to drive the light-emitting unit OLED to emit light. The pixel driving circuit further includes: a light-emitting control circuit 141, a second reset circuit 151, a third reset circuit 161, and a storage circuit 171. The light-emitting control circuit 141 is connected to the first power supply terminal VDD, the first current transmission terminal of the first driving circuit 111, the second current transmission terminal of the first driving circuit 111, the enable signal terminal EM, and the first electrode of the light-emitting unit OLED. The light-emitting control circuit 141 is used to respond to a signal from the enable signal terminal EM to connect the first power supply terminal VDD and the first current transmission terminal of the first driving circuit 111, and to respond to a signal from the enable signal terminal EM to connect the second current transmission terminal of the first driving circuit 111 and the first electrode of the light-emitting unit OLED. The second reset circuit 151 is connected to the first electrode of the light-emitting unit OLED, the second initial signal terminal Vinit2, and the second reset circuit 161. The first reset signal terminal Re2 is used for transmitting the signal of the second initial signal terminal Vinit2 to the first electrode of the light-emitting unit OLED in response to the signal of the second reset signal terminal Re2; the third reset circuit 161 is connected to the first current transmission terminal of the first drive circuit 111, the third initial signal terminal Vinit3, and the second reset signal terminal Re2; the third reset circuit 161 is used for transmitting the signal of the third initial signal terminal Vinit3 to the first current transmission terminal of the first drive circuit 111 in response to the signal of the second reset signal terminal Re2; the storage circuit 171 is connected between the control signal terminal of the first drive circuit 111 and the first power supply terminal VDD.

[0217] In this exemplary embodiment, as shown in Figure 3, the pixel driving circuit also includes: a first reset circuit 181, the first reset circuit 181 is connected to the second current transmission terminal of the first driving circuit 111, the first initial signal terminal Vinit1, and the first reset signal terminal Re1, and the first reset circuit 181 is used to respond to the signal of the first reset signal terminal Re1 to transmit the signal of the first initial signal terminal Vinit1 to the second current transmission terminal of the first driving circuit 111.

[0218] In this exemplary embodiment, as shown in FIG3 , the light emitting control circuit 141 includes: a fifth transistor T5 and a sixth transistor T6. The fifth transistor T5 has a first electrode connected to the first power supply terminal VDD, a second electrode connected to the first current transmission terminal of the first driving circuit 111, and a gate connected to the enable signal terminal EM. The sixth transistor T6 has a first electrode connected to the second current transmission terminal of the first driving circuit 111, a second electrode connected to the first electrode of the light emitting unit OLED, and a gate connected to the enable signal terminal EM. The second reset circuit 151 includes: a seventh transistor T7. The seventh transistor T7 has a first electrode connected to the second initial signal terminal Vinit2, a second electrode connected to the first electrode of the light emitting unit OLED, and a gate connected to the second reset signal terminal Re2. The third reset circuit 161 includes: an eighth transistor T8. The eighth transistor T8 has a first electrode connected to the third initial signal terminal Vinit3, a second electrode connected to the first current transmission terminal of the first driving circuit 111, and a gate connected to the second reset signal terminal Re2. The storage circuit 171 includes: a capacitor C. The capacitor C has a first electrode connected to the control signal terminal of the first driving circuit 111, and a second electrode connected to the first power supply terminal VDD.

[0219] In this exemplary embodiment, as shown in FIG3 , the first reset circuit 181 includes: a first transistor T1 , a first electrode of the first transistor T1 being connected to the first initial signal terminal Vinit1 , a second electrode being connected to the second current transmission terminal of the first driving circuit 111 , and a gate being connected to the first reset signal terminal Re1 .

[0220] In this exemplary embodiment, as shown in FIG3 , the first transistor T1 , the first driving transistor T31 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 may be P-type transistors, and the second transistor T2 and the redundant second transistor T2S may be N-type transistors.

[0221] When the second transistor T2 in the pixel driving circuit shown in FIG3 can be used normally, that is, when the gate of the second transistor T2 does not leak electricity to its source and drain through impurity particles, the driving method of the pixel driving circuit can be as shown in FIG2. When the connection between the transistor channel region in the compensation circuit 131 and the control signal terminal in the first driving circuit is interrupted, the redundant second transistor T2S replaces the second transistor T2. As shown in FIG4, it is a timing diagram of each node in an exemplary embodiment of the pixel driving circuit shown in FIG3. Among them, G1S represents the timing of the redundant first gate driving signal terminal G1S, G2 represents the timing of the second gate driving signal terminal G2, Re2 represents the timing of the second reset signal terminal Re2, Re1 represents the timing of the first reset signal terminal Re1, and EM represents the timing of the enable signal terminal EM. A driving cycle of the pixel driving circuit can also include a first reset phase t1, a second reset phase t2, a data writing phase t3, a third reset phase t4, and a light-emitting phase t5.

[0222] During the first reset phase t1, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit OLED, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the first driving transistor T31 to improve the hysteresis problem of the first driving transistor T31. During the second reset phase t2, the redundant first gate driving signal terminal G1S outputs a high-level signal, the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 and the second transistor T2 are turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the gate of the first driving transistor T31 through the first transistor T1 and the redundant second transistor T2S. During the data writing phase t3, the second gate drive signal terminal G2 outputs a low-level signal, the redundant first gate drive signal terminal G1S outputs a high-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da writes the compensation voltage Vdata+Vth to the gate of the first driver transistor T31 via the fourth transistor T4 and the redundant second transistor T2S, where Vdata is the voltage of the data signal at the data signal terminal Da, and Vth is the threshold voltage of the first driver transistor T31. During the third reset phase t4, the second reset signal terminal RE2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting element OLED, and the third initial signal terminal Vinit3 inputs the third initial signal to the first electrode of the first driver transistor T31. During the light-emitting phase t5, the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the first driver transistor T31 drives the light-emitting element OLED to emit light under the action of the compensation voltage Vdata+Vth stored on the capacitor C.

[0223] It should be understood that in other exemplary embodiments, the pixel driving circuit shown in FIG3 may also have other driving methods. For example, the driving method may not include the third reset phase t4 or the first reset phase t1. In addition, in other exemplary embodiments, the pixel driving circuit shown in FIG3 may not include the third reset circuit 161.

[0224] FIG5 is a schematic diagram of the structure of another exemplary embodiment of a pixel driving circuit according to the present disclosure. In this exemplary embodiment, a first reset circuit 181 is connected to the control signal terminal, the first initial signal terminal Vinit1, and the first reset signal terminal Re1 of the first driving circuit 111. The first reset circuit 181 is configured to respond to a signal at the first reset signal terminal Re1 and transmit the signal at the first initial signal terminal Vinit1 to the control signal terminal of the first driving circuit 111. The first reset circuit 181 may include a first transistor T1, wherein a first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, a second electrode is connected to the control signal terminal of the first driving circuit 111, and a gate is connected to the first reset signal terminal Re1.

[0225] In this exemplary embodiment, as shown in Figure 5, the first driving transistor T31, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type transistors, and the first transistor T1, the second transistor T2, and the redundant second transistor T2S can be N-type transistors.

[0226] Figure 6 shows a timing diagram of various nodes in an exemplary embodiment of the pixel driving circuit shown in Figure 5. G1S represents the timing of the redundant first gate driving signal terminal G1S, G2 represents the timing of the second gate driving signal terminal G2, Re2 represents the timing of the second reset signal terminal Re2, Re1 represents the timing of the first reset signal terminal Re1, and EM represents the timing of the enable signal terminal EM. A driving cycle of the pixel driving circuit may also include a first reset phase t1, a second reset phase t2, a data writing phase t3, a third reset phase t4, and a light-emitting phase t5.

[0227] During the first reset phase t1, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit OLED, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the first driving transistor T31 to improve the hysteresis problem of the first driving transistor T31. During the second reset phase t2, the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the gate of the first driving transistor T31 through the first transistor T1. During the data writing phase t3, the second gate driving signal terminal G2 outputs a low-level signal, the redundant first gate driving signal terminal G1S outputs a high-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da writes a compensation voltage Vdata+Vth to the gate of the first driving transistor T31 through the fourth transistor T4 and the second transistor T2, where Vdata is the voltage of the data signal on the data signal terminal Da and Vth is the threshold voltage of the first driving transistor T31. During the third reset phase t4, the second reset signal terminal RE2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit OLED, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the first driving transistor T31. During the light-emitting phase t5, the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the first driving transistor T31 drives the light-emitting unit OLED to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C.

[0228] It should be understood that in other exemplary embodiments, the pixel driving circuit shown in FIG5 may also have other driving methods. For example, the driving method may not include the third reset phase t4 or the first reset phase t1. In addition, in other exemplary embodiments, the pixel driving circuit shown in FIG5 may not include the third reset circuit 161.

[0229] FIG7 is a schematic diagram of another exemplary embodiment of a pixel driving circuit according to the present disclosure. A redundant compensation circuit 132 is connected to the control signal terminal and the first current transmission terminal of the first driving circuit 111. The redundant compensation circuit 132 is configured to respond to a signal from the redundant first gate driving signal terminal G1S to conduct the control signal terminal and the first current transmission terminal of the first driving circuit 111. The redundant circuit further includes a redundant data write circuit 122. The redundant data write circuit 122 is connected to the second current transmission terminal and the data signal terminal Da of the first driving circuit 111. The redundant data write circuit 121 is configured to respond to a signal from the redundant second gate driving signal terminal G2S to transmit a data signal from the data signal terminal Da to the second current transmission terminal of the first driving circuit 111.

[0230] In this exemplary embodiment, as shown in FIG7 , the redundancy compensation circuit 132 includes a redundant second transistor T2S, wherein a first electrode of the redundant second transistor T2 is connected to the control signal terminal of the first drive circuit 111, a second electrode is connected to the first current transmission terminal of the first drive circuit 111, and a gate is connected to the redundant first gate drive signal terminal G1S. The redundant data write circuit 122 includes a redundant fourth transistor T4S, wherein a first electrode of the redundant fourth transistor T4S is connected to the data signal terminal Da, a second electrode is connected to the second current transmission terminal of the first drive circuit 111, and a gate is connected to the redundant second gate drive signal terminal G2S.

[0231] In this exemplary embodiment, as shown in FIG7 , the signal timings at the redundant first gate drive signal terminal G1S and the first gate drive signal terminal G1 can be the same. It should be understood that in other exemplary embodiments, the signal timings at the redundant first gate drive signal terminal G1S and the first gate drive signal terminal G1 can also be different, and accordingly, the signal timings at the redundant second gate drive signal terminal G2S, the first reset signal terminal Re1, the second reset signal terminal Re2, and the enable signal terminal EM also need to be adjusted accordingly. The timings at the redundant second gate drive signal terminal GS2 and the second gate drive signal terminal G2 can be the same. It should be understood that in other exemplary embodiments, the signal timings at the redundant second gate drive signal terminal G2S and the second gate drive signal terminal G2 can also be different, and accordingly, the signal timings at the redundant first gate drive signal terminal G1S, the first reset signal terminal Re1, the second reset signal terminal Re2, and the enable signal terminal EM also need to be adjusted accordingly.

[0232] When the second transistor T2 in the pixel driving circuit shown in FIG7 can be used normally, the redundant second gate driving signal terminal G2S outputs a high level, the redundant first gate driving signal terminal G1S outputs a low level, the redundant fourth transistor T4S is turned off, and the redundant second transistor T2S is turned off. The driving method of the pixel driving circuit can be as shown in FIG2 .

[0233] When the connection between the transistor channel region in the compensation circuit 131 and the control signal terminal in the first drive circuit is interrupted, the second gate drive signal terminal G2 outputs a high-level signal, and the fourth transistor T4 is turned off. As shown in Figure 8, it is a timing diagram of each node in an exemplary embodiment of the pixel drive circuit shown in Figure 7. Among them, G1S represents the timing of the redundant first gate drive signal terminal G1S, G2S represents the timing of the redundant second gate drive signal terminal G2S, Re2 represents the timing of the second reset signal terminal Re2, Re1 represents the timing of the first reset signal terminal Re1, and EM represents the timing of the enable signal terminal EM. A drive cycle of the pixel drive circuit may include a first reset phase t1, a second reset phase t2, a data write phase t3, a third reset phase t4, and a light-emitting phase t5.

[0234] During the first reset phase t1, the second reset signal terminal Re2 outputs a low-level signal, the redundant first gate drive signal terminal G1S outputs a high-level signal, the seventh transistor T7, the eighth transistor T8, and the redundant second transistor T2S are turned on, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit OLED, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the first drive transistor T31 to improve the hysteresis problem of the first drive transistor T31. The third initial signal terminal Vinit3 can also reset the gate of the first drive transistor T31 through the eighth transistor T8 and the redundant second transistor T2S. During the second reset phase t2, the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the second electrode of the first drive transistor T31 to improve the hysteresis problem of the first drive transistor T31. During the data writing phase t3, the redundant second gate drive signal terminal G2S outputs a low-level signal, the redundant first gate drive signal terminal G1S outputs a high-level signal, the redundant fourth transistor T4S and the redundant second transistor T2S are turned on, and the data signal terminal Da writes the compensation voltage Vdata+Vth to the gate of the first drive transistor T31 via the redundant fourth transistor T4S and the redundant second transistor T2S, where Vdata is the voltage of the data signal at the data signal terminal Da, and Vth is the threshold voltage of the first drive transistor T31. During the third reset phase t4, the second reset signal terminal RE2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting element OLED, and the third initial signal terminal Vinit3 inputs the third initial signal to the first electrode of the first drive transistor T31. During the light-emitting phase t5, the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the first drive transistor T31 drives the light-emitting element OLED to emit light under the action of the compensation voltage Vdata+Vth stored on the capacitor C.

[0235] When the second transistors T2 in the display panel are all able to function normally, that is, the connection between the transistor channel region in the compensation circuit 131 and the control signal terminal in the first drive circuit is not interrupted, the display panel can include a first drive mode and a second drive mode. In the first drive mode: the pixel drive circuit shown in FIG7 can be driven by the drive method shown in FIG2; in the second drive mode: the pixel drive circuit shown in FIG7 can be driven by the drive method shown in FIG8, wherein, in the second drive mode, the redundant first gate drive signal terminal G1S can output a low-level signal. The display panel can be driven alternately in the first drive mode and the second drive mode. This setting can increase the service life of the second transistor T2 and improve the reliability of the display panel.

[0236] It should be understood that in other exemplary embodiments, the pixel driving circuit shown in FIG. 7 may also employ other driving methods. For example, the driving method may not include the third reset phase t4 or the first reset phase t1. Furthermore, in other exemplary embodiments, the pixel driving circuit shown in FIG. 7 may not include the third reset circuit 161. The first reset circuit in the pixel driving circuit shown in FIG. 7 may also be directly connected to the control signal terminal of the first driving circuit to transmit the signal from the first initial signal terminal directly to the control signal terminal of the first driving circuit in response to a control signal.

[0237] Figure 9 shows a schematic diagram of another exemplary embodiment of a pixel driver circuit disclosed herein. At least one driver circuit may further include a second driver circuit 112; a redundancy compensation circuit 132 connected to a control signal terminal and a current transmission terminal of the second driver circuit 112. Redundancy compensation circuit 132 is configured to conduct the control signal terminal and the current transmission terminal of the second driver circuit 112 in response to a signal from the redundant first gate drive signal terminal G1S. In this exemplary embodiment, the second driver circuit 112 can provide a driving current to the light-emitting unit.

[0238] In this exemplary embodiment, as shown in Figure 9, the first current transmission terminal of the first driving circuit 111 is connected to the first current transmission terminal of the second driving circuit 112; the redundant compensation circuit 132 is connected to the control signal terminal and the second current transmission terminal of the second driving circuit 112, and the redundant compensation circuit 132 is used to respond to the signal of the redundant first gate driving signal terminal G1S to turn on the control signal terminal and the second current transmission terminal of the second driving circuit 112.

[0239] In this exemplary embodiment, as shown in FIG9 , the redundant circuit further includes: a redundant light-emitting control circuit 142, a redundant first reset circuit 182, and a redundant storage circuit 172. The redundant light-emitting control circuit 142 is connected to the first power supply terminal VDD, the first current transmission terminal of the second driver circuit 112, the second current transmission terminal of the second driver circuit 112, and the first electrode of the light-emitting unit OLED. The redundant light-emitting control circuit 142 is configured to connect the first power supply terminal VDD to the first current transmission terminal of the second driver circuit 112, and to connect the second current transmission terminal of the second driver circuit 112 to the first electrode of the light-emitting unit OLED, in response to the redundant enable signal terminal EMS. The redundant first reset circuit 182 is connected to the second current transmission terminal of the second driver circuit 112 and the first initial signal terminal Vinit1. The first reset circuit 181 is configured to transmit the signal of the first initial signal terminal Vinit1 to the second current transmission terminal of the second driver circuit 112 in response to the redundant first reset signal terminal Re1S. The redundant storage circuit 172 is connected between the control signal terminal of the second driver circuit 112 and the first power supply terminal VDD.

[0240] In this exemplary embodiment, as shown in FIG9 , the second driving circuit 112 includes: a second driving transistor T32, the gate of the second driving transistor T32 forming a control signal terminal of the second driving current, a first electrode of the second driving transistor T32 forming a first current transmission terminal of the second driving circuit 112, and a second electrode of the second driving transistor T32 forming a second current transmission terminal of the second driving circuit 112; the redundant compensation circuit 132 includes: a redundant second transistor T2S, a first electrode of the redundant second transistor T2S connected to the gate of the second driving transistor T32, and a second electrode connected to the second electrode of the second driving transistor T32; the redundant light emitting control circuit 142 includes: a redundant fifth transistor T5S, a redundant sixth transistor T5S, and a redundant sixth transistor T5S. 6S, a first electrode of the redundant fifth transistor T5S is connected to the first power supply terminal VDD, and a second electrode is connected to the first current transmission terminal of the second driving circuit 112; a first electrode of the redundant sixth transistor T6S is connected to the second current transmission terminal of the second driving circuit 112, and a second electrode is connected to the first electrode of the light-emitting unit OLED; the redundant first reset circuit 181 includes: a redundant first transistor T1S, a first electrode of the redundant first transistor T1 is connected to the first initial signal terminal Vinit1, and a second electrode is connected to the second current transmission terminal of the second driving circuit 112; the redundant storage circuit 172 includes: a redundant capacitor CS, a first electrode of the redundant capacitor CS is connected to the control signal terminal of the second driving circuit 112, and a second electrode is connected to the first power supply terminal.

[0241] When the second transistor T2 in the pixel driving circuit is functioning normally and the redundant circuit is not operating, FIG10 is a timing diagram of each node in an exemplary embodiment of the pixel driving circuit shown in FIG9 . In particular, G1 represents the timing of the first gate driving signal terminal G1, G2 represents the timing of the second gate driving signal terminal G2, Re2 represents the timing of the second reset signal terminal Re2, Re1 represents the timing of the first reset signal terminal Re1, and EM represents the timing of the enable signal terminal EM. A driving cycle of the pixel driving circuit may include a first reset phase t1, a data writing phase t2, a second reset phase t3, and a light-emitting phase t4.

[0242] During the first reset phase t1, the first gate drive signal terminal G1 outputs a high level signal, the first reset signal terminal Re1 outputs a low level signal, the first transistor T1 and the second transistor T2 are turned on, and the first initial signal terminal Vinit1 inputs a first initial signal to the gate of the first drive transistor T31 via the first transistor T1 and the second transistor T2. During the data write phase t2, the second gate drive signal terminal G2 outputs a low level signal, the first gate drive signal terminal G1 outputs a high level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da writes a compensation voltage Vdata+Vth to the gate of the first drive transistor T31 via the fourth transistor T4 and the second transistor T2, where Vdata is the voltage of the data signal on the data signal terminal Da and Vth is the threshold voltage of the first drive transistor T31. During the second reset phase t3, the second reset signal terminal Re2 outputs a low level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit OLED. In the light emitting stage t4: the enable signal terminal EM outputs a low level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the first driving transistor T31 drives the light emitting unit OLED to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C.

[0243] When the connection between the transistor channel region in the compensation circuit 131 and the control signal terminal in the first drive circuit is interrupted, the redundant circuit begins to operate. FIG11 is a timing diagram of each node in an exemplary embodiment of the pixel drive circuit shown in FIG9 . G1S represents the timing of the redundant first gate drive signal terminal G1S, G2S represents the timing of the redundant second gate drive signal terminal G2, Re2 represents the timing of the second reset signal terminal RE2, Re1S represents the timing of the redundant first reset signal terminal Re1S, and EMS represents the timing of the redundant enable signal terminal EMS. A drive cycle of the pixel drive circuit may also include a first reset phase t1, a data writing phase t2, a second reset phase t3, and a light-emitting phase t4.

[0244] During the first reset phase t1, the redundant first gate drive signal terminal G1S outputs a high level, the redundant first reset signal terminal Re1S outputs a low level signal, the redundant first transistor T1S and the redundant second transistor T2S are turned on, and the first initial signal terminal Vinit1 inputs a first initial signal to the gate of the second drive transistor T32 via the redundant first transistor T1S and the redundant second transistor T2S. During the data write phase t2, the redundant second gate drive signal terminal G2S outputs a low level signal, the redundant first gate drive signal terminal G1S outputs a high level signal, the redundant fourth transistor T4S and the redundant second transistor T2S are turned on, and the data signal terminal Da writes a compensation voltage Vdata+Vth to the gate of the second drive transistor T32 via the redundant fourth transistor T4S and the redundant second transistor T2S, where Vdata is the voltage of the data signal on the data signal terminal Da and Vth is the threshold voltage of the second drive transistor T32. During the second reset phase t3, the second reset signal terminal Re2 outputs a low level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit OLED. In the light emitting stage t4: the redundant enable signal terminal EMS outputs a low level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the second driving transistor T32 drives the light emitting unit OLED to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C.

[0245] It should be understood that in other exemplary embodiments, the first reset circuit in the pixel driving circuit shown in Figure 9 can also be directly connected to the control signal terminal of the first driving circuit to directly transmit the signal of the first initial signal terminal to the control signal terminal of the first driving circuit in response to a control signal. Accordingly, the pixel driving circuit can also include a redundant first reset circuit, and the redundant first reset circuit can also be directly connected to the control signal terminal of the second driving circuit to directly transmit the signal of the first initial signal terminal to the control signal terminal of the second driving circuit in response to a control signal.

[0246] This exemplary embodiment also provides a display panel comprising a plurality of the aforementioned pixel drive circuits. Before the display panel leaves the factory, the second transistors in the aforementioned pixel drive circuits are tested. If gate-to-source / drain leakage is detected in the second transistors, the connection between the second transistor channel region and the gate of the first drive transistor is disconnected, thereby replacing the second transistor T2 with a redundant second transistor T2S. Therefore, in the display panel provided by this exemplary embodiment, the connection between the second transistor channel region and the gate of the first drive transistor may be disconnected in some pixel drive circuits.

[0247] This exemplary embodiment also provides a display panel, which may include a base substrate, a blocking layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source-drain layer, and a second source-drain layer stacked in sequence. An insulating layer may be provided between the above-mentioned adjacent layers. As shown in Figures 12-26, Figure 12 is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein, Figure 13 is a structural layout diagram of the blocking layer in Figure 12, Figure 14 is a structural layout diagram of the first active layer in Figure 12, Figure 15 is a structural layout diagram of the first gate layer in Figure 12, Figure 16 is a structural layout diagram of the second gate layer in Figure 12, Figure 17 is a structural layout diagram of the second active layer in Figure 12, Figure 18 is a structural layout diagram of the third gate layer in Figure 12, Figure 19 is a structural layout diagram of the first source-drain layer in Figure 12, Figure 20 is a structural layout diagram of the second source-drain layer in Figure 12, and Figure 21 is a structural layout diagram of the blocking layer and the first active layer in Figure 12. FIG22 is a structural layout diagram of the shielding layer, first active layer, and first gate layer in FIG12 ; FIG23 is a structural layout diagram of the shielding layer, first active layer, first gate layer, and second gate layer in FIG12 ; FIG24 is a structural layout diagram of the shielding layer, first active layer, first gate layer, second gate layer, and second active layer in FIG12 ; FIG25 is a structural layout diagram of the shielding layer, first active layer, first gate layer, second gate layer, second active layer, and third gate layer in FIG12 ; FIG26 is a structural layout diagram of the shielding layer, first active layer, first gate layer, second gate layer, second active layer, third gate layer, and first source and drain layer in FIG12 . The display panel may include multiple pixel driving circuits as shown in FIG3 . The multiple pixel driving circuits are arranged in an array along a second direction Y and a first direction X, wherein the first direction X and the second direction Y intersect. For example, the first direction X may be a row direction, and the second direction Y may be a column direction.

[0248] As shown in FIG. 12 , 13 and 21 , the shielding layer includes a plurality of shielding portions 81 distributed in an array along the first direction X and the second direction Y, and the shielding portions 81 are connected to each other.

[0249] As shown in Figures 12, 14, and 22, the first active layer may include: a first active portion 71, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, a sixteenth active portion 716, a seventeenth active portion 717, and a first initial signal line Vinit1. The first active portion 71 is used to form the channel region of the first transistor T1; the third active portion 73 can be used to form the channel region of the first driving transistor T31; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the ninth active portion 79 is connected between the third active portion 73 and the sixth active portion 76; the tenth active portion 710 and the tenth active portion 720 are connected to each other. The twelfth active portion 712 is connected to both ends of the eighth active portion 78; the eleventh active portion 711 is connected between the fifth active portion 75 and the third active portion 73; the thirteenth active portion 713 is connected to a side of the fourth active portion 74 away from the third active portion 73; the fourteenth active portion 714 is connected to a side of the seventh active portion 77 away from the sixth active portion 76; the fifteenth active portion 715 is connected to a side of the fifth active portion 75 away from the third active portion 73; the sixteenth active portion 716 is connected between the seventh active portion 77 and the sixth active portion 76; and the seventeenth active portion 717 and the first initial signal line Vinit1 are connected to both ends of the first active portion 71. The first initial signal line Vinit1 can be used to provide the first initial signal terminal shown in FIG. The orthographic projection of the first initial signal line Vinit1 on the substrate extends along the first direction X. The first initial signal line Vinit1 is connected to multiple first active portions 71 in the same row of pixel driving circuits. The first active layer may be formed of polysilicon material. Accordingly, the first transistor T1 , the first driving transistor T31 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 may be P-type low-temperature polysilicon thin film transistors.

[0250] The orthographic projection of the shielding portion 81 on the substrate can at least partially overlap the orthographic projection of the third active portion 73 on the substrate. The shielding portion 81 can shield the third active portion 73 from light, thereby improving the stability of the output characteristics of the first drive transistor. The shielding layer can be a conductive structure, and the shielding layer can be connected to a stable voltage source to provide signal shielding for the pixel drive circuit.

[0251] As shown in Figures 12, 15, and 22, the first gate layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal in Figure 3; the enable signal line EM can be used to provide the enable signal terminal in Figure 3; the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 3; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 3. The orthographic projection of the second gate line G2 on the substrate, the orthographic projection of the enable signal line EM on the substrate, the orthographic projection of the first reset signal line Re1 on the substrate, and the orthographic projection of the second reset signal line Re2 on the substrate can all extend along the first direction X. The second gate line G2 includes a plurality of second sub-gate lines G21, and the orthographic projections of the plurality of second sub-gate lines G21 on the substrate are spaced apart along the first direction X. The orthographic projection of the second sub-gate line G21 on the substrate overlaps the orthographic projection of the fourth active portion 74 on the substrate. Part of the second sub-gate line G21 forms the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projection of the fifth active portion 75 and the orthographic projection of the sixth active portion 76 on the substrate. Part of the enable signal line EM can form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The first reset signal line Re1 includes multiple first sub-reset signal lines Re11. The orthographic projections of the multiple first sub-reset signal lines Re11 on the substrate are spaced apart along the first direction X. The orthographic projections of the first sub-reset signal lines Re11 on the substrate can overlap the orthographic projection of the first active portion 71 on the substrate. Part of the first sub-reset signal line Re11 forms the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate can overlap the orthographic projection of the seventh active portion 77 and the orthographic projection of the eighth active portion 78 on the substrate. Portions of the second reset signal line Re2 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 on the substrate overlaps the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 can be used to form the gate of the first drive transistor T31 and the first electrode of the capacitor C. The display panel can use the first gate layer as a mask to perform a conductorization process on the first active layer. Specifically, the area of ​​the first active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first gate layer forms a conductor structure.

[0252] As shown in Figures 12, 16, and 23, the second gate layer may include: a third gate line 2G1, a second conductive portion 22, and a redundant third gate line 2G1S. The orthographic projection of the third gate line 2G1 on the base substrate and the orthographic projection of the redundant third gate line 2G1S on the base substrate both extend along the first direction X. The third gate line 2G1 can be used to provide the first gate drive signal terminal in Figure 3, and the redundant third gate line 2G1S is used to provide the redundant first gate drive signal terminal in Figure 3. The orthographic projection of the second conductive portion 22 on the base substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the base substrate. The second conductive portion 22 is used to form the second electrode of the capacitor C.

[0253] As shown in Figures 12, 17, and 24, the second active layer may include an active portion 9, which may include: a second active portion 92, a redundant second active portion 92S, a nineteenth active portion 919 connected between the second active portion 92 and the redundant second active portion 92S, a twentieth active portion 920 connected to the side of the second active portion 92 away from the redundant second active portion 92S, and a twenty-first active portion 921 connected to the side of the redundant second active portion 92S away from the second active portion 92. The second active portion 92 is used to form the channel region of the second transistor T2, and the redundant second active portion 92S is used to form the channel region of the redundant second transistor T2S. The second active layer may be formed of indium gallium zinc oxide, and accordingly, the second transistor T2 and the redundant second transistor T2S may be N-type metal oxide thin film transistors. The orthographic projection of the third gate line 2G1 on the substrate may overlap the orthographic projection of the second active portion 92 on the substrate, and a portion of the structure of the third gate line 2G1 may be used to form the bottom gate of the second transistor T2. The orthographic projection of the redundant third gate line 2G1S on the base substrate may cover the orthographic projection of the redundant second active portion 92S on the base substrate, and a partial structure of the redundant third gate line 2G1S may be used to form a bottom gate of the redundant second transistor T2S.

[0254] As shown in Figures 12, 18, and 25, the third gate layer may include a first gate line 3G1, a redundant first gate line 3G1S, and a second initial signal line Vinit2. The orthographic projection of the first gate line 3G1 on the base substrate, the orthographic projection of the redundant first gate line 3G1S on the base substrate, and the orthographic projection of the second initial signal line Vinit2 on the base substrate may extend along a first direction X. The first gate line 3G1 may be used to provide the first gate drive signal terminal in Figure 3, the orthographic projection of the first gate line 3G1 on the base substrate may cover the orthographic projection of the second active portion 92 on the base substrate, and a partial structure of the first gate line 3G1 may be used to form the top gate of the second transistor T2. At the same time, the first gate line 3G1 may be connected to the third gate line 2G1 through a via located in the border area of ​​the display panel. The redundant first gate line 3G1S can be used to provide the redundant first gate drive signal terminal in Figure 3. The orthographic projection of the redundant first gate line 3G1S on the base substrate can cover the orthographic projection of the redundant second active portion 92S on the base substrate. The partial structure of the redundant first gate line 3G1S can be used to form the top gate of the redundant second transistor T2S. At the same time, the redundant first gate line 3G1S can be connected to the redundant third gate line 2G1S through a via located in the display panel frame area. The second initial signal line Vinit2 is used to provide the second initial signal terminal in Figure 3. In addition, the display panel can use the third gate layer as a mask to perform conductor processing on the second active layer. That is, the area of ​​the second active layer covered by the third gate layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third gate layer forms a conductor structure.

[0255] As shown in Figure 25, when the gate of the second transistor leaks electricity to the source and drain, the channel region of the second transistor and the gate of the first driving transistor can be interrupted in the second active layer along the dotted line EE in Figure 25, and the dotted line EE can be located between the second active portion 72 and the nineteenth active portion 919.

[0256] As shown in Figures 12, 19, and 26, the first source-drain layer may include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, a third initial signal line Vinit3, a second reset connection line 4Re2, a second gate connection line 4G2, and a first reset connection line 4Re1. The first bridge portion 41 may be connected to the ninth active portion 79, the twentieth active portion 920, the twenty-first active portion 921, and the seventeenth active portion 717 through vias, respectively, to connect the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the redundant second transistor, and the second electrode of the first drive transistor T31. The second bridge portion 42 is connected to the fourteenth active portion 714 and the second initial signal line Vinit2 through vias, respectively, to connect the first electrode of the seventh transistor T7 and the second initial signal line. The third bridge portion 43 is connected to the thirteenth active portion 713 through a via, to connect the first electrode of the fourth transistor T4. The fourth bridge portion 44 connects the eleventh active portion 711 and the tenth active portion 710 through vias, respectively, to connect the second electrode of the eighth transistor T8 and the first electrode of the first driving transistor T31. The fifth bridge portion 45 connects the second conductive portion 22 and the fifteenth active portion 715 through vias, respectively, to connect the second electrode of the capacitor C and the first electrode of the fifth transistor T5. The orthographic projection of the fifth bridge portion 45 on the substrate extends along the first direction X. The fifth bridge portion 45 connects multiple second conductive portions 22 and multiple fifteenth active portions 715 in the same row of pixel driving circuits. The sixth bridge portion 46 connects the nineteenth active portion 919 and the first conductive portion 11 through vias, respectively, to connect the gate of the first driving transistor T31 and the first electrode of the second transistor T2 and the first electrode of the redundant second transistor. The second conductive portion 22 may have an opening 221 formed therein, and a via connecting the sixth bridge portion 46 and the first conductive portion 11 is disposed through the opening 221. The seventh bridge portion 47 is connected to the sixteenth active portion 716 via a via to connect to the second electrode of the sixth transistor. The third initial signal line Vinit3 is used to provide the third initial signal terminal in Figure 3. The orthographic projection of the third initial signal line Vinit3 on the substrate extends along the first direction X. The third initial signal line Vinit3 is connected to the twelfth active portion 712 via a via to connect the first electrode and the third initial signal terminal of the eighth transistor. The first reset connection line 4Re1 is connected to multiple first sub-reset signal lines Re11 located in the same row of pixel driving circuits via a via. The square resistance of the first source and drain layer is less than the square resistance of the first gate layer. This configuration can reduce the voltage drop on the first reset signal line Re1. The second reset connection line 4Re2 is connected to the second reset signal line Re2 via a via. This configuration can also reduce the voltage drop on the second reset signal line Re2.The second gate connection line 4G2 can be connected to a plurality of second sub-gate lines G21 in the same row of pixel driving circuits through vias. This arrangement can also reduce the voltage drop on the second gate line G2.

[0257] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in other conductive layers. For example, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in the second gate layer, the third gate layer, the first source and drain layer, etc.

[0258] As shown in Figures 12 and 20 , the second source / drain layer may include a data line Da, a first power line VDD, and an eighth bridge portion 58. The orthographic projections of the data line Da and the first power line VDD on the substrate extend along the second direction Y. The data line Da is used to provide the data signal terminal shown in Figure 3 , and the first power line VDD is used to provide the first power terminal shown in Figure 3 . The eighth bridge portion 58 is connected to the seventh bridge portion 47 via a via.

[0259] As shown in Figures 12 and 20, the second source and drain layer may further include a third initial connection line 5Vinit3. The orthographic projection of the third initial connection line 5Vinit3 on the base substrate extends along the second direction Y. The third initial connection line 5Vinit3 may be connected to at least a portion of the third initial signal line Vinit3 intersecting therewith via a via. This configuration can reduce the intrinsic resistance of the third initial signal line Vinit3, thereby reducing the voltage drop of the initial signal on the third initial signal line Vinit3, thereby improving the display uniformity of the display panel. It should be understood that in other exemplary embodiments, the second source and drain layer may include one or more of the first initial connection line, the second initial connection line, and the third initial connection line. The orthographic projection of the first initial connection line on the base substrate extends along the second direction Y. The first initial connection line may be connected to at least a portion of the first initial signal line intersecting therewith via a via. The orthographic projection of the second initial connection line on the base substrate extends along the second direction Y. The second initial connection line may be connected to at least a portion of the second initial signal line intersecting therewith via a via.

[0260] As shown in Figure 12-26, in the same pixel driving circuit: the orthographic projection of the first gate line 3G1 on the substrate is located between the orthographic projection of the second gate line G2 on the substrate and the orthographic projection of the first conductive portion 11 on the substrate, and the orthographic projection of the redundant first gate line 3G1S on the substrate is located between the orthographic projection of the second gate line G2 on the substrate and the orthographic projection of the first gate line 3G1 on the substrate.

[0261] As shown in FIG. 12-26 , in the first direction X of the same pixel driving circuit, the orthographic projection of the redundant second active portion 92S on the base substrate is located between the orthographic projection of the second active portion 92 on the base substrate and the orthographic projection of the fifth active portion 75 on the base substrate.

[0262] As shown in Figures 12-26, the size of the orthographic projection of the twenty-first active portion 921 on the substrate substrate in the first direction X is greater than the size of the orthographic projection of the redundant second active portion 92 on the substrate substrate in the first direction X, and the orthographic projection of the twenty-first active portion 921 on the substrate substrate overlaps with the orthographic projection of the second gate line G2 on the substrate substrate. The twenty-first active portion 921 can shield the coupling effect of the second gate line G2 on the sixth bridge portion 46, thereby improving the voltage stability of the gate of the first drive transistor during the light-emitting stage. In addition, in the data writing stage of the pixel drive circuit, the second gate line G2 is pulled low, and the second gate line G2 can pull down the voltage of the second electrode and gate of the first drive transistor through the twenty-first active portion 921, thereby increasing the speed at which the data line writes the compensation voltage to the gate of the first drive transistor.

[0263] In this exemplary embodiment, as shown in FIG27 , which is a partial cross-sectional view of the display panel shown in FIG12 taken along the dotted line AA, the display panel may further include a buffer layer 101, a first insulating layer 102, a second insulating layer 103, a third insulating layer 104, a fourth insulating layer 105, a first dielectric layer 106, a passivation layer 107, and a first planarization layer 108. The substrate 100, the shielding layer, the buffer layer 101, the first active layer, the first insulating layer 102, the first gate layer, the second insulating layer 103, the second gate layer, the third insulating layer 104, the second active layer, the fourth insulating layer 105, the third gate layer, the first dielectric layer 106, the first source and drain layer, the passivation layer 107, the first planarization layer 108, and the second source and drain layer are stacked in sequence. The buffer layer 101, first insulating layer 102, second insulating layer 103, third insulating layer 104, and fourth insulating layer 105 can be single-layer or multi-layer structures. The materials of the first insulating layer 102, second insulating layer 103, third insulating layer 104, and fourth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 106 can be a silicon nitride layer. The material of the first planarization layer 108 can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding (SOG), etc. The passivation layer 107 can be a silicon oxide layer. The base substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer can be an inorganic material. The materials of the first, second, and third gate layers can be molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacked conductive layers. The first source / drain layer and the second source / drain layer may include a metal material, for example, one of molybdenum, aluminum, copper, titanium, and niobium, or an alloy thereof, or a molybdenum / titanium alloy or stack, or a conductive layer such as a titanium / aluminum / titanium stack. The sheet resistance of any one of the first source / drain layer and the second source / drain layer may be less than the sheet resistance of any one of the first gate layer, the second gate layer, and the third gate layer.

[0264] This exemplary embodiment also provides a display panel, which may include a substrate, a blocking layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source-drain layer, and a second source-drain layer stacked in sequence. An insulating layer may be provided between the above-mentioned adjacent layers. As shown in Figures 28-42, Figure 28 is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein, Figure 29 is a structural layout diagram of the blocking layer in Figure 28, Figure 30 is a structural layout diagram of the first active layer in Figure 28, Figure 31 is a structural layout diagram of the first gate layer in Figure 28, Figure 32 is a structural layout diagram of the second gate layer in Figure 28, Figure 33 is a structural layout diagram of the second active layer in Figure 28, Figure 34 is a structural layout diagram of the third gate layer in Figure 28, Figure 35 is a structural layout diagram of the first source-drain layer in Figure 28, Figure 36 is a structural layout diagram of the second source-drain layer in Figure 28, and Figure 37 is a structural layout diagram of the blocking layer and the first active layer in Figure 28. FIG38 is a structural layout diagram of the shielding layer, first active layer, and first gate layer in FIG28 ; FIG39 is a structural layout diagram of the shielding layer, first active layer, first gate layer, and second gate layer in FIG28 ; FIG40 is a structural layout diagram of the shielding layer, first active layer, first gate layer, second gate layer, and second active layer in FIG28 ; FIG41 is a structural layout diagram of the shielding layer, first active layer, first gate layer, second gate layer, second active layer, and third gate layer in FIG28 ; and FIG42 is a structural layout diagram of the shielding layer, first active layer, first gate layer, second gate layer, second active layer, third gate layer, and first source and drain layer in FIG28 . The display panel may include multiple pixel driving circuits as shown in FIG7 . The multiple pixel driving circuits are arranged in an array along a second direction Y and a first direction X, wherein the first direction X and the second direction Y intersect. For example, the first direction X may be a row direction, and the second direction Y may be a column direction.

[0265] As shown in Figures 28, 29 and 37, the shielding layer includes a plurality of shielding portions 81 distributed in an array along the first direction X and the second direction Y, and the shielding portions 81 are connected to each other.

[0266] As shown in Figures 28, 30, and 38, the first active layer may include: a first active portion 71, a third active portion 73, a fourth active portion 74, a redundant fourth active portion 74S, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, a sixteenth active portion 716, a seventeenth active portion 717, and a first initial signal line Vinit1. The first active portion 71 is used to form a channel region of the first transistor T1. The third active portion 73 may be used to form a channel region of the first driving transistor T31; the fourth active portion 74 may be used to form a channel region of the fourth transistor T4; the redundant fourth active portion 74S may be used to form a channel region of the redundant fourth transistor T4S; the fifth active portion 75 may be used to form a channel region of the fifth transistor T5; the sixth active portion 76 may be used to form a channel region of the sixth transistor T6; the seventh active portion 77 may be used to form a channel region of the seventh transistor T7; the eighth active portion 78 may be used to form a channel region of the eighth transistor T8; the ninth active portion 79 is connected between the third active portion 73 and the sixth active portion 76; the tenth active portion 710 and the twelfth active portion 711 are connected to each other. 2 is connected to both ends of the eighth active portion 78; the eleventh active portion 711 is connected between the fifth active portion 75 and the third active portion 73; the thirteenth active portion 713 is connected to a side of the fourth active portion 74 away from the third active portion 73, and is connected to a side of the redundant fourth active portion 74S away from the third active portion 73; the fourteenth active portion 714 is connected to a side of the seventh active portion 77 away from the sixth active portion 76; the fifteenth active portion 715 is connected to a side of the fifth active portion 75 away from the third active portion 73; the sixteenth active portion 716 is connected between the seventh active portion 77 and the sixth active portion 76, and the seventeenth active portion 717 is connected between the fourth active portion 74 and the third active portion 73. The first initial signal line Vinit1 can be used to provide the first initial signal terminal in Figure 7. The orthographic projection of the first initial signal line Vinit1 on the substrate extends along the first direction X. The first initial signal line Vinit1 is connected to multiple first active portions 71 in the same row of pixel driving circuits. The first active layer can be formed of polycrystalline silicon material. Accordingly, the first transistor T1, the first driving transistor T31, the fourth transistor T4, the redundant fourth transistor T4S, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low-temperature polycrystalline silicon thin film transistors.

[0267] The orthographic projection of the shielding portion 81 on the substrate can at least partially overlap the orthographic projection of the third active portion 73 on the substrate. The shielding portion 81 can shield the third active portion 73 from light, thereby improving the stability of the output characteristics of the first drive transistor. The shielding layer can be a conductive structure, and the shielding layer can be connected to a stable voltage source to provide signal shielding for the pixel drive circuit.

[0268] As shown in Figures 28, 31, and 38, the first gate layer may include: a first conductive portion 11, a second gate line G2, a redundant second gate line segment G21S, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal shown in Figure 7; the enable signal line EM can be used to provide the enable signal terminal shown in Figure 7; the first reset signal line Re1 can be used to provide the first reset signal terminal shown in Figure 7; the second reset signal line Re2 can be used to provide the second reset signal terminal shown in Figure 7; and the redundant second gate line segment G21S can be used to provide the redundant second gate drive signal terminal shown in Figure 7. The orthographic projection of the second gate line G2 on the substrate, the orthographic projection of the enable signal line EM on the substrate, the orthographic projection of the first reset signal line Re1 on the substrate, and the orthographic projection of the second reset signal line Re2 on the substrate can all extend along the first direction X. The second gate line G2 includes a plurality of second sub-gate lines G21, the orthographic projections of the plurality of second sub-gate lines G21 on the substrate being spaced apart along the first direction X. The orthographic projection of the second sub-gate line G21 on the substrate overlaps the orthographic projection of the fourth active portion 74 on the substrate. Part of the second sub-gate line G21 forms the gate of the fourth transistor. The orthographic projection of the redundant second gate line segment G21S on the substrate overlaps the orthographic projection of the redundant fourth active portion 74S on the substrate. Part of the redundant second gate line segment G21S forms the gate of the redundant fourth transistor. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projections of the fifth active portion 75 and the sixth active portion 76 on the substrate. Part of the enable signal line EM can form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The first reset signal line Re1 includes multiple first sub-reset signal lines Re11. The orthographic projections of the multiple first sub-reset signal lines Re11 on the substrate are spaced apart along the first direction X. The orthographic projections of the first sub-reset signal lines Re11 on the substrate can overlap the orthographic projection of the first active portion 71 on the substrate. Part of the first sub-reset signal line Re11 forms the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate can overlap the orthographic projection of the seventh active portion 77 and the orthographic projection of the eighth active portion 78 on the substrate. Portions of the second reset signal line Re2 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 on the substrate overlaps the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 can be used to form the gate of the first drive transistor T31 and the first electrode of the capacitor C. The display panel can use the first gate layer as a mask to perform a conductorization process on the first active layer. Specifically, the area of ​​the first active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first gate layer forms a conductor structure.

[0269] As shown in Figures 28, 32, and 39, the second gate layer may include: a third gate line 2G1, a second conductive portion 22, and a redundant third gate line 2G1S. The orthographic projection of the third gate line 2G1 on the base substrate and the orthographic projection of the redundant third gate line 2G1S on the base substrate both extend along the first direction X. The third gate line 2G1 can be used to provide the first gate drive signal terminal in Figure 7, and the redundant third gate line 2G1S is used to provide the redundant first gate drive signal terminal in Figure 7. The orthographic projection of the second conductive portion 22 on the base substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the base substrate. The second conductive portion 22 is used to form the second electrode of the capacitor C.

[0270] As shown in Figures 28, 33, and 40, the second active layer may include an active portion 9, which may include: a second active portion 92, a redundant second active portion 92S, a nineteenth active portion 919 connected between the second active portion 92 and the redundant second active portion 92S, a twentieth active portion 920 connected to the side of the second active portion 92 away from the redundant second active portion 92S, and a twenty-first active portion 921 connected to the side of the redundant second active portion 92S away from the second active portion 92. The second active portion 92 is used to form the channel region of the second transistor T2, and the redundant second active portion 92S is used to form the channel region of the redundant second transistor T2S. The second active layer may be formed of indium gallium zinc oxide, and accordingly, the second transistor T2 and the redundant second transistor T2S may be N-type metal oxide thin film transistors. The orthographic projection of the third gate line 2G1 on the substrate may overlap the orthographic projection of the second active portion 92 on the substrate, and a portion of the structure of the third gate line 2G1 may be used to form the bottom gate of the second transistor T2. The orthographic projection of the redundant third gate line 2G1S on the base substrate may cover the orthographic projection of the redundant second active portion 92S on the base substrate, and a partial structure of the redundant third gate line 2G1S may be used to form a bottom gate of the redundant second transistor T2S.

[0271] As shown in Figures 28, 34, and 41, the third gate layer may include a first gate line 3G1, a redundant first gate line 3G1S, and a second initial signal line Vinit2. The orthographic projection of the first gate line 3G1 on the base substrate, the orthographic projection of the redundant first gate line 3G1S on the base substrate, and the orthographic projection of the second initial signal line Vinit2 on the base substrate may extend along a first direction X. The first gate line 3G1 may be used to provide the first gate drive signal terminal in Figure 7. The orthographic projection of the first gate line 3G1 on the base substrate may cover the orthographic projection of the second active portion 92 on the base substrate. A partial structure of the first gate line 3G1 may be used to form the top gate of the second transistor T2. At the same time, the first gate line 3G1 may be connected to the third gate line 2G1 through a via located in the border area of ​​the display panel. The redundant first gate line 3G1S can be used to provide the redundant first gate drive signal terminal in Figure 7. The orthographic projection of the redundant first gate line 3G1S on the base substrate can cover the orthographic projection of the redundant second active portion 92S on the base substrate. Part of the structure of the redundant first gate line 3G1S can be used to form the top gate of the redundant second transistor T2S. At the same time, the redundant first gate line 3G1S can be connected to the redundant third gate line 2G1S through a via located in the display panel frame area. The second initial signal line Vinit2 is used to provide the second initial signal terminal in Figure 7. In addition, the display panel can use the third gate layer as a mask to perform conductor processing on the second active layer. That is, the area of ​​the second active layer covered by the third gate layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third gate layer forms a conductor structure.

[0272] As shown in Figures 28, 34, and 41, in the same pixel driving circuit, the orthographic projection of the first gate line 3G1 on the substrate is located between the orthographic projection of the second gate line G2 on the substrate and the orthographic projection of the first conductive portion 11 on the substrate, the orthographic projection of the redundant first gate line 3G1S on the substrate is located between the orthographic projection of the second gate line G2 on the substrate and the orthographic projection of the first gate line 3G1 on the substrate, and the orthographic projection of the redundant second gate line segment G21S on the substrate is located on the side of the orthographic projection of the second gate line G2 on the substrate away from the orthographic projection of the first gate line 3G1 on the substrate.

[0273] As shown in Figures 28, 34, and 41, in the first direction of the same pixel driving circuit: the orthographic projection of the redundant second active portion 92S on the substrate is located between the orthographic projection of the second active portion 92 on the substrate and the orthographic projection of the fourth active portion 74 on the substrate, and the orthographic projection of the redundant fourth active portion 74S on the substrate is located between the orthographic projection of the fourth active portion 74 on the substrate and the orthographic projection of the sixth active portion 76 on the substrate.

[0274] As shown in FIG. 28 , 34 , and 41 , the length direction of the channel region of the redundant fourth transistor T4S is the first direction X.

[0275] As shown in Figure 41, when the gate of the second transistor leaks electricity to the source and drain, the channel region of the second transistor and the gate of the first driving transistor can be interrupted in the second active layer along the dotted line FF in Figure 41, and the dotted line FF can be located between the second active portion 72 and the nineteenth active portion 919.

[0276] As shown in Figures 28, 35, and 42, the first source-drain layer may include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, a third initial signal line Vinit3, a second reset connection line 4Re2, a second gate connection line 4G2, a redundant second gate connection line 4G2S, and a first reset connection line 4Re1. The first bridge portion 41 may be connected to the ninth active portion 79 and the twentieth active portion 920 through vias, respectively, to connect the second electrode of the second transistor T2 and the second electrode of the first drive transistor T31. The second bridge portion 42 may be connected to the fourteenth active portion 714 and the second initial signal line Vinit2 through vias, respectively, to connect the first electrode of the seventh transistor T7 and the second initial signal line. The third bridge portion 43 may be connected to the thirteenth active portion 713 through a via, to connect the first electrode of the fourth transistor T4. The fourth bridge portion 44 connects the eleventh active portion 711 and the tenth active portion 710 through vias, respectively, to connect the second electrode of the eighth transistor T8 and the first electrode of the first driving transistor T31. The fifth bridge portion 45 connects the second conductive portion 22 and the fifteenth active portion 715 through vias, respectively, to connect the second electrode of the capacitor C and the first electrode of the fifth transistor T5. The orthographic projection of the fifth bridge portion 45 on the substrate extends along the first direction X. The fifth bridge portion 45 connects multiple second conductive portions 22 and multiple fifteenth active portions 715 in the same row of pixel driving circuits. The sixth bridge portion 46 connects the nineteenth active portion 919 and the first conductive portion 11 through vias, respectively, to connect the gate of the first driving transistor T31 and the first electrode of the second transistor T2. The second conductive portion 22 may have an opening 221 formed therein, and a via connecting the sixth bridge portion 46 and the first conductive portion 11 is provided through the opening 221. The seventh bridge portion 47 is connected to the sixteenth active portion 716 via a via to connect to the second electrode of the sixth transistor. The third initial signal line Vinit3 is used to provide the third initial signal terminal in Figure 7. The orthographic projection of the third initial signal line Vinit3 on the substrate extends along the first direction X. The third initial signal line Vinit3 is connected to the twelfth active portion 712 via a via to connect the first electrode and the third initial signal terminal of the eighth transistor. The first reset connection line 4Re1 is connected to multiple first sub-reset signal lines Re11 located in the same row of pixel driving circuits via a via. The square resistance of the first source and drain layer is less than the square resistance of the first gate layer. This configuration can reduce the voltage drop on the first reset signal line Re1. The second reset connection line 4Re2 is connected to the second reset signal line Re2 via a via. This configuration can also reduce the voltage drop on the second reset signal line Re2.The second gate connection line 4G2 can be connected to multiple second sub-gate lines G21 located in the same row of pixel driving circuits through vias. This setting can also reduce the voltage drop on the second gate line G2. The redundant second gate connection line 4G2S can be connected to multiple redundant second gate line segments G21S located in the same row of pixel driving circuits through vias. This setting can also reduce the voltage drop on the redundant second gate line segments G21S.

[0277] As shown in Figures 28-42, the size of the orthographic projection of the twenty-first active portion 921 on the substrate in the first direction X is greater than the size of the orthographic projection of the redundant second active portion 92 on the substrate in the first direction X, and the orthographic projection of the twenty-first active portion 921 on the substrate overlaps with the orthographic projection of the second gate line G2 on the substrate. The twenty-first active portion 921 can shield the coupling effect of the second gate line G2 on the sixth bridge portion 46, thereby improving the voltage stability of the gate of the first drive transistor during the light-emitting stage. In addition, during the data writing stage of the pixel drive circuit, the second gate line G2 is pulled low, and the second gate line G2 can pull down the voltage of the second electrode and gate of the first drive transistor through the twenty-first active portion 921, thereby increasing the speed at which the data line writes the compensation voltage to the gate of the first drive transistor.

[0278] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in other conductive layers. For example, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in the second gate layer, the third gate layer, the first source and drain layer, etc.

[0279] As shown in Figures 28 and 36 , the second source / drain layer may include a data line Da, a first power line VDD, and an eighth bridge portion 58. The orthographic projections of the data line Da and the first power line VDD on the substrate extend along the second direction Y. The data line Da is used to provide the data signal terminal shown in Figure 7 , and the first power line VDD is used to provide the first power terminal shown in Figure 7 . The eighth bridge portion 58 is connected to the seventh bridge portion 47 via a via.

[0280] As shown in Figures 28 and 36, the second source and drain layer may further include a third initial connection line 5Vinit3. The orthographic projection of the third initial connection line 5Vinit3 on the base substrate extends along the second direction Y. The third initial connection line 5Vinit3 may be connected to at least a portion of the third initial signal line Vinit3 intersecting therewith via a via. This configuration can reduce the intrinsic resistance of the third initial signal line Vinit3, thereby reducing the voltage drop of the initial signal on the third initial signal line Vinit3, thereby improving the display uniformity of the display panel. It should be understood that in other exemplary embodiments, the second source and drain layer may include one or more of the first initial connection line, the second initial connection line, and the third initial connection line. The orthographic projection of the first initial connection line on the base substrate extends along the second direction Y. The first initial connection line may be connected to at least a portion of the first initial signal line intersecting therewith via a via. The orthographic projection of the second initial connection line on the base substrate extends along the second direction Y. The second initial connection line may be connected to at least a portion of the second initial signal line intersecting therewith via a via.

[0281] In this exemplary embodiment, as shown in FIG43 , which is a partial cross-sectional view of the display panel shown in FIG28 taken along dotted line BB, the display panel may further include a buffer layer 101, a first insulating layer 102, a second insulating layer 103, a third insulating layer 104, a fourth insulating layer 105, a first dielectric layer 106, a passivation layer 107, and a first planarization layer 108. The substrate 100, the shielding layer, the buffer layer 101, the first active layer, the first insulating layer 102, the first gate layer, the second insulating layer 103, the second gate layer, the third insulating layer 104, the second active layer, the fourth insulating layer 105, the third gate layer, the first dielectric layer 106, the first source and drain layer, the passivation layer 107, the first planarization layer 108, and the second source and drain layer are stacked in sequence. The buffer layer 101, first insulating layer 102, second insulating layer 103, third insulating layer 104, and fourth insulating layer 105 can be single-layer or multi-layer structures. The materials of the first insulating layer 102, second insulating layer 103, third insulating layer 104, and fourth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 106 can be a silicon nitride layer. The material of the first planarization layer 108 can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding (SOG), etc. The passivation layer 107 can be a silicon oxide layer. The base substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer can be an inorganic material. The materials of the first, second, and third gate layers can be molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacked conductive layers. The first source / drain layer and the second source / drain layer may include a metal material, for example, one of molybdenum, aluminum, copper, titanium, and niobium, or an alloy thereof, or a molybdenum / titanium alloy or stack, or a conductive layer such as a titanium / aluminum / titanium stack. The sheet resistance of any one of the first source / drain layer and the second source / drain layer may be less than the sheet resistance of any one of the first gate layer, the second gate layer, and the third gate layer.

[0282] As shown in FIG44 , it is a structural diagram of another exemplary embodiment of the pixel driving circuit disclosed in the present invention. The pixel driving circuit shown in FIG44 differs from the pixel driving circuit shown in FIG3 only in that the pixel driving circuit shown in FIG44 does not include the eighth transistor.

[0283] This exemplary embodiment also provides a display panel, which may include a base substrate, a blocking layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source-drain layer, and a second source-drain layer stacked in sequence. An insulating layer may be provided between the above-mentioned adjacent layers. As shown in Figures 45-59, Figure 45 is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein, Figure 46 is a structural layout diagram of the blocking layer in Figure 45, Figure 47 is a structural layout diagram of the first active layer in Figure 45, Figure 48 is a structural layout diagram of the first gate layer in Figure 45, Figure 49 is a structural layout diagram of the second gate layer in Figure 45, Figure 50 is a structural layout diagram of the second active layer in Figure 45, Figure 51 is a structural layout diagram of the third gate layer in Figure 45, Figure 52 is a structural layout diagram of the first source-drain layer in Figure 45, Figure 53 is a structural layout diagram of the second source-drain layer in Figure 45, and Figure 54 is a structural layout diagram of the blocking layer and the first active layer in Figure 45. Figure 55 is the structural layout of the blocking layer, the first active layer, and the first gate layer in Figure 45, Figure 56 is the structural layout of the blocking layer, the first active layer, the first gate layer, and the second gate layer in Figure 45, Figure 57 is the structural layout of the blocking layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in Figure 45, Figure 58 is the structural layout of the blocking layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in Figure 45, and Figure 59 is the structural layout of the blocking layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source and drain layer in Figure 45.

[0284] The display panel may include multiple pixel driving circuits as shown in Figure 44. As shown in Figure 45, the display panel may include multiple pixel units distributed in a first direction X and a second direction Y. The pixel units may include a first pixel driving circuit Pix1 and a second pixel driving circuit Pix2 adjacently distributed in the first direction X. At least part of the structure of the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 may be arranged in mirror symmetry about a mirror symmetry plane CC. The mirror symmetry plane CC may be perpendicular to the substrate. The orthographic projection of the first pixel driving circuit Pix1 on the substrate and the orthographic projection of the second pixel driving circuit Pix2 on the substrate may at least partially be arranged symmetrically about the intersection of the mirror symmetry plane CC and the substrate as an axis of symmetry. The first direction X and the second direction Y intersect. For example, the first direction X may be a row direction, and the second direction Y may be a column direction.

[0285] As shown in Figures 45, 46 and 54, the shielding layer includes a plurality of shielding portions 81 distributed in an array along the first direction X and the second direction Y, and the shielding portions 81 are connected to each other.

[0286] As shown in Figures 45, 47, and 55, the first active layer may include: a first active portion 71, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, a ninth active portion 79, a tenth active portion 710, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, a sixteenth active portion 716, and a seventeenth active portion 717. The first active portion 71 is used to form the channel region of the first transistor T1; the third active portion 73 may be used to form the channel region of the first driving transistor T31; the fourth active portion 74 may be used to form the channel region of the fourth transistor T4; the fifth active portion 75 may be used to form the channel region of the fifth transistor T5; the sixth active portion 76 may be used to form the channel region of the sixth transistor T6; the seventh active portion 77 may be used to form the channel region of the seventh transistor T7; the thirteenth active portion 713 is connected to the fourth active portion 74. The fourteenth active portion 714 is connected to a side of the seventh active portion 77 away from the sixth active portion 76; the fifteenth active portion 715 is connected to a side of the fifth active portion 75 away from the third active portion 73. In the same pixel unit, two pixel driving circuits can share the same fifteenth active portion 715; the sixteenth active portion 716 is connected between the seventh active portion 77 and the sixth active portion 76; the seventeenth active portion 717 and the eighteenth active portion 718 are connected to both ends of the first active portion 71. The first active layer can be formed of polysilicon material. Accordingly, the first transistor T1, the first driving transistor T31, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polysilicon thin film transistors.

[0287] The orthographic projection of the shielding portion 81 on the substrate can at least partially overlap the orthographic projection of the third active portion 73 on the substrate. The shielding portion 81 can shield the third active portion 73 from light, thereby improving the stability of the output characteristics of the first drive transistor. The shielding layer can be a conductive structure, and the shielding layer can be connected to a stable voltage source to provide signal shielding for the pixel drive circuit.

[0288] As shown in Figures 45, 48, and 55, the first gate layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal in Figure 44; the enable signal line EM can be used to provide the enable signal terminal in Figure 44; the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 44; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 44. The orthographic projection of the second gate line G2 on the base substrate, the orthographic projection of the enable signal line EM on the base substrate, the orthographic projection of the first reset signal line Re1 on the base substrate, and the orthographic projection of the second reset signal line Re2 on the base substrate can all extend along the first direction X. The orthographic projection of the second gate line G2 on the base substrate covers the orthographic projection of the fourth active portion 74 on the base substrate, and a portion of the structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projection of the fifth active portion 75 and the orthographic projection of the sixth active portion 76 on the substrate. Portions of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 on the substrate overlaps the orthographic projection of the first active portion 71 on the substrate. Portions of the first reset signal line Re1 can be used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate overlaps the orthographic projection of the seventh active portion 77 on the substrate. Portions of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7. The orthographic projection of the first conductive portion 11 on the substrate overlaps the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 can be used to form the gate of the first drive transistor T31 and the first electrode of the capacitor C. The display panel can use the first gate layer as a mask to conduct conductor processing on the first active layer, that is, the area of ​​the first active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first gate layer forms a conductor structure.

[0289] As shown in Figures 45, 49, and 56, the second gate layer may include: a third gate line 2G1, a redundant third gate line 2G1S, a second conductive portion 22, and a first initial signal line Vinit1. The orthographic projections of the third gate line 2G1, the redundant third gate line 2G1S, and the first initial signal line Vinit1 on the base substrate extend along the first direction X. The third gate line 2G1 can be used to provide the first gate drive signal terminal in Figure 44. The first initial signal line Vinit1 can be used to provide the first initial signal terminal in Figure 44, and the redundant third gate line 2G1S is used to provide the redundant first gate drive signal terminal in Figure 44. The orthographic projection of the second conductive portion 22 on the base substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the base substrate. The second conductive portion 22 is used to form the second electrode of the capacitor C.

[0290] As shown in Figures 45, 50, and 57, the second active layer may include an active portion 9, which may include: a second active portion 92, a redundant second active portion 92S, a nineteenth active portion 919 connected between the second active portion 92 and the redundant second active portion 92S, a twentieth active portion 920 connected to the side of the second active portion 92 away from the redundant second active portion 92S, and a twenty-first active portion 921 connected to the side of the redundant second active portion 92S away from the second active portion 92. The second active portion 92 is used to form the channel region of the second transistor T2, and the redundant second active portion 92S is used to form the channel region of the redundant second transistor T2S. The second active layer may be formed of indium gallium zinc oxide, and accordingly, the second transistor T2 and the redundant second transistor T2S may be N-type metal oxide thin film transistors. The orthographic projection of the third gate line 2G1 on the substrate may overlap the orthographic projection of the second active portion 92 on the substrate, and a portion of the structure of the third gate line 2G1 may be used to form the bottom gate of the second transistor T2. The orthographic projection of the redundant third gate line 2G1S on the base substrate may cover the orthographic projection of the redundant second active portion 92S on the base substrate, and a partial structure of the redundant third gate line 2G1S may be used to form a bottom gate of the redundant second transistor T2S.

[0291] As shown in Figures 45, 51, and 58, the third gate layer may include a first gate line 3G1, a redundant first gate line 3G1S, and a second initial signal line Vinit2. The orthographic projections of the first gate line 3G1, the redundant first gate line 3G1S, and the second initial signal line Vinit2 on the base substrate may all extend along the first direction X. The first gate line 3G1 may be used to provide the first gate drive signal terminal in Figure 44. The orthographic projection of the first gate line 3G1 on the base substrate may cover the orthographic projection of the second active portion 92 on the base substrate. A partial structure of the first gate line 3G1 may be used to form the top gate of the second transistor T2. At the same time, the first gate line 3G1 may be connected to the third gate line 2G1 through a via located in the border area of ​​the display panel. The redundant first gate line 3G1S can be used to provide the redundant first gate drive signal terminal in Figure 44. The orthographic projection of the redundant first gate line 3G1S on the base substrate can cover the orthographic projection of the redundant second active portion 92S on the base substrate. Part of the structure of the redundant first gate line 3G1S can be used to form the top gate of the redundant second transistor T2S. At the same time, the redundant first gate line 3G1S can be connected to the redundant third gate line 2G1S through a via located in the display panel frame area. The second initial signal line Vinit2 is used to provide the second initial signal terminal in Figure 44. In addition, the display panel can use the third gate layer as a mask to perform conductor processing on the second active layer. That is, the area of ​​the second active layer covered by the third gate layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third gate layer forms a conductor structure.

[0292] As shown in Figures 45, 51, and 58, in the same pixel driving circuit, the orthographic projection of the redundant first gate line 3G1S on the substrate is located between the orthographic projection of the first reset signal line Re1 and the orthographic projection of the first gate line 3G1 on the substrate, and the orthographic projection of the second gate line G2 on the substrate is located between the orthographic projection of the first gate line 3G1 and the orthographic projection of the redundant first gate line 3G1S on the substrate. This pixel driving circuit has a high degree of integration.

[0293] As shown in Figures 45, 51, and 58, in the first direction X of the same pixel driving circuit, the orthographic projection of the redundant second active portion 92S on the base substrate is located between the orthographic projection of the second active portion 92 on the base substrate and the orthographic projection of the fifth active portion 75 on the base substrate.

[0294] As shown in Figure 58, when the gate of the second transistor leaks electricity to the source and drain, the channel region of the second transistor and the gate of the first driving transistor can be interrupted in the second active layer along the dotted line HH in Figure 58, and the dotted line HH can be located between the second active portion 72 and the nineteenth active portion 919.

[0295] As shown in Figures 45, 52, and 59, the first source-drain layer may include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, a ninth bridge portion 49, a first fan-out line FIPH, and a tenth bridge portion 410. The first bridge portion 41 is connected to the twenty-first active portion 921, the twentieth active portion 920, the seventeenth active portion 717, and the ninth active portion 79 through vias, respectively, to connect the second electrode of the first transistor, the second electrode of the redundant second transistor, the second electrode of the second transistor, and the second electrode of the first driver transistor. The second bridge portion 42 is connected to the fourteenth active portion 714 and the second initial signal line Vinit2 through vias, respectively, to connect the first electrode and the second initial signal terminal of the seventh transistor. The third bridge portion 43 is connected to the thirteenth active portion 713 through a via, to connect the first electrode of the fourth transistor. The fifth bridge portion 45 is connected to the second conductive portion 22 and the fifteenth active portion 715 through vias, respectively, to connect the second electrode of the capacitor C and the first electrode of the fifth transistor T5. Two pixel driving circuits in the same pixel unit can share the same fifth bridge portion 45. The sixth bridge portion 46 is connected to the nineteenth active portion 919 and the first conductive portion 11 through vias, respectively, to connect the gate of the first driving transistor T31 and the first electrode of the second transistor T2 and the first electrode of the redundant second transistor T2S. The second conductive portion 22 may have an opening 221 formed therein, and a via connected between the sixth bridge portion 46 and the first conductive portion 11 is provided through the opening 221. The seventh bridge portion 47 is connected to the sixteenth active portion 716 through a via, to connect the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6. The ninth bridge portion 49 connects the first initial signal line Vinit1 and the eighteenth active portion 718 via vias, thereby connecting the first electrode of the first transistor to the first initial signal terminal. Two adjacent pixel units in the first direction X can share the same ninth bridge portion 49. The orthographic projection of the first fan-out line FIPH on the substrate can extend along the first direction X. The first fan-out line FIPH can serve as a fan-out line connecting the data line in the FIP (Fanout In Pixel). A portion of the tenth bridge portion 410 can be connected to the same layer as the first fan-out line FIPH. The first fan-out line FIPH can be connected to the column-direction data fan-out line vias via the tenth bridge portion 410. The portion of the tenth bridge portion 410 can be spaced apart from the first fan-out line FIPH. The column-direction data fan-out line is also connected to the portion of the eleventh conductive portion 511 via vias. The portion of the eleventh conductive portion 511 can ensure uniform reflective and light transmittance characteristics at different locations on the display panel.

[0296] As shown in Figures 45 and 53, the second source-drain layer may include: a data line Da, a first power line VDD, a second fan-out line FIPV, and an eighth bridge portion 58. The orthographic projections of the data line Da, the first power line VDD, and the second fan-out line FIPV on the substrate may extend along the second direction Y. The data line Da is used to provide the data signal terminal shown in Figure 44, and the first power line VDD is used to provide the first power terminal shown in Figure 44. The data line Da can be connected to the third bridge portion 43 via a via to connect the data signal terminal and the first electrode of the fourth transistor. The first power line VDD can be connected to the fifth bridge portion 45 via a via to connect the first electrode of the fifth transistor and the first power terminal. The second fan-out line FIPV can serve as a fan-out line connecting the data line in the FIP (Fanout In Pixel) and can be connected to the tenth bridge portion 410 via a via. The eighth bridge portion 58 is connected to the seventh bridge portion 47 via a via.

[0297] FIG60 is a partial cross-sectional view of the display panel shown in FIG45 taken along the dotted line DD. The display panel may further include a buffer layer 101, a first insulating layer 102, a second insulating layer 103, a third insulating layer 104, a fourth insulating layer 105, a first dielectric layer 106, a passivation layer 107, and a first planarization layer 108. The substrate 100, the shielding layer, the buffer layer 101, the first active layer, the first insulating layer 102, the first gate layer, the second insulating layer 103, the second gate layer, the third insulating layer 104, the second active layer, the fourth insulating layer 105, the third gate layer, the first dielectric layer 106, the first source and drain layer, the passivation layer 107, the first planarization layer 108, and the second source and drain layer are stacked in sequence. The buffer layer 101, first insulating layer 102, second insulating layer 103, third insulating layer 104, and fourth insulating layer 105 can be single-layer or multi-layer structures. The materials of the first insulating layer 102, second insulating layer 103, third insulating layer 104, and fourth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 106 can be a silicon nitride layer. The material of the first planarization layer 108 can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding (SOG), etc. The passivation layer 107 can be a silicon oxide layer. The base substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer can be an inorganic material. The materials of the first, second, and third gate layers can be molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacked conductive layers. The first source / drain layer and the second source / drain layer may include a metal material, for example, one of molybdenum, aluminum, copper, titanium, and niobium, or an alloy thereof, or a molybdenum / titanium alloy or stack, or a conductive layer such as a titanium / aluminum / titanium stack. The sheet resistance of any one of the first source / drain layer and the second source / drain layer may be less than the sheet resistance of any one of the first gate layer, the second gate layer, and the third gate layer.

[0298] It should be noted that in the above exemplary embodiment, the black squares drawn on the side of the first source and drain layer facing away from the substrate represent vias connecting the first source and drain layer to other layers facing the substrate; the black squares drawn on the side of the second source and drain layer facing away from the substrate represent vias connecting the second source and drain layer to other layers facing the substrate. Different vias represented by black squares in different locations can penetrate different insulating layers.

[0299] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematics. In addition, qualifiers such as first and second are only used to limit different structure names, and they do not have a specific order meaning. The same structural layer can be formed by the same composition process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends in a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction.

[0300] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, a television, or other display device.

[0301] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0302] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0303] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A pixel driving circuit, wherein: The pixel driving circuit includes: at least one driving circuit, the driving circuit comprising a control signal terminal and two current transmission terminals, the two current transmission terminals comprising a first current transmission terminal and a second current transmission terminal, the driving circuit being configured to generate a driving current between the two current transmission terminals according to a signal from the control signal terminal, the at least one driving circuit comprising a first driving circuit; a data writing circuit connected to the first current transmission terminal and the data signal terminal of the first driving circuit, the data writing circuit being configured to respond to a control signal to transmit a signal from the data signal terminal to the first current transmission terminal of the first driving circuit; a compensation circuit connected to the second current transmission terminal, the control signal terminal, and the first gate drive signal terminal of the first drive circuit, the compensation circuit being configured to conduct the control signal terminal and the second current transmission terminal of the first drive circuit in response to a signal at the first gate drive signal terminal; A redundant circuit, comprising a redundant compensation circuit, wherein the redundant compensation circuit is connected between a control signal terminal and a current transmission terminal of the driving circuit, and the redundant compensation circuit is used to respond to a control signal to conduct the control signal terminal and the current transmission terminal connected thereto.

2. The pixel driving circuit according to claim 1, wherein: The redundancy compensation circuit is connected to the control signal terminal and the second current transmission terminal of the first driving circuit, and is used for responding to a control signal to conduct the control signal terminal and the second current transmission terminal of the first driving circuit.

3. The pixel driving circuit according to claim 1, wherein: The redundancy compensation circuit is connected to the control signal terminal and the first current transmission terminal of the first driving circuit, and is used to respond to a control signal to conduct the control signal terminal and the first current transmission terminal of the first driving circuit; The redundant circuit further includes: The redundant data writing circuit is connected to the second current transmission end and the data signal end of the first driving circuit, and is used to respond to a control signal to transmit the data signal of the data signal end to the second current transmission end of the first driving circuit.

4. The pixel driving circuit according to claim 1, wherein: The at least one driving circuit includes a second driving circuit; The redundant compensation circuit is connected to a control signal terminal and a current transmission terminal of the second driving circuit, and is used for responding to a control signal to conduct the control signal terminal and the current transmission terminal of the second driving circuit.

5. The pixel driving circuit according to claim 4, wherein: The first current transmission end of the first driving circuit is connected to the first current transmission end of the second driving circuit; The redundancy compensation circuit is connected to the control signal terminal and the second current transmission terminal of the second driving circuit, and is used for responding to a control signal to conduct the control signal terminal and the second current transmission terminal of the second driving circuit.

6. The pixel driving circuit according to claim 5, wherein: The pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit further includes: a light-emitting control circuit connected to a first power supply terminal, a first current transmission terminal of the first driving circuit, a second current transmission terminal of the first driving circuit, an enable signal terminal, and a first electrode of the light-emitting unit, the light-emitting control circuit being configured to connect the first power supply terminal and the first current transmission terminal of the first driving circuit in response to a signal from the enable signal terminal, and to connect the second current transmission terminal of the first driving circuit and the first electrode of the light-emitting unit in response to a signal from the enable signal terminal; a first reset circuit, the first reset circuit being connected to the second current transmission terminal of the first driving circuit, the first initial signal terminal, and the first reset signal terminal, the first reset circuit being configured to respond to a signal at the first reset signal terminal to transmit a signal at the first initial signal terminal to the second current transmission terminal of the first driving circuit; a second reset circuit, connected to the first electrode of the light-emitting unit, the second initial signal terminal, and the second reset signal terminal, the second reset circuit being configured to respond to a signal at the second reset signal terminal to transmit a signal at the second initial signal terminal to the first electrode of the light-emitting unit; a storage circuit connected between the control signal terminal of the first driving circuit and the first power supply terminal; The redundant circuit further includes: A redundant light emitting control circuit is connected to the first power supply terminal, the first current transmission terminal of the second driving circuit, the second current transmission terminal of the second driving circuit, and the first electrode of the light emitting unit. The redundant light emitting control circuit is used to respond to a control signal to connect the first power supply terminal and the first current transmission terminal of the second driving circuit, and connect the second current transmission terminal of the second driving circuit. a transmission end and a first electrode of the light emitting unit; a redundant first reset circuit, the redundant first reset circuit being connected to the second current transmission terminal and the first initial signal terminal of the second driving circuit, the first reset circuit being configured to transmit a signal from the first initial signal terminal to the second current transmission terminal of the second driving circuit in response to a control signal; The redundant storage circuit is connected between the control signal terminal of the second driving circuit and the first power supply terminal.

7. The pixel driving circuit according to any one of claims 1 to 5, wherein: The pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit further includes: a light-emitting control circuit connected to a first power supply terminal, a first current transmission terminal of the first driving circuit, a second current transmission terminal of the first driving circuit, an enable signal terminal, and a first electrode of the light-emitting unit, the light-emitting control circuit being configured to connect the first power supply terminal and the first current transmission terminal of the first driving circuit in response to a signal from the enable signal terminal, and to connect the second current transmission terminal of the first driving circuit and the first electrode of the light-emitting unit in response to a signal from the enable signal terminal; a second reset circuit, connected to the first electrode of the light-emitting unit, the second initial signal terminal, and the second reset signal terminal, the second reset circuit being configured to respond to a signal at the second reset signal terminal to transmit a signal at the second initial signal terminal to the first electrode of the light-emitting unit; a third reset circuit, connected to the first current transmission terminal, the third initial signal terminal, and the second reset signal terminal of the first driving circuit, the third reset circuit being configured to respond to a signal from the second reset signal terminal to transmit a signal from the third initial signal terminal to the first current transmission terminal of the first driving circuit; The storage circuit is connected between the control signal terminal of the first driving circuit and the first power supply terminal.

8. The pixel driving circuit according to claim 7, wherein: The pixel driving circuit further includes: A first reset circuit, wherein the first reset circuit is connected to the control signal terminal, the first initial signal terminal, and the first reset signal terminal of the first driving circuit, and the first reset circuit is used to respond to the signal of the first reset signal terminal to transmit the signal of the first initial signal terminal to the control signal terminal of the first driving circuit.

9. The pixel driving circuit according to claim 7, wherein: The pixel driving circuit further includes: A first reset circuit, wherein the first reset circuit is connected to the second current transmission end, the first initial signal end, and the first reset signal end of the first drive circuit, and the first reset circuit is used to respond to the signal of the first reset signal end to transmit the signal of the first initial signal end to the second current transmission end of the first drive circuit.

10. The pixel driving circuit according to claim 1, wherein: The first driving circuit includes: a first driving transistor, wherein a gate of the first driving transistor forms a control signal terminal of the first driving circuit, a first electrode of the first driving transistor forms a first current transmission terminal of the first driving circuit, and a second electrode of the first driving transistor forms a second current transmission terminal of the first driving circuit; The data writing circuit includes: a fourth transistor, wherein a first electrode of the fourth transistor is connected to the data signal terminal, a second electrode of the fourth transistor is connected to the first electrode of the first driving transistor, and a gate of the fourth transistor is connected to a second gate driving signal terminal; The compensation circuit comprises: A second transistor, wherein a first electrode of the second transistor is connected to the gate of the first driving transistor, a second electrode of the second transistor is connected to the second electrode of the first driving transistor, and a gate of the second transistor is connected to the first gate driving signal terminal.

11. The pixel driving circuit according to claim 2, wherein: The redundancy compensation circuit includes: A redundant second transistor, wherein a first electrode of the redundant second transistor is connected to the control signal terminal of the first driving circuit, and a second electrode of the redundant second transistor is connected to the second current transmission terminal of the first driving circuit.

12. The pixel driving circuit according to claim 3, wherein: The redundancy compensation circuit includes: a redundant second transistor, wherein a first electrode of the redundant second transistor is connected to the control signal terminal of the first driving circuit, and a second electrode of the redundant second transistor is connected to the first current transmission terminal of the first driving circuit; The redundant data writing circuit includes: A redundant fourth transistor, wherein a first electrode of the redundant fourth transistor is connected to the data signal end, and a second electrode of the redundant fourth transistor is connected to the second current transmission end of the first driving circuit.

13. The pixel driving circuit according to claim 5, wherein: The second driving circuit includes: a second driving transistor, wherein the gate of the second driving transistor forms a control signal terminal of the second driving current, the first electrode of the second driving transistor forms a first current transmission terminal of the second driving circuit, and the second electrode of the second driving transistor forms a second current transmission terminal of the second driving circuit; The redundancy compensation circuit includes: A redundant second transistor, wherein a first electrode of the redundant second transistor is connected to the gate of the second driving transistor, and a second electrode of the redundant second transistor is connected to the second electrode of the second driving transistor.

14. The pixel driving circuit according to claim 6, wherein: The light emitting control circuit includes: a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power supply terminal, a second electrode of the fifth transistor is connected to the first current transmission terminal of the first driving circuit, and a gate of the fifth transistor is connected to the enable signal terminal; a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second current transmission terminal of the first driving circuit, a second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, and a gate of the sixth transistor is connected to the enable signal terminal; The first reset circuit includes: a first transistor, wherein a first electrode of the first transistor is connected to the first initial signal terminal, a second electrode of the first transistor is connected to the second current transmission terminal of the first driving circuit, and a gate of the first transistor is connected to the first reset signal terminal; The second reset circuit includes: a seventh transistor, wherein a first electrode of the seventh transistor is connected to the second initial signal terminal, a second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, and a gate of the seventh transistor is connected to the second reset signal terminal; The storage circuit includes: a capacitor, wherein a first electrode of the capacitor is connected to the control signal terminal of the first driving circuit, and a second electrode of the capacitor is connected to the first power supply terminal; The redundant light emitting control circuit includes: a redundant fifth transistor, wherein a first electrode of the redundant fifth transistor is connected to the first power supply terminal, and a second electrode of the redundant fifth transistor is connected to the first current transmission terminal of the second driving circuit; A redundant sixth transistor, a first electrode of the redundant sixth transistor is connected to the second driving circuit a second current transmission end of the circuit, the second electrode being connected to the first electrode of the light emitting unit; The redundant first reset circuit includes: a redundant first transistor, wherein a first electrode of the redundant first transistor is connected to the first initial signal terminal, and a second electrode of the redundant first transistor is connected to the second current transmission terminal of the second driving circuit; The redundant storage circuit comprises: A redundant capacitor, wherein a first electrode of the redundant capacitor is connected to the control signal terminal of the second driving circuit, and a second electrode of the redundant capacitor is connected to the first power supply terminal.

15. The pixel driving circuit according to claim 7, wherein: The light emitting control circuit includes: a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power supply terminal, a second electrode of the fifth transistor is connected to the first current transmission terminal of the first driving circuit, and a gate of the fifth transistor is connected to the enable signal terminal; a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second current transmission terminal of the first driving circuit, a second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, and a gate of the sixth transistor is connected to the enable signal terminal; The second reset circuit includes: a seventh transistor, wherein a first electrode of the seventh transistor is connected to the second initial signal terminal, a second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, and a gate of the seventh transistor is connected to the second reset signal terminal; The third reset circuit includes: an eighth transistor, wherein a first electrode of the eighth transistor is connected to the third initial signal terminal, a second electrode of the eighth transistor is connected to the first current transmission terminal of the first driving circuit, and a gate of the eighth transistor is connected to the second reset signal terminal; The storage circuit includes: A capacitor, wherein a first electrode of the capacitor is connected to the control signal terminal of the first driving circuit, and a second electrode of the capacitor is connected to the first power supply terminal.

16. The pixel driving circuit according to claim 8, wherein: The first reset circuit includes: A first transistor, wherein a first electrode of the first transistor is connected to the first initial signal terminal, a second electrode is connected to the control signal terminal of the first driving circuit, and a gate is connected to the first reset signal terminal.

17. The pixel driving circuit according to claim 9, wherein: The first reset circuit includes: A first transistor, wherein a first electrode of the first transistor is connected to the first initial signal terminal, a second electrode is connected to the second current transmission terminal of the first driving circuit, and a gate is connected to the first reset signal terminal.

18. A display panel, wherein: The display panel comprises the pixel driving circuit according to any one of claims 1 to 17.

19. The display panel according to claim 18, wherein: In at least part of the pixel driving circuit, the connection between the channel region of the transistor in the compensation circuit and the control signal terminal of the first driving circuit is interrupted.

20. A display panel, wherein: The display panel includes a pixel driving circuit, and the pixel driving circuit includes: a first driving transistor; a fourth transistor, a first electrode of which is connected to the data line, and a second electrode of which is connected to the first electrode of the first driving transistor; a second transistor, a first electrode of which is connected to the gate of the first driving transistor, and a second electrode of which is connected to the second electrode of the first driving transistor; A redundant second transistor has a first electrode connected to the gate of the first driving transistor, and the redundant second transistor is used to write a compensation voltage into the gate of the first driving transistor.

21. The display panel according to claim 20, wherein: The second electrode of the redundant second transistor is connected to the second electrode of the first driving transistor, and the display panel further includes: substrate; a first active layer located on one side of the base substrate, the first active layer comprising a third active portion and a fourth active portion, the third active portion being used to form a channel region of the first driving transistor, and the fourth active portion being used to form a channel region of the fourth transistor; a first gate layer, located on a side of the first active layer facing away from the base substrate, the first gate layer comprising a first conductive portion and a second gate line, an orthographic projection of the first conductive portion on the base substrate overlapping an orthographic projection of the third active portion on the base substrate, the first conductive portion being used to form a gate of the first driving transistor, an orthographic projection of the second gate line on the base substrate extending along a first direction and covering an orthographic projection of the fourth active portion on the base substrate, and a portion of the second gate line being used to form a gate of the fourth transistor; The second active layer is located on a side of the first gate layer away from the substrate. The second active layer includes a second active portion and a redundant second active portion, wherein the second active portion is used to form a channel region of the second transistor, and the redundant second active portion is used to form a channel region of the redundant second transistor; A third gate layer is located on a side of the second active layer facing away from the base substrate, the third gate layer includes a first gate line and a redundant first gate line, the orthographic projection of the first gate line on the base substrate extends along the first direction and covers the orthographic projection of the second active portion on the base substrate, a partial structure of the first gate line is used to form a top gate of the second transistor, the orthographic projection of the redundant first gate line on the base substrate extends along the first direction and covers the orthographic projection of the redundant second active portion on the base substrate, and a partial structure of the redundant first gate line is used to form a top gate of the redundant second transistor.

22. The display panel according to claim 21, wherein: In the same pixel driving circuit: The orthographic projection of the first gate line on the substrate is located between the orthographic projection of the second gate line on the substrate and the orthographic projection of the first conductive portion on the substrate, and the orthographic projection of the redundant first gate line on the substrate is located between the orthographic projection of the second gate line on the substrate and the orthographic projection of the first gate line on the substrate.

23. The display panel according to claim 21, wherein The pixel driving circuit further includes a first transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first driving transistor is connected to a second electrode of the first driving transistor, and a gate of the first transistor is connected to a first reset signal line; The orthographic projection of the first reset signal line on the base substrate extends along the first direction; In the same pixel driving circuit: the orthographic projection of the redundant first gate line on the substrate is located between the orthographic projection of the first reset signal line on the substrate and the orthographic projection of the first gate line on the substrate, and the orthographic projection of the second gate line on the substrate is located between the orthographic projection of the first gate line on the substrate and the orthographic projection of the redundant first gate line on the substrate.

24. The display panel according to claim 21, wherein The pixel driving circuit further includes a fifth transistor, a first electrode of the fifth transistor being connected to the first power line, and a second electrode of the fifth transistor being connected to the first electrode of the first driving transistor; The first active layer further includes a fifth active portion, the fifth active portion being used to form the first active layer. The channel region of the five transistors; In the first direction of the same pixel driving circuit, an orthographic projection of the redundant second active portion on the base substrate is located between an orthographic projection of the second active portion on the base substrate and an orthographic projection of the fifth active portion on the base substrate.

25. The display panel according to claim 21, wherein The display panel further includes a light emitting unit, and the pixel driving circuit further includes a first transistor and a sixth transistor; The first electrode of the first transistor is connected to the first initial signal line, the second electrode is connected to the second electrode of the first driving transistor, and the gate is connected to the first reset signal line; The first electrode of the sixth transistor is connected to the second electrode of the first driving transistor, and the second electrode is connected to the first electrode of the light emitting unit; The second active layer further comprises: a twentieth active portion connected to a side of the second active portion away from the redundant second active portion; a twenty-first active portion connected to a side of the redundant second active portion away from the second active portion; The first active layer further comprises: a first active portion, wherein the first active portion is used to form a channel region of the first transistor; a sixth active portion, the sixth active portion being configured to form a channel region of the sixth transistor; a seventeenth active portion connected to one side of the first active portion; a ninth active portion connected between the third active portion and the sixth active portion; The display panel further includes: The first source-drain layer is located on a side of the third gate layer away from the base substrate, and the first source-drain layer includes a first bridge portion, which is connected to the 20th active portion, the 21st active portion, the 17th active portion, and the 9th active portion through vias respectively.

26. The display panel according to claim 20, wherein: The second electrode of the redundant second transistor is connected to the first electrode of the first driving transistor, and the pixel driving circuit further includes: A redundant fourth transistor has a first electrode connected to the data line and a second electrode connected to the second electrode of the first driving transistor.

27. The display panel according to claim 26, wherein: The display panel further includes: substrate; a first active layer located on one side of the base substrate, the first active layer comprising a third active portion, a fourth active portion, and a redundant fourth active portion, the third active portion being used to form a channel region of the first driving transistor, the fourth active portion being used to form a channel region of the fourth transistor, and the redundant fourth active portion being used to form a channel region of the redundant fourth transistor; a first gate layer, located on a side of the first active layer facing away from the base substrate, the first gate layer comprising a first conductive portion, a second gate line, and a redundant second gate line segment, the orthographic projection of the first conductive portion on the base substrate overlapping the orthographic projection of the third active portion on the base substrate, the first conductive portion being used to form the gate of the first driving transistor, the orthographic projection of the second gate line on the base substrate extending along a first direction and covering the orthographic projection of the fourth active portion on the base substrate, a partial structure of the second gate line being used to form the gate of the fourth transistor, the orthographic projection of the redundant second gate line segment on the base substrate covering the orthographic projection of the redundant fourth active portion on the base substrate, and a partial structure of the redundant second gate line segment being used to form the gate of the redundant fourth transistor; a second active layer, located on a side of the first gate layer facing away from the base substrate, the second active layer comprising a second active portion and a redundant second active portion, the second active portion being used to form a channel region of the second transistor, and the redundant second active portion being used to form a channel region of the redundant second transistor; A third gate layer is located on a side of the second active layer facing away from the base substrate, the third gate layer includes a first gate line and a redundant first gate line, the orthographic projection of the first gate line on the base substrate extends along the first direction and covers the orthographic projection of the second active portion on the base substrate, a partial structure of the first gate line is used to form a top gate of the second transistor, the orthographic projection of the redundant first gate line on the base substrate extends along the first direction and covers the orthographic projection of the redundant second active portion on the base substrate, and a partial structure of the redundant first gate line is used to form a top gate of the redundant second transistor.

28. The display panel according to claim 27, wherein: In the same pixel driving circuit: The orthographic projection of the first gate line on the substrate is located between the orthographic projection of the second gate line on the substrate and the orthographic projection of the first conductive portion on the substrate, and the orthographic projection of the redundant first gate line on the substrate is located between the orthographic projection of the second gate line on the substrate. The orthographic projection of the redundant second gate line segment on the substrate is between the orthographic projection on the substrate and the orthographic projection of the first gate line on the substrate, and the orthographic projection of the redundant second gate line segment on the substrate is located on a side of the orthographic projection of the second gate line on the substrate away from the orthographic projection of the first gate line on the substrate.

29. The display panel according to claim 27, wherein: The display panel further includes a light-emitting unit, and the pixel driving circuit further includes a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second electrode of the first driving transistor, and a second electrode is connected to the first electrode of the light-emitting unit; The first active layer further comprises: a sixth active portion, the sixth active portion being configured to form a channel region of the sixth transistor; In the first direction of the same pixel driving circuit: The orthographic projection of the redundant second active portion on the substrate is located between the orthographic projection of the second active portion on the substrate and the orthographic projection of the fourth active portion on the substrate, and the orthographic projection of the redundant fourth active portion on the substrate is located between the orthographic projection of the fourth active portion on the substrate and the orthographic projection of the sixth active portion on the substrate.

30. The display panel according to claim 27, wherein The pixel driving circuit further includes a first transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first driving transistor is connected to a second electrode of the first driving transistor, and a gate of the first transistor is connected to a first reset signal line; The first active layer further includes a first active portion, and the first active portion is used to form a channel region of the first transistor; The redundant fourth active portion is connected to the fourth active portion, the third active portion, and the first active portion in the same layer.

31. The display panel according to claim 27, wherein: A length direction of the channel region of the redundant fourth transistor is a first direction.

32. The display panel according to claim 27, wherein: An orthographic projection of the redundant fourth active portion on the base substrate extends along a second direction, and the second direction intersects the first direction; The display panel includes a plurality of the redundant fourth active portions, wherein orthographic projections of the plurality of the redundant fourth active portions on the base substrate are distributed along the first direction, and the display panel further includes: A redundant second gate connection line is provided, wherein the redundant second gate connection line is connected to a plurality of the redundant fourth active portions distributed in the first direction through via holes.

33. The display panel according to claim 21 or 27, wherein: The second active layer further comprises: a twenty-first active portion, connected to a side of the redundant second active portion away from the second active portion, wherein a size of an orthographic projection of the twenty-first active portion on the base substrate in the first direction is larger than a size of an orthographic projection of the redundant second active portion on the base substrate in the first direction; An orthographic projection of the twenty-first active portion on the base substrate overlaps with an orthographic projection of the second gate line on the base substrate.

34. A display device, wherein: The display device comprises the display panel according to any one of claims 18 to 33.

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