Shift register unit, circuit driving method, driving substrate, and display device

Abstract

A shift register unit, a circuit driving method, a driving substrate, and a display device. The shift register unit comprises: a first access circuit (101) and an output circuit (102), wherein the first access circuit (101) is connected to an input voltage and a first clock pulse, and is turned on when the first clock pulse is at a high potential, and by means of the input voltage, a voltage of a first connection point is kept at a high potential; and the output circuit (102) is connected to the first access circuit (101) at the first connection point, is connected to a connection voltage and a source voltage, is turned on when the first connection point is connected to a high-potential voltage, outputs the source voltage to an output end, and uses the connection voltage to keep the output voltage stably at a high potential.

Description

Shift register unit, circuit driving method, driving substrate and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on April 2, 2024, with application number 202410396988.1 and invention name “Shift register unit, circuit driving method, driving substrate and display device”, the content of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a shift register unit, a circuit driving method, a driving substrate, and a display device. Background Art

[0003] In some technologies' shift register units, the output voltage is often affected by other transistors and becomes unstable. Generally speaking, since other transistors connected to the output voltage may exist in the circuit, their threshold voltage may drift negatively, resulting in failure to completely shut down and leakage, which in turn causes the output voltage connected to them to be pulled down and unable to remain stable.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] Embodiments of the present disclosure provide a shift register unit, a circuit driving method, a driving substrate, and a display device.

[0007] In a first aspect, an embodiment of the present disclosure provides a shift register unit, comprising: a first access circuit and an output circuit;

[0008] The first access circuit is connected to the input voltage and the first clock pulse, and is configured to be turned on when the first clock pulse is at a high level, and the input voltage keeps the voltage of the first connection point at a high level;

[0009] The output circuit is connected to the first access circuit at the first connection point, connected to the connection voltage and the source voltage, and is configured to turn on when the first connection point is connected to a high potential voltage, output the source voltage to the output end, and use the connection voltage to keep the output voltage stable at a high potential.

[0010] In some exemplary embodiments, the shift register unit further includes: a charging circuit and a second access circuit;

[0011] The charging circuit is connected to the output circuit at a second connection point and is configured to charge from the second access circuit when the first clock pulse is at a low level, and to discharge to the second connection point when the first clock pulse is at a high level and the input voltage is at a low level, so as to maintain the voltage of the second connection point at a high level;

[0012] The second access circuit is connected to the charging circuit at a third connection point and is configured to connect an input voltage and a second clock pulse. When the first clock pulse is at a low potential, the second clock pulse is used to maintain the voltage at the third connection point at a high potential to discharge the charging circuit. The first clock pulse and the second clock pulse have opposite high and low potentials.

[0013] The output circuit is further configured to connect a low potential voltage from the first connection point to make the output voltage low potential, and when connecting a high potential voltage from the second connection point, use the connection voltage to keep the output voltage stable at a low potential.

[0014] In some exemplary embodiments, the first access circuit includes: a first transistor and a second transistor;

[0015] The source of the first transistor is connected to the input voltage, the gate of the first transistor is connected to the first clock pulse, and the drain of the first transistor is connected to the fourth connection point; the first transistor is configured to be turned on when the first clock pulse is at a high potential, and apply the input voltage at a high potential to the fourth connection point;

[0016] The source of the second transistor is connected to the fourth connection point, the gate of the second transistor is connected to the first clock pulse, and the drain of the second transistor is connected to the first connection point; the second transistor is configured to be turned on when the first clock pulse is a high potential, to connect the input voltage from the fourth connection point, and to apply the input voltage to the first connection point to pull the voltage of the first connection point to a high potential.

[0017] In some exemplary embodiments, the connection voltage includes a first connection voltage and a second connection voltage, the second connection voltage being less than the first connection voltage;

[0018] The output circuit includes: a third transistor, a fourth transistor and a fifth transistor;

[0019] The source of the third transistor is connected to the source voltage, and the gate of the third transistor is connected to the first connection point; the third transistor is configured to be turned on when the first connection point is at a high potential, and output the source voltage as a high-potential output voltage through the drain;

[0020] The source of the fourth transistor is connected to the drain of the third transistor, the gate of the fourth transistor is connected to the second connection point and the first connection voltage, and the drain of the fourth transistor is connected to the first connection voltage; the fourth transistor is configured to be turned off when the voltage of the second connection point is at a low potential, so as to maintain the output voltage output by the drain of the third transistor at a high potential;

[0021] The source of the fifth transistor is connected to the second connection point, the gate of the fifth transistor is connected to the first connection point, and the drain of the fifth transistor is connected to the second connection voltage; the fifth transistor is configured to be turned on when the voltage of the first connection point is a high potential, and to use the second connection voltage of the drain to pull down the voltage of the second connection point to a low potential.

[0022] In some exemplary embodiments, the charging circuit includes: a storage capacitor, a sixth transistor, and a seventh transistor;

[0023] One end of the storage capacitor is connected to the third connection point; the storage capacitor is configured to be charged when the voltage of the third connection point is at a high potential, and to be discharged when the voltage of the third connection point is at a low potential;

[0024] The source of the sixth transistor is connected to the first clock pulse, the gate of the sixth transistor is connected to the third connection point, and the drain of the sixth transistor is connected to the other end of the storage capacitor; the sixth transistor is configured to be turned on when the third connection point is at a high potential;

[0025] The source of the seventh transistor is connected to the other end of the storage capacitor and the drain of the sixth transistor, the gate of the seventh transistor is connected to the first clock pulse, and the drain of the seventh transistor is connected to the second connection point; the seventh transistor is configured to turn on when the first clock pulse is a high potential so that the storage capacitor discharges to the second connection point, and to turn off when the first clock pulse is a low potential.

[0026] In some exemplary embodiments, the first access circuit further includes: an eighth transistor;

[0027] The gate of the eighth transistor is connected to the first connection point, the source of the eighth transistor is connected to the source voltage, and the drain of the eighth transistor is connected to the fourth connection point;

[0028] The eighth transistor is configured to be turned on when the voltage of the first connection point has not completely dropped to a low potential, apply the source voltage to the fourth connection point, and keep the voltage of the fourth connection point higher than the voltage of the first connection point so that the second transistor does not leak when it is not completely turned off.

[0029] In some exemplary embodiments, the second access circuit includes: a first sub-circuit and a second sub-circuit;

[0030] The first sub-circuit is connected to the second clock pulse and the third connection point, and is configured to be turned on when the second clock pulse is at a high voltage, and to pull up the voltage of the third connection point to a high voltage;

[0031] The second sub-circuit is connected to the input voltage and the low voltage, and is connected to the first sub-circuit at the third connection point, and is configured to turn on when the input voltage and the first clock pulse are both at a high potential, and pull down the third connection point to a low potential;

[0032] The low voltage includes the second clock pulse or the second connection voltage at a low potential.

[0033] In some exemplary embodiments, the first sub-circuit includes a ninth transistor;

[0034] The source of the ninth transistor and the gate of the ninth transistor are connected to the second clock pulse, and the drain of the ninth transistor is connected to the third connection point;

[0035] The ninth transistor is configured to be turned on when the second clock pulse is at a high potential, and to apply the high potential second clock pulse to the third connection point to keep the third connection point at a high potential.

[0036] In some exemplary embodiments, the second sub-circuit includes: a tenth transistor and an eleventh transistor;

[0037] The gate of the tenth transistor is connected to the first clock pulse, and the source of the tenth transistor is connected to the third connection point; the tenth transistor is configured to be turned on when the first clock pulse is at a high voltage;

[0038] The source of the eleventh transistor is connected to the drain of the tenth transistor, the gate of the eleventh transistor is connected to the input voltage, and the drain of the eleventh transistor is connected to the low voltage; the eleventh transistor is configured to turn on when the input voltage is connected; and the eleventh transistor is configured to connect the low voltage and the third connection point when it is turned on at the same time as the tenth transistor, and use the low voltage to pull down the voltage of the third connection point to a low potential.

[0039] In some exemplary embodiments, the first sub-circuit includes a twelfth transistor;

[0040] The source of the twelfth transistor is connected to the source voltage, the gate of the twelfth transistor is connected to the second clock pulse, and the drain of the twelfth transistor is connected to the third connection point;

[0041] The twelfth transistor is configured to be turned on when the second clock pulse is at a high potential, and to apply the high potential source voltage to the third connection point to keep the third connection point at a high potential.

[0042] In some exemplary embodiments, the second sub-circuit includes a thirteenth transistor;

[0043] The thirteenth transistor is a dual-gate transistor, a source of the thirteenth transistor is connected to the third connection point, a first gate of the thirteenth transistor is connected to the input voltage, and a drain of the thirteenth transistor is connected to the low voltage;

[0044] The thirteenth transistor is configured to be turned on when the input voltage is connected, connect the low voltage and the third connection point, and use the low voltage to pull down the voltage of the third connection point to a low potential.

[0045] In some exemplary embodiments, the second sub-circuit includes: a tenth transistor and a fourteenth transistor;

[0046] The gate of the tenth transistor is connected to the first clock pulse, and the source of the tenth transistor is connected to the third connection point; the tenth transistor is configured to be turned on when the first clock pulse is at a high voltage;

[0047] The source of the fourteenth transistor is connected to the drain of the tenth transistor, the gate of the fourteenth transistor is connected to the fourth connection point, and the drain of the fourteenth transistor is connected to the low voltage; the fourteenth transistor is configured to be turned on when the input voltage is connected from the fourth connection point; and the fourteenth transistor is configured to be turned on at the same time as the tenth transistor, to connect the low voltage and the third connection point, and to use the low voltage to pull down the voltage of the third connection point to a low potential.

[0048] In some exemplary embodiments, the second sub-circuit includes a fifteenth transistor;

[0049] The fifteenth transistor is a dual-gate transistor, a source of the fifteenth transistor is connected to the third connection point, a first gate of the fifteenth transistor is connected to the fourth connection point, and a drain of the fifteenth transistor is connected to the low voltage;

[0050] The fifteenth transistor is configured to be turned on when the input voltage is connected, connect the low voltage and the third connection point, and use the low voltage to pull down the voltage of the third connection point to a low potential.

[0051] In a second aspect, an embodiment of the present disclosure further provides a circuit driving method, applicable to the shift register unit described in any one of the above exemplary embodiments, the circuit driving method comprising:

[0052] Connecting the first access circuit to an input voltage and a first clock pulse, and turning on the first access circuit when the first clock pulse is at a high level, wherein the input voltage maintains a voltage at the first connection point at a high level;

[0053] The output circuit is connected to the connection voltage and the source voltage, and is turned on when the first connection point is connected to a high potential voltage, and the source voltage is output to the output end. The connection voltage is used to keep the output voltage stable at a high potential, and the output circuit and the first connection circuit are connected to the first connection point.

[0054] In a third aspect, an embodiment of the present disclosure further provides a driving substrate, comprising the shift register unit described in any one of the above exemplary embodiments.

[0055] In a fourth aspect, an embodiment of the present disclosure further provides a display device, comprising the driving substrate described in the above exemplary embodiment.

[0056] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. Other advantages of the present disclosure can be realized and obtained through the solutions described in the description and the drawings.

[0057] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0058] Summary of the Figures

[0059] The following is a brief introduction to the drawings used in the embodiments of the present disclosure or some technical descriptions. The drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0060] FIG1 is a schematic diagram of a cascade circuit of multiple shift register units according to an embodiment of the present disclosure;

[0061] FIG2 is a first circuit diagram of a shift register unit according to an embodiment of the present disclosure;

[0062] FIG3 is a timing diagram of a shift register unit according to an embodiment of the present disclosure;

[0063] FIG4 is a second circuit diagram of the shift register unit according to an embodiment of the present disclosure;

[0064] FIG5 is a third circuit diagram of the shift register unit according to an embodiment of the present disclosure;

[0065] FIG6 is a fourth circuit diagram of the shift register unit according to an embodiment of the present disclosure;

[0066] FIG7 is a fifth circuit diagram of the shift register unit according to an embodiment of the present disclosure;

[0067] FIG8 is a sixth circuit diagram of the shift register unit according to an embodiment of the present disclosure;

[0068] FIG9 is a seventh circuit diagram of the shift register unit according to an embodiment of the present disclosure;

[0069] FIG10 is a first simulation diagram of a shift register unit according to an embodiment of the present disclosure;

[0070] FIG11 is a second simulation diagram of the shift register unit according to an embodiment of the present disclosure;

[0071] FIG12 is a flow chart of a circuit driving method according to an embodiment of the present disclosure.

[0072] Details

[0073] The embodiments of the present disclosure will be described below with reference to the accompanying drawings. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be arbitrarily combined with each other.

[0074] In the embodiments of the present disclosure, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0075] As described in the background technology section, the shift register units in some technologies still struggle to meet actual needs. A problem with the shift register units in some technologies is that the output voltage in these shift register units is often affected by other transistors and becomes unstable. Generally speaking, because other transistors connected to the output voltage may exist in the circuit, when the threshold voltage of the other transistors connected to the output voltage drifts negatively, the other transistors connected to the output voltage cannot be completely turned off and leak current, thereby causing the output voltage connected to the other transistors to be pulled down and unable to remain stable.

[0076] One or more exemplary embodiments of the present disclosure provide a shift register unit. Based on a first access circuit and an output circuit connected to a first connection point, the first access circuit is turned on when a first clock pulse with a high potential is connected, thereby conducting the input voltage connected to the first connection point, thereby raising the voltage of the first connection point and turning on the output circuit. The input voltage is then applied to the outside of the shift register unit of this stage as the output voltage. At the same time, the output circuit turns off other transistors that can lower the output voltage through the low potential connection voltage connected to it, thereby ensuring that the output voltage at this time can be maintained at a stable high potential.

[0077] FIG1 is a cascade circuit diagram of multiple shift register units according to an embodiment of the present disclosure, and FIG1 illustrates a gate drive circuit. In an exemplary embodiment of the present disclosure, as shown in FIG1 , the gate drive circuit may include multiple cascaded shift register units, wherein, among the multiple cascaded shift register units, the first shift register unit receives an input voltage from outside the gate drive circuit, and the input voltage of each non-first shift register unit, except the first shift register unit, is the output voltage of the previous shift register unit.

[0078] For example, as shown in FIG1 , the input voltage IN of the shift register unit m is the output voltage Out of the shift register unit m-1 of the previous stage. <m-1>, the output voltage Out of the shift register unit m, that is, the output voltage Out in FIG1 <m>, can be used as the input voltage IN of the next stage shift register unit m+1, and the output voltage of the shift register unit m+1 is Out<m+1> It can be used as the input voltage of the next-stage shift register unit m+2.

[0079] In some exemplary embodiments, as shown in Figure 1, for any shift register unit, the first clock pulse CK, the second clock pulse CB, the first source voltage GVDD1, the second source voltage GVDD2, the first connection voltage GVSS1 and the second connection voltage GVSS2 can be connected from the circuit, wherein the second connection voltage GVSS2 is greater than the first connection voltage GVSS1, and the high and low potentials of the first clock pulse CK and the second clock pulse CB are opposite in part of the time period.

[0080] In some exemplary embodiments, the first source voltage GVDD1 and the second source voltage GVDD2 may be different source voltages. When the first source voltage GVDD1 and the second source voltage GVDD2 are different source voltages, the first source voltage GVDD1 may be greater than the second source voltage GVDD2, for example, the second source voltage GVDD2 is 10V and GVDD1 is 20V, or the second source voltage GVDD2 may be greater than the first source voltage GVDD1, for example, the second source voltage GVDD2 is 20V and the first source voltage GVDD1 is 10V.

[0081] In some other exemplary embodiments, the first source voltage GVDD1 and the second source voltage GVDD2 may be the same source voltage. For example, the first source voltage GVDD1 and the second source voltage GVDD2 may both be 20V.

[0082] An exemplary embodiment of the present disclosure provides a shift register unit, and Figure 2 is a first circuit diagram of the shift register unit of the embodiment of the present disclosure. As shown in Figure 2, the shift register unit may include: a first access circuit 101 and an output circuit 102;

[0083] The first access circuit 101 is connected to the input voltage IN and the first clock pulse CK, and is turned on when the first clock pulse CK is at a high level. The input voltage IN keeps the voltage at the first connection point Q at a high level.

[0084] The output circuit 102 is connected to the first access circuit 101 at the first connection point Q, and is connected to the connection voltage GVSS and the source voltage GVDD. It is turned on when the first connection point Q is connected to a high potential voltage, outputs the source voltage IN to the output end, and uses the connection voltage to keep the output voltage OUT stable at a high potential.

[0085] Here, FIG2 is an illustration of a shift register unit of any level in any driving substrate. As shown in FIG2 , the shift register unit may include: a first access circuit 101 and an output circuit 102 , wherein the first access circuit 101 and the output circuit 102 are connected to a first connection point Q.

[0086] In some exemplary embodiments, the first access circuit 101 accesses the input voltage IN and the first clock pulse CK from the outside of the shift register unit; the output circuit 102 connects the first source voltage GVDD1 and the connection voltage GVSS outside the shift register unit, and the output circuit 102 can output the output voltage OUT to the outside of the shift register unit.

[0087] In this way, in the shift register unit provided in the exemplary embodiment of the present disclosure, based on the first access circuit 101 and the output circuit 102 connected to the first connection point Q, the first access circuit 101 can be turned on when the first clock pulse CK with a high potential is accessed, thereby conducting the input voltage connected to the first connection point Q, thereby pulling up the voltage of the first connection point Q, and turning on the output circuit 102, and then applying the input voltage connected to the outside of the shift register unit of this level as the output voltage. At the same time, the output circuit 102 turns off other transistors that can pull down the output voltage through the low-potential connection voltage connected, thereby ensuring that the output voltage at this time can be maintained at a stable high potential.

[0088] Figure 3 is a timing diagram of the operation of a shift register unit. As shown in Figure 3, the operation process of the shift register unit may include: a P1 phase, a P2 phase, and a P3 phase.

[0089] The exemplary embodiment of the present disclosure is described below with reference to the working timing diagram shown in FIG3 through the working process of the shift register unit shown in FIG2 .

[0090] In some exemplary embodiments, as shown in FIG3 , in the P1 phase, the first access circuit 101 is connected to a high potential input voltage IN, which may be the output voltage OUT of the previous stage shift register unit in FIG3 . <m-1>, and the first access circuit 101 is connected to the high potential input voltage IN (ie the output voltage OUT of the previous stage shift register unit in FIG3 <m-1>) and wait for the first clock pulse CK to become a high level.

[0091] 3, the high potential of the input voltage IN can be the same as the first source voltage GVDD1, and the low potential of the input voltage IN can be the same as the first connection voltage GVSS1, that is, the output voltage OUT of the previous stage shift register unit in FIG3 <m-1>The high potential of can be the same as the first source voltage GVDD1, and the output voltage OUT of the previous stage shift register unit in FIG3 <m-1>The low potential of GVSS1 may be the same as the first connection voltage GVSS1.

[0092] In some exemplary embodiments, as shown in FIG2 , when the first clock pulse CK becomes a high voltage, the first access circuit 101 is turned on and discharges to the first connection point Q, that is, in the P1 phase, the first access circuit 101 applies the high voltage input voltage IN to the first connection point Q to keep the voltage of the first connection point Q at a high voltage.

[0093] In some exemplary embodiments, a high potential of the first clock pulse CK may be the same as the first source voltage GCDD1 , and a low potential of the first clock pulse CK may be the same as the second connection voltage GVSS2 .

[0094] In some exemplary embodiments, as shown in FIG2 , the output circuit 102 is connected to the first source voltage GVDD1 from the outside of the shift register unit of this stage. After the output circuit 102 is connected to the high potential output voltage IN from the first connection point Q, the connected first source voltage GVDD1 is output as the output voltage OUT to the outside of the shift register unit of this stage, that is, the output circuit 102 outputs the output voltage OUT in FIG3 <m>Output to the shift register unit m+1 of the next stage.

[0095] In some exemplary embodiments, as shown in FIG3 , the high potential of the output voltage OUT may be the same as the first source voltage GVDD1, and the low potential of the output voltage OUT may be the same as the first connection voltage GVSS1, that is, the output voltage OUT output to the next stage shift register unit in FIG3 <m>The high potential of can be the same as the first source voltage GVDD1, and the output voltage OUT output to the next stage shift register unit in FIG3 <m>The low potential of may be the same as the first connection voltage GVSS1.

[0096] In some exemplary embodiments, in phase P1, when the first clock pulse CK and the input voltage IN are both at high potentials, such that the first connection point Q is at a high potential, the output circuit 102 can maintain the output voltage OUT at a stable high potential using the connection voltage GVSS.

[0097] In some exemplary embodiments, the output circuit 102 is connected to a low-potential connection voltage GVSS, and uses the connection voltage GVSS to turn off transistors that can pull down the output voltage OUT, so that the output voltage OUT is not pulled down by other transistors, thereby maintaining a stable high potential in the P2 stage.

[0098] In some exemplary embodiments, in the P3 phase, the input voltage IN is at a low potential, and the voltage applied to the first connection point Q is also at a low potential. At this time, the output circuit 102 receives a low potential voltage from the first connection point Q and sets the output voltage OUT to a low potential.

[0099] In this way, in the shift register unit provided in the exemplary embodiment of the present disclosure, the first access circuit 101 is turned on by the first clock pulse CK, thereby pulling the first connection point Q between the first access circuit 101 and the output circuit 102 to a high potential, thereby turning on the output circuit 102, and after turning on, the output voltage OUT is applied to the outside of the shift register unit of this stage, and at the same time, by accessing a low-potential connection voltage, the output voltage OUT is maintained at a stable high potential.

[0100] An exemplary embodiment of the present disclosure provides a shift register unit. FIG4 is a second circuit diagram of the shift register unit according to an embodiment of the present disclosure. As shown in FIG4 , the shift register unit may further include a second access circuit 104 and a charging circuit 103. The charging circuit 103 and the output circuit 102 are connected at a second connection point QB, and the second access circuit 104 and the charging circuit 103 are connected at a third connection point PQB.

[0101] In some exemplary embodiments, as shown in FIG. 4 , the charging circuit 103 receives a first clock pulse CK from outside the shift register unit; the second access circuit 104 receives an input voltage IN and receives a second clock pulse CB from outside the shift register unit.

[0102] In some exemplary embodiments, a high potential of the second clock pulse CB may be the same as the first source voltage GCDD1 , and a low potential of the second clock pulse CB may be the same as the second connection voltage GVSS2 .

[0103] The exemplary embodiment of the present disclosure is described below with reference to the working timing diagram shown in FIG3 and through the working process of the shift register unit shown in FIG4 .

[0104] In some exemplary embodiments, as shown in FIG3 , in phase P1 , when the first clock pulse CK connected to the charging circuit 103 is at a low potential, the charging circuit 103 is not connected to the output circuit 102 , and the second connection circuit 104 charges the charging circuit 103 through the third connection point PQB.

[0105] In some exemplary embodiments, when the first clock pulse CK is at a high potential, when in the P1 stage, the input voltage IN is at a high potential, and no charging is performed from the second connection circuit 104. When the third connection point PQB is at a low potential, the potential of the second connection point QB is pulled down to turn off the transistor in the output circuit 102 that can pull down the output voltage OUT, thereby cooperating with the aforementioned embodiment. In the P1 stage, the first clock pulse CK and the input voltage IN are at a high potential at the same time, and the transistor that can pull down the output voltage OUT is turned off, so that the output voltage OUT maintains a stable high potential in the P2 stage.

[0106] In some exemplary embodiments, when the first clock pulse CK is at a high potential, when in the P3 stage, the input voltage IN is at a low potential, and discharge is directed to the second connection point to turn on the transistor in the output circuit 102 that can pull down the output voltage OUT in the P3 stage, thereby causing the output voltage OUT to be further pulled down in the P3 stage and maintain a stable low potential.

[0107] In some exemplary embodiments, in the P1 phase, when the input voltage IN and the first clock pulse CK are both high, the second clock pulse CB is low, and the voltage of the third connection point PQB is pulled down to a low level using the low-level second clock pulse CB.

[0108] In some exemplary embodiments, in phase P3, when the first clock pulse CK is at a low potential, the second clock pulse CB is at a high potential, and the voltage of the third connection point PQB is pulled up to a high potential by the connected high potential second clock pulse CB.

[0109] In this way, in the shift register unit provided in the exemplary embodiment of the present disclosure, the second access circuit 104, according to the potential of the input voltage IN and the first clock pulse CK, when both are high potentials, uses the accessed low voltage to pull down the voltage of the third connection point PQB, and when the first clock pulse is low potential, uses the high potential second clock pulse CB to pull up the voltage of PQB, thereby realizing the discharge and charging of the charging circuit 103; and then the charging circuit 103 is charged when the potential is high and discharged when the potential is low according to the different voltages of the third connection point PQB, thereby controlling the voltage of the second connection point QB, so that the output circuit 102 can use the high potential of the second connection point to maintain the output voltage OUT at a stable low voltage in the P3 stage when the output voltage IN is low potential.

[0110] In some exemplary embodiments, as shown in FIG. 4 , the first access circuit 101 may include a first transistor T1 and a second transistor T2 .

[0111] Among them, the gate of the first transistor T1 is connected to the first clock pulse CK from outside the shift register unit of this stage, the source of the first transistor T1 is connected to the input voltage IN from outside the shift register unit of this stage, the drain of the first transistor T1 and the source of the second transistor T2 are connected to the fourth connection point PQ; the gate of the second transistor T2 is connected to the first clock pulse CK from outside the shift register unit of this stage, and the drain of the second transistor T2 and the output circuit 102 are connected to the first connection point Q.

[0112] In some exemplary embodiments, as shown in FIG3 , in the P1 phase, when the first clock pulse CK connected to the first transistor T1 is at a high potential, the first transistor T1 is turned on, and after being turned on, the input voltage IN at a high potential is applied to the fourth connection point PQ.

[0113] In some exemplary embodiments, in the P1 phase, when the first clock pulse CK is at a high potential, the second transistor T2 is also turned on. After being turned on, the high potential voltage connected from the fourth connection point PQ is applied to the first connection point Q to pull the voltage of the first connection point Q to a high potential.

[0114] In some exemplary embodiments, in the P2 phase, the input voltage IN maintains a high potential. When the first clock pulse CK is high, the first transistor T1 and the second transistor T2 continue to discharge toward the first connection point Q as in the P1 phase to maintain the first connection point Q in a high potential state.

[0115] In some exemplary embodiments, in the P3 phase, the input voltage In is at a low potential, and when the first clock pulse CK is at a high potential, the first transistor T1 and the second transistor T2 are turned on. When the first transistor T1 is turned on, the voltage of the fourth connection point PQ is pulled down to a low potential by the low potential input voltage IN. When the second transistor T2 is turned on, the voltage of the first connection point Q is pulled down to a low potential by the low potential voltage of the fourth connection point PQ.

[0116] Thus, in the shift register unit provided in the exemplary embodiment of the present disclosure, the first access circuit 101 is turned on and off by the first clock pulse CK connected to the first transistor T1 and the second transistor T2, thereby adjusting the voltage of the first connection point Q using the first clock pulse.

[0117] In some embodiments of the present disclosure, as shown in FIG4 , the connection voltage GVSS connected to the output circuit 102 in the aforementioned embodiment may include a first connection voltage GVSS1 and a second connection voltage GVSS2 ; the output circuit 102 may include a third transistor T3 , a fourth transistor T4 and a fifth transistor T5 .

[0118] The gate of the third transistor T3 is connected to the first connection point Q, the source of the third transistor T3 is connected to the first source voltage GVDD1, the drain of the third transistor T3 is connected to the source of the fourth transistor T4, and the output voltage OUT is output to the outside of the shift register unit of this stage.

[0119] In some exemplary embodiments, the gate of the fourth transistor T4 is connected to the second connection point QB, the drain of the fourth transistor T4 is connected to the first connection voltage GVSS1 , and the source of the fourth transistor T4 is connected to the drain of the third transistor T3 outputting the voltage OUT.

[0120] In some exemplary embodiments, a gate of the fifth transistor T5 is connected to the first connection point Q, a source of the fifth transistor T5 is connected to the second connection point QB, and a drain of the fifth transistor T5 is connected to the second connection voltage GVSS2.

[0121] In some exemplary embodiments, during phases P1 and P2, the first connection point Q is maintained at a high potential, the third transistor T3 is turned on, and the first source voltage GVDD1 connected to the third transistor T3 is output as the output voltage OUT to the outside of the shift register unit of this stage.

[0122] In some exemplary embodiments, the high potential first connection point Q turns on the fifth transistor T5, so that the low potential second connection voltage GVSS2 connected to the fifth transistor T5 is connected to the second connection point QB, so that the voltage of the second connection point QB is pulled down to a low potential.

[0123] In some exemplary embodiments, the voltage of the second connection point QB with a low potential turns off the fourth transistor T4, so that when the output voltage OUT is at a high potential, the fourth transistor T4 in the turned-off state does not pull down the output voltage OUT, so that the output voltage OUT is maintained at a stable high potential.

[0124] In some exemplary embodiments, during the P3 phase, the first connection point Q is maintained at a low potential, and the third transistor T3 is turned off, so that the output voltage OUT output by the third transistor T3 is a low potential.

[0125] In some exemplary embodiments, the low potential first connection point Q turns off the fifth transistor T5 , so that the second connection point QB is disconnected from the low potential second connection voltage GVSS2 and is pulled up to a high potential by the charging circuit 103 .

[0126] In some exemplary embodiments, the high-potential second connection point QB turns on the fourth transistor T4, so that the drain of T3 is connected to the low-potential first connection voltage GVSS1, so that the output voltage OUT at the low potential output by the drain of T3 is continuously pulled down to a low potential by the first connection voltage GVSS1.

[0127] In some exemplary embodiments, as shown in FIG. 4 , the output circuit 102 may further include: a first storage capacitor C1 and a second storage capacitor C2 .

[0128] Among them, one end of the first storage capacitor C1 is connected to the gate of the third transistor T3, and the other end of the first storage capacitor C1 is connected to the drain of the third transistor T3; one end of the second storage capacitor C2 is connected to the gate of the fourth transistor T4, and the other end of the second storage capacitor C2 is connected to the first connection voltage GVSS1.

[0129] In this way, in the shift register unit provided in the exemplary embodiment of the present disclosure, the third transistor T3 in the output circuit 102 is controlled to be turned on and off based on the voltage of the first connection point Q, so that when it is turned on, the connected first source voltage GVDD1 is output as the output voltage OUT. At the same time, in the P1 and P2 stages, by turning on the fifth transistor T5, the second connection voltage GVSS2 less than the first connection voltage GVSS1 is utilized, that is, the source-gate voltage Vgs of the fourth transistor T4 is utilized to keep the fourth transistor T4 in the off state, so that the output voltage OUT will not be pulled down by the fourth transistor T4 in the P1 and P2 stages and can be maintained at a stable high potential. In the P3 stage, the fourth transistor T4 is turned on by connecting the voltage of the second connection point QB at a high potential, so that the output voltage OUT is continuously pulled down by the fourth transistor T4 in the P3 stage and maintained at a stable low potential.

[0130] In some exemplary embodiments, as shown in FIG. 4 , the charging circuit 103 may include: a third storage capacitor C3 , a sixth transistor T6 , and a seventh transistor T7 .

[0131] One end of the third storage capacitor C3 is connected to the third connection point PQB and the gate of the sixth transistor T6 , and the other end of the third storage capacitor C3 is connected to the drain of the sixth transistor T6 and the source of the seventh transistor T7 .

[0132] In some exemplary embodiments, the gate of the sixth transistor T6 is connected to the third connection point PQB, the source of the sixth transistor T6 is connected to the first clock pulse CK, and the drain of the sixth transistor T6 is connected to the third storage capacitor C3 and the source of the seventh transistor T7.

[0133] In some exemplary embodiments, a gate of the seventh transistor T7 is connected to the first clock pulse CK, a source of the seventh transistor T7 is connected to C3 and the drain of the sixth transistor T6 , and a drain of the seventh transistor T7 is connected to the second connection point QB.

[0134] In some exemplary embodiments, during the P1 and P2 phases, the input voltage IN is maintained at a high potential, and when the first clock pulse CK is at a low potential, the seventh transistor T7 is turned off. At this time, the second clock pulse CB is at a high potential, the third connection point PQB is at a high potential, and the sixth transistor T6 is turned on, outputting the connected first clock pulse CK to the third storage capacitor C3, so that the third storage capacitor C3 is charged from the high potential third connection point PQB and the high potential first clock pulse CK output by the sixth transistor T6.

[0135] In some exemplary embodiments, during the P3 phase, the input voltage IN is maintained at a low potential. When the first clock pulse CK is at a high potential, the seventh transistor T7 is turned on, so that the third connection point is connected to the second connection point QB through T7 in some exemplary embodiments. At this time, the third storage capacitor C3 discharges to the second connection point QB, so that the voltage of the second connection point QB is pulled down to a low potential.

[0136] In this way, in the shift register unit provided in the exemplary embodiment of the present disclosure, the third storage capacitor C3 in the charging circuit 103 is charged and discharged according to the voltage of the third connection point PQB, and is combined with the difference in the high and low potentials of the first clock pulse CK to realize discharge to the second connection point QB in the P3 stage.

[0137] In some exemplary embodiments, as shown in FIG. 4 , the first access circuit 101 may further include an eighth transistor T8 .

[0138] The gate of the eighth transistor T8 is connected to the first connection point Q, the source of the eighth transistor T8 is connected to the second source voltage GVDD2, and the drain of the eighth transistor T8 is connected to the fourth connection point PQ.

[0139] In some exemplary embodiments, during the P3 phase, the input voltage IN enters a low potential. When the first clock pulse CK is at a low potential, the second transistor T2 is turned off, and the voltage at the first connection point Q drops to a low potential. However, in some cases, the second transistor T2 may not be completely turned off, but may be partially turned off. Furthermore, upon entering the P3 phase, the first connection point Q may not be completely directly lowered to a low potential. In this case, leakage may occur in the second transistor T2 due to the voltage at the first connection point Q. After being turned on by the voltage at the first connection point Q, the eighth transistor T8 can apply the second source voltage GVDD2 to the fourth connection point PQ. The source of the second transistor T2 is connected to the fourth connection point PQ, and the drain of the second transistor T2 is connected to the first connection point Q. Therefore, the source voltage of the second transistor T2 is higher than the drain voltage, thereby preventing leakage of the second transistor T2 at this time.

[0140] In this way, in the shift register unit provided in the exemplary embodiment of the present disclosure, after the eighth transistor T8 in the first access circuit 101 is turned on in the P3 stage, the second source voltage GVDD2 is applied to the fourth connection point PQ, thereby achieving discharge of the fourth connection point PQ at a low potential in the P3 stage, so that the voltage of the fourth connection point PQ is higher than the voltage of the first connection point Q, thereby avoiding the leakage problem of the second transistor T2.

[0141] The exemplary embodiments of the present disclosure provide a shift register unit. FIG5 is a third circuit diagram of the shift register unit according to the exemplary embodiments of the present disclosure. As shown in FIG5 , the shift register unit may further include a second access circuit 104 and a charging circuit 103. The second access circuit 104 may include a first sub-circuit 1041 and a second sub-circuit 1042.

[0142] Among them, the first sub-circuit 1041 is connected to the second clock pulse CB and is connected to the third connection point PQB; the second sub-circuit 1042 is connected to a low voltage from the outside of the shift register unit of this level and is connected to the input voltage, wherein the low voltage connected to the second sub-circuit 1042 can be the second clock pulse CB at a low potential, or can be the second connection voltage GVSS2 maintained at a low potential.

[0143] In this way, when the second clock pulse CB is at a high potential, the first clock pulse CK is at a low potential, so that the second sub-circuit 1041 is closed and the first sub-circuit 1041 is turned on. The first sub-circuit 1041 in the turned-on state uses the second clock pulse CB and pulls the voltage of the third connection point PQB to a high potential, thereby discharging to the charging circuit 103, so that the charging circuit 103 can be charged from the third connection point PQB at a high potential at this time; when the second clock pulse CB is at a low potential, the first sub-circuit 1041 is closed.

[0144] In some exemplary embodiments, during the P1 phase and the P2 phase, the input voltage IN is maintained at a high potential. When the first clock pulse is at a high potential, the second sub-circuit 1042 is turned on, thereby connecting the input low voltage to the third connection point PQB, so that the voltage of the third connection point PQB is pulled down to a low potential.

[0145] In this way, in the shift register unit provided in the exemplary embodiment of the present disclosure, the first sub-circuit 1041 in the second access circuit 104 is turned on when the second clock pulse CB is at a high potential by accessing the second clock pulse CB, and the fourth connection point is pulled up to a high potential, and the second clock pulse CB accessed by the second sub-circuit 1042 is used to realize that when the first clock pulse CK is at a high potential, the second clock pulse CB at a low potential is used to pull down the voltage of the third connection point PQB.

[0146] In some exemplary embodiments, as shown in FIG. 5 , the first sub-circuit 1041 may include a ninth transistor T9 .

[0147] The gate of the ninth transistor T9 is connected to the second clock pulse CB, the source of the ninth transistor T9 is connected to the second clock pulse CB, and the drain of the ninth transistor T9 is connected to the third connection point PQB.

[0148] In some exemplary embodiments, when the second clock pulse CB is at a high potential, T9 is turned on to apply the high potential of the second clock pulse CB of the source to the third connection point PQB, so that the third connection point PQB at a high potential charges the charging circuit 103 .

[0149] In this way, in the shift register unit provided in the exemplary embodiment of the present disclosure, the ninth transistor T9 in the first sub-circuit 1041 is turned on when the second clock pulse CB is at a high potential, so that the third connection point PQB is pulled to a high potential by the high potential second clock pulse CB connected to the ninth transistor T9.

[0150] In some exemplary embodiments, as shown in FIG. 5 , the second sub-circuit 1042 may include a tenth transistor T10 and an eleventh transistor T11 .

[0151] The gate of the tenth transistor T10 is connected to the first clock pulse CK, the source of the tenth transistor T10 is connected to the third connection point PQB, and the drain of the tenth transistor T10 is connected to the source of the eleventh transistor T11.

[0152] In some exemplary embodiments, a gate of the eleventh transistor T11 is connected to the input voltage IN, and a drain of the eleventh transistor T11 is connected to the second clock pulse CB.

[0153] In some exemplary embodiments, during the P1 and P2 phases, the input voltage IN is maintained at a high potential, so that the eleventh transistor T11 remains turned on. When the first clock pulse CK is at a high potential, the tenth transistor T10 is turned on. At this time, the second clock pulse CB is at a low potential, so that the low-potential second clock pulse CB connected to the eleventh transistor T11 is turned on and the third connection point PQB, thereby pulling the voltage of PQB down to a low potential.

[0154] In some exemplary embodiments, during the P1 and P2 phases, when the first clock pulse CK is at a low level, the tenth transistor T10 is turned off and cannot conduct the low voltage to the third connection point PQB, thereby not affecting the ninth transistor T9 from charging the third connection point PQB.

[0155] In some exemplary embodiments, during the P3 phase, the input voltage IN is maintained at a low potential, and the eleventh transistor T11 is turned off, so that the second clock pulse CB or other low voltage is not conducted to the third connection point PQB.

[0156] In this way, in the shift register unit provided in the exemplary embodiment of the present disclosure, the first clock pulse CK connected to the gate of the tenth transistor T10 and the input voltage IN connected to the gate of the eleventh transistor T11 can realize that when the first clock pulse CK and the input voltage CK are both high voltages, the entire circuit of the tenth transistor T10 and the eleventh transistor T11 is turned on, thereby realizing the use of the second clock pulse CB at a low potential at this time to pull down the voltage of the third connection point PQB.

[0157] An exemplary embodiment of the present disclosure provides a shift register unit. FIG6 is a fourth circuit diagram of the shift register unit according to an embodiment of the present disclosure. As shown in FIG6 , the shift register unit may further include a second access circuit 104 and a charging circuit 103. The second access circuit 104 may include a first sub-circuit 1041 and a second sub-circuit 1042. The first sub-circuit 1041 may include a twelfth transistor T12.

[0158] The gate of the twelfth transistor T12 is connected to the second clock pulse CB, the source of the twelfth transistor T12 is connected to the second source voltage GVDD2 , and the drain of the twelfth transistor T12 is connected to the third connection point PQB.

[0159] In some exemplary embodiments, when the second clock pulse CB is high, the twelfth transistor T12 is turned on and applies the high potential of the second source voltage GVDD2 to the third connection point PQB, so that the third connection point PQB at a high potential charges the charging circuit 103 .

[0160] In this way, in the shift register unit provided in the exemplary embodiment of the present disclosure, the second source voltage GVDD2 is connected to the source of the twelfth transistor T12 in the first sub-circuit 1041, and the second source voltage GVDD2 can be used to pull up the potential of the third connection point PQB when the second clock pulse CB is at a high potential. This can avoid the situation where the voltage required to be applied is too high in the process of pulling up the voltage of the third connection point PQB when both the source of the ninth transistor T9 and the gate of the ninth transistor T9 are connected to the second clock pulse CB, thereby causing the high potential second clock pulse CB to be insufficient to pull up the voltage of the third connection point PQB to a high potential.

[0161] An exemplary embodiment of the present disclosure provides a shift register unit. FIG7 is a fifth circuit diagram of the shift register unit according to an embodiment of the present disclosure. As shown in FIG7 , the shift register unit may further include a second access circuit 104 and a charging circuit 103. The second access circuit 104 may include a first sub-circuit 1041 and a second sub-circuit 1042. The second sub-circuit 1042 includes a thirteenth transistor T13.

[0162] The thirteenth transistor T13 may have a dual-gate structure, a gate of the thirteenth transistor T13 is connected to the input voltage IN, a source of the thirteenth transistor T13 is connected to the third connection point PQB, and a drain of the thirteenth transistor T13 is connected to the second clock pulse CB.

[0163] In some exemplary embodiments, during the P1 and P2 phases, the input voltage IN is maintained at a high voltage, so that T13 remains turned on, thereby allowing the second clock pulse CB connected to T13 to be conductive with the third connection point PQB when it is at a low voltage, thereby pulling the voltage of PQB down to a low voltage.

[0164] In some exemplary embodiments, during the P3 phase, the input voltage IN is maintained at a low potential, and the thirteenth transistor T13 is turned off, so that the second clock pulse CB or other low voltage is not conducted to the third connection point PQB.

[0165] In this way, in the shift register unit provided in the exemplary embodiment of the present disclosure, in the second sub-circuit 1042, by utilizing a single transistor (i.e., the thirteenth transistor T13) to replace the tenth transistor T10 and the eleventh transistor T11, and by designing the thirteenth transistor T13 as a dual-gate structure, the conduction capability between the second clock pulse CB and the third connection point PQB is enhanced, thereby achieving an effect similar to that of using two transistors, the tenth transistor T10 and the eleventh transistor T11, in the aforementioned embodiment.

[0166] An exemplary embodiment of the present disclosure provides a shift register unit. FIG7 is a sixth circuit diagram of the shift register unit according to an embodiment of the present disclosure. As shown in FIG8 , the shift register unit may further include a second access circuit 104 and a charging circuit 103. The second access circuit 104 may include a first sub-circuit 1041 and a second sub-circuit 1042. The second sub-circuit 1042 may include a tenth transistor T10 and a fourteenth transistor T14.

[0167] In some exemplary embodiments, a gate of the tenth transistor T10 is connected to the first clock pulse CK, a source of the tenth transistor T10 is connected to the third connection point PQB, and a drain of the tenth transistor T10 is connected to the source of the fourteenth transistor T14.

[0168] In some exemplary embodiments, a gate of the fourteenth transistor T14 is connected to the fourth connection point PQ, and a drain of the fourteenth transistor T14 is connected to the second clock pulse CB.

[0169] In some exemplary embodiments, during the P1 and P2 phases, the input voltage IN is maintained at a high potential. When the first clock pulse CK is at a high potential, the first transistor T1 and the tenth transistor T10 are turned on, so that the potential of the fourth connection point PQ is at a high potential, thereby turning on the fourteenth transistor T14. At this time, the second clock pulse CB is at a low potential, so that the low-potential second clock pulse CB connected to the fourteenth transistor T14 is turned on and the third connection point PQB, thereby pulling the voltage of PQB down to a low potential.

[0170] In some exemplary embodiments, during the P1 and P2 phases, when the first clock pulse CK is at a low level, the tenth transistor T10 and the fourteenth transistor T14 are both turned off, and cannot conduct the low voltage to the third connection point PQB, thereby not affecting the ninth transistor T9 from charging the third connection point PQB.

[0171] In some exemplary embodiments, during the P3 phase, the input voltage IN is maintained at a low potential, and regardless of whether the first clock pulse CK is at a high potential or a low potential, the fourteenth transistor T14 is turned off, so that the second clock pulse CB or other low voltage connected thereto is not conducted to the third connection point PQB.

[0172] Thus, in the shift register unit provided in the exemplary embodiment of the present disclosure, in the second sub-circuit 1042, the gate of the eleventh transistor T11 in the aforementioned embodiment is directly connected to the input voltage IN, and is replaced by a fourteenth transistor T14 in this embodiment whose gate is connected to the fourth connection point PQ, thereby achieving the control of turning on and off of the fourteenth transistor T14 by the potential of the fourth connection point PQ, that is, when the first transistor T1 is turned off, the fourteenth transistor T14 can be turned off.

[0173] An exemplary embodiment of the present disclosure provides a shift register unit. FIG9 is a seventh circuit diagram of the shift register unit according to an exemplary embodiment of the present disclosure. As shown in FIG9 , the shift register unit may further include a second access circuit 104 and a charging circuit 103. The second access circuit 104 may include a first sub-circuit 1041 and a second sub-circuit 1042. The second sub-circuit 1042 may include a fifteenth transistor T15.

[0174] The fifteenth transistor T15 may have a dual-gate structure, a gate of the fifteenth transistor T15 is connected to the fourth connection point PQ, a source of the fifteenth transistor T15 is connected to the third connection point PQB, and a drain of the fifteenth transistor T15 is connected to the second clock pulse CB.

[0175] In some exemplary embodiments, during the P1 and P2 phases, when the first clock pulse CK is at a high potential, the first transistor T1 is turned on, so that the potential of the fourth connection point PQ is at a high potential, thereby turning on the fifteenth transistor T15. At this time, the second clock pulse CB is at a low potential, so that the low-potential second clock pulse CB connected to the fifteenth transistor T15 is turned on and the third connection point PQB, thereby pulling the voltage of PQB down to a low potential.

[0176] In some exemplary embodiments, during the P1 and P2 phases, when the first clock pulse CK is at a low level, the fifteenth transistor T15 is turned off and cannot conduct the low voltage to the third connection point PQB, thereby not affecting the ninth transistor T9 from charging the third connection point PQB.

[0177] In some exemplary embodiments, during the P3 phase, the input voltage IN is maintained at a low potential, and regardless of whether the first clock pulse CK is at a high potential or a low potential, the fifteenth transistor T15 is turned off, so that the second clock pulse CB or other low voltage connected thereto is not conducted to the third connection point PQB.

[0178] In this way, in the shift register unit provided in the exemplary embodiment of the present disclosure, based on the first access circuit 101 and the output circuit 102 connected to the first connection point, it is turned on when the first clock pulse CK of the first access high potential is connected, so that the input voltage IN is conducted to the first connection point Q, thereby pulling up the voltage of the first connection point Q, and turning on the output circuit 102, and then applying the input voltage IN to the outside of the shift register unit of this level, and serving as the output voltage OUT. At the same time, the output circuit 102 turns off other transistors that can pull down the output voltage OUT through the low-potential connection voltage connected, thereby ensuring that the output voltage OUT at this time can be maintained at a stable high potential.

[0179] In some exemplary embodiments, FIG10 shows a first simulation schematic diagram of the circuit of any of the aforementioned exemplary embodiments of the present disclosure, and FIG11 shows a second simulation schematic diagram of the circuit of any of the aforementioned exemplary embodiments of the present disclosure, wherein, as shown in FIG10 , the first simulation schematic diagram represents the output voltage OUT when the threshold voltage Vth of the transistor is -2 V. As shown in FIG11 , the second simulation schematic diagram represents the output voltage OUT when the threshold voltage Vth of the transistor is 4 V.

[0180] It can be seen from FIG. 10 and FIG. 11 that in the shift register unit provided in the exemplary embodiment of the present disclosure, the output voltage OUT can still be kept stable while the Vth of the transistor has a relatively large range.

[0181] For the convenience of description, the above devices are described as being functionally divided into various modules. Of course, when implementing the embodiments of the present disclosure, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0182] The embodiments of the present disclosure further provide a circuit driving method, which is applicable to the shift register unit of any of the aforementioned exemplary embodiments of the present disclosure.

[0183] FIG12 is a flow chart of a circuit driving method according to an embodiment of the present disclosure. As shown in FIG12 , the circuit driving method may include the following steps:

[0184] Step S1201: connect a first access circuit to an input voltage and a first clock pulse, and turn on when the first clock pulse is at a high potential. The input voltage keeps the voltage at the first connection point at a high potential.

[0185] Step S1202: connect the output circuit to the connection voltage and the source voltage, turn on when the first connection point is connected to a high-potential voltage, output the source voltage to the output end, and use the connection voltage to keep the output voltage stable at a high potential. The output circuit and the first connection circuit are connected to the first connection point.

[0186] The circuit driving method embodiment described above is applicable to the shift register unit described in any of the aforementioned exemplary embodiments of the present disclosure, and is similar to the description of the aforementioned shift register unit embodiment, and has similar beneficial effects as the shift register unit embodiment. For technical details not disclosed in the circuit driving method embodiment of the present disclosure, those skilled in the art should refer to the description of the shift register unit embodiment of the present disclosure for understanding, and will not be repeated here.

[0187] The methods of the embodiments of the present disclosure can be performed by a single device, such as a computer or server. The methods of the embodiments of the present disclosure can also be applied in a distributed scenario, where multiple devices cooperate to perform the method. In such a distributed scenario, one of the multiple devices may only perform one or more steps of the methods of the embodiments of the present disclosure, and the multiple devices will interact with each other to complete the method.

[0188] The foregoing describes some embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than described in the above embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0189] The present disclosure further provides a driving substrate, comprising at least one shift register unit as described in any of the above exemplary embodiments.

[0190] The present disclosure also provides a display device, comprising the driving substrate as described in any of the above exemplary embodiments.

[0191] The description of the above drive substrate and display device embodiments is similar to the description of the above shift register unit embodiment, and has similar beneficial effects as the shift register unit embodiment. For technical details not disclosed in the driver substrate and display device embodiments of the present disclosure, those skilled in the art are referred to the description of the shift register unit embodiment of the present disclosure for understanding, and will not be repeated here.

[0192] Those skilled in the art will understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Within the scope of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0193] In addition, to simplify the description and discussion, and so as not to obscure the embodiments of the present disclosure, known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided figures. In addition, devices may be shown in block diagram form to avoid obscuring the embodiments of the present disclosure, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present disclosure are to be implemented (i.e., these details can be well within the purview of those skilled in the art). Where exemplary details (e.g., circuits) are set forth to describe exemplary embodiments of the present disclosure, it will be apparent to those skilled in the art that embodiments of the present disclosure can be implemented without these exemplary details or with variations in these exemplary details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0194] Although the present disclosure has been described in conjunction with exemplary embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may utilize the discussed embodiments.

[0195] The embodiments of the present disclosure are intended to encompass all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included within the scope of protection of the present disclosure.< / m> < / m> < / m> < / m>

Claims

1. A shift register unit, comprising: a first access circuit and an output circuit; The first access circuit is connected to the input voltage and the first clock pulse, and is configured to be turned on when the first clock pulse is at a high level, and the input voltage keeps the voltage of the first connection point at a high level; The output circuit is connected to the first access circuit at the first connection point, connected to the connection voltage and the source voltage, and is configured to turn on when the first connection point is connected to a high potential voltage, output the source voltage to the output end, and use the connection voltage to keep the output voltage stable at a high potential.

2. The shift register unit according to claim 1 , further comprising: A charging circuit and a second access circuit; The charging circuit is connected to the output circuit at a second connection point and is configured to charge from the second access circuit when the first clock pulse is at a low level, and to discharge to the second connection point when the first clock pulse is at a high level and the input voltage is at a low level, so as to maintain the voltage of the second connection point at a high level; The second access circuit is connected to the charging circuit at a third connection point and is configured to connect an input voltage and a second clock pulse. When the first clock pulse is at a low potential, the second clock pulse is used to maintain the voltage at the third connection point at a high potential to discharge the charging circuit. The first clock pulse and the second clock pulse have opposite high and low potentials. The output circuit is further configured to connect a low potential voltage from the first connection point to make the output voltage low potential, and when connecting a high potential voltage from the second connection point, use the connection voltage to keep the output voltage stable at a low potential.

3. The shift register unit according to claim 2, wherein: The first access circuit includes: a first transistor and a second transistor; The source of the first transistor is connected to the input voltage, the gate of the first transistor is connected to the first clock pulse, and the drain of the first transistor is connected to the fourth connection point; the first transistor is configured to turn on when the first clock pulse is at a high potential, and apply the input voltage at a high potential to the fourth connection point; The source of the second transistor is connected to the fourth connection point, the gate of the second transistor is connected to the first clock pulse, and the drain of the second transistor is connected to the first connection point; the second transistor is configured to be turned on when the first clock pulse is a high potential, to connect the input voltage from the fourth connection point, and to apply the input voltage to the first connection point to pull the voltage of the first connection point to a high potential.

4. The shift register unit according to claim 3, wherein: The connection voltage includes a first connection voltage and a second connection voltage, wherein the second connection voltage is less than the first connection voltage; The output circuit includes: a third transistor, a fourth transistor and a fifth transistor; The source of the third transistor is connected to the source voltage, and the gate of the third transistor is connected to the first connection point; the third transistor is configured to be turned on when the first connection point is at a high potential, and output the source voltage as a high-potential output voltage through the drain of the third transistor; The source of the fourth transistor is connected to the drain of the third transistor, the gate of the fourth transistor is connected to the second connection point and the first connection voltage, and the drain of the fourth transistor is connected to the first connection voltage; the fourth transistor is configured to be turned off when the voltage of the second connection point is low, so as to maintain the output voltage output by the drain of the third transistor at a high voltage; The source of the fifth transistor is connected to the second connection point, the gate of the fifth transistor is connected to the first connection point, and the drain of the fifth transistor is connected to the second connection voltage; the fifth transistor is configured to be turned on when the voltage of the first connection point is a high potential, and to use the second connection voltage of the drain to pull down the voltage of the second connection point to a low potential.

5. The shift register unit according to claim 4, wherein: The charging circuit includes: a storage capacitor, a sixth transistor and a seventh transistor; One end of the storage capacitor is connected to the third connection point; the storage capacitor is configured to be charged when the voltage of the third connection point is at a high potential, and to be discharged when the voltage of the third connection point is at a low potential; The source of the sixth transistor is connected to the first clock pulse, the gate of the sixth transistor is connected to the third connection point, and the drain of the sixth transistor is connected to the other end of the storage capacitor; the sixth transistor is configured to be turned on when the third connection point is at a high potential; The source of the seventh transistor is connected to the other end of the storage capacitor and the drain of the sixth transistor, the gate of the seventh transistor is connected to the first clock pulse, and the drain of the seventh transistor is connected to the second connection point; the seventh transistor is configured to turn on when the first clock pulse is a high potential so that the storage capacitor discharges to the second connection point, and to turn off when the first clock pulse is a low potential.

6. The shift register unit according to claim 4, wherein: The first access circuit further includes: an eighth transistor; The gate of the eighth transistor is connected to the first connection point, the source of the eighth transistor is connected to the source voltage, and the drain of the eighth transistor is connected to the fourth connection point; The eighth transistor is configured to be turned on when the voltage of the first connection point has not completely dropped to a low potential, apply the source voltage to the fourth connection point, and keep the voltage of the fourth connection point higher than the voltage of the first connection point so that the second transistor does not leak when it is not completely turned off.

7. The shift register unit according to claim 4, wherein: The second access circuit includes: a first sub-circuit and a second sub-circuit; The first sub-circuit is connected to the second clock pulse and the third connection point, and is configured to be turned on when the second clock pulse is at a high voltage, and to pull up the voltage of the third connection point to a high voltage; The second sub-circuit is connected to the input voltage and the low voltage, and is connected to the first sub-circuit at the third connection point, and is configured to turn on when the input voltage and the first clock pulse are both at a high potential, and pull down the third connection point to a low potential; The low voltage includes the second clock pulse or the second connection voltage at a low potential.

8. The shift register unit according to claim 7, wherein: The first sub-circuit includes a ninth transistor; The source of the ninth transistor and the gate of the ninth transistor are connected to the second clock pulse, and the drain of the ninth transistor is connected to the third connection point; The ninth transistor is configured to be turned on when the second clock pulse is at a high potential, and to apply the high potential second clock pulse to the third connection point to keep the third connection point at a high potential.

9. The shift register unit according to claim 7, wherein: The second sub-circuit includes: a tenth transistor and an eleventh transistor; The gate of the tenth transistor is connected to the first clock pulse, and the source of the tenth transistor is connected to the third connection point; the tenth transistor is configured to be turned on when the first clock pulse is at a high voltage; The source of the eleventh transistor is connected to the drain of the tenth transistor, the gate is connected to the input voltage, and the drain is connected to the low voltage; The eleventh transistor is configured to turn on when the input voltage is connected; and the eleventh transistor is configured to connect the low voltage and the third connection point when it is turned on at the same time as the tenth transistor, and use the low voltage to pull down the voltage of the third connection point to a low potential.

10. The shift register unit according to claim 7, wherein: The first sub-circuit includes a twelfth transistor; The source of the twelfth transistor is connected to the source voltage, the gate of the twelfth transistor is connected to the second clock pulse, and the drain of the twelfth transistor is connected to the third connection point; The twelfth transistor is configured to be turned on when the second clock pulse is at a high potential, and to apply the high potential source voltage to the third connection point to keep the third connection point at a high potential.

11. The shift register unit according to claim 7, wherein: The second sub-circuit includes a thirteenth transistor; The thirteenth transistor is a dual-gate transistor, a source of the thirteenth transistor is connected to the third connection point, a first gate of the thirteenth transistor is connected to the input voltage, and a drain of the thirteenth transistor is connected to the low voltage; The thirteenth transistor is configured to be turned on when the input voltage is connected, connect the low voltage and the third connection point, and use the low voltage to pull down the voltage of the third connection point to a low potential.

12. The shift register unit according to claim 7, wherein: The second sub-circuit includes: a tenth transistor and a fourteenth transistor; The gate of the tenth transistor is connected to the first clock pulse, and the source of the tenth transistor is connected to the third connection point; the tenth transistor is configured to be turned on when the first clock pulse is at a high voltage; The source of the fourteenth transistor is connected to the drain of the tenth transistor, the gate of the fourteenth transistor is connected to the fourth connection point, and the drain of the fourteenth transistor is connected to the low voltage; The fourteenth transistor is configured to be turned on when the input voltage is connected to the fourth connection point; and the fourteenth transistor is configured to connect the low voltage and the third connection point when it is turned on at the same time as the tenth transistor, and use the low voltage to pull down the voltage of the third connection point to a low potential.

13. The shift register unit according to claim 7, wherein: The second sub-circuit includes a fifteenth transistor; The fifteenth transistor is a dual-gate transistor, the source of the fifteenth transistor is connected to the third connection point, the first gate of the fifteenth transistor is connected to the fourth connection point, and the drain of the fifteenth transistor is connected to the low voltage; the fifteenth transistor is configured to turn on when the input voltage is connected, connect the low voltage and the third connection point, and use the low voltage to pull down the voltage of the third connection point to a low potential.

14. A circuit driving method, applicable to the shift register unit according to any one of claims 1 to 13, the circuit driving method comprising: Connecting the first access circuit to an input voltage and a first clock pulse, and turning on the first access circuit when the first clock pulse is at a high level, wherein the input voltage maintains a voltage at the first connection point at a high level; The output circuit is connected to the connection voltage and the source voltage, and is turned on when the first connection point is connected to a high potential voltage, and the source voltage is output to the output end. The connection voltage is used to keep the output voltage stable at a high potential, and the output circuit and the first connection circuit are connected to the first connection point.

15. A driving substrate, comprising: A plurality of shift register units according to any one of claims 1 to 13.

16. A display device comprising: The drive substrate according to claim 15.

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