Shift register and control method therefor, gate driving circuit, and display apparatus

Abstract

A shift register and a control method therefor, a gate driving circuit, and a display apparatus. The shift register comprises: an input circuit (11), which is electrically connected to a control signal input end (IN), a first clock signal end (CK) and a first node (Q); a pull-up circuit (21), which is electrically connected to the input circuit (11), a first voltage end (GVDD) and the first node (Q), and is configured to control, on the basis of a signal of the first node (Q), the input circuit (11) to output a control signal; a first pull-down circuit (31), which is electrically connected to the first node (Q), a second voltage end (GVSS2) and a second node (QB), and is configured to control a signal of the second node (QB) on the basis of the signal of the first node (Q); a second pull-down circuit (32), which is electrically connected to the second node (QB), a third voltage end (GVSS1) and a second clock signal end (CB), and is configured to control the signal of the second node (QB) on the basis of a signal of the second clock signal end (CB); and an output circuit (12), which is electrically connected to the first node (Q), the second node (QB) and a control signal output end (OUT).

Description

Shift register and control method thereof, gate drive circuit and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on April 2, 2024, with application number 202410397038.0 and invention name “A shift register and its control method, gate drive circuit and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, the technical field of display devices, and in particular to a shift register and a control method thereof, a gate drive circuit, and a display device. Background Art

[0003] Display device driver circuits often utilize numerous components, and the stability of the components' electrical characteristics impacts the functionality of the driver circuits. For example, when the threshold voltage (Vth) of a transistor within a driver circuit drifts, it affects the transistor's on-off characteristics, potentially causing the display device's driver circuit to malfunction.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] Embodiments of the present disclosure provide a shift register and a control method thereof, a gate driving circuit, and a display device.

[0007] In one aspect, an embodiment of the present disclosure provides a shift register, comprising:

[0008] an input circuit electrically connected to the control signal input terminal, the first clock signal terminal, and the first node, and configured to output the control signal inputted from the control signal input terminal under the control of the signal inputted from the first clock signal terminal;

[0009] a pull-up circuit electrically connected to the input circuit, the first voltage terminal, and the first node, and configured to control the input circuit to output the control signal according to a signal of the first node;

[0010] a first pull-down circuit electrically connected to the first node, the second voltage terminal, and the second node, and configured to control the signal of the second node according to the signal of the first node;

[0011] a second pull-down circuit electrically connected to the second node, the third voltage terminal, and the second clock signal terminal, and configured to control the signal of the second node according to the signal of the second clock signal terminal;

[0012] an output circuit electrically connected to the first node, the second node, and the control signal output terminal, and configured to output the control signal to the control signal output terminal according to signals of the first node and the second node;

[0013] The potential of the second voltage terminal is lower than the potential of the third voltage terminal.

[0014] Optionally, the pull-up circuit includes:

[0015] A first transistor, wherein the source of the first transistor is electrically connected to the input circuit, the drain of the first transistor is electrically connected to the first voltage terminal, and the gate of the first transistor is electrically connected to the first node, and is configured to control the conduction or disconnection between the source and the drain of the first transistor according to a signal of the first node.

[0016] Optionally, the first pull-down circuit includes:

[0017] a second transistor, wherein the source of the second transistor is electrically connected to the second node, the drain of the second transistor is electrically connected to the second voltage terminal, and the gate of the second transistor is electrically connected to the first node, and is configured to control the conduction or disconnection between the source and the drain of the second transistor according to the signal of the first node.

[0018] Optionally, the first pull-down circuit further includes: a third transistor and a fourth transistor;

[0019] The source of the third transistor is electrically connected to the drain of the second transistor and the drain of the fourth transistor, the drain of the third transistor is electrically connected to the second voltage terminal, and the gate of the third transistor is electrically connected to the first node, and is configured to control the connection or disconnection between the source and drain of the third transistor according to the signal of the first node;

[0020] The source of the fourth transistor is electrically connected to the first voltage terminal, and the gate of the fourth transistor is electrically connected to the second node, and is configured to control the conduction or disconnection between the source and the drain of the fourth transistor according to the signal of the second node.

[0021] Optionally, the second pull-down circuit includes: a fifth transistor and a sixth transistor;

[0022] The source of the fifth transistor is electrically connected to the second clock signal terminal, the drain of the fifth transistor is electrically connected to the second node, the gate of the fifth transistor is electrically connected to the second clock signal terminal and the source of the sixth transistor, and is configured to control the connection or disconnection between the source and drain of the fifth transistor according to the signal of the second clock signal terminal;

[0023] The drain of the sixth transistor is electrically connected to the third voltage terminal, and the gate of the sixth transistor is electrically connected to the first clock signal terminal or the control signal input terminal, and is configured to control the conduction or disconnection between the source and the drain of the sixth transistor according to the signal of the first clock signal terminal or the control signal input terminal.

[0024] Optionally, the second pull-down circuit further includes: a seventh transistor;

[0025] The source of the seventh transistor is electrically connected to the drain of the sixth transistor, the drain of the seventh transistor is electrically connected to the third voltage terminal, and the gate of the seventh transistor is electrically connected to the first clock signal terminal, and is configured to control the conduction or disconnection between the source and drain of the seventh transistor according to the signal of the first clock signal terminal.

[0026] Optionally, the device further comprises: a third pull-down circuit;

[0027] The third pull-down circuit includes: an eighth transistor, the source of the eighth transistor is electrically connected to the first node, the drain of the eighth transistor is electrically connected to the third voltage terminal, and the gate of the eighth transistor is electrically connected to the reset signal terminal, and is configured to control the output circuit to be turned on or off according to the signal of the reset signal terminal.

[0028] Optionally, the output circuit includes:

[0029] a ninth transistor, wherein the source of the ninth transistor is electrically connected to the second clock signal terminal, the drain of the ninth transistor is electrically connected to the first node and the control signal output terminal, and the gate of the ninth transistor is electrically connected to the first node, and is configured to output the control signal to the control signal output terminal according to the signals of the first node and the second clock signal terminal.

[0030] Optionally, the output circuit further includes: a fourth pull-down circuit;

[0031] The fourth pull-down circuit includes: a tenth transistor, the source of the tenth transistor is electrically connected to the drain of the ninth transistor, the first node and the control signal output terminal, the drain of the tenth transistor is electrically connected to the second node and the third voltage terminal, and the gate of the tenth transistor is electrically connected to the second node, and is configured to control the ninth transistor to output the control signal according to the signal of the second node.

[0032] Optionally, the input circuit includes: an eleventh transistor and a twelfth transistor;

[0033] The source of the eleventh transistor is electrically connected to the control signal input terminal, the drain of the eleventh transistor is electrically connected to the source of the first transistor and the source of the twelfth transistor, and the gate of the eleventh transistor is electrically connected to the first clock signal terminal, and is configured to control the connection or disconnection between the source and the drain of the eleventh transistor according to the signal of the first clock signal terminal;

[0034] The drain of the twelfth transistor is electrically connected to the first node, and the gate of the twelfth transistor is electrically connected to the first clock signal end, and is configured to control the conduction or disconnection between the source and the drain of the twelfth transistor according to the signal of the first clock signal end.

[0035] In yet another aspect, an embodiment of the present disclosure further provides a shift register control method, which is applied to the shift register in the above embodiment, comprising:

[0036] In a first timing sequence, the control signal input terminal and the first clock signal terminal are at a high level, and the second clock signal terminal is at a low level;

[0037] In the second timing, the control signal input terminal and the second clock signal terminal are at a low level, and the first clock signal terminal is at a high level;

[0038] In a third time sequence, the control signal input terminal and the first clock signal terminal are at a low level, and the second clock signal terminal is at a high level;

[0039] The first time sequence, the second time sequence and the third time sequence are periodically alternated, and the first voltage terminal is a common voltage terminal, and the second voltage terminal and the third voltage terminal are ground voltage terminals.

[0040] In yet another aspect, an embodiment of the present disclosure further provides a gate driving circuit, comprising: a first clock signal line, a second clock signal line, and a plurality of cascaded shift registers according to any one of the above embodiments;

[0041] In the order of cascading, the first clock signal terminal and the second clock signal terminal of the shift register are alternately electrically connected to the first clock signal line or the second clock signal line.

[0042] On the other hand, an embodiment of the present disclosure further provides a display device, comprising: the shift register in any one of the above embodiments, or the gate driving circuit in any one of the above embodiments.

[0043] The display device provided by the embodiments of the present disclosure includes the shift register or gate driving circuit in the above embodiments, and also has all the advantages of the above shift register or gate driving circuit.

[0044] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. Other advantages of the present disclosure can be realized and obtained through the solutions described in the description and the drawings.

[0045] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0046] Summary of the Figures

[0047] The accompanying drawings are for reference and illustration purposes only and are not intended to limit the scope of protection of the present disclosure. The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present disclosure. The embodiments described in this specification are only some of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0048] FIG1 shows a structural block diagram of a shift register in an embodiment provided by the present disclosure.

[0049] FIG2 shows a circuit diagram of a shift register according to an embodiment of the present disclosure.

[0050] FIG3 shows a circuit diagram of yet another shift register in an embodiment provided by the present disclosure.

[0051] FIG4 shows a circuit diagram of yet another shift register in an embodiment provided by the present disclosure.

[0052] FIG5 shows a circuit diagram of yet another shift register in an embodiment provided by the present disclosure.

[0053] FIG6 shows a circuit diagram of yet another shift register in an embodiment provided by the present disclosure.

[0054] FIG7 shows a schematic diagram of the working timing of a shift register in an embodiment provided by the present disclosure.

[0055] FIG8 shows a schematic diagram of a cascade connection of a gate driving circuit in an embodiment provided by the present disclosure.

[0056] Details

[0057] In order to make the purpose, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the exemplary embodiments described herein are only used to explain the present disclosure and are not intended to limit the present disclosure.

[0058] Display devices often use a large number of transistors, such as metal oxide semiconductor field effect transistors (MOS), to realize the gate circuit driving of light-emitting components. In the case of a positive or negative drift in the threshold voltage Vth of the transistor, the gate drive circuit may not work properly because the transistor cannot be turned on or off in time. For example, if the threshold voltage Vth of the transistor drifts negatively, when the voltage that causes the state of the transistor to change cannot be reduced, it may cause the source and drain of the transistor to be unable to be disconnected, causing the circuit in which the transistor is located to malfunction. For another example, taking the transistor included in the drive circuit as an example, due to the presence of many defects on the interface between amorphous silicon (a-Si) and silicon nitride (SiNx), long-term application of bias voltage will cause charge to accumulate on the interface between a-Si and SiNx. The electric field formed by this charge will be superimposed on the gate voltage, causing the threshold voltage Vth of the transistor to drift, thereby affecting the on-off characteristics of the transistor, which can easily cause the drive circuit of the display device to be unable to drive normally.

[0059] The embodiments of the present disclosure propose a shift register and a control method thereof, a gate drive circuit, and a display device. The pull-up circuit is controlled through a first node, so that when the threshold voltage of a transistor in an input circuit drifts and cannot be disconnected, the pull-up circuit can pull up the first node, thereby avoiding leakage of the first node. In addition, the second node is pulled down by a combination of a first pull-down circuit and a second pull-down circuit. By utilizing the potential of the second voltage terminal being lower than the potential of the third voltage terminal, the transistor in the output circuit can be disconnected when the threshold voltage of the transistor in the output circuit drifts and cannot be disconnected, thereby maintaining the normal operation of the shift register and improving the functional stability of the shift register.

[0060] Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0061] The embodiments of the present disclosure provide a shift register, which may also be referred to as a GOA unit.

[0062] Figure 1 shows a structural block diagram of a shift register according to an embodiment of the present disclosure. As shown in Figure 1 , the shift register may include: an input circuit 11 , a pull-up circuit 21 , a first pull-down circuit 31 , a second pull-down circuit 32 , and an output circuit 12 .

[0063] In some optional embodiments, the input circuit 11 is electrically connected to the control signal input terminal IN, the first clock signal terminal CK and the first node Q, and is configured to output the control signal input to the control signal input terminal IN under the control of the signal input to the first clock signal terminal CK.

[0064] In some optional embodiments, the control signal may include a driving control signal of a gate of a pixel circuit in a display device.

[0065] In some optional embodiments, the control signal output by the control signal input terminal IN to the input circuit 11 may vary periodically. The first clock signal terminal CK is configured to output a first clock signal, and the potential of the first clock signal may vary periodically. For example, within a cycle of the control signal, the potential of the first clock signal is at least partially the same as the potential of the control signal. For example, during the period when the control signal remains at a high level, the first clock signal may remain at a high level.

[0066] In some optional embodiments, the pull-up circuit 21 is electrically connected to the input circuit 11 , the first voltage terminal GVDD, and the first node Q, and is configured to control the input circuit 11 to output a control signal according to a signal at the first node Q.

[0067] In some optional embodiments, the first pull-down circuit 31 is electrically connected to the first node Q, the second voltage terminal GVSS2 and the second node QB, and is configured to control the signal of the second node QB according to the signal of the first node Q.

[0068] In some optional embodiments, the second pull-down circuit 32 is electrically connected to the second node QB, the third voltage terminal GVSS1 and the second clock signal terminal CB, and is configured to control the signal of the second node QB according to the signal of the second clock signal terminal CB.

[0069] In some optional embodiments, the second clock signal terminal CB is configured to output a second clock signal. For example, the potentials of the first clock signal and the second clock signal can remain opposite, i.e., the first clock signal and the second clock signal are mutually inverted signals. For example, the potential of the second clock signal terminal CB can vary periodically. For example, when the first clock signal terminal CK outputs a high level, the second clock signal terminal CB outputs a low level.

[0070] In some optional embodiments, the output circuit 12 is electrically connected to the first node Q, the second node QB and the control signal output terminal OUT, and is configured to output a control signal to the control signal output terminal OUT based on the signals of the first node Q and the second node QB.

[0071] In some optional embodiments, the above circuit may be implemented by including transistors. For example, as shown in Figures 2 to 6, the transistors (such as the first transistor T3, the second transistor T6, etc.) in the circuits in one or more exemplary embodiments described below may be metal oxide semiconductor field effect transistors or thin film transistors (TFTs), and may be configured to implement at least one of the following functions: signal modulation, rectification, and signal amplification. Exemplarily, one or more transistors may include a source, a drain, and a gate, or one or more transistors may include an emitter, a collector, and a base.

[0072] In some optional implementations, the shift register may further include a capacitor, which is configured to at least one of store charge and perform filtering.

[0073] In some optional implementations, the first voltage terminal GVDD is a common voltage terminal, or a positive power supply voltage terminal. The second voltage terminal GVSS2 and the third voltage terminal GVSS1 are ground voltage terminals, or negative power supply voltage terminals.

[0074] In some optional implementations, the potential of the second voltage terminal GVSS2 is lower than the potential of the third voltage terminal GVSS1 .

[0075] In this way, in the shift register provided in the exemplary embodiment of the present disclosure, the pull-up circuit 21 is controlled by the first node Q, so that when the threshold voltage of the transistor in the input circuit 11 drifts and cannot be disconnected, the pull-up circuit 21 can pull up the first node Q, thereby avoiding leakage of the first node Q, and the second node QB is pulled down by the combination of the first pull-down circuit 31 and the second pull-down circuit 32. By utilizing the potential of the second voltage terminal GVSS2 being lower than the potential of the third voltage terminal GVSS1, the transistor in the output circuit 12 can be disconnected when the threshold voltage of the transistor in the output circuit 12 drifts and cannot be disconnected, thereby maintaining the normal operation of the shift register, improving the functional stability of the shift register, and stably realizing the function of the shift register to receive and store data and shift the data bits in an orderly manner.

[0076] FIG2 shows a circuit diagram of a shift register in an embodiment provided by the present application. In the shift register provided by the exemplary embodiment of the present disclosure, a transistor and a positive power supply voltage terminal can be used to pull up the first node Q to prevent the first node Q from leaking when the threshold voltage of the transistor in the input circuit 11 drifts. In some optional embodiments, as shown in FIG2 , the pull-up circuit 21 may include: a first transistor T3; wherein the source of the first transistor T3 is electrically connected to the input circuit 11, the drain of the first transistor T3 is electrically connected to the first voltage terminal GVDD, and the gate of the first transistor T3 is electrically connected to the first node Q; the first transistor T3 is configured to control the conduction or disconnection between the source of the first transistor T3 and the drain of the first transistor T3 according to the signal of the first node Q.

[0077] In the shift register provided by the exemplary embodiments of the present disclosure, in order to enable the output circuit 12 to stably output a low-level state for a long time, the second node QB can be pulled down using a transistor and a negative power supply voltage terminal. To this end, in some optional embodiments, as shown in FIG2 , the first pull-down circuit 31 may include: a second transistor T6; wherein the source of the second transistor T6 is electrically connected to the second node QB, the drain of the second transistor T6 is electrically connected to the second voltage terminal GVSS2, and the gate of the second transistor T6 is electrically connected to the first node Q; the second transistor T6 is configured to control the connection or disconnection between the source of the second transistor T6 and the drain of the second transistor T6 according to the signal of the first node Q.

[0078] In the shift register provided by the exemplary embodiments of the present disclosure, the first pull-down circuit 31 and the second pull-down circuit 32 cooperate, and the potential of the second voltage terminal GVSS2 is lower than the potential of the third voltage terminal GVSS1. This prevents negative drift in the transistors in the output circuit 12, effectively disconnecting the transistors in the output circuit 12. This allows the output circuit 12 to output a low-level state more stably for a long period of time. To this end, in some optional embodiments, as shown in FIG. 2 , the second pull-down circuit 32 may include a fifth transistor T4 and a sixth transistor T5.

[0079] In some optional embodiments, as shown in Figure 2, the source of the fifth transistor T4 is electrically connected to the second clock signal terminal CB, the drain of the fifth transistor T4 is electrically connected to the second node QB, and the gate of the fifth transistor T4 is electrically connected to the second clock signal terminal CB and the source of the sixth transistor T5; the fifth transistor T4 is configured to control the conduction or disconnection between the source and the drain of the fifth transistor T4 according to the signal of the second clock signal terminal CB.

[0080] In some further optional embodiments, as shown in FIG2 , the second pull-down circuit 32 may further include: a first capacitor C3 ; wherein the first capacitor C3 may be disposed between the second clock signal terminal CB and the gate of the fifth transistor T4 ; the first capacitor C3 is configured to store charge and filter.

[0081] In some optional embodiments, as shown in Figure 2, the drain of the sixth transistor T5 is electrically connected to the third voltage terminal GVSS1, and the gate of the sixth transistor T5 is electrically connected to the control signal input terminal IN; the sixth transistor T5 is configured to control the conduction or disconnection between the source and the drain of the sixth transistor T5 according to the signal of the control signal input terminal IN.

[0082] In some further optional embodiments, as shown in FIG3 , the drain of the sixth transistor T5 is electrically connected to the third voltage terminal GVSS1, and the gate of the sixth transistor T5 is electrically connected to the first clock signal terminal CK; the sixth transistor T5 is configured to control the conduction or disconnection between the source and the drain of the sixth transistor T5 according to the signal of the first clock signal terminal CK.

[0083] FIG4 shows a circuit diagram of another shift register in an embodiment of the present disclosure. In order to enable the output circuit 12 to output a low-level state more stably for a long time, in some optional embodiments, as shown in FIG4 , the first pull-down circuit 31 may further include: a third transistor T6 'and a fourth transistor T10. Wherein:

[0084] The source of the third transistor T6' is electrically connected to the drain of the second transistor T6 and the drain of the fourth transistor T10, the drain of the third transistor T6' is electrically connected to the second voltage terminal GVSS2, and the gate of the third transistor T6' is electrically connected to the first node Q; the third transistor T6' is configured to control the conduction or disconnection between the source and the drain of the third transistor T6' according to the signal of the first node Q.

[0085] The source of the fourth transistor T10 is electrically connected to the first voltage terminal GVDD, and the gate of the fourth transistor T10 is electrically connected to the second node QB; the fourth transistor T10 is configured to control the conduction or disconnection between the source and the drain of the fourth transistor T10 according to the signal of the second node QB.

[0086] Thus, in the shift register provided by the exemplary embodiments of the present disclosure, the fourth transistor T10 and the first voltage terminal GVDD can be used to effectively prevent leakage of the second node QB from the first pull-down circuit 31, thereby enabling the output circuit 12 to output a low-level state more stably for a long period of time. Furthermore, the cooperation between the first pull-down circuit 31 and the second pull-down circuit 32, and the lower potential of the second voltage terminal GVSS2 than the third voltage terminal GVSS1, can be used to prevent the transistors in the output circuit 12 from drifting negatively, effectively disconnecting the transistors in the output circuit 12, thereby enabling the output circuit 12 to output a low-level state more stably for a long period of time.

[0087] FIG5 shows a circuit diagram of another shift register according to an embodiment of the present disclosure. In one or more exemplary embodiments described above, the second pull-down circuit 32 utilizes the second clock signal terminal CB to periodically charge the second node QB, thereby indirectly controlling the output circuit 12. To enhance the charging control of the second node QB, in some alternative embodiments, as shown in FIG5 , the second pull-down circuit 32 may further include a seventh transistor T5′.

[0088] The source of the seventh transistor T5' is electrically connected to the drain of the sixth transistor T5, the drain of the seventh transistor T5' is electrically connected to the third voltage terminal GVSS1, and the gate of the seventh transistor T5' is electrically connected to the first clock signal terminal CK; the seventh transistor T5' is configured to control the conduction or disconnection between the source of the seventh transistor T5' and the drain of the seventh transistor T5' according to the signal of the first clock signal terminal CK.

[0089] The present disclosure further provides a shift register, in which a circuit can be provided to achieve reset or initialization of the shift register. To this end, in some optional implementations, as shown in FIG5 , the shift register can further include: a third pull-down circuit 33 .

[0090] The third pull-down circuit 33 may include: an eighth transistor T9; the source of the eighth transistor T9 is electrically connected to the first node Q, the drain of the eighth transistor T9 is electrically connected to the third voltage terminal GVSS1, and the gate of the eighth transistor T9 is electrically connected to the reset signal terminal RST; the eighth transistor T9 is configured to control the output circuit 12 to be turned on or off according to the signal of the reset signal terminal RST.

[0091] In some optional implementations, taking the shift register cascade light-emitting method applied to a display device as an example, resetting or initialization can be implemented in the fourth timing sequence and the fifth timing sequence.

[0092] In some optional embodiments, in the fourth timing sequence, the reset signal terminal RST is turned on and is at a high level, and the first nodes Q of the shift registers of all rows in the display device are all pulled down to the third voltage terminal GVSS1 through the eighth transistor T9. The third voltage terminal GVSS1 can be a ground voltage terminal, and the ninth transistor T7 in the output circuit 12 of the shift registers of all rows is turned off.

[0093] In some optional embodiments, in the fifth timing sequence, the high-level signal from the first clock signal terminal CK or the second clock signal terminal CB charges the second node QB through the fifth transistor T4, turning on the tenth transistor T8 and maintaining the control signal output terminal OUT electrically connected to the output circuit 12 at a low level.

[0094] Therefore, through the fourth timing and the fifth timing in the above embodiment, the first node Q can be pulled down to the potential of the third voltage terminal GVSS1, and the second node QB can be pulled up to the potential of the first voltage terminal GVDD, so that the shift registers of all rows in the display device can be reset.

[0095] In the shift register provided by the exemplary embodiment of the present disclosure, the output circuit 12 can be controlled by a transistor. To this end, in some optional embodiments, as shown in Figure 2, the output circuit 12 may include: a ninth transistor T7; the source of the ninth transistor T7 is electrically connected to the second clock signal terminal CB, the drain of the ninth transistor T7 is electrically connected to the first node Q and the control signal output terminal OUT, and the gate of the ninth transistor T7 is electrically connected to the first node Q; the ninth transistor T7 is configured to output a control signal to the control signal output terminal OUT according to the signals of the first node Q and the second clock signal terminal CB.

[0096] In some further optional embodiments, as shown in FIG2 , the output circuit 12 may further include: a second capacitor C1 ; the second capacitor C1 is disposed between the first node Q and the control signal output terminal OUT and the drain of the ninth transistor T7 , and the second capacitor C1 is configured to store charge and filter.

[0097] In the shift register provided by the exemplary embodiment of the present disclosure, a pull-down circuit may be further provided in the output circuit 12 to implement signal output control. To this end, in some optional embodiments, as shown in FIG2 , the output circuit 12 may include: a fourth pull-down circuit 34 .

[0098] In some optional embodiments, as shown in Figure 2, the fourth pull-down circuit 34 may include: a tenth transistor T8; the source of the tenth transistor T8 is electrically connected to the drain of the ninth transistor T7, the first node Q and the control signal output terminal OUT, the drain of the tenth transistor T8 is electrically connected to the second node QB and the third voltage terminal GVSS1, and the gate of the tenth transistor T8 is electrically connected to the second node QB; the tenth transistor T8 is configured to control the ninth transistor T7 to output a control signal according to the signal of the second node QB.

[0099] In some further optional embodiments, the second capacitor C1 may also be disposed between the first node Q and the control signal output terminal OUT, the drain of the ninth transistor T7 and the source of the tenth transistor T8 , and is configured to store charge and filter.

[0100] In some further optional embodiments, as shown in FIG2 , the fourth pull-down circuit 34 may further include: a third capacitor C2 ; the third capacitor C2 is disposed between the second node QB and the third voltage terminal GVSS1 and the drain of the tenth transistor T8 , and the third capacitor C2 is configured to store charge and filter.

[0101] FIG6 shows a circuit diagram of another shift register according to an embodiment of the present disclosure. In the shift register provided in the exemplary embodiment of the present disclosure, at least two transistors may be provided in the input circuit 11 to implement input control of the control signal. To this end, in some optional embodiments, as shown in FIG6 , the input circuit 11 may include: an eleventh transistor T1 and a twelfth transistor T2.

[0102] The source of the eleventh transistor T1 is electrically connected to the control signal input terminal IN, the drain of the eleventh transistor T1 is electrically connected to the source of the first transistor T3 and the source of the twelfth transistor T2, and the gate of the eleventh transistor T1 is electrically connected to the first clock signal terminal CK; the eleventh transistor T1 is configured to control the conduction or disconnection between the source and the drain of the eleventh transistor T1 according to the signal of the first clock signal terminal CK.

[0103] The drain of the twelfth transistor T2 is electrically connected to the first node Q, and the gate of the twelfth transistor T2 is electrically connected to the first clock signal terminal CK; the twelfth transistor T2 is configured to control the conduction or disconnection between the source of the twelfth transistor T2 and the drain of the twelfth transistor T2 according to the signal of the first clock signal terminal CK.

[0104] In order to further improve the functional stability of the shift register, in some optional implementations, the shift register may further include: a second transistor T6, a third transistor T6', a fourth transistor T10, a fifth transistor T4, a sixth transistor T5 and a seventh transistor T5'. The relevant electrical connection methods and the functions played in the circuit can refer to the above embodiments.

[0105] The exemplary embodiment of the present disclosure further provides a control method for a shift register. FIG7 shows a schematic diagram of the working timing of a shift register in an embodiment provided by the present disclosure. As shown in FIG7 , the control method for a shift register may include:

[0106] In step S601 , in a first timing sequence, the control signal input terminal IN and the first clock signal terminal CK are at a high level, and the second clock signal terminal CB is at a low level.

[0107] Based on the shift register in the above embodiment, in conjunction with FIG2 , in some optional implementations, in a first timing sequence, a high-level control signal is input to the control signal input terminal IN, a high-level clock signal is input to the first clock signal terminal CK, the eleventh transistor T1 and the twelfth transistor T2 are turned on, the first node Q is pulled high, and at this time, the ninth transistor T7 in the output circuit 12 is turned on. When a high-level signal pulse of the second clock signal terminal CB arrives in the next timing sequence, the control signal output terminal OUT outputs a high-level control signal. At the same time, the first node Q is pulled high, turning on the second transistor T6 and the third transistor T6', and the second node QB is pulled down to the potential of the second voltage terminal GVSS2. Since the potential of the second voltage terminal GVSS2 is lower than the potential of the third voltage terminal GVSS1, the Vgs of the tenth transistor T8 is less than 0V, and the tenth transistor T8 is turned off. At the same time, the sixth transistor T5 is turned on, the gate voltage of the fifth transistor T4 is pulled down to the third voltage terminal GVSS1, and the fifth transistor T4 is turned off.

[0108] In step S602 , in the second timing sequence, the control signal input terminal IN and the second clock signal terminal CB are at a low level, and the first clock signal terminal CK is at a high level.

[0109] Based on the shift register in the above embodiment, in combination with Figure 2, in some optional implementations, in the second timing, the control signal input terminal IN becomes a low level, the first clock signal terminal CK is at a high level, the eleventh transistor T1 and the twelfth transistor T2 are turned on, the first node Q is pulled low, the ninth transistor T7 is turned off, and the first transistor T3 is turned off, and the second transistor T6 is close to the disconnected state.

[0110] Step S603: In the third timing sequence, the control signal input terminal IN and the first clock signal terminal CK are at a low level, and the second clock signal terminal CB is at a high level.

[0111] Based on the shift register in the above embodiment, in combination with Figure 2, in some optional implementations, in the third timing, the second clock signal terminal CB is at a high level, the control signal input terminal IN and the first clock signal terminal CK are at a low level, the sixth transistor T5 is in a disconnected state, and the fifth transistor T4 is turned on by bootstrap coupling through the first capacitor C3. The high level of the second clock signal terminal CB pulls up the second node QB and intermittently charges the second node QB to reach a high level potential. At the same time, the third capacitor C2 maintains the high level potential of the second node QB.

[0112] In some optional implementations, the first timing, the second timing, and the third timing are periodically alternated, and the first voltage terminal GVDD is a common voltage terminal, and the second voltage terminal GVSS2 and the third voltage terminal GVSS1 are ground voltage terminals.

[0113] In this way, the control method of the shift register provided by the exemplary embodiment of the present disclosure is based on the shift register in the above-mentioned embodiment. It only needs to utilize the periodic transformation of the signal timing to partially eliminate or completely eliminate the adverse effects caused by the threshold voltage drift of the transistors in the shift register, thereby realizing the stable operation of the shift register.

[0114] Figure 8 shows a schematic diagram of a cascade connection of a gate drive circuit in one embodiment of the present disclosure. As shown in Figure 8, the present disclosure further provides a gate drive circuit comprising: a first clock signal line, a second clock signal line, and a plurality of cascaded shift registers in the above embodiments.

[0115] In some optional implementations, the gate driving circuit may be a GOA circuit.

[0116] In some optional implementations, along the cascade order, the first clock signal terminal CK and the second clock signal terminal CB of the shift register are alternately electrically connected to the first clock signal line or the second clock signal line.

[0117] In some optional implementations, along the cascade order, starting from the second row of shift registers, the control signal input terminal IN in any shift register may be electrically connected to the control signal output terminal OUT in the previous stage shift register.

[0118] In some optional implementations, the control signal input terminal IN in the first-stage shift register may be electrically connected to the start signal terminal (STV).

[0119] In this way, the gate drive circuit provided by the exemplary embodiment of the present disclosure includes the shift register in the above embodiment, has all the advantages of the above shift register, and, through the alternating access of the first clock signal line and the second clock signal line to the shift register, can effectively realize cascade light-emitting drive, and then apply the gate drive circuit to the display device.

[0120] The exemplary embodiments of the present disclosure further provide a display device, which may include: the shift register or the gate driving circuit in one or more of the above exemplary embodiments.

[0121] Exemplarily, the display device may include electronic devices such as mobile phones, tablet computers, and terminal displays.

[0122] Thus, the display device provided by the exemplary embodiments of the present disclosure includes the shift register or gate driving circuit in the above embodiments, and also has all the advantages of the above shift register or gate driving circuit.

[0123] The descriptions of the shift register control method, gate drive circuit, and display device embodiments described above are similar to those of the aforementioned shift register embodiments and have similar beneficial effects as those of the shift register embodiments. For technical details not disclosed in the driver substrate and display device embodiments of the present disclosure, those skilled in the art should refer to the description of the shift register embodiments of the present disclosure for understanding, and will not be repeated here.

[0124] The exemplary embodiments of the present disclosure further provide a readable storage medium, in which instructions are stored. When a computer executes the instructions, the computer executes the steps of the shift register control method in any of the above embodiments.

[0125] An exemplary embodiment of the present disclosure provides an electronic device, comprising: a processor and a communication interface; the communication interface and the processor are coupled, and the processor is configured to run a computer program or instruction to implement the steps of the shift register control method in any of the above embodiments.

[0126] Exemplary embodiments of the present disclosure provide a computer program product comprising instructions. When the computer program product is run on a signal detection device, the signal detection device is caused to execute the steps of the shift register control method in any of the above embodiments.

[0127] The multiple embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the multiple embodiments can be referenced to each other.

[0128] In the description of this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this disclosure, "plurality" means two or more, unless otherwise expressly specified.

[0129] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, devices, or computer program products. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0130] The embodiments of the present disclosure are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device produce a device for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0131] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0132] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0133] In this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or terminal device that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not preclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0134] In the description of the present disclosure, unless otherwise specified, “plurality” means two or more.

[0135] It should be noted that in the embodiments of the present disclosure, words such as "exemplarily" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present disclosure should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in an exemplary manner.

[0136] The terms "and / or" and "and / or" in this article are merely a way to describe the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0137] This document uses illustrative examples to illustrate the principles and implementation methods of the present disclosure. The description of the above examples is only intended to help understand the technical solutions and core concepts of the present disclosure. Although exemplary embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they understand the basic inventive concepts. Therefore, the appended claims are intended to include the exemplary embodiments and all changes and modifications that fall within the scope of the embodiments of the present disclosure.

Claims

1. A shift register comprising: an input circuit electrically connected to the control signal input terminal, the first clock signal terminal, and the first node, and configured to output the control signal inputted from the control signal input terminal under the control of the signal inputted from the first clock signal terminal; a pull-up circuit electrically connected to the input circuit, the first voltage terminal, and the first node, and configured to control the input circuit to output the control signal according to a signal of the first node; a first pull-down circuit electrically connected to the first node, the second voltage terminal, and the second node, and configured to control a signal of the second node according to a signal of the first node; a second pull-down circuit electrically connected to the second node, the third voltage terminal, and the second clock signal terminal, and configured to control the signal of the second node according to the signal of the second clock signal terminal; an output circuit electrically connected to the first node, the second node, and the control signal output terminal, and configured to output the control signal to the control signal output terminal according to signals of the first node and the second node; The potential of the second voltage terminal is lower than the potential of the third voltage terminal.

2. The shift register according to claim 1, wherein: The pull-up circuit comprises: A first transistor, wherein the source of the first transistor is electrically connected to the input circuit, the drain of the first transistor is electrically connected to the first voltage terminal, and the gate of the first transistor is electrically connected to the first node, and is configured to control the conduction or disconnection between the source and the drain of the first transistor according to a signal of the first node.

3. The shift register according to claim 1, wherein: The first pull-down circuit comprises: a second transistor, wherein the source of the second transistor is electrically connected to the second node, the drain of the second transistor is electrically connected to the second voltage terminal, and the gate of the second transistor is electrically connected to the first node, and is configured to control the conduction or disconnection between the source and the drain of the second transistor according to the signal of the first node.

4. The shift register according to claim 3, wherein: The first pull-down circuit further includes: a third transistor and a fourth transistor; The source of the third transistor is electrically connected to the drain of the second transistor and the drain of the fourth transistor, the drain of the third transistor is electrically connected to the second voltage terminal, and the gate of the third transistor is electrically connected to the first node, and is configured to control the connection or disconnection between the source and drain of the third transistor according to the signal of the first node; The source of the fourth transistor is electrically connected to the first voltage terminal, and the gate of the fourth transistor is electrically connected to the second node, and is configured to control the conduction or disconnection between the source and the drain of the fourth transistor according to the signal of the second node.

5. The shift register according to claim 1, wherein: The second pull-down circuit includes: a fifth transistor and a sixth transistor; The source of the fifth transistor is electrically connected to the second clock signal terminal, the drain of the fifth transistor is electrically connected to the second node, the gate of the fifth transistor is electrically connected to the second clock signal terminal and the source of the sixth transistor, and is configured to control the connection or disconnection between the source and drain of the fifth transistor according to the signal of the second clock signal terminal; The drain of the sixth transistor is electrically connected to the third voltage terminal, and the gate of the sixth transistor is electrically connected to the first clock signal terminal or the control signal input terminal, and is configured to control the conduction or disconnection between the source and the drain of the sixth transistor according to the signal of the first clock signal terminal or the control signal input terminal. The shift register according to claim 5 , wherein: The second pull-down circuit further includes: a seventh transistor; The source of the seventh transistor is electrically connected to the drain of the sixth transistor, the drain of the seventh transistor is electrically connected to the third voltage terminal, and the gate of the seventh transistor is electrically connected to the first clock signal terminal, and is configured to control the conduction or disconnection between the source and drain of the seventh transistor according to the signal of the first clock signal terminal.

7. The shift register according to claim 1 , further comprising: The third pull-down circuit; The third pull-down circuit includes: an eighth transistor, the source of the eighth transistor is electrically connected to the first node, the drain of the eighth transistor is electrically connected to the third voltage terminal, and the gate of the eighth transistor is electrically connected to the reset signal terminal, and is configured to control the output circuit to be turned on or off according to the signal of the reset signal terminal.

8. The shift register according to claim 1, wherein: The output circuit includes: a ninth transistor, wherein the source of the ninth transistor is electrically connected to the second clock signal terminal, the drain of the ninth transistor is electrically connected to the first node and the control signal output terminal, and the gate of the ninth transistor is electrically connected to the first node, and is configured to output the control signal to the control signal output terminal according to the signals of the first node and the second clock signal terminal.

9. The shift register according to claim 8, wherein: The output circuit further includes: a fourth pull-down circuit; The fourth pull-down circuit includes: a tenth transistor, the source of the tenth transistor is electrically connected to the drain of the ninth transistor, the first node and the control signal output terminal, the drain of the tenth transistor is electrically connected to the second node and the third voltage terminal, and the gate of the tenth transistor is electrically connected to the second node, and is configured to control the ninth transistor to output the control signal according to the signal of the second node.

10. The shift register according to claim 2, wherein: The input circuit includes: an eleventh transistor and a twelfth transistor; The source of the eleventh transistor is electrically connected to the control signal input terminal, the drain of the eleventh transistor is electrically connected to the source of the first transistor and the source of the twelfth transistor, and the gate of the eleventh transistor is electrically connected to the first clock signal terminal, and is configured to control the connection or disconnection between the source and the drain of the eleventh transistor according to the signal of the first clock signal terminal; The drain of the twelfth transistor is electrically connected to the first node, and the gate of the twelfth transistor is electrically connected to the first clock signal end, and is configured to control the conduction or disconnection between the source and the drain of the twelfth transistor according to the signal of the first clock signal end.

11. A shift register control method, applied to the shift register according to any one of claims 1 to 10, the control method comprising: In a first timing sequence, the control signal input terminal and the first clock signal terminal are at a high level, and the second clock signal terminal is at a low level; In the second timing, the control signal input terminal and the second clock signal terminal are at a low level, and the first clock signal terminal is at a high level; In a third time sequence, the control signal input terminal and the first clock signal terminal are at a low level, and the second clock signal terminal is at a high level; The first time sequence, the second time sequence and the third time sequence are periodically alternated, and the first voltage terminal is a common voltage terminal, and the second voltage terminal and the third voltage terminal are ground voltage terminals.

12. A gate drive circuit comprising: a first clock signal line, a second clock signal line, and a plurality of cascaded shift registers according to any one of claims 1 to 10; In the order of cascading, the first clock signal terminal and the second clock signal terminal of the shift register are alternately electrically connected to the first clock signal line or the second clock signal line.

13. A display device comprising: The shift register according to any one of claims 1 to 10, or the gate drive circuit according to claim 12.

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