Shift register, gate driving circuit, and display device

Abstract

The present disclosure relates to the technical field of display, and provides a shift register, a gate driving circuit, and a display device. The shift register of the present disclosure comprises: an input sub-circuit configured to, in response to an input signal of a signal input end, pre-charge a pull-up node by means of the input signal; an output sub-circuit configured to output a clock signal by means of a signal output end in response to the potential of the pull-up node; a pull-down control sub-circuit configured to respond to a power supply voltage, and control the potential of a pull-down node by means of the power supply voltage; a first pull-down sub-circuit configured to, in response to the potential of the pull-up node and by means of a first non-working level signal, pull down the potential of the pull-down node electrically connected to the first pull-down sub-circuit; and at least one first auxiliary sub-circuit configured to, when a touch phase ends and under the control of a first control signal, discharge the pull-down node electrically connected to the at least one first auxiliary sub-circuit.

Description

Shift register, gate drive circuit and display device Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a shift register, a gate driving circuit, and a display device. Background Art

[0002] With the continuous development of display technology, the development of displays in recent years has gradually shown a trend of high integration and low cost. One of the very important technologies is the mass production of GOA (Gate Driver on Array) technology. GOA technology is used to integrate the TFT (Thin Film Transistor) gate switch circuit on the array substrate of the display panel to form a scan drive for the display panel, thereby eliminating the gate driver integrated circuit part. This not only reduces product costs in terms of material costs and manufacturing processes, but also allows the display panel to achieve a beautiful design with symmetry on both sides and narrow borders. At the same time, since the gate direction bonding process can be eliminated, it is also beneficial to improve production capacity and yield. This gate switch circuit integrated on the array substrate using GOA technology is also called a GOA circuit or a shift register circuit. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art and provides a shift register, a gate drive circuit and a display device.

[0004] An embodiment of the present disclosure provides a shift register, which includes an input subcircuit, an output subcircuit, at least one pull-down control subcircuit, and at least one first pull-down subcircuit;

[0005] The input sub-circuit is configured to precharge a pull-up node in response to an input signal at a signal input terminal by the input signal; the pull-up node is a connection node between the input sub-circuit, the output sub-circuit, and the first pull-down sub-circuit;

[0006] The output sub-circuit is configured to output the clock signal through the signal output terminal in response to the potential of the pull-up node;

[0007] The pull-down control subcircuit is configured to respond to a power supply voltage and control the potential of the pull-down node through the power supply voltage; one pull-down control subcircuit is connected to one first pull-down subcircuit, and a connection node between the two is the pull-down node;

[0008] The first pull-down sub-circuit is configured to pull down the potential of the pull-down node electrically connected thereto through a first non-working level signal in response to the potential of the pull-up node; wherein,

[0009] The shift register further includes at least one first auxiliary sub-circuit, each of the first auxiliary sub-circuits being electrically connected to one of the pull-down nodes; the first auxiliary sub-circuit being configured to discharge the pull-down node electrically connected thereto under the control of a first control signal after the touch phase ends.

[0010] The pull-down control sub-circuit, the first pull-down sub-circuit, and the first auxiliary sub-circuit are all multiple in number, and one pull-down node is electrically connected to one pull-down control sub-circuit, one first pull-down sub-circuit, and one first auxiliary sub-circuit;

[0011] Each of the first auxiliary sub-circuits is electrically connected to the same first control signal terminal, and operates simultaneously under the first control signal received by the first control signal terminal, and discharges the pull-down nodes corresponding to each of the first auxiliary sub-circuits before scanning the current frame.

[0012] The shift register further includes a first global reset subcircuit configured to globally reset the pull-up node through a first non-working level signal under the control of the first global reset signal;

[0013] The global reset signal is multiplexed as the first control signal.

[0014] Wherein, the global reset sub-circuit includes a fifteenth transistor;

[0015] The first electrode of the fifteenth transistor is connected to the pull-up node, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the first global reset signal terminal and each of the first auxiliary sub-circuits.

[0016] Wherein, the first auxiliary sub-circuit includes a seventeenth transistor;

[0017] The first electrode of the seventeenth transistor is connected to one of the pull-down nodes, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the first global reset signal terminal.

[0018] The frame start signal is multiplexed into the first control signal.

[0019] Wherein, the first auxiliary sub-circuit includes a seventeenth transistor;

[0020] The first electrode of the seventeenth transistor is connected to the pull-down node, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the frame start signal terminal.

[0021] The number of the pull-down control sub-circuit, the first pull-down sub-circuit, and the first auxiliary sub-circuit are all two, the number of the pull-down nodes is two, the two pull-down nodes are respectively a first pull-down node and a second pull-down node, and the first pull-down node is electrically connected to one pull-down control sub-circuit, one first pull-down sub-circuit, and one first auxiliary sub-circuit; the second pull-down node is electrically connected to another pull-down control sub-circuit, another first pull-down sub-circuit, and another first auxiliary sub-circuit;

[0022] The potential of the first pull-down node is multiplexed as a first control signal of a first auxiliary sub-circuit, and the second pull-down node is discharged through the first non-working level signal; the potential of the second pull-down node is multiplexed as a first control signal of another first auxiliary sub-circuit, and the first pull-down node is discharged through the first non-working level signal.

[0023] Wherein, the first auxiliary sub-circuit includes a seventeenth transistor;

[0024] The first electrode of the seventeenth transistor in one of the first auxiliary sub-circuits is connected to the first pull-down node, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the second pull-down node; the first electrode of the seventeenth transistor in another of the first auxiliary sub-circuits is connected to the first second pull-down node, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the first pull-down node.

[0025] The shift register further includes a second auxiliary sub-circuit configured to discharge the output of the signal output terminal through a first non-working level signal in response to a touch enable signal.

[0026] Wherein, the second auxiliary sub-circuit includes an eighteenth transistor;

[0027] The first electrode of the eighteenth transistor is connected to the signal output terminal, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the touch enable signal terminal.

[0028] Wherein, the shift register further includes at least one second pull-down sub-circuit, and one of the second pull-down sub-circuits is electrically connected to one of the pull-down nodes;

[0029] The second pull-down sub-circuit is configured to pull down the potential of the pull-down node electrically connected thereto via a first non-operating level signal in response to an input signal.

[0030] Wherein, the second pull-down sub-circuit includes a seventh transistor;

[0031] The first electrode of the seventh transistor is connected to the corresponding pull-down node, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the signal input terminal.

[0032] Wherein, the shift register further includes

[0033] The first reset subcircuit is configured to reset the pull-up node through a first non-working level signal under the control of the reset signal.

[0034] The second reset sub-circuit is configured to reset the signal output terminal through a second non-working level signal under the control of the reset signal.

[0035] Wherein, the first reset sub-circuit includes a second transistor; the second reset sub-circuit includes a fourth transistor;

[0036] The first electrode of the second transistor is connected to the pull-up node, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the reset signal terminal;

[0037] The first electrode of the fourth transistor is connected to the signal output terminal, the second electrode is connected to the second non-working level signal terminal, and the control electrode is connected to the reset signal terminal.

[0038] Wherein, the shift register further includes at least one first noise reduction sub-circuit and at least one second noise reduction sub-circuit; one of the pull-down nodes is electrically connected to one of the first noise reduction sub-circuit and one of the second noise reduction sub-circuit;

[0039] The first noise reduction sub-circuit is configured to reduce noise on the output of the pull-up node through a first non-working level signal under the control of the pull-down node electrically connected thereto;

[0040] The second noise reduction sub-circuit is configured to reduce noise on the output of the signal output terminal through a second non-working level signal under the control of the pull-down node electrically connected thereto.

[0041] Wherein, the first noise reduction sub-circuit includes a tenth transistor; the second noise reduction sub-circuit includes a thirteenth transistor;

[0042] The first electrode of the tenth transistor is connected to the pull-up node, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the corresponding pull-down node;

[0043] The first electrode of the thirteenth transistor is connected to the signal output terminal, the second electrode is connected to the second non-working level signal terminal, and the control electrode is connected to the corresponding pull-down node.

[0044] The shift register further includes a cascade sub-circuit configured to output the clock signal through a cascade signal terminal in response to the potential of the pull-up node.

[0045] Wherein, the cascade sub-circuit includes an eleventh transistor;

[0046] The first electrode of the eleventh transistor is connected to the constant signal terminal, the second electrode is connected to the cascade signal terminal, and the control electrode is connected to the pull-up node.

[0047] The shift register further includes a third noise reduction sub-circuit configured to reduce noise on the output of the cascade signal terminal through a first non-working level signal under the control of the pull-down node electrically connected thereto.

[0048] Wherein, the third noise reduction sub-circuit includes a twelfth transistor;

[0049] The first electrode of the twelfth transistor is connected to the cascade signal terminal, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the corresponding pull-down node.

[0050] The shift register further includes a second global reset sub-circuit configured to discharge the signal output terminal through a first non-working level signal in response to a second global reset signal.

[0051] Wherein, the second global reset sub-circuit includes a fourteenth transistor;

[0052] The first electrode of the fourteenth transistor is connected to the signal output terminal, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the second global reset signal terminal.

[0053] Wherein, the input sub-circuit includes a first transistor;

[0054] The first electrode and the control electrode of the first transistor are both connected to the signal input terminal, and the second electrode is connected to the pull-up node.

[0055] Wherein, the output sub-circuit includes a third transistor and a storage capacitor;

[0056] The first electrode of the third transistor is connected to the clock signal terminal, the second electrode is connected to the signal output terminal and the second terminal of the storage capacitor, and the control electrode is connected to the first terminal of the storage capacitor and the pull-up node.

[0057] Wherein, the pull-down control subcircuit includes a fifth transistor;

[0058] The first electrode of the fifth transistor is connected to the control electrode and the power supply voltage terminal, and the second electrode is connected to the corresponding pull-down node.

[0059] Wherein, the first pull-down sub-circuit includes a sixth transistor;

[0060] The first electrode of the sixth transistor is connected to the corresponding pull-down node, the second electrode is connected to the non-operating voltage end, and the control electrode is connected to the signal input end.

[0061] Wherein, each sub-circuit in the shift register includes at least a thin film transistor, and the thin film transistor is an oxide thin film transistor.

[0062] An embodiment of the present disclosure provides a shift register, which includes an input subcircuit, an output subcircuit, at least one pull-down control subcircuit, and at least one first pull-down subcircuit;

[0063] the input subcircuit configured to precharge the pull-up node by the input signal in response to the input signal at the signal input terminal; a connection node between the input subcircuit, the output subcircuit, and the pull-down subcircuit;

[0064] The output sub-circuit is configured to output the clock signal through the signal output terminal in response to the potential of the pull-up node;

[0065] The pull-down control subcircuit is configured to respond to a power supply voltage and control the potential of the pull-down node through the power supply voltage; one pull-down control subcircuit is connected to one first pull-down subcircuit, and a connection node between the two is the pull-down node;

[0066] The first pull-down sub-circuit is configured to pull down the potential of the pull-down node electrically connected thereto through a first non-working level signal in response to the potential of the pull-up node; wherein,

[0067] The shift register further includes a second auxiliary sub-circuit configured to discharge the output of the signal output terminal through a first non-working level signal in response to a touch enable signal.

[0068] The input subcircuit includes a first transistor; the output subcircuit includes a third transistor and a storage capacitor; the pull-down control subcircuit includes a fifth transistor; the first pull-down subcircuit includes a sixth transistor; and the second auxiliary subcircuit includes an eighteenth transistor.

[0069] The first electrode and the control electrode of the first transistor are both connected to the signal input terminal, and the second electrode is connected to the pull-up node; the first electrode of the third transistor is connected to the clock signal terminal, the second electrode is connected to the signal output terminal and the second terminal of the storage capacitor, and the control electrode is connected to the first terminal of the storage capacitor and the pull-up node; the first electrode of the fifth transistor is connected to its control electrode and the power supply voltage terminal, and the second electrode is connected to the corresponding pull-down node; the first electrode of the sixth transistor is connected to the corresponding pull-down node, the second electrode is connected to the non-working voltage terminal, and the control electrode is connected to the signal input terminal; the first electrode of the eighteenth transistor is connected to the signal output terminal, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the touch enable signal terminal.

[0070] An embodiment of the present disclosure provides a gate driving circuit, which includes any of the shift registers described above.

[0071] An embodiment of the present disclosure provides a display device including the above-mentioned gate driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] FIG1 is a circuit diagram of an exemplary shift register.

[0073] FIG2 is a timing diagram corresponding to the shift register shown in FIG1 .

[0074] Figure 3 is a simulation diagram of the touch noise defect at the end of the scan of a WQXGA product.

[0075] FIG4 is a circuit diagram of a first exemplary shift register according to an embodiment of the present disclosure.

[0076] FIG5 is a timing diagram corresponding to the shift register shown in FIG4 .

[0077] FIG6 is a circuit diagram of a second exemplary shift register according to an embodiment of the present disclosure.

[0078] FIG7 is a timing diagram corresponding to the shift register shown in FIG6 .

[0079] FIG8 is a circuit diagram of a shift register according to a third example of an embodiment of the present disclosure.

[0080] FIG9 is a circuit diagram of a shift register according to a fourth example of an embodiment of the present disclosure.

[0081] FIG10 is a circuit diagram of a shift register according to a fifth example of an embodiment of the present disclosure.

[0082] FIG11 is a timing diagram corresponding to the shift register shown in FIG10 . DETAILED DESCRIPTION

[0083] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0084] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0085] It should be noted that the transistors used in the embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present invention, in order to distinguish the source and drain of the transistor, one of the poles is called the first pole, the other pole is called the second pole, and the gate is called the control pole. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. The following embodiments are explained with N-type transistors. When an N-type transistor is used, the first pole is the source of the N-type transistor, and the second pole is the drain of the N-type transistor. When the gate input is a high level, the source and drain are turned on, and the P-type is the opposite. It can be imagined that the use of P-type transistors is something that a person skilled in the art can easily think of without creative work, and therefore it is also within the scope of protection of the embodiments of the present invention.

[0086] Among them, since the transistor used in the embodiment of the present invention is an N-type transistor, the working level signal in the embodiment of the present invention refers to a high level signal, and the first low level signal is a first low level signal; the corresponding working level end is a high level signal end, and the low level end is a first low level signal end.

[0087] Typically, a display panel includes multiple gate lines and multiple data lines. The gate lines and data lines intersect to define multiple pixel regions, each of which is provided with pixel cells. The structure of the display panel is described below using the example of the direction in which each gate line extends as a row direction and the direction in which each data line extends as a column direction. When the display panel is driven to display, gate scan signals are written to the gate lines row by row, and data voltage signals are written to the data lines simultaneously, so that the pixel cells in the display panel are illuminated row by row, depending on the image to be displayed.

[0088] Among them, the gate scan signal is provided by the gate drive circuit, and the data voltage signal is provided by the source drive circuit; in the related technology, the gate drive circuit can be integrated into the gate drive chip, and the source drive circuit can be integrated into the source drive chip; and currently, in order to reduce the number of chips and achieve a narrow frame or no frame, a technology for integrating the gate drive circuit on an array substrate (Gate On Array; GOA) is provided; wherein, the gate drive circuit includes a plurality of cascaded shift registers integrated on the array substrate, each shift register is connected to a gate line one-to-one, and is used to provide a gate scan signal to the gate line connected thereto.

[0089] In order to make it clearer how the shift register unit realizes the output of the gate scanning signal, a specific example of the shift register unit is used for explanation below.

[0090] Figure 1 is a circuit diagram of an exemplary shift register. As shown in Figure 1 , the shift register includes an input subcircuit 1, an output subcircuit 3, a cascade subcircuit 4, a first reset subcircuit 21, a second reset subcircuit 22, two pull-down control subcircuits 5 / 5', two first pull-down subcircuits 6 / 6', two second pull-down subcircuits 7 / 7', two first noise reduction subcircuits 8 / 8', two second noise reduction subcircuits 9 / 9', two third noise reduction subcircuits 10 / 10', a first global reset subcircuit 11, and a second global reset subcircuit 12. Input subcircuit 1 is configured to precharge a pull-up node PU in response to an input signal at a signal input terminal Input. Pull-up node PU is a connection node between input subcircuit 1, output subcircuit 3, and the two first pull-down subcircuits 6 / 6'. Output subcircuit 3 is configured to output a clock signal through a signal output terminal G_out in response to the potential of pull-up node PU. The first reset subcircuit 21 is configured to reset the pull-up node PU via a first low-level signal under the control of a reset signal. The second reset subcircuit 22 is configured to reset the output of the signal output terminal G_out via a second low-level signal under the control of a reset signal. The cascade subcircuit 4 is configured to output the clock signal via the cascade signal terminal OC in response to the potential of the pull-up node PU. The pull-down control subcircuit is configured to respond to the power supply voltage and control the potential of the pull-down node via the power supply voltage; one pull-down control subcircuit is connected to one first pull-down subcircuit, and the connection node between the two is a pull-down node. The first pull-down subcircuit is configured to pull down the potential of the pull-down node electrically connected thereto via a first low-level signal in response to the potential of the pull-up node PU. The second pull-down subcircuit is configured to pull down the potential of the pull-down node electrically connected thereto via a first low-level signal in response to an input signal. The first noise reduction subcircuit is configured to reduce the noise of the output of the pull-up node PU via a first low-level signal under the control of the pull-down node connected thereto. The second noise reduction sub-circuit is configured to reduce noise on the output of the signal output terminal G_out via a second low-level signal under the control of the pull-down node connected thereto. The third noise reduction sub-circuit is configured to reduce noise on the output of the cascade signal terminal OC under the control of the pull-down node connected thereto. The first global reset sub-circuit 11 is configured to discharge the pull-up node PU via a first low-level signal in response to the first global reset signal. The second global reset sub-circuit 12 is configured to discharge the output of the signal output terminal G_out via a second low-level signal in response to the second global reset signal.

[0091] Among them, there are two pull-down control sub-circuits 5 / 5', two first pull-down sub-circuits 6 / 6', two second pull-down sub-circuits 7 / 7', two first noise reduction sub-circuits 8 / 8', two second noise reduction sub-circuits 9 / 9', and two third noise reduction sub-circuits 10 / 10'. The pull-down control sub-circuit 5 is correspondingly connected to one first pull-down sub-circuit 6 and one second pull-down sub-circuit 7, and the connection node between the three is the first pull-down node PD1. The pull-down control sub-circuit 5' is correspondingly connected to one first pull-down sub-circuit 6' and one second pull-down sub-circuit 7', and the connection node between the three is the first pull-down node PD1PD2. The first pull-down node PD1 is connected to one first noise reduction sub-circuit 8, one second noise reduction sub-circuit 9, and one third noise reduction sub-circuit 10. The second pull-down node PD2 is connected to another first noise reduction sub-circuit 8', another second noise reduction sub-circuit 9', and another third noise reduction sub-circuit 10'. The two pull-down control subcircuits 5 / 5' in the shift register have identical structures and functions, except that when the shift register is operating, the two pull-down control subcircuits 5 / 5' operate in time-sharing mode. That is, the timing of the control signals controlling the two pull-down control subcircuits 5 / 5' is opposite. Similarly, the two first pull-down subcircuits 6 / 6' have identical structures and functions and operate in time-sharing mode; the two second pull-down subcircuits 7 / 7' have identical structures and functions and operate in time-sharing mode; the two first noise reduction subcircuits 8 / 8' have identical structures and functions and operate in time-sharing mode; the two second noise reduction subcircuits 9 / 9' have identical structures and functions and operate in time-sharing mode; and the two third noise reduction subcircuits 10 / 10' have identical structures and functions and operate in time-sharing mode. The first global reset signal can be a pre-frame start signal to discharge the pull-up node PU before the current frame scan.

[0092] Specifically, the input subcircuit 1 includes a first transistor M1. The first reset subcircuit 21 includes a second transistor M2. The second reset subcircuit 11 includes a fourth transistor M4. The output subcircuit 3 includes a third transistor M3 and a storage capacitor C1. The cascade subcircuit 4 includes an eleventh transistor M11. The first global reset subcircuit 11 includes a fifteenth transistor M15. The second global reset subcircuit 12 includes a fourteenth transistor M14. Each pull-down control subcircuit includes a fifth transistor; the fifth transistors in the two pull-down control subcircuits 5 / 5' are represented by M5 and M5', respectively. Each first pull-down subcircuit includes a sixth transistor; the sixth transistors in the two first pull-down subcircuits 6 / 6' are represented by M6 and M6', respectively. Each second pull-down subcircuit includes a sixth transistor; the seventh transistors in the two second pull-down subcircuits 7 / 7' are represented by M7 and M7', respectively. Each first noise reduction subcircuit includes a tenth transistor; the tenth transistors in the two first noise reduction subcircuits 8 / 8' are represented by M10 and M10', respectively. Each second noise reduction sub-circuit includes a thirteenth transistor, and the thirteenth transistors in the two second noise reduction sub-circuits 9 / 9' are represented by M13 and M13' respectively. Each third noise reduction sub-circuit includes a tenth transistor, and the twelfth transistors in the two third noise reduction sub-circuits 10 / 10' are represented by M12 and M12' respectively.

[0093] Furthermore, the gate and source of M1 are connected to the signal input terminal Input, and the drain of M1 is connected to the pull-up node PU. The gate of M2 is connected to the reset signal terminal Reset, the source of M2 is connected to the pull-up node PU, and the drain of M2 is connected to the first low-level signal terminal LVGL. The gate of M4 is connected to the reset signal terminal Reset, the source of M4 is connected to the signal output terminal G_out, and the drain of M4 is connected to the second low-level signal terminal VGL. The gate of M3 is connected to the pull-up node PU, the source of M3 is connected to the clock signal terminal CLK, and the drain of M3 is connected to the signal output terminal G_out. The gate of M11 is connected to the pull-up node PU, the source of M11 is connected to the clock signal terminal CLK, and the drain of M11 is connected to the cascade signal terminal OC. The first end of C1 is connected to the pull-up node PU, and the second end of C1 is connected to the signal output terminal G_out. The gate and source of M5 are both connected to the first power supply voltage terminal VDD1, and the drain of M5 is connected to the first pull-down node PD1. The gate and source of M5' are both connected to the second power supply voltage terminal VDD2, and the drain of M5 is connected to the second pull-down node PD2. The gate of M6 is connected to the pull-up node PU, the source of M6 is connected to the first pull-up node PU, and the drain of M6 is connected to the first low-level signal terminal LVGL. The gate of M6' is connected to the pull-up node PU, the source of M6' is connected to the second pull-up node PU, and the drain of M6' is connected to the first low-level signal terminal LVGL. The gate of M7 is connected to the signal input terminal Input, the source of M7 is connected to the first pull-up node PU, and the drain of M7 is connected to the first low-level signal terminal LVGL. The gate of M7' is connected to the signal input terminal Input, the source of M7' is connected to the second pull-up node PU, and the drain of M7' is connected to the first low-level signal terminal LVGL. The gate of M10 is connected to the first pull-down node PD1, the source of M10 is connected to the pull-up node PU, and the drain of M10 is connected to the first low-level signal terminal LVGL. The gate of M10' is connected to the second pull-down node PD2, the source of M10' is connected to the pull-up node PU, and the drain of M10' is connected to the first low-level signal terminal LVGL. The gate of M12 is connected to the first pull-down node PD1, the source of M12 is connected to the cascade signal terminal OC, and the drain of M12 is connected to the first low-level signal terminal LVGL. The gate of M12' is connected to the second pull-down node PD2, the source of M12' is connected to the cascade signal terminal OC, and the drain of M12' is connected to the first low-level signal terminal LVGL. The gate of M13 is connected to the first pull-down node PD1, the source of M13 is connected to the signal output terminal G_out, and the drain of M13 is connected to the second low-level signal terminal VGL. The gate of M13' is connected to the second pull-down node PD2, the source of M13' is connected to the signal output terminal G_out, and the drain of M13' is connected to the first low-level signal terminal LVGL. The gate of M14 is connected to the second global reset signal terminal Total_RST, the source of M14 is connected to the signal output terminal G_out, and the drain of M14 is connected to the second low level signal terminal VGL.The gate of M15 is connected to the first global reset signal terminal Total_RST1 , the source of M15 is connected to the signal output terminal G_out, and the drain of M15 is connected to the first low-level signal terminal LVGL.

[0094] FIG2 is a timing diagram corresponding to the shift register shown in FIG1 ; in conjunction with FIG2 , the operation of the shift register may specifically include the following stages:

[0095] In the discharge stage, before the frame, that is, before display, a high-level signal is input to the first global reset signal terminal Total_RST1 and the second global reset signal terminal Total_RST, the fourteenth transistor and the fifteenth transistor are turned on, and the pull-up node PU and the signal output terminal G_out are discharged through the first low-level signal input by the first low-level signal terminal LVGL to prevent residual charge on the pull-up node PU and the signal output terminal G_out from causing display abnormalities.

[0096] In the input stage, a high-level signal is input to the signal input terminal Input, M1 is turned on, and the pull-up node PU is pulled high by the high-level signal, and C1 is charged. At the same time, M6 and M6', M7 and M7' are all turned on, pulling down the first pull-down node PD1 and the second pull-down node PD2 to avoid affecting the potential of the pull-up node PU.

[0097] In the output stage, since the pull-up node PU is pulled high in the input stage, M3 and M13 are turned on, and the high-level signal input by the clock signal terminal CLK is output to the gate line connected thereto through the signal output terminal G_out. At the same time, the cascade signal terminal OC outputs the same signal as the signal output terminal G_out, that is, a high-level signal is output to the pull-up reset signal terminal Reset of the previous stage shift register unit and the signal input terminal Input of the next stage shift register unit.

[0098] During the reset phase, a high-level signal is input to the reset signal terminal Reset, turning on M2 and M4. The first low-level signal input to the first low-level signal terminal LVGL pulls down the potentials of the pull-up node PU and the signal output terminal G_out, thereby resetting them. Simultaneously, the pull-down control node and the first pull-down node PD1 are both high-level signals, turning on M10, M13, and M12, respectively, to reduce noise on the outputs of the pull-up node PU, the signal output terminal G_out, and the cascade signal terminal OC. This continues until the next frame scan begins, when the potential of the pull-up node PU is pulled high.

[0099] For the above-mentioned 19T1C shift register, the thin film transistors therein can be oxide thin film transistors. Since the two pull-down control sub-circuits work in time-sharing mode, the VDD1 and VDD2 signals corresponding to the first power supply voltage terminal VDD1 and the second power supply voltage terminal VDD2 connected to the two pull-down control sub-circuits can be switched during the blanking phase (Blanking) between displaying two frames of images, replacing the single-channel VDD DC noise reduction. Accordingly, the first pull-down node PD1 and the second pull-down node PD2 signals follow the switching of the VDD1 and VDD2 signals to switch between high and low levels. There are two discharge paths for the first pull-down node PD1 and the second pull-down node PD2: 1. When the current row signal input terminal Input is written with a high-level signal, discharge through M7 and M7'; 2. When the current row pull-up node PU is at a high level, discharge through M6 and M6'. Both discharge methods are for discharging the pull-down node of this bank when the GOA of this bank is working. For a shift register composed of oxide thin film transistors, where the Ioff of the thin film transistors is low, if the above two methods are not adopted, the high-level pull-down node will take a long time to discharge by natural dissipation.

[0100] For TDDI products, the IC typically collects raw data from the AA area by displaying a modulation waveform on a fixed row. For example, a WQXGA product (resolution 2560*1600) has 2560 rows. When the gate drive circuit scans row X1, it collects the raw data for the entire surface. In this case, the 1st through X1st shift registers operate one by one. When the gate drive circuit scans row X2, it collects the raw data for the entire surface. In this case, the 1st through X2nd shift registers operate one by one. This means that during the first acquisition, the signal input terminals Input and pull-up nodes PU of rows 1 to X1 have been raised, and the charge of the pull-down nodes can be discharged through the above two methods; during the second acquisition, the signal input terminals Input and pull-up nodes PU of rows X1 to X2 have been raised, and the charge of the pull-down nodes can be discharged through the above two methods; the signal input terminals Input and pull-up nodes PU of rows X2 to 2560 have not been raised, and the charge of the pull-down nodes cannot be discharged.

[0101] It should be noted that, referring to Figure 2, during the touch stage, the clock signal written to the clock signal terminal CLK is different from the clock signal written during normal display. Since the display panel is an invalid display during the touch stage, the effective level of the clock signal written to the shift register during the touch stage is lower than the effective level of the clock signal written during normal display.

[0102] Take the example of the first power supply voltage switching from a high level to a low level and the second power supply voltage switching from a low level to a high level. In the first frame after the switch, since the touch stage finishes collecting Rawdata, the gate drive circuit only scans row X2, that is, the first pull-down node PD1 of each shift register corresponding to rows X2 to 2560 is not discharged. Due to the high Ion characteristic of the oxide thin-film transistor product, the second pull-down node PD2 rises rapidly, resulting in an abnormal state where both the first pull-down node PD1 and the second pull-down node PD2 are high. Thereafter, when the scan reaches the abnormal row, the signal input terminal Input and the pull-up node PU arrive normally, discharging the abnormal first pull-down node PD1. The first pull-down node PD1 and the second pull-down node PD2 return from the abnormal two-high state to the normal one-high-one-low state. Therefore, in the second frame after the switch and subsequent frames, the first pull-down node PD1 and the second pull-down node PD2 are in the normal one-high-one-low state. Therefore, since the first pull-down node PD1 and the second pull-down node PD2 are both high in the first frame after switching, which is different from the state in which the first pull-down node PD1 and the second pull-down node PD2 are high and low in the second frame and subsequent frames after switching, the signal output terminal G_out inconsistently reflects the VGL Modulation waveform, causing differences in the original data collected by the IC and generating touch noise defects.

[0103] Specifically, as shown in Figure 3 (a), there is no noise at the beginning of the scan (near the first row) (-100 < value < 100, uniform distribution); noise exists at the end of the scan (near the 2560th row) (value < -200, uniform green). As shown in Figure 3 (b), the difference between the raw data is the noise level. There is a sudden change in the raw data during each VDD1 and VDD2 switching cycle, that is, there is a large noise fluctuation during each VDD1 / 2 switching cycle; the VDD1 and VDD2 switching cycle is 240 frames. Among them, point1, point2, point3, and point4 represent four points at the end of the scan (DP side). The raw data values ​​of point1, point2, point3, and point4 all show periodic changes consistent with the VDD1 and VDD2 switching cycle. In other words, the noise (difference in raw data) is related to the switching between VDD1 and VDD2.

[0104] In response to the above technical problems, the present disclosure provides the following technical solutions.

[0105] Before describing the embodiments of the present disclosure, it should be noted that the number of the pull-down control sub-circuit, the first pull-down sub-circuit, the first noise reduction sub-circuit, the second noise reduction sub-circuit and the third noise reduction sub-circuit in the embodiments of the present disclosure can be 1, or can be 2 or more. In the embodiments of the present disclosure, only the number of the pull-down control sub-circuit, the first pull-down sub-circuit, the first noise reduction sub-circuit, the second noise reduction sub-circuit and the third noise reduction sub-circuit are 2; the timing of the first global reset signal and the second global reset signal is the same; the thin film transistors in each sub-circuit are explained using oxide thin film transistors as an example.

[0106] First example: Figure 4 is a circuit diagram of the shift register of the first example of the embodiment of the present disclosure; as shown in Figure 4, the shift register includes an input sub-circuit 1, an output sub-circuit 3, two pull-down control sub-circuits 5 / 5', two first pull-down sub-circuits 6 / 6', and two first auxiliary sub-circuits 13 / 13'. The input sub-circuit 1 is configured to respond to the input signal of the signal input terminal Input and pre-charge the pull-up node PU through the input signal; the pull-up node PU is the connection node between the input sub-circuit 1, the output sub-circuit 3, and the first pull-down sub-circuit 6 / 6'; the output sub-circuit 3 is configured to respond to the potential of the pull-up node PU and output the clock signal through the signal output terminal G_out; the pull-down control sub-circuit is configured to respond to the power supply voltage and control the potential of the pull-down node through the power supply voltage; a pull-down control sub-circuit is connected to a first pull-down sub-circuit, and the connection node between the two is a pull-down node; the first pull-down sub-circuit is configured to respond to the potential of the pull-up node PU and pull down the potential of the pull-down node electrically connected to it through a first low-level signal; the first auxiliary sub-circuit is configured to discharge the pull-down node electrically connected to it under the control of the first control signal after the touch phase ends.

[0107] In this example, by adding a first auxiliary sub-circuit, after the touch stage of the display panel ends and before the current frame scan, the first auxiliary sub-circuit is controlled by a first control signal to discharge the pull-down node, thereby effectively avoiding output abnormalities caused by differences in the pull-down node potentials of each shift register.

[0108] Since in this example there are two pull-down control sub-circuits and two first pull-down sub-circuits, there are also two pull-down nodes, namely the first pull-down node PD1 and the second pull-down node PD2. The power supply voltage terminal to which the pull-down control sub-circuit electrically connected to the first pull-down node PD1 is connected is referred to as the first power supply voltage terminal VDD1, and the power supply voltage terminal to which the pull-down control sub-circuit electrically connected to the second pull-down node PD2 is connected is referred to as the second power supply voltage terminal VDD2.

[0109] In some examples, the two first auxiliary sub-circuits 13 / 13' can be connected to the same first control signal terminal Total_RST2, that is, the two first auxiliary sub-circuits 13 / 13' can be controlled simultaneously. For example, before the current frame scan, the first control signal input through the first control signal terminal Total_RST2 controls the two first auxiliary sub-circuits 13 / 13' to work simultaneously, discharging the first pull-down node PD1 and the second pull-down node PD2 respectively.

[0110] In some examples, the shift register may also include a cascade subcircuit 4, a first reset subcircuit 21, a second reset subcircuit 22, two second pull-down subcircuits 7 / 7', two first noise reduction subcircuits 8 / 8', two second noise reduction subcircuits 9 / 9' and two third noise reduction subcircuits 10 / 10', a first global reset subcircuit 11 and a second global reset subcircuit 12.

[0111] The first reset subcircuit 21 is configured to reset the pull-up node PU via a first low-level signal under the control of a reset signal. The second reset subcircuit 22 is configured to reset the signal output terminal G_out via a second low-level signal under the control of a reset signal. The cascade subcircuit 4 is configured to output the clock signal via the cascade signal terminal OC in response to the potential of the pull-up node PU. The second pull-down subcircuit is configured to pull down the potential of the pull-down node electrically connected thereto via a first low-level signal in response to an input signal. The first noise reduction subcircuit is configured to perform noise reduction on the output of the pull-up node PU under the control of the pull-down node connected thereto. The second noise reduction subcircuit is configured to perform noise reduction on the output of the signal output terminal G_out under the control of the pull-down node connected thereto. The third noise reduction subcircuit is configured to perform noise reduction on the output of the cascade signal terminal OC under the control of the pull-down node connected thereto. The first global reset subcircuit 11 is configured to discharge the pull-up node PU via a first low-level signal in response to the first global reset signal. The second global reset sub-circuit 12 is configured to discharge the output of the signal output terminal G_out through a second low-level signal in response to the second global reset signal.

[0112] Continuing with Figure 4 , two pull-down control sub-circuits 5 / 5', two first pull-down sub-circuits 6 / 6', two second pull-down sub-circuits 7 / 7', two first noise reduction sub-circuits 8 / 8', two second noise reduction sub-circuits 9 / 9', and two third noise reduction sub-circuits 10 / 10' are connected to a first pull-down sub-circuit and a second pull-down sub-circuit, with the connection node being the first pull-down node PD1. The pull-down control sub-circuits are connected to a first pull-down sub-circuit and a second pull-down sub-circuit, with the connection node being the first pull-down node PD1. The first pull-down node PD1 connects a first noise reduction sub-circuit, a second noise reduction sub-circuit, and a third noise reduction sub-circuit. The second pull-down node PD2 connects another first noise reduction sub-circuit, another second noise reduction sub-circuit, and another third noise reduction sub-circuit. The two pull-down control subcircuits 5 / 5' in the shift register have identical structures and functions, except that when the shift register is operating, the two pull-down control subcircuits 5 / 5' operate in time-sharing mode. That is, the timing of the control signals controlling the two pull-down control subcircuits 5 / 5' is opposite. Similarly, the two first pull-down subcircuits 6 / 6' have identical structures and functions and operate in time-sharing mode; the two second pull-down subcircuits 7 / 7' have identical structures and functions and operate in time-sharing mode; the two first noise reduction subcircuits 8 / 8' have identical structures and functions and operate in time-sharing mode; the two second noise reduction subcircuits 9 / 9' have identical structures and functions and operate in time-sharing mode; and the two third noise reduction subcircuits 10 / 10' have identical structures and functions and operate in time-sharing mode. The first global reset signal can be a pre-frame start signal to discharge the pull-up node PU before the current frame scan.

[0113] Specifically, the input subcircuit 1 includes a first transistor M1. The first reset subcircuit 21 includes a second transistor M2. The second reset subcircuit 22 includes a fourth transistor M4. The output subcircuit 3 includes a third transistor M3 and a storage capacitor C1. The cascade subcircuit 4 includes an eleventh transistor M11. The first global reset subcircuit 112 includes a fifteenth transistor M15. The second global reset subcircuit 122 includes a fourteenth transistor M14. Each pull-down control subcircuit includes a fifth transistor; the fifth transistors in the two pull-down control subcircuits 5 / 5'5 / 5' are represented by M5 and M5', respectively. Each first pull-down subcircuit includes a sixth transistor; the sixth transistors in the two first pull-down subcircuits 6 / 6'6 / 6' are represented by M6 and M6', respectively. Each first pull-down subcircuit includes a sixth transistor; the seventh transistors in the two second pull-down subcircuits 7 / 7' are represented by M7 and M7', respectively. Each first noise reduction sub-circuit includes a tenth transistor, with the tenth transistor in the two first noise reduction sub-circuits 8 / 8' being represented by M10 and M10', respectively. Each second noise reduction sub-circuit includes a thirteenth transistor, with the thirteenth transistor in the two second noise reduction sub-circuits 9 / 9' being represented by M13 and M13', respectively. Each third noise reduction sub-circuit includes a tenth transistor, with the twelfth transistor in the two third noise reduction sub-circuits 10 / 10' being represented by M12 and M12', respectively. Each first auxiliary sub-circuit includes a seventeenth transistor, with the seventeenth transistor in the two first auxiliary sub-circuits 13 / 13' being represented by M17 and M17', respectively.

[0114] Furthermore, the gate and source of M1 are connected to the signal input terminal Input, and the drain of M1 is connected to the pull-up node PU. The gate of M2 is connected to the reset signal terminal Reset, the source of M2 is connected to the pull-up node PU, and the drain of M2 is connected to the first low-level signal terminal LVGL. The gate of M4 is connected to the reset signal terminal Reset, the source of M4 is connected to the signal output terminal G_out, and the drain of M4 is connected to the second low-level signal terminal VGL. The gate of M3 is connected to the pull-up node PU, the source of M3 is connected to the clock signal terminal CLK, and the drain of M3 is connected to the signal output terminal G_out. The gate of M11 is connected to the pull-up node PU, the source of M11 is connected to the clock signal terminal CLK, and the drain of M11 is connected to the cascade signal terminal OC. The first end of C1 is connected to the pull-up node PU, and the second end of C1 is connected to the signal output terminal G_out. The gate and source of M5 are both connected to the first power supply voltage terminal VDD1, and the drain of M5 is connected to the first pull-down node PD1. The gate and source of M5' are both connected to the second power supply voltage terminal VDD2, and the drain of M5 is connected to the second pull-down node PD2. The gate of M6 is connected to the pull-up node PU, the source of M6 is connected to the first pull-up node PU, and the drain of M6 is connected to the first low-level signal terminal LVGL. The gate of M6' is connected to the pull-up node PU, the source of M6' is connected to the second pull-up node PU, and the drain of M6' is connected to the first low-level signal terminal LVGL. The gate of M7 is connected to the signal input terminal Input, the source of M7 is connected to the first pull-up node PU, and the drain of M7 is connected to the first low-level signal terminal LVGL. The gate of M7' is connected to the signal input terminal Input, the source of M7' is connected to the second pull-up node PU, and the drain of M7' is connected to the first low-level signal terminal LVGL. The gate of M10 is connected to the first pull-down node PD1, the source of M10 is connected to the pull-up node PU, and the drain of M10 is connected to the first low-level signal terminal LVGL. The gate of M10' is connected to the second pull-down node PD2, the source of M10' is connected to the pull-up node PU, and the drain of M10' is connected to the first low-level signal terminal LVGL. The gate of M12 is connected to the first pull-down node PD1, the source of M12 is connected to the cascade signal terminal OC, and the drain of M12 is connected to the first low-level signal terminal LVGL. The gate of M12' is connected to the second pull-down node PD2, the source of M12' is connected to the cascade signal terminal OC, and the drain of M12' is connected to the first low-level signal terminal LVGL. The gate of M13 is connected to the first pull-down node PD1, the source of M13 is connected to the signal output terminal G_out, and the drain of M13 is connected to the second low-level signal terminal VGL. The gate of M13' is connected to the second pull-down node PD2, the source of M13' is connected to the signal output terminal G_out, and the drain of M13' is connected to the first low-level signal terminal LVGL. The gate of M14 is connected to the second global reset signal terminal Total_RST, the source of M14 is connected to the signal output terminal G_out, and the drain of M14 is connected to the second low level signal terminal VGL.The gate of M15 is connected to the first global reset signal terminal Total_RST1, the source of M15 is connected to the signal output terminal G_out, and the drain of M15 is connected to the first low-level signal terminal LVGL. The gate of M17 is connected to the first control signal terminal Total_RST2, the source of M17 is connected to the first pull-down node PD1, and the drain of M17 is connected to the first low-level signal terminal LVGL. The gate of M17' is connected to the first control signal terminal Total_RST2, the source of M17' is connected to the first pull-down node PD1, and the drain of M17' is connected to the first low-level signal terminal LVGL.

[0115] FIG5 is a timing diagram corresponding to the shift register shown in FIG4 ; as shown in FIG5 , the operation of the shift register may specifically include the following stages:

[0116] During the discharge phase, before a frame is displayed, a high-level signal is input to the first global reset signal terminal Total_RST1 and the second global reset signal terminal Total_RST. M14 and M15 are turned on, and the pull-up node PU and the signal output terminal G_out are discharged via the first low-level signal input via the first low-level signal terminal LVGL. This prevents residual charge on the pull-up node PU and the signal output terminal G_out from causing display abnormalities. A high-level signal is written to the first control signal terminal Total_RST2. M17 and M17' are turned on, and the first pull-down node PD1 and the second pull-down node PD2 are discharged via the first low-level signal input via the first low-level signal terminal LVGL.

[0117] In the input stage, a high-level signal is input to the signal input terminal Input, M1 is turned on, and the pull-up node PU is pulled high by the high-level signal, and C1 is charged. At the same time, M6 and M6', M7 and M7' are all turned on, pulling down the first pull-down node PD1 and the second pull-down node PD2 to avoid affecting the potential of the pull-up node PU.

[0118] In the output stage, since the pull-up node PU is pulled high in the input stage, M3 and M13 are turned on, and the high-level signal input by the clock signal terminal CLK is output to the gate line connected thereto through the signal output terminal G_out. At the same time, the cascade signal terminal OC outputs the same signal as the signal output terminal G_out, that is, a high-level signal is output to the pull-up reset signal terminal Reset of the previous stage shift register unit and the signal input terminal Input of the next stage shift register unit.

[0119] During the reset phase, a high-level signal is input to the reset signal terminal Reset, turning on M2 and M4. The first low-level signal input to the first low-level signal terminal LVGL pulls down the potentials of the pull-up node PU and the signal output terminal G_out, thereby resetting them. Simultaneously, the pull-down control node and the first pull-down node PD1 are both high-level signals, turning on M10, M13, and M12, respectively, to reduce noise on the outputs of the pull-up node PU, the signal output terminal G_out, and the cascade signal terminal OC. This continues until the next frame scan begins, when the potential of the pull-up node PU is pulled high.

[0120] Second example: Figure 6 is a circuit diagram of the shift register of the second example of the embodiment of the present disclosure; as shown in Figure 6, the structure of this example is roughly the same as that of the first example, with the only difference being that, in this example, the first global reset signal input to the first global reset signal terminal Total_RST1 is multiplexed as the first control signal, that is, the two first auxiliary sub-circuits 13 / 13' are both connected to the first global reset signal terminal Total_RST1.

[0121] Specifically, referring to Figure 6 , the input subcircuit 1 includes a first transistor M1. The first reset subcircuit 21 includes a second transistor M2. The second reset subcircuit includes a fourth transistor M4. The output subcircuit 3 includes a third transistor M3 and a storage capacitor C1. The cascade subcircuit 4 includes an eleventh transistor M11. The first global reset subcircuit 11 includes a fifteenth transistor M15. The second global reset subcircuit 12 includes a fourteenth transistor M14. Each pull-down control subcircuit includes a fifth transistor; the fifth transistors in the two pull-down control subcircuits 5 / 5' are represented by M5 and M5', respectively. Each first pull-down subcircuit includes a sixth transistor; the sixth transistors in the two first pull-down subcircuits 6 / 6' are represented by M6 and M6', respectively. Each first pull-down subcircuit includes a sixth transistor; the seventh transistors in the two second pull-down subcircuits 7 / 7' are represented by M7 and M7', respectively. Each first noise reduction subcircuit includes a tenth transistor; the tenth transistors in the two first noise reduction subcircuits 8 / 8' are represented by M10 and M10', respectively. Each second noise reduction sub-circuit includes a thirteenth transistor, with the thirteenth transistors in the two second noise reduction sub-circuits 9 / 9' being represented by M13 and M13', respectively. Each third noise reduction sub-circuit includes a tenth transistor, with the twelfth transistors in the two third noise reduction sub-circuits 10 / 10' being represented by M12 and M12', respectively. Each first auxiliary sub-circuit includes a seventeenth transistor, with the seventeenth transistors in the two first auxiliary sub-circuits 13 / 13' being represented by M17 and M17', respectively.

[0122] Furthermore, the gate and source of M1 are connected to the signal input terminal Input, and the drain of M1 is connected to the pull-up node PU. The gate of M2 is connected to the reset signal terminal Reset, the source of M2 is connected to the pull-up node PU, and the drain of M2 is connected to the first low-level signal terminal LVGL. The gate of M4 is connected to the reset signal terminal Reset, the source of M4 is connected to the signal output terminal G_out, and the drain of M4 is connected to the second low-level signal terminal VGL. The gate of M3 is connected to the pull-up node PU, the source of M3 is connected to the clock signal terminal CLK, and the drain of M3 is connected to the signal output terminal G_out. The gate of M11 is connected to the pull-up node PU, the source of M11 is connected to the clock signal terminal CLK, and the drain of M11 is connected to the cascade signal terminal OC. The first end of C1 is connected to the pull-up node PU, and the second end of C1 is connected to the signal output terminal G_out. The gate and source of M5 are both connected to the first power supply voltage terminal VDD1, and the drain of M5 is connected to the first pull-down node PD1. The gate and source of M5' are both connected to the second power supply voltage terminal VDD2, and the drain of M5 is connected to the second pull-down node PD2. The gate of M6 is connected to the pull-up node PU, the source of M6 is connected to the first pull-up node PU, and the drain of M6 is connected to the first low-level signal terminal LVGL. The gate of M6' is connected to the pull-up node PU, the source of M6' is connected to the second pull-up node PU, and the drain of M6' is connected to the first low-level signal terminal LVGL. The gate of M7 is connected to the signal input terminal Input, the source of M7 is connected to the first pull-up node PU, and the drain of M7 is connected to the first low-level signal terminal LVGL. The gate of M7' is connected to the signal input terminal Input, the source of M7' is connected to the second pull-up node PU, and the drain of M7' is connected to the first low-level signal terminal LVGL. The gate of M10 is connected to the first pull-down node PD1, the source of M10 is connected to the pull-up node PU, and the drain of M10 is connected to the first low-level signal terminal LVGL. The gate of M10' is connected to the second pull-down node PD2, the source of M10' is connected to the pull-up node PU, and the drain of M10' is connected to the first low-level signal terminal LVGL. The gate of M12 is connected to the first pull-down node PD1, the source of M12 is connected to the cascade signal terminal OC, and the drain of M12 is connected to the first low-level signal terminal LVGL. The gate of M12' is connected to the second pull-down node PD2, the source of M12' is connected to the cascade signal terminal OC, and the drain of M12' is connected to the first low-level signal terminal LVGL. The gate of M13 is connected to the first pull-down node PD1, the source of M13 is connected to the signal output terminal G_out, and the drain of M13 is connected to the second low-level signal terminal VGL. The gate of M13' is connected to the second pull-down node PD2, the source of M13' is connected to the signal output terminal G_out, and the drain of M13' is connected to the first low-level signal terminal LVGL. The gate of M14 is connected to the second global reset signal terminal Total_RST, the source of M14 is connected to the signal output terminal G_out, and the drain of M14 is connected to the second low level signal terminal VGL.The gate of M15 is connected to the first global reset signal terminal Total_RST1, the source of M15 is connected to the signal output terminal G_out, and the drain of M15 is connected to the first low-level signal terminal LVGL. The gate of M17 is connected to the first global reset signal terminal Total_RST1, the source of M17 is connected to the first pull-down node PD1, and the drain of M17 is connected to the first low-level signal terminal LVGL. The gate of M17' is connected to the first global reset signal terminal Total_RST1, the source of M17' is connected to the first pull-down node PD1, and the drain of M17' is connected to the first low-level signal terminal LVGL.

[0123] FIG7 is a timing diagram corresponding to the shift register shown in FIG6 . As shown in FIG7 , the operation of the shift register may specifically include the following stages:

[0124] During the discharge phase, before a frame is displayed, a high-level signal is input to the first global reset signal terminal Total_RST1 and the second global reset signal terminal Total_RST. M14 and M15 are turned on, and the pull-up node PU and the signal output terminal G_out are discharged via the first low-level signal input via the first low-level signal terminal LVGL. This prevents residual charge on the pull-up node PU and the signal output terminal G_out from causing display abnormalities. Simultaneously, due to the high-level signal input to the first global reset signal terminal Total_RST1, M17 and M17' are turned on, and the first pull-down node PD1 and the second pull-down node PD2 are discharged via the first low-level signal input via the first low-level signal terminal LVGL.

[0125] In the input stage, a high-level signal is input to the signal input terminal Input, M1 is turned on, and the pull-up node PU is pulled high by the high-level signal, and C1 is charged. At the same time, M6 and M6', M7 and M7' are all turned on, pulling down the first pull-down node PD1 and the second pull-down node PD2 to avoid affecting the potential of the pull-up node PU.

[0126] In the output stage, since the pull-up node PU is pulled high in the input stage, M3 and M13 are turned on, and the high-level signal input by the clock signal terminal CLK is output to the gate line connected thereto through the signal output terminal G_out. At the same time, the cascade signal terminal OC outputs the same signal as the signal output terminal G_out, that is, a high-level signal is output to the pull-up reset signal terminal Reset of the previous stage shift register unit and the signal input terminal Input of the next stage shift register unit.

[0127] During the reset phase, a high-level signal is input to the reset signal terminal Reset, turning on M2 and M4. The first low-level signal input to the first low-level signal terminal LVGL pulls down the potentials of the pull-up node PU and the signal output terminal G_out, thereby resetting them. Simultaneously, the pull-down control node and the first pull-down node PD1 are both high-level signals, turning on M10, M13, and M12, respectively, to reduce noise on the outputs of the pull-up node PU, the signal output terminal G_out, and the cascade signal terminal OC. This continues until the next frame scan begins, when the potential of the pull-up node PU is pulled high.

[0128] Third Example: FIG8 is a circuit diagram of a shift register according to the third example of the present disclosure. As shown in FIG8 , the structure of this example is substantially the same as that of the first example, differing only in that the frame-start signal in the gate drive circuit is used as the first control signal. For example, the input signals of the first through fourth shift registers in the gate drive circuit are provided by the frame-start signal terminal STV. When the input signals of the first through fourth shift registers are written high, the first auxiliary sub-circuits in each shift register stage will operate, pulling down the first pull-down node PD1 and the second pull-down node PD2 to discharge. In other words, the first auxiliary sub-circuit of the shift register in this example is connected to the frame-start signal terminal STV.

[0129] Specifically, referring to Figure 8 , the input subcircuit 1 includes a first transistor M1. The first reset subcircuit 21 includes a second transistor M2. The second reset subcircuit 22 includes a fourth transistor M4. The output subcircuit 3 includes a third transistor M3 and a storage capacitor C1. The cascade subcircuit 4 includes an eleventh transistor M11. The first global reset subcircuit 11 includes a fifteenth transistor M15. The second global reset subcircuit 12 includes a fourteenth transistor M14. Each pull-down control subcircuit includes a fifth transistor; the fifth transistors in the two pull-down control subcircuits 5 / 5' are represented by M5 and M5', respectively. Each first pull-down subcircuit includes a sixth transistor; the sixth transistors in the two first pull-down subcircuits 6 / 6' are represented by M6 and M6', respectively. Each first pull-down subcircuit includes a sixth transistor; the seventh transistors in the two second pull-down subcircuits 7 / 7' are represented by M7 and M7', respectively. Each first noise reduction subcircuit includes a tenth transistor; the tenth transistors in the two first noise reduction subcircuits 8 / 8' are represented by M10 and M10', respectively. Each second noise reduction sub-circuit includes a thirteenth transistor, with the thirteenth transistors in the two second noise reduction sub-circuits 9 / 9' being represented by M13 and M13', respectively. Each third noise reduction sub-circuit includes a tenth transistor, with the twelfth transistors in the two third noise reduction sub-circuits 10 / 10' being represented by M12 and M12', respectively. Each first auxiliary sub-circuit includes a seventeenth transistor, with the seventeenth transistors in the two first auxiliary sub-circuits 13 / 13' being represented by M17 and M17', respectively.

[0130] Furthermore, the gate and source of M1 are connected to the signal input terminal Input, and the drain of M1 is connected to the pull-up node PU. The gate of M2 is connected to the reset signal terminal Reset, the source of M2 is connected to the pull-up node PU, and the drain of M2 is connected to the first low-level signal terminal LVGL. The gate of M4 is connected to the reset signal terminal Reset, the source of M4 is connected to the signal output terminal G_out, and the drain of M4 is connected to the second low-level signal terminal VGL. The gate of M3 is connected to the pull-up node PU, the source of M3 is connected to the clock signal terminal CLK, and the drain of M3 is connected to the signal output terminal G_out. The gate of M11 is connected to the pull-up node PU, the source of M11 is connected to the clock signal terminal CLK, and the drain of M11 is connected to the cascade signal terminal OC. The first end of C1 is connected to the pull-up node PU, and the second end of C1 is connected to the signal output terminal G_out. The gate and source of M5 are both connected to the first power supply voltage terminal VDD1, and the drain of M5 is connected to the first pull-down node PD1. The gate and source of M5' are both connected to the second power supply voltage terminal VDD2, and the drain of M5 is connected to the second pull-down node PD2. The gate of M6 is connected to the pull-up node PU, the source of M6 is connected to the first pull-up node PU, and the drain of M6 is connected to the first low-level signal terminal LVGL. The gate of M6' is connected to the pull-up node PU, the source of M6' is connected to the second pull-up node PU, and the drain of M6' is connected to the first low-level signal terminal LVGL. The gate of M7 is connected to the signal input terminal Input, the source of M7 is connected to the first pull-up node PU, and the drain of M7 is connected to the first low-level signal terminal LVGL. The gate of M7' is connected to the signal input terminal Input, the source of M7' is connected to the second pull-up node PU, and the drain of M7' is connected to the first low-level signal terminal LVGL. The gate of M10 is connected to the first pull-down node PD1, the source of M10 is connected to the pull-up node PU, and the drain of M10 is connected to the first low-level signal terminal LVGL. The gate of M10' is connected to the second pull-down node PD2, the source of M10' is connected to the pull-up node PU, and the drain of M10' is connected to the first low-level signal terminal LVGL. The gate of M12 is connected to the first pull-down node PD1, the source of M12 is connected to the cascade signal terminal OC, and the drain of M12 is connected to the first low-level signal terminal LVGL. The gate of M12' is connected to the second pull-down node PD2, the source of M12' is connected to the cascade signal terminal OC, and the drain of M12' is connected to the first low-level signal terminal LVGL. The gate of M13 is connected to the first pull-down node PD1, the source of M13 is connected to the signal output terminal G_out, and the drain of M13 is connected to the first low-level signal terminal LVGL. The gate of M13' is connected to the second pull-down node PD2, the source of M13' is connected to the signal output terminal G_out, and the drain of M13' is connected to the second low-level signal terminal VGL. The gate of M14 is connected to the second global reset signal terminal Total_RST, the source of M14 is connected to the signal output terminal G_out, and the drain of M14 is connected to the second low level signal terminal VGL.The gate of M15 is connected to the first global reset signal terminal Total_RST1, the source of M15 is connected to the signal output terminal G_out, and the drain of M15 is connected to the first low-level signal terminal LVGL. The gate of M17 is connected to the frame-start signal terminal STV, the source of M17 is connected to the first pull-down node PD1, and the drain of M17 is connected to the first low-level signal terminal LVGL. The gate of M17' is connected to the frame-start signal terminal STV, the source of M17' is connected to the first pull-down node PD1, and the drain of M17' is connected to the first low-level signal terminal LVGL.

[0131] As shown in FIG7 , the operation of the shift register may specifically include the following stages:

[0132] In the discharge stage, before the frame, that is, before display, a high-level signal is input to the first global reset signal terminal Total_RST1 and the second global reset signal terminal Total_RST, M14 and M15 are turned on, and the pull-up node PU and the signal output terminal G_out are discharged through the first low-level signal input by the first low-level signal terminal LVGL to prevent residual charge on the pull-up node PU and the signal output terminal G_out from causing display abnormalities.

[0133] During the input phase, a high-level signal is input to the signal input terminal Input, turning M1 on. This high-level signal pulls up the pull-up node PU and charges C1. Simultaneously, M6 and M6', as well as M7 and M7', are turned on, pulling down the first pull-down node PD1 and the second pull-down node PD2 to avoid affecting the potential of the pull-up node PU. Simultaneously, a high-level signal is input to the signal input terminal Input (i.e., the frame start signal terminal STV of the first to fourth stage shift registers), causing M17 and M17' to turn on. This discharges the first pull-down node PD1 and the second pull-down node PD2 via the first low-level signal input from the first low-level signal terminal LVGL.

[0134] In the output stage, since the pull-up node PU is pulled high in the input stage, M3 and M13 are turned on, and the high-level signal input by the clock signal terminal CLK is output to the gate line connected thereto through the signal output terminal G_out. At the same time, the cascade signal terminal OC outputs the same signal as the signal output terminal G_out, that is, a high-level signal is output to the pull-up reset signal terminal Reset of the previous stage shift register unit and the signal input terminal Input of the next stage shift register unit.

[0135] During the reset phase, a high-level signal is input to the reset signal terminal Reset, turning on M2 and M4. The first low-level signal input to the first low-level signal terminal LVGL pulls down the potentials of the pull-up node PU and the signal output terminal G_out, thereby resetting them. Simultaneously, the pull-down control node and the first pull-down node PD1 are both high-level signals, turning on M10, M13, and M12, respectively, to reduce noise on the outputs of the pull-up node PU, the signal output terminal G_out, and the cascade signal terminal OC. This continues until the next frame scan begins, when the potential of the pull-up node PU is pulled high.

[0136] Fourth Example: Figure 9 is a circuit diagram of a shift register according to the fourth example of the present disclosure. As shown in Figure 9, this example has a substantially identical structure to the first example, differing only in that, in this example, one of the first auxiliary sub-circuits is controlled by the first voltage supply terminal, while the other is controlled by the second voltage supply terminal VDD2. Specifically, because the two pull-down control sub-circuits 5 / 5' in this embodiment operate alternately—for example, one pull-down control sub-circuit operates during odd frames, while the other operates during even frames—when the pull-down control sub-circuits operate, the power supply voltage to which they are connected transitions from a low level to a high level. In this example, one of the first auxiliary sub-circuits is controlled by the first pull-down node PD1 and discharges the second pull-down node PD2 via a first low-level signal inputted via the first low-level signal terminal LVGL. The other first auxiliary sub-circuit is controlled by the second pull-down node PD2 and discharges the first pull-down node PD1 via a first low-level signal inputted via the first low-level signal terminal LVGL. The pull-up of the first pull-down node PD1 depends on the first power supply voltage, and the pull-up of the second pull-down node PD2 depends on the second power supply voltage. In this way, when the first power supply voltage terminal VDD1 inputs a high level, the second pull-down node PD2 is discharged, and when the second power supply voltage terminal VDD2 inputs a high level, the first pull-down node PD1 is discharged.

[0137] Specifically, referring to FIG10 , the input subcircuit 1 includes a first transistor M1. The first reset subcircuit 21 includes a second transistor M2. The second reset subcircuit 22 includes a fourth transistor M4. The output subcircuit 3 includes a third transistor M3 and a storage capacitor C1. The cascade subcircuit 4 includes an eleventh transistor M11. The first global reset subcircuit 11 includes a fifteenth transistor M15. The second global reset subcircuit 12 includes a fourteenth transistor M14. Each pull-down control subcircuit includes a fifth transistor; the fifth transistors in the two pull-down control subcircuits 5 / 5' are represented by M5 and M5', respectively. Each first pull-down subcircuit includes a sixth transistor; the sixth transistors in the two first pull-down subcircuits 6 / 6' are represented by M6 and M6', respectively. Each first pull-down subcircuit includes a sixth transistor; the seventh transistors in the two second pull-down subcircuits 7 / 7' are represented by M7 and M7', respectively. Each first noise reduction sub-circuit includes a tenth transistor, with the tenth transistor in the two first noise reduction sub-circuits 8 / 8' being represented by M10 and M10', respectively. Each second noise reduction sub-circuit includes a thirteenth transistor, with the thirteenth transistor in the two second noise reduction sub-circuits 9 / 9' being represented by M13 and M13', respectively. Each third noise reduction sub-circuit includes a tenth transistor, with the twelfth transistor in the two third noise reduction sub-circuits 10 / 10' being represented by M12 and M12', respectively. Each first auxiliary sub-circuit includes a seventeenth transistor, with the seventeenth transistor in the two first auxiliary sub-circuits 13 / 13' being represented by M17 and M17', respectively.

[0138] Furthermore, the gate and source of M1 are connected to the signal input terminal Input, and the drain of M1 is connected to the pull-up node PU. The gate of M2 is connected to the reset signal terminal Reset, the source of M2 is connected to the pull-up node PU, and the drain of M2 is connected to the first low-level signal terminal LVGL. The gate of M4 is connected to the reset signal terminal Reset, the source of M4 is connected to the signal output terminal G_out, and the drain of M4 is connected to the second low-level signal terminal VGL. The gate of M3 is connected to the pull-up node PU, the source of M3 is connected to the clock signal terminal CLK, and the drain of M3 is connected to the signal output terminal G_out. The gate of M11 is connected to the pull-up node PU, the source of M11 is connected to the clock signal terminal CLK, and the drain of M11 is connected to the cascade signal terminal OC. The first end of C1 is connected to the pull-up node PU, and the second end of C1 is connected to the signal output terminal G_out. The gate and source of M5 are both connected to the first power supply voltage terminal VDD1, and the drain of M5 is connected to the first pull-down node PD1. The gate and source of M5' are both connected to the second power supply voltage terminal VDD2, and the drain of M5 is connected to the second pull-down node PD2. The gate of M6 is connected to the pull-up node PU, the source of M6 is connected to the first pull-up node PU, and the drain of M6 is connected to the first low-level signal terminal LVGL. The gate of M6' is connected to the pull-up node PU, the source of M6' is connected to the second pull-up node PU, and the drain of M6' is connected to the first low-level signal terminal LVGL. The gate of M7 is connected to the signal input terminal Input, the source of M7 is connected to the first pull-up node PU, and the drain of M7 is connected to the first low-level signal terminal LVGL. The gate of M7' is connected to the signal input terminal Input, the source of M7' is connected to the second pull-up node PU, and the drain of M7' is connected to the first low-level signal terminal LVGL. The gate of M10 is connected to the first pull-down node PD1, the source of M10 is connected to the pull-up node PU, and the drain of M10 is connected to the first low-level signal terminal LVGL. The gate of M10' is connected to the second pull-down node PD2, the source of M10' is connected to the pull-up node PU, and the drain of M10' is connected to the first low-level signal terminal LVGL. The gate of M12 is connected to the first pull-down node PD1, the source of M12 is connected to the cascade signal terminal OC, and the drain of M12 is connected to the first low-level signal terminal LVGL. The gate of M12' is connected to the second pull-down node PD2, the source of M12' is connected to the cascade signal terminal OC, and the drain of M12' is connected to the first low-level signal terminal LVGL. The gate of M13 is connected to the first pull-down node PD1, the source of M13 is connected to the signal output terminal G_out, and the drain of M13 is connected to the first low-level signal terminal LVGL. The gate of M13' is connected to the second pull-down node PD2, the source of M13' is connected to the signal output terminal G_out, and the drain of M13' is connected to the second low-level signal terminal VGL. The gate of M14 is connected to the second global reset signal terminal Total_RST, the source of M14 is connected to the signal output terminal G_out, and the drain of M14 is connected to the second low level signal terminal VGL.The gate of M15 is connected to the first global reset signal terminal Total_RST1, the source of M15 is connected to the signal output terminal G_out, and the drain of M15 is connected to the first low-level signal terminal LVGL. The gate of M17 is connected to the first pull-down node PD1, the source of M17 is connected to the first pull-down node PD1, and the drain of M17 is connected to the first low-level signal terminal LVGL. The gate of M17' is connected to the second pull-down node PD2, the source of M17' is connected to the first pull-down node PD1, and the drain of M17' is connected to the first low-level signal terminal LVGL.

[0139] When the first power supply voltage written to the shift register's first power supply voltage terminal VDD1 switches from a low level to a high level, M17 turns on, discharging the second pull-down node PD2 via a first low-level signal. When the second power supply voltage written to the shift register's second power supply voltage terminal VDD2 switches from a low level to a high level, M17' turns on, discharging the first pull-down node PD1 via a first low-level signal. This approach prevents inconsistent response of the signal output terminal G_out to the first low-level signal after switching between the first and second power supply voltages, which could lead to poor TP noise caused by differences when the IC collects raw data from different frames.

[0140] As shown in FIG11 , the operation of the shift register may specifically include the following stages:

[0141] In the discharge stage, before the frame, that is, before display, a high-level signal is input to the first global reset signal terminal Total_RST1 and the second global reset signal terminal Total_RST, the fourteenth transistor and the fifteenth transistor are turned on, and the pull-up node PU and the signal output terminal G_out are discharged through the first low-level signal input by the first low-level signal terminal LVGL to prevent residual charge on the pull-up node PU and the signal output terminal G_out from causing display abnormalities.

[0142] In the input stage, a high-level signal is input to the signal input terminal Input, M1 is turned on, and the pull-up node PU is pulled high by the high-level signal, and C1 is charged. At the same time, M6 and M6', M7 and M7' are all turned on, pulling down the first pull-down node PD1 and the second pull-down node PD2 to avoid affecting the potential of the pull-up node PU.

[0143] In the output stage, since the pull-up node PU is pulled high in the input stage, M3 and M13 are turned on, and the high-level signal input by the clock signal terminal CLK is output to the gate line connected thereto through the signal output terminal G_out. At the same time, the cascade signal terminal OC outputs the same signal as the signal output terminal G_out, that is, a high-level signal is output to the pull-up reset signal terminal Reset of the previous stage shift register unit and the signal input terminal Input of the next stage shift register unit.

[0144] During the reset phase, a high-level signal is input to the reset signal terminal Reset, turning on M2 and M4. The first low-level signal input to the first low-level signal terminal LVGL pulls down the potentials of the pull-up node PU and the signal output terminal G_out, thereby resetting them. Simultaneously, the pull-down control node and the first pull-down node PD1 are both high-level signals, turning on M10, M13, and M12, respectively, to reduce noise on the outputs of the pull-up node PU, the signal output terminal G_out, and the cascade signal terminal OC. This continues until the next frame scan begins, when the potential of the pull-up node PU is pulled high.

[0145] Fifth example: Figure 10 is a circuit diagram of the shift register of the fifth example of the embodiment of the present disclosure; as shown in Figure 10, the shift register includes an input sub-circuit 1, an output sub-circuit 3, two pull-down control sub-circuits 5 / 5', two first pull-down sub-circuits 6 / 6', and a second auxiliary sub-circuit 14. The input sub-circuit 1 is configured to respond to the input signal of the signal input terminal Input and pre-charge the pull-up node PU through the input signal; the input sub-circuit 1, the output sub-circuit 3 and the connection node between the pull-down sub-circuit; the output sub-circuit 3 is configured to respond to the potential of the pull-up node PU and output the clock signal through the signal output terminal G_out; the pull-down control sub-circuit is configured to respond to the power supply voltage and control the potential of the pull-down node through the power supply voltage; a pull-down control sub-circuit is connected to a first pull-down sub-circuit, and the connection node between the two is a pull-down node; the first pull-down sub-circuit is configured to respond to the potential of the pull-up node PU and pull down the potential of the pull-down node electrically connected thereto through a first low-level signal; the second auxiliary sub-circuit 14 is configured to respond to the touch enable signal and discharge the output of the signal output terminal G_out through a first low-level signal.

[0146] In this example, by adding a second auxiliary sub-circuit 14, when the display panel enters the touch stage, the touch enable signal is used to control the operation of the first auxiliary sub-circuit, and the signal output terminal G_out is pulled down so that the output of the signal output terminal G_out is consistent with the first low-level signal, thereby avoiding the output difference of the signal output terminal G_out in different frames caused by the different potentials of the pull-down node.

[0147] Since in this example there are two pull-down control sub-circuits and two first pull-down sub-circuits, there are also two pull-down nodes, namely the first pull-down node PD1 and the second pull-down node PD2. The power supply voltage terminal to which the pull-down control sub-circuit electrically connected to the first pull-down node PD1 is connected is referred to as the first power supply voltage terminal VDD1, and the power supply voltage terminal to which the pull-down control sub-circuit electrically connected to the second pull-down node PD2 is connected is referred to as the second power supply voltage terminal VDD2.

[0148] In some examples, the two first auxiliary sub-circuits 13 / 13' can be connected to the same first control signal terminal Total_RST2, that is, the two first auxiliary sub-circuits 13 / 13' can be controlled simultaneously. For example, before the current frame scan, the first control signal input through the first control signal terminal Total_RST2 controls the two first auxiliary sub-circuits 13 / 13' to work simultaneously, discharging the first pull-down node PD1 and the second pull-down node PD2 respectively.

[0149] In some examples, the shift register may further include a cascade subcircuit 4, a reset subcircuit 2, two second pull-down subcircuits 7 / 7', two first noise reduction subcircuits 8 / 8', two second noise reduction subcircuits 9 / 9' and two third noise reduction subcircuits 10 / 10', a first global reset subcircuit 11 and a second global reset subcircuit 12.

[0150] The first reset subcircuit 21 is configured to reset the pull-up node PU via a first low-level signal under the control of a reset signal. The second reset subcircuit 22 is configured to reset the signal output terminal G_out via a second low-level signal under the control of a reset signal. The cascade subcircuit 4 is configured to output the clock signal via the cascade signal terminal OC in response to the potential of the pull-up node PU. The second pull-down subcircuit is configured to pull down the potential of the pull-down node electrically connected thereto via a first low-level signal in response to an input signal. The first noise reduction subcircuit is configured to perform noise reduction on the output of the pull-up node PU under the control of the pull-down node connected thereto. The second noise reduction subcircuit is configured to perform noise reduction on the output of the signal output terminal G_out under the control of the pull-down node connected thereto. The third noise reduction subcircuit is configured to perform noise reduction on the output of the cascade signal terminal OC under the control of the pull-down node connected thereto. The first global reset subcircuit 11 is configured to discharge the pull-up node PU via a first low-level signal in response to the first global reset signal. The second global reset sub-circuit 12 is configured to discharge the output of the signal output terminal G_out through a second low-level signal in response to the second global reset signal.

[0151] Continuing with FIG10 , two pull-down control subcircuits 5 / 5', two first pull-down subcircuits 6 / 6', two second pull-down subcircuits 7 / 7', two first noise reduction subcircuits 8 / 8', two second noise reduction subcircuits 9 / 9', and two third noise reduction subcircuits 10 / 10' are connected to a first pull-down subcircuit and a second pull-down subcircuit, with the connection node being the first pull-down node PD1. The pull-down control subcircuits are connected to a first pull-down subcircuit and a second pull-down subcircuit, with the connection node being the first pull-down nodes PD1 and PD2. The first pull-down node PD1 connects a first noise reduction subcircuit, a second noise reduction subcircuit, and a third noise reduction subcircuit 9. The second pull-down node PD2 connects another first noise reduction subcircuit, another second noise reduction subcircuit, and another third noise reduction subcircuit. The two pull-down control subcircuits 5 / 5' in the shift register have identical structures and functions, except that when the shift register is operating, the two pull-down control subcircuits 5 / 5' operate in time-sharing mode. That is, the timing of the control signals controlling the two pull-down control subcircuits 5 / 5' is opposite. Similarly, the two first pull-down subcircuits 6 / 6' have identical structures and functions and operate in time-sharing mode; the two second pull-down subcircuits 7 / 7' have identical structures and functions and operate in time-sharing mode; the two first noise reduction subcircuits 8 / 8' have identical structures and functions and operate in time-sharing mode; the two second noise reduction subcircuits 9 / 9' have identical structures and functions and operate in time-sharing mode; and the two third noise reduction subcircuits 10 / 10' have identical structures and functions and operate in time-sharing mode. The first global reset signal can be a pre-frame start signal to discharge the pull-up node PU before the current frame scan.

[0152] Specifically, input subcircuit 1 includes a first transistor M1. Reset subcircuit 2 includes a second transistor M2 and a fourth transistor M4. Output subcircuit 3 includes a third transistor M3 and a storage capacitor C1. Cascade subcircuit 4 includes an eleventh transistor M11. First global reset subcircuit 11 includes a fifteenth transistor M15. Second global reset subcircuit 12 includes a fourteenth transistor M14. Each pull-down control subcircuit includes a fifth transistor; the fifth transistors in the two pull-down control subcircuits 5 / 5' are represented by M5 and M5', respectively. Each first pull-down subcircuit includes a sixth transistor; the sixth transistors in the two first pull-down subcircuits 6 / 6' are represented by M6 and M6', respectively. Each first pull-down subcircuit includes a sixth transistor; the seventh transistors in the two second pull-down subcircuits 7 / 7' are represented by M7 and M7', respectively. Each first noise reduction subcircuit includes a tenth transistor; the tenth transistors in the two first noise reduction subcircuits 8 / 8' are represented by M10 and M10', respectively. Each second noise reduction sub-circuit includes a thirteenth transistor, with the thirteenth transistors in the two second noise reduction sub-circuits 9 / 9' being represented by M13 and M13', respectively. Each third noise reduction sub-circuit includes a tenth transistor, with the twelfth transistors in the two third noise reduction sub-circuits 10 / 10' being represented by M12 and M12', respectively. Each second auxiliary sub-circuit 14 includes an eighteenth transistor M18.

[0153] Furthermore, the gate and source of M1 are connected to the signal input terminal Input, and the drain of M1 is connected to the pull-up node PU. The gate of M2 is connected to the reset signal terminal Reset, the source of M2 is connected to the pull-up node PU, and the drain of M2 is connected to the first low-level signal terminal LVGL. The gate of M4 is connected to the reset signal terminal Reset, the source of M4 is connected to the signal output terminal G_out, and the drain of M4 is connected to the second low-level signal terminal VGL. The gate of M3 is connected to the pull-up node PU, the source of M3 is connected to the clock signal terminal CLK, and the drain of M3 is connected to the signal output terminal G_out. The gate of M11 is connected to the pull-up node PU, the source of M11 is connected to the clock signal terminal CLK, and the drain of M11 is connected to the cascade signal terminal OC. The first end of C1 is connected to the pull-up node PU, and the second end of C1 is connected to the signal output terminal G_out. The gate and source of M5 are both connected to the first power supply voltage terminal VDD1, and the drain of M5 is connected to the first pull-down node PD1. The gate and source of M5' are both connected to the second power supply voltage terminal VDD2, and the drain of M5 is connected to the second pull-down node PD2. The gate of M6 is connected to the pull-up node PU, the source of M6 is connected to the first pull-up node PU, and the drain of M6 is connected to the first low-level signal terminal LVGL. The gate of M6' is connected to the pull-up node PU, the source of M6' is connected to the second pull-up node PU, and the drain of M6' is connected to the first low-level signal terminal LVGL. The gate of M7 is connected to the signal input terminal Input, the source of M7 is connected to the first pull-up node PU, and the drain of M7 is connected to the first low-level signal terminal LVGL. The gate of M7' is connected to the signal input terminal Input, the source of M7' is connected to the second pull-up node PU, and the drain of M7' is connected to the first low-level signal terminal LVGL. The gate of M10 is connected to the first pull-down node PD1, the source of M10 is connected to the pull-up node PU, and the drain of M10 is connected to the first low-level signal terminal LVGL. The gate of M10' is connected to the second pull-down node PD2, the source of M10' is connected to the pull-up node PU, and the drain of M10' is connected to the first low-level signal terminal LVGL. The gate of M12 is connected to the first pull-down node PD1, the source of M12 is connected to the cascade signal terminal OC, and the drain of M12 is connected to the first low-level signal terminal LVGL. The gate of M12' is connected to the second pull-down node PD2, the source of M12' is connected to the cascade signal terminal OC, and the drain of M12' is connected to the first low-level signal terminal LVGL. The gate of M13 is connected to the first pull-down node PD1, the source of M13 is connected to the signal output terminal G_out, and the drain of M13 is connected to the first low-level signal terminal LVGL. The gate of M13' is connected to the second pull-down node PD2, the source of M13' is connected to the signal output terminal G_out, and the drain of M13' is connected to the second low-level signal terminal VGL. The gate of M14 is connected to the second global reset signal terminal Total_RST, the source of M14 is connected to the signal output terminal G_out, and the drain of M14 is connected to the second low level signal terminal VGL.The gate of M15 is connected to the first global reset signal terminal Total_RST1, the source of M15 is connected to the signal output terminal G_out, and the drain of M15 is connected to the first low-level signal terminal LVGL. The gate of M18 is connected to the touch enable signal terminal, the source of M18 is connected to the signal output terminal G_out, and the drain of M18 is connected to the first low-level signal terminal LVGL.

[0154] When the display panel enters the touch stage, the eighteenth transistor is controlled to open through the touch enable signal, and the signal output terminal G_out is pulled down to make the output of the signal output terminal G_out consistent with the first low-level signal, thereby avoiding the output difference of the signal output terminal G_out in different frames affected by the different potentials of the pull-down node.

[0155] FIG11 is a timing diagram corresponding to the shift register shown in FIG10 . As shown in FIG11 , the operation of the shift register may specifically include the following stages:

[0156] In the discharge stage, before the frame, that is, before display, a high-level signal is input to the first global reset signal terminal Total_RST1 and the second global reset signal terminal Total_RST, the fourteenth transistor and the fifteenth transistor are turned on, and the pull-up node PU and the signal output terminal G_out are discharged through the first low-level signal input by the first low-level signal terminal LVGL to prevent residual charge on the pull-up node PU and the signal output terminal G_out from causing display abnormalities.

[0157] In the input stage, a high-level signal is input to the signal input terminal Input, M1 is turned on, and the pull-up node PU is pulled high by the high-level signal, and C1 is charged. At the same time, M6 and M6', M7 and M7' are all turned on, pulling down the first pull-down node PD1 and the second pull-down node PD2 to avoid affecting the potential of the pull-up node PU.

[0158] In the output stage, since the pull-up node PU is pulled high in the input stage, M3 and M13 are turned on, and the high-level signal input by the clock signal terminal CLK is output to the gate line connected thereto through the signal output terminal G_out. At the same time, the cascade signal terminal OC outputs the same signal as the signal output terminal G_out, that is, a high-level signal is output to the pull-up reset signal terminal Reset of the previous stage shift register unit and the signal input terminal Input of the next stage shift register unit.

[0159] During the reset phase, a high-level signal is input to the reset signal terminal Reset, turning on M2 and M4. The first low-level signal input to the first low-level signal terminal LVGL pulls down the potentials of the pull-up node PU and the signal output terminal G_out, thereby resetting them. Simultaneously, the pull-down control node and the first pull-down node PD1 are both high-level signals, turning on M10, M13, and M12, respectively, to reduce noise on the outputs of the pull-up node PU, the signal output terminal G_out, and the cascade signal terminal OC. This continues until the next frame scan begins, when the potential of the pull-up node PU is pulled high.

[0160] Of course, for the first to fourth examples described above, a second auxiliary sub-circuit 14 can be added to any of the above circuits. When the display panel enters the touch phase, the touch enable signal controls the opening of the eighteenth transistor, thereby pulling down the signal output terminal G_out so that the output of the signal output terminal G_out is consistent with the first low-level signal, thereby avoiding the difference in the output of the signal output terminal G_out in different frames due to the different potentials of the pull-down node. Specifically, referring to FIG11 , in the touch phase, that is, when the touch enable signal is a high-level signal, the outputs of the signal output terminal G_out at the first scan row and the signal output terminal G_out at the last scan row are both consistent with the first low-level signal.

[0161] The embodiments of the present disclosure provide a gate driving circuit, which may include any of the above-mentioned shift registers.

[0162] The embodiments of the present disclosure provide a display panel, which may include any of the above-mentioned gate driving circuits.

[0163] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A shift register comprising an input subcircuit, an output subcircuit, at least one pull-down control subcircuit, and at least one first pull-down subcircuit; The input sub-circuit is configured to precharge a pull-up node in response to an input signal at a signal input terminal by the input signal; the pull-up node is a connection node between the input sub-circuit, the output sub-circuit, and the first pull-down sub-circuit; The output sub-circuit is configured to output the clock signal through the signal output terminal in response to the potential of the pull-up node; The pull-down control subcircuit is configured to respond to a power supply voltage and control the potential of the pull-down node by the power supply voltage; One of the pull-down control sub-circuits is connected to one of the first pull-down sub-circuits, and a connection node between the two is the pull-down node; The first pull-down sub-circuit is configured to pull down the potential of the pull-down node electrically connected thereto through a first non-working level signal in response to the potential of the pull-up node; wherein, The shift register further includes at least one first auxiliary sub-circuit, each of the first auxiliary sub-circuits being electrically connected to one of the pull-down nodes; the first auxiliary sub-circuit being configured to discharge the pull-down node electrically connected thereto under the control of a first control signal after the touch phase ends.

2. The shift register according to claim 1, wherein: The pull-down control sub-circuit, the first pull-down sub-circuit, and the first auxiliary sub-circuit are all plural in number, and one pull-down node is electrically connected to one pull-down control sub-circuit, one first pull-down sub-circuit, and one first auxiliary sub-circuit; Each of the first auxiliary sub-circuits is electrically connected to the same first control signal terminal, and operates simultaneously under the first control signal received by the first control signal terminal, and discharges the pull-down nodes corresponding to each of the first auxiliary sub-circuits before scanning the current frame.

3. The shift register according to claim 1, wherein: It also includes a first global reset sub-circuit, configured to globally reset the pull-up node through a first non-working level signal under the control of the first global reset signal; The global reset signal is multiplexed as the first control signal.

4. The shift register according to claim 3, wherein: The global reset sub-circuit includes a fifteenth transistor; The first electrode of the fifteenth transistor is connected to the pull-up node, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the first global reset signal terminal and each of the first auxiliary sub-circuits.

5. The shift register according to claim 4, wherein: The first auxiliary sub-circuit includes a seventeenth transistor; The first electrode of the seventeenth transistor is connected to one of the pull-down nodes, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the first global reset signal terminal. The shift register according to claim 1 , wherein: The frame start signal is multiplexed into the first control signal.

7. The shift register according to claim 6, wherein: The first auxiliary sub-circuit includes a seventeenth transistor; The first electrode of the seventeenth transistor is connected to the pull-down node, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the frame start signal terminal.

8. The shift register according to claim 1, wherein: The number of the pull-down control sub-circuit, the first pull-down sub-circuit, and the first auxiliary sub-circuit are all two, the number of the pull-down nodes is two, the two pull-down nodes are respectively a first pull-down node and a second pull-down node, and the first pull-down node is electrically connected to one pull-down control sub-circuit, one first pull-down sub-circuit, and one first auxiliary sub-circuit; the second pull-down node is electrically connected to another pull-down control sub-circuit, another first pull-down sub-circuit, and another first auxiliary sub-circuit; The potential of the first pull-down node is multiplexed as a first control signal of a first auxiliary sub-circuit, and the second pull-down node is discharged through the first non-working level signal; the potential of the second pull-down node is multiplexed as a first control signal of another first auxiliary sub-circuit, and the first pull-down node is discharged through the first non-working level signal.

9. The shift register according to claim 8, wherein: The first auxiliary sub-circuit includes a seventeenth transistor; The first electrode of the seventeenth transistor in one of the first auxiliary sub-circuits is connected to the first pull-down node, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the second pull-down node; the first electrode of the seventeenth transistor in another of the first auxiliary sub-circuits is connected to the first second pull-down node, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the first pull-down node.

10. The shift register according to claim 1, wherein: The device further includes a second auxiliary sub-circuit configured to discharge the output of the signal output terminal through a first non-working level signal in response to a touch enable signal.

11. The shift register according to claim 10, wherein: The second auxiliary sub-circuit includes an eighteenth transistor; The first electrode of the eighteenth transistor is connected to the signal output terminal, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the touch enable signal terminal.

12. The shift register according to any one of claims 1 to 11, wherein: It also includes at least one second pull-down sub-circuit, wherein one of the second pull-down sub-circuit is electrically connected to one of the pull-down nodes; The second pull-down sub-circuit is configured to pull down the potential of the pull-down node electrically connected thereto via a first non-operating level signal in response to an input signal.

13. The shift register according to claim 12, wherein: The second pull-down sub-circuit includes a seventh transistor; The first electrode of the seventh transistor is connected to the corresponding pull-down node, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the signal input terminal.

14. The shift register according to any one of claims 1 to 11, wherein: Also includes: The first reset subcircuit is configured to reset the pull-up node through a first non-working level signal under the control of the reset signal. The second reset sub-circuit is configured to reset the signal output end through a second non-working level signal under the control of the reset signal.

15. The shift register according to claim 14, wherein: The first reset sub-circuit includes a second transistor; the second reset sub-circuit includes a fourth transistor; The first electrode of the second transistor is connected to the pull-up node, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the reset signal terminal; The first electrode of the fourth transistor is connected to the signal output terminal, the second electrode is connected to the second non-working level signal terminal, and the control electrode is connected to the reset signal terminal.

16. The shift register according to any one of claims 1 to 11, wherein: It also includes at least one first noise reduction sub-circuit and at least one second noise reduction sub-circuit; one of the pull-down nodes is electrically connected to one of the first noise reduction sub-circuit and one of the second noise reduction sub-circuit; The first noise reduction sub-circuit is configured to reduce noise on the output of the pull-up node through a first non-working level signal under the control of the pull-down node electrically connected thereto; The second noise reduction sub-circuit is configured to reduce noise on the output of the signal output terminal through a second non-working level signal under the control of the pull-down node electrically connected thereto.

17. The shift register according to claim 16, wherein: The first noise reduction sub-circuit includes a tenth transistor; the second noise reduction sub-circuit includes a thirteenth transistor; The first electrode of the tenth transistor is connected to the pull-up node, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the corresponding pull-down node; The first electrode of the thirteenth transistor is connected to the signal output terminal, the second electrode is connected to the second non-working level signal terminal, and the control electrode is connected to the corresponding pull-down node.

18. The shift register according to any one of claims 1 to 11, wherein: The system further includes a cascade sub-circuit configured to output a clock signal through a cascade signal terminal in response to the potential of the pull-up node.

19. The shift register according to claim 18, wherein: The cascade sub-circuit includes an eleventh transistor; The first electrode of the eleventh transistor is connected to the constant signal terminal, the second electrode is connected to the cascade signal terminal, and the control electrode is connected to the pull-up node.

20. The shift register according to claim 18, wherein It also includes a third noise reduction sub-circuit, which is configured to reduce the noise of the output of the cascade signal terminal through a first non-working level signal under the control of the pull-down node electrically connected thereto.

21. The shift register according to claim 20, wherein: The third noise reduction sub-circuit includes a twelfth transistor; The first electrode of the twelfth transistor is connected to the cascade signal terminal, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the corresponding pull-down node.

22. The shift register according to any one of claims 1 to 11, wherein: The system further includes a second global reset sub-circuit configured to discharge the signal output terminal through a second non-working level signal in response to a second global reset signal.

23. The shift register according to claim 22, wherein: The second global reset sub-circuit includes a fourteenth transistor; The first electrode of the fourteenth transistor is connected to the signal output terminal, the second electrode is connected to the second non-working level signal terminal, and the control electrode is connected to the second global reset signal terminal.

24. The shift register according to any one of claims 1 to 11, wherein: The input subcircuit includes a first transistor; The first electrode and the control electrode of the first transistor are both connected to the signal input terminal, and the second electrode is connected to the pull-up node.

25. The shift register according to any one of claims 1 to 11, wherein: The output sub-circuit includes a third transistor and a storage capacitor; The first electrode of the third transistor is connected to the clock signal terminal, the second electrode is connected to the signal output terminal and the second terminal of the storage capacitor, and the control electrode is connected to the first terminal of the storage capacitor and the pull-up node.

26. The shift register according to any one of claims 1 to 11, wherein: The pull-down control subcircuit includes a fifth transistor; The first electrode of the fifth transistor is connected to the control electrode and the power supply voltage terminal, and the second electrode is connected to the corresponding pull-down node.

27. The shift register according to any one of claims 1 to 11, wherein: The first pull-down sub-circuit includes a sixth transistor; The first electrode of the sixth transistor is connected to the corresponding pull-down node, the second electrode is connected to the non-operating voltage end, and the control electrode is connected to the signal input end.

28. The shift register according to any one of claims 1 to 11, wherein: Each sub-circuit in the shift register at least includes a thin film transistor, and the thin film transistor is an oxide thin film transistor.

29. A shift register comprising an input subcircuit, an output subcircuit, at least one pull-down control subcircuit, and at least one first pull-down subcircuit; the input subcircuit configured to precharge the pull-up node by the input signal in response to the input signal at the signal input terminal; a connection node between the input subcircuit, the output subcircuit, and the pull-down subcircuit; The output sub-circuit is configured to output the clock signal through the signal output terminal in response to the potential of the pull-up node; The pull-down control subcircuit is configured to respond to a power supply voltage and control the potential of the pull-down node by the power supply voltage; One of the pull-down control sub-circuits is connected to one of the first pull-down sub-circuits, and a connection node between the two is the pull-down node; The first pull-down sub-circuit is configured to pull down the potential of the pull-down node electrically connected thereto through a first non-working level signal in response to the potential of the pull-up node; wherein, The shift register further includes a second auxiliary sub-circuit configured to discharge the output of the signal output terminal through a first non-working level signal in response to a touch enable signal.

30. The shift register according to claim 29, wherein: The input subcircuit includes a first transistor; the output subcircuit includes a third transistor and a storage capacitor; the pull-down control subcircuit includes a fifth transistor; the first pull-down subcircuit includes a sixth transistor; and the second auxiliary subcircuit includes an eighteenth transistor. The first electrode and the control electrode of the first transistor are both connected to the signal input terminal, and the second electrode is connected to the pull-up node; the first electrode of the third transistor is connected to the clock signal terminal, the second electrode is connected to the signal output terminal and the second terminal of the storage capacitor, and the control electrode is connected to the first terminal of the storage capacitor and the pull-up node; the first electrode of the fifth transistor is connected to its control electrode and the power supply voltage terminal, and the second electrode is connected to the corresponding pull-down node; the first electrode of the sixth transistor is connected to the corresponding pull-down node, the second electrode is connected to the non-working voltage terminal, and the control electrode is connected to the signal input terminal; the first electrode of the eighteenth transistor is connected to the signal output terminal, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the touch enable signal terminal.

31. A gate driving circuit comprising the shift register according to any one of claims 1 to 30.

32. A display device comprising the gate driving circuit according to claim 31.

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