Data decoding error correction method and apparatus, and storage medium and electronic apparatus

Abstract

The embodiments of the present disclosure provide a data decoding error correction method and apparatus, and a storage medium and an electronic apparatus. The method comprises: determining a plurality of test sequences on the basis of soft information of data to be decoded; removing a first test sequence and second test sequences from among the plurality of test sequences to obtain a target test sequence, wherein the first test sequence is a test sequence that failed in hard decoding, and the second test sequences are N-1 test sequences among N test sequences which succeeded in hard decoding and have the same flipped position after hard decoding, N being a positive integer greater than 1; and on the basis of the target test sequence, performing decoding error correction on the data to be decoded.

Description

Data decoding error correction method, device, storage medium and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on Chinese patent application CN202410388828.2, filed on April 1, 2024, entitled “Data decoding and error correction method, device, storage medium and electronic device”, and claims the priority of the patent application. All the disclosed contents are incorporated into this application by reference. Technical Field

[0003] The embodiments of the present disclosure relate to the field of communication technology, and more specifically, to a data decoding and error correction method, device, storage medium, and electronic device. Background Art

[0004] Forward Error Correction (FEC) uses Bose-Chaudhuri-Hocquenghem (BCH) decoding at both the transmitter and receiver to implement multi-bit error correction. This involves using BCH codes for encoding and decoding, and utilizing the redundant bits added during the BCH decoding process for error correction. BCH decoding offers the advantages of strong error correction capabilities and the ability to perform multi-bit error correction.

[0005] BCH decoding is categorized into soft-decision decoding (soft decoding) and hard-decision decoding (hard decoding). While hard-decision decoding is simple to design and easy to implement, its performance is very poor, and it can only correct a single bit error. Soft-decision decoding can achieve better coding gain, but its implementation is much more difficult than hard-decision decoding. Each candidate codeword generated by soft-decision decoding requires a complete hard-decision decoding. Furthermore, a soft-decision decoder requires additional modules in addition to a hard-decision decoder core. As the number of codeword bits at the receiver increases, soft-decision decoding based on BCH codes requires greater hardware complexity, increased decoding latency, and increased error correction time and resource consumption. Therefore, reducing decoding complexity and resource consumption while maintaining the error correction performance of soft-decision decoding is an urgent issue. Summary of the Invention

[0006] The embodiments of the present disclosure provide a data decoding and error correction method, apparatus, storage medium, and electronic device to at least solve the problems of high decoding complexity and large delay in the BCH soft decoding method in the related art.

[0007] According to one embodiment of the present disclosure, a data decoding and error correction method is provided, comprising: determining multiple test sequences based on soft information of data to be decoded; removing a first test sequence and a second test sequence from the multiple test sequences to obtain a target test sequence, wherein the first test sequence is a test sequence in which hard decoding fails; the second test sequence is N-1 test sequences among N test sequences in which hard decoding succeeds and which have the same flip position after hard decoding; wherein N is a positive integer greater than 1; and performing decoding and error correction on the data to be decoded based on the target test sequence.

[0008] According to another embodiment of the present disclosure, a data decoding and error correction device is provided, comprising: a determination module configured to determine multiple test sequences based on soft information of data to be decoded; a removal module configured to remove a first test sequence and a second test sequence from the multiple test sequences to obtain a target test sequence, wherein the first test sequence is a test sequence in which hard decoding fails; the second test sequence is a test sequence in which hard decoding succeeds and is N-1 test sequences among N test sequences with the same flip position after hard decoding; and an error correction module configured to decode and error correct the data to be decoded based on the target test sequence.

[0009] According to another embodiment of the present disclosure, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is configured to execute the steps in the above method embodiment when running.

[0010] According to another embodiment of the present disclosure, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in the above method embodiment.

[0011] According to another embodiment of the present disclosure, a computer program product is provided, including a computer program and instructions, wherein the computer program and instructions implement the steps in the above method embodiment when executed by a processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG1 is a schematic diagram of a BCH cascade decoding process according to an embodiment of the present disclosure;

[0013] FIG2 is a schematic diagram of a soft decoding process according to an embodiment of the present disclosure;

[0014] FIG3 is a flow chart of a data decoding and error correction method according to an embodiment of the present disclosure;

[0015] FIG4 is a schematic diagram of the relative position relationship between multiple unreliable bits according to an embodiment of the present disclosure;

[0016] FIG5 is a schematic diagram showing a case where a flipped unreliable bit exists among a plurality of unreliable bits according to an embodiment of the present disclosure;

[0017] FIG6 is a schematic diagram showing a plurality of unreliable bits having the same position as a decoding error position according to an embodiment of the present disclosure;

[0018] FIG7 is a flow chart of a test sequence removal method according to an embodiment of the present disclosure;

[0019] FIG8 is a structural block diagram of a data decoding and error correction device according to an embodiment of the present disclosure;

[0020] FIG9 is a block diagram of the hardware structure of a communication device that executes a decoding method or a decoding error correction method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0022] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0023] Conventional BCH soft decision decoding uses soft decision decoding with strong error correction capability to perform multiple iterations to ensure the decoding error correction capability. For example, according to the input soft information, a code element positions with the lowest credibility are selected as the estimated error positions. For a code element position with the lowest credibility, b corresponding error positions will be generated. Test sequences, and conventional BCH soft-decision decoding requires b times of error detection and error location search on b test sequences, resulting in 2*b estimated error locations. Multiple soft-decision decoding requires significant decoding resources and time. Large values ​​of b lead to extremely high decoding complexity and significant decoding delay, creating a bottleneck that hinders reducing soft-decision decoding resource consumption and complexity.

[0024] An embodiment of the present disclosure provides a BCH cascade decoding method, which can be applied to the decoding device of Figure 1. As shown in Figure 1, the decoding device includes: a front-stage module data processing module, multiple decoding modules, multiple decoding iteration modules and a post-decoding data processing module.

[0025] The input data to be decoded (i.e., the original codeword) undergoes data processing (e.g., data rearrangement) in a pre-stage data processing module and is then input into a decoding module. The processed original codeword is decoded and updated in multiple decoding modules and multiple decoding iteration modules, and the output value is decoded by a post-stage data processing module and mapped to an output data format. The decoding iteration module can use a BCH (256, 239) code with an error correction capability of t = 2, selecting data to form a codeword according to a codeword selection method specified by the algorithm. The (256, 239) BCH code is obtained by extending the (255, 239) BCH code by 1 parity bit.

[0026] Each decoding module or each decoding iteration module in FIG1 includes a soft decoding process or multiple parallel soft decoding processes. FIG2 is a schematic diagram of the soft decoding process according to an embodiment of the present disclosure. As shown in FIG2 , the soft decoding process mainly includes:

[0027] Step S1, calculating the initial syndrome, initial parity check bit and original codeword reliability according to the input original codeword of the previous decoding iteration module;

[0028] Step S2, obtaining the unreliable bit, initial syndrome, and initial parity check bit of the original codeword;

[0029] Step S3, determining the syndromes and parity bits of all test sequences based on the unreliable bits, initial syndromes, and initial parity bits of the original codeword;

[0030] Step S4: input multiple test sequences into the decoding core module for hard decoding; the decoding core module outputs hard decoding results, the number and position of bits flipped in the test sequence, and other information.

[0031] Step S5, determining an optimal test sequence (i.e., optimal codeword) and a suboptimal test sequence (i.e., suboptimal codeword) based on the hard decoding result;

[0032] Step S6: Correct the input codeword of the previous decoding iteration module according to the optimal test sequence and the suboptimal test sequence of step S5 to update the input of the previous decoding iteration module; and output the updated codeword.

[0033] The present disclosure also provides a data decoding method that can reduce resource consumption and complexity. FIG3 is a flow chart of the data decoding and error correction method according to the present disclosure. As shown in FIG3 , the flow chart includes the following steps:

[0034] Step S302 , determining multiple test sequences based on soft information of the data to be decoded; the data to be decoded, i.e., the original codeword, includes multiple code elements. For example, if the original codeword is 1110011001, each “1” or “0” is a code element.

[0035] In step S302 of this embodiment, multiple test sequences are determined based on soft information of the data to be decoded, including: determining the decoding reliability of each codeword in the data to be decoded based on the soft information, and obtaining Q codewords with the lowest decoding reliability, where Q is a positive integer; determining the positions of the Q codewords in the data to be decoded as unreliable bits of the data to be decoded; and flipping one or more unreliable bits in the data to be decoded, respectively, to determine the multiple test sequences based on the data to be decoded after flipping the unreliable bits.

[0036] For example, based on the soft information, the eight code elements with the lowest decoding reliability in the original code word are determined, i.e., Q=8; based on the original code word, the hard bits of the code elements at 0, any 1, any 2, or any 3 positions in these eight unreliable bits are flipped to obtain p test sequences, where:

[0037] Q is a positive integer.

[0038] After step S302 of this embodiment, the method further includes: inputting the multiple test sequences into a decoder to obtain hard decoding results of the multiple test sequences; determining target hard decoding results of target symbols indicating decoding errors from the hard decoding results of the multiple test sequences; and selecting the N test sequences having the same flip position after hard decoding from the M test sequences corresponding to the target hard decoding results, where M is less than p.

[0039] For example, after determining p test sequences, the p test sequences are input into a related decoding module to perform BCH hard decoding on the p test sequences respectively. The BCH hard decoding results include: successful hard decoding with no error position, successful hard decoding with an error position, and hard decoding failure.

[0040] The hard decoding is successful and there is no error position, that is, after performing BCH hard decoding on a test sequence, a hard decoding result can be obtained, and there is no codeword with a sign flip in the hard decoding result; wherein, there is no codeword that produces a sign flip, which means there is no error position.

[0041] Hard decoding is successful but there is an error position. That is, after BCH hard decoding of a test sequence, a hard decoding result can be obtained, but the hard decoding result contains codewords with sign flips. The presence of codewords with sign flips indicates an error position.

[0042] Hard decoding fails, that is, after performing BCH hard decoding on a test sequence, no hard decoding result is obtained.

[0043] In one embodiment, the N test sequences having the same flipped position after hard decoding are selected from the M test sequences corresponding to the target hard decoding results, including: if the position of the target symbol in the i-th test sequence coincides with the unreliable bit, determining whether all the unreliable bits are flipped; wherein the value of i is 0, 1, 2, ..., M; if all the unreliable bits are not flipped, selecting the i-th test sequence from the M test sequences based on the number of coincident positions, and using the i-th test sequence as one of the N test sequences; if there is a flipped unreliable bit among all the unreliable bits, selecting the i-th test sequence from the M test sequences based on the relationship between the position of the target sub-symbol and the position of the flipped unreliable bit, and using the i-th test sequence as one of the N test sequences, wherein the target sub-symbol is the symbol in the target symbol corresponding to the coincident position.

[0044] In one embodiment, selecting the i-th test sequence from the M test sequences based on the number of identical positions includes: selecting the i-th test sequence from the M test sequences when the number of identical positions in the i-th test sequence meets a preset threshold.

[0045] In one embodiment, selecting the i-th test sequence from the M test sequences based on a position relationship between a target sub-code element and a position of the flipped unreliable bit includes selecting the i-th test sequence from the M test sequences when the position relationship of the i-th test sequence does not satisfy a preset position condition.

[0046] As shown in Figures 4-6, each unreliable bit is assigned a corresponding serial number. The rightmost small box in Figure 4 indicates the smallest position (i.e., the smallest serial number). The relative positions of the eight most unreliable bits (unreliable bit 0-unreliable bit 7) are indicated by white small boxes. The flip position of the current test sequence is indicated by a gray small box. As shown in Figure 5, there is one flipped unreliable bit among all the unreliable bits. The decoding error position of the current test sequence is indicated by a black small box. As shown in Figure 6, there are two decoding error positions in the current test sequence, and these two decoding error positions are the same as the positions of the two unreliable bits.

[0047] In one embodiment, the preset position condition includes the maximum value of the flipped unreliable bit being less than the minimum value of the position of the target sub-symbol. The maximum value of the flipped unreliable bit is the maximum sequence number assigned to the flipped unreliable bit, and the minimum value of the position of the target sub-symbol is the minimum sequence number assigned to the position of the target sub-symbol.

[0048] In one embodiment, selecting the i-th test sequence from the M test sequences based on the positional relationship between the flipped unreliable bits and the sub-target symbols includes: when the positional relationship of the i-th test sequence satisfies a preset position condition, taking the union of the flipped unreliable bits and the target sub-symbol positions to obtain a position set; and selecting the i-th test sequence from the M test sequences based on the number of positions in the position set.

[0049] In one embodiment, selecting the i-th test sequence from the M test sequences based on the number of positions in the position set includes: selecting the i-th test sequence from the M test sequences when the number of positions in the position set meets a preset threshold.

[0050] Step S304: Remove the first test sequence and the second test sequence from the multiple test sequences to obtain a target test sequence, wherein the first test sequence is a test sequence that fails hard decoding; the second test sequence is a test sequence that succeeds hard decoding and is N-1 test sequences among N test sequences with the same flip position after hard decoding; wherein N is a positive integer greater than 1:

[0051] As previously mentioned, conventional BCH soft-decision decoding requires error detection for all p test sequences, consuming significant resources. Therefore, to facilitate implementation and reduce resource consumption, the p test sequences are screened in step S304 of this embodiment. Specifically, the results of hard decoding of the p test sequences fall into three categories: hard decoding failure, hard decoding success with an error position, and hard decoding success with no error position. Test sequences with hard decoding failures are directly removed, while test sequences with hard decoding success and no error position are retained as valid test sequences. The remaining test sequences with successful decoding but error positions are further determined to determine whether they overlap with other test sequences. This overlap occurs because if all unreliable positions match the error positions flipped by hard decoding, the test sequence with the flipped error position will overlap with the remaining test sequences after hard decoding. Therefore, only one of these duplicate test sequences needs to be retained.

[0052] The test sequence removal method is described by taking the original codeword (239, 256) BCH codeword as an example, wherein the unreliable bit Q of the original codeword is 8, the error correction capability t is 2, and when the parity check value P is 0, X is 2; when P is 1, X is 1 / 3. The algorithm simulation data shows that the number of remaining valid codewords retained after the deduplication logic is less than half of the original number, which effectively reduces the resource consumption of subsequent decoding. Figure 7 is a flow chart of the test sequence removal method according to an embodiment of the present disclosure. As shown in Figure 7, for any test sequence, the number of flipped bits (i.e., the number of flipped code elements) and their positions, the current error position, the decoding flag (used to identify the hard decoding result of the test sequence), and the intermediate parameter X of the test sequence are used as input parameters to determine whether the test sequence (i.e., the current test sequence in Figure 7) is removed. Specifically, the removal method includes the following steps:

[0053] Step S701, determine the hard decoding result; if the hard decoding result is a hard decoding failure, remove the test sequence; if the hard decoding result is a hard decoding success with no error location, execute step S706; if the hard decoding result is a hard decoding success with an error location, execute step S702.

[0054] Step S702: Determine whether the error position and the unreliable bit are in the same position. If so, proceed to step S703; otherwise, proceed to step S706. The error position corresponds to the position of the target symbol in the above embodiment, i.e., the position of the symbol with the decoding error after hard decoding of the test sequence.

[0055] Step S703: Determine whether all unreliable bits have not been flipped. If so, execute step S705; otherwise, execute step S704.

[0056] In step S704, it is determined whether the maximum value of the flipped unreliable bits is less than the minimum value at which the unreliable bits coincide with the error positions. If so, the test sequence is removed. If not, step S705 is executed. The coincidence of the unreliable bits and the error positions corresponds to the target sub-symbol in the above embodiment.

[0057] Step S705 , determine whether the sum of the number of flipped unreliable bits and the number of positions where unreliable bits are identical to error positions is equal to an intermediate parameter X; if so, remove the test sequence; otherwise, execute step S706 .

[0058] Step S706: retain the inner product of the test sequence.

[0059] Referring to Figures 4-6, the reason why the test sequence is removed is explained by taking a branch in the deduplication implementation process as an example. When a test sequence flips three positions in total after attempting hard decoding, namely unreliable bit 2, unreliable bit 4, and unreliable bit 6, this test sequence is repeated with a test sequence that directly flips the three positions of unreliable bit 2, unreliable bit 4, and unreliable bit 6 and decodes successfully without errors. Therefore, it meets the conditions for removal.

[0060] The number of test sequences to be decoded is closely related to the complexity of soft decoding and resource consumption. Therefore, by removing repeated test sequences and reducing the number of test sequences, the complexity of subsequent functional modules can be reduced.

[0061] Step S306 : performing decoding and error correction on the data to be decoded based on the target test sequence.

[0062] In step S306 of this embodiment, the steps include: calculating a Euclidean distance between each target test sequence and a hard decision sequence based on soft values ​​of flipped unreliable bits and hard decoding error positions corresponding to the target test sequence; determining an optimal test sequence and a suboptimal test sequence from the target test sequences based on the Euclidean distance; and performing decoding and error correction on the data to be decoded based on the optimal test sequence and the suboptimal test sequence.

[0063] Through the above steps, since the test sequences that failed hard decoding and the test sequences that succeeded hard decoding but contained errors are removed from multiple test sequences, and decoding is then performed based on the removed target test sequences, the problems of time-consuming decoding error correction and high hardware complexity in related technologies can be solved, thereby effectively reducing the number of test sequences and reducing the complexity of subsequent decoding function modules.

[0064] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present disclosure.

[0065] This embodiment also provides a data decoding and error correction device for implementing the above-mentioned embodiments and preferred embodiments. Details already described will not be repeated. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0066] FIG8 is a structural block diagram of a data decoding and error correction device according to an embodiment of the present disclosure. As shown in FIG8 , the data decoding device 800 includes: a determination module 810 , a removal module 820 and a decoding module 830 .

[0067] A determination module 810 is configured to determine a plurality of test sequences based on soft information of the data to be decoded;

[0068] a removal module 820 configured to remove a first test sequence and a second test sequence from the plurality of test sequences to obtain a target test sequence, wherein the first test sequence is a test sequence in which hard decoding fails; and the second test sequence is a test sequence in which hard decoding succeeds and N-1 test sequences among N test sequences in which flip positions are the same after hard decoding;

[0069] The error correction module 830 is configured to perform decoding and error correction on the data to be decoded based on the target test sequence.

[0070] The above embodiments of the present disclosure may be applied to the OFEC algorithm scheme in the OPENROADM standard.

[0071] Through the above steps, during the soft decoding process, the first test sequence and the second test sequence in all test sequences will be removed. Thereafter, when decoding and error correction are performed on the data to be decoded, only the target test sequence needs to be calculated, without the need to calculate all the test sequences. This reduces the decoding complexity and delay of the entire soft decoding, as well as the complexity of the subsequent decoding function modules.

[0072] It should be noted that each of the above modules can be implemented via software or hardware. The latter can be implemented in the following ways, but is not limited to: all of the above modules are located in the same processor; or, the above modules are located in different processors in any combination. In actual implementation, the module naming and functional division in the above data decoding device can be adjusted according to actual circumstances, as long as the steps of the data decoding method in the above embodiment can be implemented. These details will not be repeated here.

[0073] For example, the data decoding device in the above embodiment can be a decoder or computing device including a processor, a memory, and a functional module. The function of each module in the above embodiment can be implemented by an independent processor, or all modules or part of the modules can also share a processor. When the data decoding device receives soft information of the data to be decoded, it can execute the process instructions set in the functional module through the processor, thereby completing the functions of each module and performing decoding and error correction on the data to be decoded.

[0074] The decoding methods, decoding error correction methods, or data decoding devices of the above-described embodiments can be applied to various types of communication devices, such as optical modules in large data center equipment, optical modules in mobile Internet devices, and optical modules in Internet of Things devices, thereby implementing decoding and error correction of decoded data in various application scenarios. These communication devices receive data to be decoded and execute the above-described decoding methods or various embodiments of the decoding error correction methods.

[0075] Figure 9 is a block diagram of the hardware structure of a communication device that runs a decoding method or a decoding error correction method according to an embodiment of the present disclosure. As shown in Figure 9, the communication device 90 may include one or more (only one is shown in Figure 9) processors 902 (the processor 902 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 904 for storing data. Optionally, the above-mentioned communication device may also include a transmission device 906 and an input and output device 908 for communication functions. It will be understood by those skilled in the art that the structure shown in Figure 9 is only for illustration and does not limit the structure of the above-mentioned communication device. For example, the communication device 90 may also include more or fewer components than those shown in Figure 9, or have a different configuration with equivalent functions or more functions than those shown in Figure 9.

[0076] The memory 904 can be used to store computer programs, for example, software programs and modules of application software, such as the computer programs corresponding to the decoding method or decoding error correction method in the embodiments of the present disclosure. The processor 902 executes various functional applications and data processing by running the computer programs stored in the memory 904, that is, implementing the above-mentioned methods. The memory 904 may include a high-speed random access memory and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 904 may further include a memory remotely located relative to the processor 902, and these remote memories may be connected to the communication device 90 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0077] The transmission device 906 is used to receive or send data via a network. Specific examples of the aforementioned network may include a wired or wireless network provided by the communication provider of the communication device 90 .

[0078] An embodiment of the present disclosure further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above method embodiments when run.

[0079] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0080] An embodiment of the present disclosure further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0081] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0082] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0083] Obviously, those skilled in the art should understand that the modules or steps of the present disclosure described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present disclosure is not limited to any particular combination of hardware and software.

[0084] The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations of the present disclosure are possible. Any modifications, equivalent substitutions, or improvements made within the principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A data decoding and error correction method, comprising: determining a plurality of test sequences based on soft information of the data to be decoded; Removing a first test sequence and a second test sequence from the multiple test sequences to obtain a target test sequence, wherein the first test sequence is a test sequence that fails hard decoding; and the second test sequence is N-1 test sequences among N test sequences that succeed in hard decoding and have the same flip position after hard decoding; wherein N is a positive integer greater than 1; Decoding and error correction are performed on the data to be decoded based on the target test sequence.

2. The method according to claim 1, wherein Multiple test sequences are determined based on the soft information of the data to be decoded, including: Determining the decoding credibility of each codeword in the to-be-decoded data based on the soft information, and obtaining Q codewords with the lowest decoding credibility, where Q is a positive integer; Determining positions of the Q code elements in the data to be decoded as unreliable bits of the data to be decoded; One or more unreliable bits in the data to be decoded are flipped respectively, and the multiple test sequences are determined based on the data to be decoded after the unreliable bits are flipped respectively.

3. The method according to claim 2, wherein: Before removing the first test sequence and the second test sequence from the plurality of test sequences, the method further includes: Inputting the plurality of test sequences into a decoder to obtain hard decoding results of the plurality of test sequences; determining, from the hard decoding results of the plurality of test sequences, a target hard decoding result for a target symbol indicating a decoding error; The N test sequences having the same flip position after hard decoding are selected from the M test sequences corresponding to the target hard decoding results.

4. The method according to claim 3, wherein: Screening out the N test sequences having the same flip position after hard decoding from the M test sequences corresponding to the target hard decoding results includes: When the position of the target symbol in the i-th test sequence is the same as the unreliable bit, determining whether all the unreliable bits are flipped; wherein the value of i is 0, 1, 2, ..., M in sequence; In a case where all the unreliable bits are not flipped, selecting the i-th test sequence from the M test sequences according to the number of identical positions, and using the i-th test sequence as one of the N test sequences; In the case where a flipped unreliable bit exists among all the unreliable bits, the i-th test sequence is screened out from the M test sequences based on a position relationship between a target sub-codeword and the flipped unreliable bit, and the i-th test sequence is used as one of the N test sequences, wherein the target sub-codeword is a codeword corresponding to the same position in the target codeword.

5. The method according to claim 4, wherein Screening the i-th test sequence from the M test sequences according to the number of the identical positions includes: When the number of the identical positions of the i-th test sequence meets a preset threshold, the i-th test sequence is selected from the M test sequences.

6. The method according to claim 4, wherein: Screening out the i-th test sequence from the M test sequences according to a position relationship between a target sub-symbol and a position of the flipped unreliable bit includes: When the position relationship of the i-th test sequence does not satisfy a preset position condition, the i-th test sequence is screened out from the M test sequences.

7. The method according to claim 4, wherein: Screening out the i-th test sequence from the M test sequences according to the positional relationship between the flipped unreliable bits and the sub-target symbols comprises: When the position relationship of the i-th test sequence satisfies a preset position condition, taking a union of the flipped unreliable bits and the target sub-symbol positions to obtain a position set; The i-th test sequence is selected from the M test sequences based on the number of positions in the position set.

8. The method according to claim 7, wherein: Filtering the i-th test sequence from the M test sequences based on the number of positions in the position set includes: When the number of positions in the position set meets a preset threshold, the i-th test sequence is selected from the M test sequences.

9. A data decoding and error correction device, comprising: a determination module configured to determine a plurality of test sequences based on soft information of the data to be decoded; a removal module configured to remove a first test sequence and a second test sequence from the multiple test sequences to obtain a target test sequence, wherein the first test sequence is a test sequence that fails hard decoding; and the second test sequence is a test sequence that succeeds hard decoding and is N-1 test sequences among N test sequences with the same flip position after hard decoding; The error correction module is configured to perform decoding and error correction on the data to be decoded based on the target test sequence.

10. A computer-readable storage medium having a computer program stored therein, wherein: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method according to any one of claims 1 to 8 when executing the computer program.

12. A computer program product, comprising a computer program and instructions, wherein when the computer program and instructions are executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

Images