Method and apparatus for manufacturing semiconductor device

Abstract

According to the present invention, a two-dimensional material thin film is formed by annealing a transition metal using, as a chalcogen starting material, an organic starting material that contains carbon, and a carbon layer is appropriately formed on the upper layer of the two-dimensional material thin film. Disclosed is a method for manufacturing a semiconductor device, the method including: a step for forming a transition metal-containing film; and a step for forming a two-dimensional material thin film by annealing the transition metal-containing film in a chalcogen atmosphere, in which an organic starting material that contains carbon is used as a chalcogen starting material, and changing the transition metal-containing film into a chalcogenide form, and also forming a carbon layer on the upper layer of the two-dimensional material thin film.

Description

Semiconductor device manufacturing method and manufacturing apparatus

[0001] The present disclosure relates to a method and apparatus for manufacturing a semiconductor device.

[0002] Patent Literature 1 (PTL 1) discloses techniques related to atomic layer deposition, particularly a method for forming a two-dimensional metal chalcogenide thin film using laser-assisted atomic layer deposition. In this patent Literature 1, a metal-containing molecular layer is adhered to the surface of a heated substrate using an atomic layer deposition (ALD) process. The metal-containing molecular layer is then reacted with a chalcogenide-containing radical precursor gas supplied using a plasma to form a two-dimensional amorphous metal chalcogenide thin film, which is then laser-annealed to form a two-dimensional crystalline metal chalcogenide thin film.

[0003] Japanese Patent Application Publication No. 2017-61743

[0004] The technology according to the present disclosure forms a two-dimensional material thin film by annealing a transition metal using an organic raw material containing carbon as a chalcogen raw material, and also appropriately forms a carbon layer on the top layer.

[0005] One aspect of the present disclosure is a method for manufacturing a semiconductor device, the method including: forming a transition metal-containing film; and annealing the transition metal-containing film in a chalcogen atmosphere using an organic raw material containing carbon as a chalcogen raw material to chalcogenize the transition metal-containing film and form a two-dimensional material thin film; and forming a carbon layer on top of the two-dimensional material thin film.

[0006] By annealing a transition metal using an organic material containing carbon as a chalcogen material, a two-dimensional material thin film can be formed, and a carbon layer can be appropriately formed on the film.

[0007] Fig. 1 is a plan view showing an outline of the configuration of a wafer processing apparatus according to the present embodiment; Fig. 2 is a schematic cross-sectional view of a laminated structure required when a two-dimensional material is used as a channel of a transistor; Fig. 3 is a schematic cross-sectional view of a process for forming a laminated structure using a two-dimensional material; Fig. 4 is a flow diagram showing a process for forming a laminated structure using a two-dimensional material; Fig. 5 is a schematic cross-sectional view of a case where a two-dimensional material thin film and a carbon layer are applied to a wiring structure; Fig. 6 is a schematic explanatory view showing a method for forming a carbon layer at an end of a two-dimensional material thin film.

[0008] In the manufacturing process of semiconductor devices, two-dimensional materials are attracting attention as a semiconductor material that can overcome the limitations of miniaturization after silicon. For example, when using two-dimensional materials as the channel of a transistor, it is known that the surface of two-dimensional materials has fewer defects that adversely affect electrical conduction than silicon, etc., making them useful in terms of electrical conduction.

[0009] Two-dimensional materials include graphene and MoS ２ (Molybdenum sulfide), MoSe ２ (Molybdenum selenide), MoTe ２ (Molybdenum telluride), WSe ２ (tungsten selenide), WTe ２ Known examples of such materials include transition metal dichalcogenides (TMDCs) such as tungsten telluride (TTA). When using a two-dimensional material as a channel of a transistor or the like, the two-dimensional material can be formed by transfer or chemical vapor deposition (CVD), and a conductive contact electrode layer that contacts the channel can be deposited by vacuum deposition.

[0010] However, the CVD method requires a long time for film formation, and various devices are required to build the stacked structure later, which poses challenges in terms of manufacturing cost and time. Furthermore, in transistors and other devices, the optimal combination with the contact electrode layer when using two-dimensional materials as the channel remains an issue, and there is a need to establish a method for building device structures using two-dimensional materials.

[0011] The technology disclosed herein has been developed in consideration of the above circumstances, and involves forming a two-dimensional material thin film by annealing a transition metal using an organic material containing chalcogen, and then appropriately forming a carbon film on top of the thin film. Then, a carbon layer is efficiently formed as a contact electrode layer together with the channel. Hereinafter, a wafer processing apparatus as a substrate processing apparatus according to this embodiment, and a method for forming a two-dimensional material thin film and a carbon film on top of the thin film, will be described with reference to the drawings. Note that in this specification and the drawings, elements having substantially the same functional configuration are designated by the same reference numerals, and redundant description will be omitted.

[0012] <Wafer Processing Apparatus> First, a wafer processing apparatus according to this embodiment will be described. Fig. 1 is a plan view showing an outline of the configuration of a wafer processing apparatus 1 according to this embodiment. The wafer processing apparatus 1 performs processes such as etching, film formation, and heat treatment (annealing) on ​​a wafer W as a substrate.

[0013] 1, the wafer processing apparatus 1 has a configuration in which an atmospheric section 10 and a reduced pressure section 11 are integrally connected via load lock modules 20 and 21. The atmospheric section 10 includes an atmospheric module that performs a desired process on a wafer W in an atmospheric pressure atmosphere. The reduced pressure section 11 includes a reduced pressure module that performs a desired process on a wafer W in a reduced pressure atmosphere.

[0014] The load lock modules 20, 21 are provided to connect a loader module 30 (described later) in the atmospheric section 10 to a transfer module 50 (described later) in the reduced pressure section 11 via a gate valve (not shown). The load lock modules 20, 21 are configured to temporarily hold a wafer W. The load lock modules 20, 21 are also configured so that the interior thereof can be switched between an atmospheric pressure atmosphere and a reduced pressure atmosphere (vacuum state).

[0015] The atmospheric section 10 has a loader module 30 equipped with a wafer transfer mechanism 40 (described later), and a load port 32 on which a FOUP 31 capable of storing a plurality of wafers W is placed. Note that an orienter module (not shown) for adjusting the horizontal orientation of the wafer W, a storage module (not shown) for storing a plurality of wafers W, and the like may be provided adjacent to the loader module 30.

[0016] The loader module 30 is made up of a rectangular housing, and the interior of the housing is maintained at atmospheric pressure. A plurality of, for example, five load ports 32 are arranged side by side on one side that constitutes the long side of the housing of the loader module 30. The load lock modules 20 and 21 are arranged side by side on the other side that constitutes the long side of the housing of the loader module 30.

[0017] A wafer transfer mechanism 40 for transferring a wafer W is provided inside the loader module 30. The wafer transfer mechanism 40 includes a transfer arm 41 that holds and moves the wafer W, a rotary table 42 that rotatably supports the transfer arm 41, and a rotary table 43 on which the rotary table 42 is mounted. Also, a guide rail 44 extending in the longitudinal direction of the loader module 30 is provided inside the loader module 30. The rotary table 43 is provided on the guide rail 44, and the wafer transfer mechanism 40 is configured to be movable along the guide rail 44.

[0018] The decompression unit 11 has a transfer module 50 that simultaneously transfers wafers W, and a processing module 60 that performs desired processing on the wafers W transferred from the transfer module 50. The interiors of the transfer module 50 and the processing module 60 are each maintained in a reduced pressure atmosphere. A plurality of processing modules 60, for example, six processing modules 60, are provided for one transfer module 50. In the following description, the six processing modules 60 may be referred to as processing modules 60a to 60f, respectively. Note that the number and arrangement of the processing modules 60 are not limited to those in this embodiment and can be set as desired.

[0019] The transfer module 50 is made of a housing having a polygonal interior (pentagonal in the illustrated example), and as described above, is connected to the load lock modules 20 and 21. The transfer module 50 transfers the wafer W loaded into the load lock module 20 to one of the processing modules 60, where the wafer W is subjected to the desired processing, and then transfers the wafer W to the atmospheric section 10 via the load lock module 21.

[0020] The processing modules 60 perform processes such as etching, film formation, and heat treatment. The processing modules 60 can be arbitrarily selected to perform processes according to the purpose of wafer processing. The processing modules 60 are connected to the transfer module 50 via gate valves 61. In the following description, the six gate valves 61 may be referred to as gate valves 61a to 61f for the processing modules 60a to 60f, respectively.

[0021] A wafer transfer mechanism 70 for transferring a wafer W is provided inside the transfer module 50. The wafer transfer mechanism 70 includes a transfer arm 71 that holds and moves the wafer W, a rotary table 72 that rotatably supports the transfer arm 71, and a rotary table 73 on which the rotary table 72 is mounted. Also, a guide rail 74 extending in the longitudinal direction of the transfer module 50 is provided inside the transfer module 50. The rotary table 73 is provided on the guide rail 74, and the wafer transfer mechanism 70 is configured to be movable along the guide rail 74.

[0022] In the transfer module 50, the transfer arm 71 receives the wafer W held in the load lock module 20 and transfers it to the processing module 60. The transfer arm 71 also holds the wafer W that has been subjected to the desired processing and transfers it to the load lock module 21.

[0023] Next, wafer processing performed using the wafer processing apparatus 1 configured as above will be described.

[0024] First, the FOUP 31 containing a plurality of wafers W is placed on the load port 32 .

[0025] Next, the wafer W is removed from the FOUP 31 by the wafer transfer mechanism 40 and loaded into the load lock module 20. Once the wafer W is loaded into the load lock module 20, the inside of the load lock module 20 is sealed and depressurized. Thereafter, the inside of the load lock module 20 and the inside of the transfer module 50 are connected to each other.

[0026] Next, the wafer W is held by the wafer transfer mechanism 70 and transferred from the load lock module 20 to the transfer module 50 .

[0027] Next, the gate valve 61 is opened, and the wafer W is loaded into the processing module 60 by the wafer transfer mechanism 70. Thereafter, the gate valve 61 is closed, and the desired processing is performed on the wafer W in the processing module 60. An example of the processing performed on the wafer W will be described later.

[0028] Next, the gate valve 61 is opened, and the wafer W is unloaded from the processing module 60 by the wafer transfer mechanism 70. Thereafter, the gate valve 61 is closed.

[0029] Next, the wafer W is loaded into the load lock module 21 by the wafer transfer mechanism 70. When the wafer W is loaded into the load lock module 21, the inside of the load lock module 21 is sealed and opened to the atmosphere. Thereafter, the inside of the load lock module 21 and the inside of the loader module 30 are connected to each other.

[0030] Next, the wafer W is held by the wafer transfer mechanism 40, and is returned from the load lock module 21 to the FOUP 31 via the loader module 30 and accommodated therein. In this way, a series of wafer processing steps in the wafer processing apparatus 1 is completed.

[0031] <Configuration of stacked structure> Figure 2 is a schematic cross-sectional view of a stacked structure 100 required when using a two-dimensional material as a transistor channel. The stacked structure 100 has a so-called stacked nanosheet structure, with the two-dimensional material as the channel. Note that a plurality of stacked structures 100 may be formed in an island shape on the wafer W, and Figure 2 illustrates a case where three stacked structures 100 are formed on the wafer W.

[0032] 2, in the stacked structure 100, a gate electrode 103, a gate insulating film 105, a two-dimensional material thin film 110, and a gate insulating film 105 are stacked on a wafer W in this order from the bottom up. Although not shown, a region on the surface of the wafer W that is in direct contact with the gate electrode 103 has insulating properties. The wafer W itself may be made of an insulator, or an insulating film may be formed on the surface of the wafer W. Then, a structure composed of the gate electrode 103, the gate insulating film 105, the two-dimensional material thin film 110, and the gate insulating film 105 is repeatedly stacked in three layers, and the gate electrode 103 is formed in the uppermost layer. That is, the two-dimensional material thin film 110 serving as a channel is arranged so that the gate insulating film 105 and the gate electrode 103 surround it.

[0033] As shown in the figure, the ends (left and right ends 110a, 110b in the figure) of the two-dimensional material thin film 110 are formed to protrude from other layers (gate electrode 103, gate insulating film 105) in each stacked structure 100. For example, in a field effect transistor with a general structure, one of these ends 110a, 110b is connected to the source and the other is connected to the drain, and the current flowing from the source to the drain is controlled by the gate (gate electrode 103).

[0034] Any method can be used to form the stacked structure 100. For example, the gate electrode 103, the gate insulating film 105, and the two-dimensional material thin film 110 can be formed by methods such as physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), vacuum deposition, sputtering, etc. Then, the stacked structure 100 can be formed by patterning the formed gate electrode 103, gate insulating film 105, and two-dimensional material thin film 110 into island shapes by etching.

[0035] <Method for Forming Laminated Structure and Carbon Layer> The processing module 60 can perform various processes on the wafer W, such as a film formation process, an etching process, and a heat treatment (hereinafter also referred to as an annealing process). As an example, the process of forming a basic laminated structure containing a transition metal on the wafer W and performing an annealing process will be described below with reference to the drawings. Note that, when multiple (e.g., six) processing modules 60a to 60f are provided as shown in FIG. 1 , the module for performing the laminated structure formation process on the wafer W and the module for performing the annealing process may be arbitrarily selected from the multiple processing modules 60. For example, the laminated structure formation process may be performed in at least one of the multiple processing modules 60, and the annealing process may be performed in another processing module 60. Furthermore, each processing step may be performed in a different processing module 60, or may be performed consecutively in the same processing module 60. In other words, the wafer processing apparatus 1 including the processing modules 60 may function as a forming apparatus for forming a two-dimensional material thin film or a carbon layer thereon.

[0036] 3 is a schematic cross-sectional view of a process for forming a stacked layer structure 200 using a two-dimensional material. Also, FIG. 4 is a flow diagram showing a process for forming a stacked layer structure 200 using a two-dimensional material. As described above, when forming a stacked layer structure 100 using a two-dimensional material as a transistor channel, it is assumed that multiple layers, such as the same gate electrode 103, gate insulating film 105, and two-dimensional material thin film 110, are stacked. However, to avoid complicating the explanation and to explain more basic principles, a basic stacked layer structure 200 including a carbon layer will be illustrated and described here.

[0037] First, as shown in Fig. 3(a), a wafer W is prepared, and as shown in Fig. 3(b), a sacrificial film 203 is formed (step S1), and a transition metal-containing film 205 is formed thereon (step S2). The material of the sacrificial film 203 is arbitrary, and for example, SiO ２ The transition metal-containing film 205 may be made of any material as long as it contains a transition metal such as Mo or W, and may be an oxide containing Mo or W, or a nitride containing Mo or W, such as MoO ３ , Mo ２ N.W. ２ O ３ , WN.

[0038] Next, as shown in FIG. 3( c), annealing is performed in a chalcogen atmosphere (steps S3 and S4). As a result, the transition metal-containing film 205 is chalcogenized and transformed into a two-dimensional material thin film 210 as shown in FIG. 3( d). Furthermore, in the annealing process, an organic material containing carbon is used as the chalcogen material. As a result, as the annealing process progresses, a carbon layer 215 is formed on the two-dimensional material thin film 210 as shown in FIG. 3( d) (step S5).

[0039] When forming the carbon layer 215, the formation rate and thickness of the carbon layer 215 can be changed depending on the conditions of the annealing treatment. For example, the formation of the carbon layer 215 can be promoted by continuing to supply the chalcogen source even after the transition metal-containing film 205 is chalcogenized during the annealing treatment. Furthermore, the thickness of the carbon layer 215 is determined depending on the time of the annealing treatment.

[0040] The conditions for the annealing process in the chalcogen atmosphere are not particularly limited. For example, in a module among the multiple process modules 60 that performs the annealing process, the processing chamber into which the target wafer W is loaded is purged with Ar, and the chalcogen source is continuously supplied from the start of the temperature increase, and the annealing process is performed. As an example, the annealing process may be performed under conditions of atmospheric pressure during the process, Ar as a diluent gas, a partial pressure of the chalcogen source of about 1%, and a temperature of 800° C.

[0041] The chalcogen raw material may be any organic raw material containing chalcogen. Examples include diethyl sulfur and diethyl disulfur, which contain sulfur (S) as the chalcogen. Other examples include diethyl selenium and diethyl diselenium, which contain selenium (Se) as the chalcogen. Other examples include diethyl tellurium and diethyl ditellurium, which contain tellurium (Te) as the chalcogen. The quality of the carbon layer 215 can be adjusted by changing the carbon source in the organic raw material containing chalcogen.

[0042] In the stacked structure 200 according to the present embodiment, the sacrificial film 203 is formed directly on the wafer W, but the present invention is not limited to this. In one embodiment, a gate electrode or a gate insulating film may be formed instead of the sacrificial film 203 as long as the material can withstand annealing treatment in a chalcogen atmosphere.

[0043] <Application to Wiring Structures of Semiconductor Devices> As described above with respect to the stacked layer structure 200, a stacked layer structure containing a transition metal can be formed on a wafer W and then annealed to form a carbon layer on the two-dimensional material thin film. This two-dimensional material thin film and carbon layer can be used in a variety of applications, for example, as a diffusion barrier film in the wiring structure of a semiconductor device. Conventionally, Ta and TaN have been known as diffusion barrier films in semiconductor devices, with thicknesses of, for example, 4 to 5 nm. However, by using a two-dimensional material thin film, it is expected that a fine diffusion barrier film, for example, 2 nm or less in thickness, with similar barrier performance can be realized.

[0044] 5 is a schematic cross-sectional view of a wiring structure 220 in which a two-dimensional material thin film and a carbon layer are applied. As shown in FIG. 5 , the wiring structure 220 includes a low-dielectric-constant interlayer insulating film 222, a two-dimensional material thin film 210, a carbon layer 215, and a metal wiring layer 225, which are formed in this order. Specific examples of materials for the metal wiring layer 225 include metals such as Cu and Al. For example, when the metal wiring layer 225 is formed of Cu, the two-dimensional material thin film 210 functions as a Cu diffusion barrier, and the carbon layer 215 has the effect of reducing water permeability. That is, by forming a layered structure containing a transition metal and performing an annealing treatment, it is possible to form a diffusion barrier layer that reduces water permeability and has sufficient barrier performance.

[0045] <Application to Transistor Channel and Contact Electrode Layer> Furthermore, as described above with reference to FIG. 2 , when forming the laminated structure 100 so as to be applied to, for example, a field-effect transistor with a general structure, a carbon layer may be formed on the ends 110 a, 110 b connected to the source and drain of the channel. FIG. 6 is a schematic diagram illustrating a method for forming a carbon layer on the ends 110 a, 110 b of the two-dimensional material thin film 110 using a two-dimensional material as the transistor channel. In the following description, elements having the same functional configuration may be described using the same reference numerals with reference to FIGS. 2 and 3 . Also, FIG. 6( a ) is a schematic diagram of the laminated structure 100 viewed from the side, and FIG. 6( b ) is a schematic diagram of the laminated structure 100 viewed obliquely from above.

[0046] In the stacked structure 100, the ends 110a and 110b of the two-dimensional material thin film 110 are formed to protrude from the side surfaces of the stacked structure 100 (see FIG. 2). When forming the stacked structure 100, the transition metal-containing film 230 is formed in advance so as to be surrounded by the gate electrode 103.

[0047] The following is an example of a method for forming the layered structure 100 for use in a field-effect transistor. First, multiple layers of transition metal-containing films 205 and sacrificial films 203 are stacked based on the method described in FIG. 3 . The sacrificial films 203 are then removed by wet etching or other means. The entire transition metal-containing film 205 is then annealed using an organic material containing carbon as a chalcogen source. This results in a two-dimensional material thin film with a carbon layer formed on the entire surface. Then, a protective film is formed on only the portion of the two-dimensional material thin film with the carbon layer formed on the surface, which is required as a contact electrode layer, and the carbon layer on the other portions is removed, and then the protective film is removed. After removing the protective film, a gate insulating film 105 and a gate electrode 103 are formed on the portion of the two-dimensional material thin film not covered by the carbon layer. In this manner, a carbon layer 232 may be formed on only a portion of the end (protruding portion 230a) of the transition metal-containing film 230, as shown in FIG. 6(b).

[0048] As another example of a method for forming the laminated structure 100, when the entire transition metal-containing film 205 is annealed, a protective film is formed only on a portion required as a contact electrode layer, and a chalcogen source not containing carbon (e.g., H ２ S). This alters the transition metal-containing film 205, resulting in a two-dimensional material thin film without a carbon layer on the surface. Next, the protective film is removed from the portion required as a contact electrode layer, a protective film is formed on the remaining portion, and the entire film is annealed using an organic material containing carbon as a chalcogen material. As described above, a gate insulating film 105 and a gate electrode 103 are formed on the portion of the two-dimensional material thin film that is not covered with the carbon layer. In this way, a carbon layer 232 may be formed on the surface of only a portion of the end (protruding portion 230a) of the transition metal-containing film 230, as shown in FIG. 6(b).

[0049] By this method, the transition metal-containing film 230 is chalcogenized and transformed into the two-dimensional material thin film 110, and a carbon layer 232 is formed on the surface of the protruding portion 230 a. Note that this carbon layer 232 may be formed so as to surround the entire periphery of the protruding portion 230 a, for example.

[0050] In this way, when forming the stacked structure 100 to be applied to a transistor, the carbon layer 232 is formed as a contact electrode layer by forming the carbon layer 232 on the surface of the two-dimensional material thin film 110 at the ends 110a and 110b. That is, by adopting a technique in which the two-dimensional material thin film 110 is formed as a channel in a transistor and the carbon layer 232 is formed as a contact electrode layer, the channel and the contact electrode layer are efficiently formed.

[0051] <Effects of the technology of the present disclosure> As described above, the method of forming a two-dimensional material thin film and forming a carbon film on top of it, which is performed by the wafer processing apparatus 1 according to the technology of the present disclosure, can improve the efficiency of manufacturing costs and manufacturing time compared to conventional film formation methods such as CVD methods.

[0052] 5, when applied to the wiring structure of a semiconductor device, a two-dimensional material thin film 210 can be formed as a Cu diffusion barrier film, and a carbon layer 215 can be formed to reduce water permeability. That is, it is possible to form a diffusion barrier layer that reduces water permeability and has sufficient barrier performance.

[0053] Furthermore, for example, as shown in FIG. 6, when applied to a transistor, the channel and the contact electrode layer can be efficiently formed by forming a two-dimensional material thin film 110 as the channel and a carbon layer 232 as the contact electrode layer.

[0054] In the above description, the wafer processing apparatus 1 can perform various processes such as film formation, etching, and annealing on the wafer W. In this case, a plurality of processing modules 60 may be used, each performing a different process, or a plurality of processes may be performed in the same module.

[0055] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The above-described embodiments may be omitted, substituted, or modified in various ways without departing from the scope and spirit of the appended claims. For example, the components of the above-described embodiments may be arbitrarily combined. Such an arbitrary combination naturally provides the functions and effects of each of the components involved in the combination, and also provides other functions and effects that are apparent to those skilled in the art from the description of this specification.

[0056] Furthermore, the effects described herein are merely descriptive or exemplary and are not limiting. In other words, the technology according to the present disclosure may achieve other effects that are apparent to those skilled in the art from the description of this specification, in addition to or in place of the above-described effects.

[0057] The following configuration examples also fall within the technical scope of the present disclosure. (1) A method for manufacturing a semiconductor device, comprising: forming a transition metal-containing film; and annealing the transition metal-containing film in a chalcogen atmosphere using an organic raw material containing carbon as a chalcogen raw material to chalcogenize the transition metal-containing film and form a two-dimensional material thin film, and forming a carbon layer on the two-dimensional material thin film. (2) The method according to (1), in which the transition metal-containing film is formed of an oxide containing Mo or W or a nitride containing Mo or W. (3) The method according to (1) or (2), in which the organic raw material containing carbon as a chalcogen raw material is selected from diethyl sulfur, diethyl disulfur, diethyl selenium, diethyl diselenium, diethyl tellurium, or diethyl ditellurium. (4) The method for manufacturing a semiconductor device according to any one of (1) to (3), wherein the semiconductor device includes a wiring structure, the wiring structure being configured by stacking an interlayer insulating film, a two-dimensional material thin film, a carbon layer, and a metal wiring layer in this order, the two-dimensional material thin film and the carbon layer being formed by a step of forming the transition metal-containing film and a step of forming a carbon layer on the two-dimensional material thin film. (5) The method for manufacturing a semiconductor device according to (4), wherein the metal wiring layer is formed of Cu or Al, and the two-dimensional material thin film is configured as a diffusion barrier film for Cu or Al. (6) The method for manufacturing a semiconductor device according to any one of (1) to (3), wherein the semiconductor device is a field effect transistor, and a stacked structure included in the field effect transistor includes a gate electrode, a gate insulating film, a two-dimensional material thin film, and a gate insulating film stacked on a substrate, the two-dimensional material thin film being configured as a channel, an end of the two-dimensional material thin film protruding from other layers, one end connected to a source and the other end connected to a drain, a carbon layer being formed on the surface of the end of the two-dimensional material thin film, and the carbon layer being configured as a contact electrode layer, and the two-dimensional material thin film and the carbon layer are formed by a step of forming the transition metal-containing film and a step of forming a carbon layer on the two-dimensional material thin film.(7) The method for manufacturing a semiconductor device according to (6), wherein the two-dimensional material thin film is formed by annealing the entire transition metal-containing film using an organic raw material containing carbon, and the contact electrode layer is configured by forming a protective film on an end of the two-dimensional material thin film having a carbon layer formed on its surface, removing the carbon layer from other portions, and then removing the protective film from the end of the two-dimensional material thin film. (8) The method for manufacturing a semiconductor device according to (6), wherein the two-dimensional material thin film is formed by annealing using a chalcogen raw material that does not contain carbon in a state where a protective film is formed on an end of the transition metal-containing film, and the contact electrode layer is configured by removing the protective film from an end of the two-dimensional material thin film that corresponds to the contact electrode layer, forming a protective film on other portions, and then annealing using an organic raw material containing carbon as a chalcogen raw material. (9) A semiconductor device manufacturing apparatus comprising: a module for forming a transition metal-containing film; and a module for annealing the transition metal-containing film in a chalcogen atmosphere using an organic raw material containing carbon as a chalcogen raw material, thereby chalcogenizing the transition metal-containing film to form a two-dimensional material thin film, and forming a carbon layer on top of the two-dimensional material thin film.

[0058] 205 Transition metal-containing film 210 Two-dimensional material thin film 215 Carbon layer

Claims

1. A method for manufacturing a semiconductor device, comprising: a step of forming a transition metal-containing film; and a step of annealing the transition metal-containing film in a chalcogen atmosphere using an organic raw material containing carbon as a chalcogen raw material to chalcogenize the transition metal-containing film and form a two-dimensional material thin film, and forming a carbon layer on top of the two-dimensional material thin film.

2. The method according to claim 1, wherein the transition metal-containing film is formed of an oxide containing Mo or W or a nitride containing Mo or W.

3. The method according to claim 1, wherein the organic material containing carbon as the chalcogen material is selected from the group consisting of diethylsulfur, diethyldisulfur, diethylselenium, diethyldiselen, diethyltellurium, and diethylditellurium.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device includes a wiring structure, the wiring structure being configured by stacking an interlayer insulating film, a two-dimensional material thin film, a carbon layer, and a metal wiring layer in this order, and the two-dimensional material thin film and the carbon layer are formed by a step of forming the transition metal-containing film and a step of forming a carbon layer on top of the two-dimensional material thin film.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the metal wiring layer is formed of Cu or Al, and the two-dimensional material thin film is configured as a diffusion prevention film for Cu or Al.

6. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a field effect transistor, wherein a stacked structure included in the field effect transistor includes a gate electrode, a gate insulating film, a two-dimensional material thin film, and a gate insulating film stacked on a substrate, wherein the two-dimensional material thin film is configured as a channel, wherein ends of the two-dimensional material thin film protrude from other layers, one connected to a source and the other connected to a drain, wherein a carbon layer is formed on the surface of the end of the two-dimensional material thin film, and wherein the carbon layer is configured as a contact electrode layer, wherein the two-dimensional material thin film and the carbon layer are formed by a step of forming the transition metal-containing film and a step of forming a carbon layer on top of the two-dimensional material thin film.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the two-dimensional material thin film is formed by subjecting the entire transition metal-containing film to an annealing treatment using an organic raw material containing carbon, and the contact electrode layer is formed by forming a protective film on an end of the two-dimensional material thin film having a carbon layer formed on its surface, removing the carbon layer from other portions, and then removing the protective film on the end of the two-dimensional material thin film.

8. The method for manufacturing a semiconductor device according to claim 6, wherein the two-dimensional material thin film is formed by performing an annealing treatment using a chalcogen source that does not contain carbon in a state where a protective film is formed on an end of the transition metal-containing film, and the contact electrode layer is formed by removing the protective film from an end of the two-dimensional material thin film that corresponds to the contact electrode layer, forming a protective film on the other portion, and performing an annealing treatment using an organic source that contains carbon as the chalcogen source.

9. An apparatus for manufacturing a semiconductor device, comprising: a module for forming a transition metal-containing film; and a module for annealing the transition metal-containing film in a chalcogen atmosphere using an organic raw material containing carbon as a chalcogen raw material, thereby chalcogenizing the transition metal-containing film to form a two-dimensional material thin film, and forming a carbon layer on top of the two-dimensional material thin film.

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