Display device

Abstract

This display device includes: a plurality of pixels disposed in a display area; a plurality of scan lines connected to the pixels; a plurality of data lines connected to the pixels; a plurality of vertical initialization lines connected to the pixels; and a common line disposed in a non-display area that is around the display area, wherein the common line is adjacent to a first side of the display area and a first round corner of the display area, and the vertical initialization lines may be adjacent to the first side and the first round corner and connected to the common line, and may extend in a second direction from the common line.

Description

display device

[0001] The present invention relates to a display device.

[0002] Electronic devices that typically provide images to users, such as smartphones, digital cameras, laptops, navigation systems, and smart televisions, include a display device for displaying the images. The display device generates images and presents the generated images to the user through a display screen.

[0003] A display device includes a plurality of pixels for generating an image and a plurality of lines connected to the pixels. The pixels are driven by receiving driving signals through the lines.

[0004] With the recent development of display devices with various shapes, display devices can have a rounded-cornered rectangular shape, rather than a rectangular shape, with rounded corners. The display area of ​​a display device can have a rounded-cornered rectangular shape depending on the shape of the display device. There is a need for technology development to easily connect lines to pixels arranged at the rounded corners.

[0005] An object of the present invention is to provide a display device capable of improving display quality by uniformly forming line resistances for pixels in a display area.

[0006] A display device according to an embodiment of the present invention may include a plurality of pixels arranged in a display area, a plurality of scan lines connected to the pixels, a plurality of data lines connected to the pixels, a plurality of vertical initialization lines connected to the pixels, and a common line arranged in a non-display area around the display area. The display area may include a first side extending in a first direction, a second side extending in a second direction intersecting the first direction adjacent to one end of the first side, and a first round corner connecting the one end of the first side to an end of the second side adjacent to the one end of the first side. The common line may be adjacent to the first side and the first round corner, and the vertical initialization lines may be adjacent to the first side and the first round corner, connected to the common line, and extend from the common line in the second direction.

[0007] A display device according to an embodiment of the present invention may include a plurality of pixels arranged in a display area, a plurality of scan lines connected to the pixels, a plurality of data lines connected to the pixels, a common line arranged in a non-display area around the display area, and a plurality of vertical initialization lines connected to the pixels. The display area may include a first side extending in a first direction, a second side and a third side extending in a second direction intersecting the first direction, respectively adjacent to both ends of the first side, a first round corner connecting the first side and the second side, and a second round corner connecting the first side and the second side. The common line may be adjacent to the first side, the first round corner, and the second round corner, and the vertical initialization lines may be adjacent to the first side, the first round corner, and the second round corner, connected to the common line, and extend in the second direction from the common line.

[0008] A display device according to an embodiment of the present invention may include a plurality of pixels arranged in a display area including sides of a rectangle extending in a first direction and a second direction intersecting the first direction and round corners connecting the sides, a plurality of scan lines connected to the pixels, a plurality of data lines connected to the pixels, a common line arranged in a non-display area around the display area and adjacent to at least one side and at least one round corner, and a plurality of vertical initialization lines arranged adjacent to the at least one side and the at least one round corner and connected to the pixels and the common line. The vertical initialization lines may extend from the common line in a direction intersecting an extension direction of the at least one side.

[0009] According to an embodiment of the present invention, vertical initialization lines connected to pixels are arranged not only on a first side extending in a first direction, but also on first and second round corners connected to both ends of the first side, so that line resistances for pixels in a display area can be uniformly formed. Accordingly, the display quality of the display device can be improved.

[0010] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0011] FIG. 2 is a drawing illustrating an example of a cross-section of the display device illustrated in FIG. 1.

[0012] FIG. 3 is a drawing illustrating an example of a cross-section of the display panel illustrated in FIG. 2.

[0013] Figure 4 is a block diagram of the display device shown in Figure 1.

[0014] FIG. 5 is a diagram showing an equivalent circuit of one of the pixels illustrated in FIG. 4.

[0015] FIG. 6 is a timing diagram of scanning signals and emission signals for explaining the operation of the pixel illustrated in FIG. 5.

[0016] FIG. 7 is a drawing exemplarily showing a cross-section of the light-emitting element, the first transistor, the fourth transistor, and the sixth transistor of the pixel illustrated in FIG. 5.

[0017] Figure 8 is a plan view of the display panel illustrated in Figure 4.

[0018] FIG. 9 is a separate drawing showing the configuration of the first initialization line arranged on the display panel illustrated in FIG. 8.

[0019] FIG. 10 is a separate drawing showing the configuration of the second initialization line arranged on the display panel illustrated in FIG. 8.

[0020] FIG. 11a is an enlarged view of a portion of the display panel adjacent to the first round corner illustrated in FIG. 9.

[0021] FIG. 11b is an enlarged view of a portion of the display panel adjacent to the second round corner illustrated in FIG. 9.

[0022] FIGS. 11c and 11d are enlarged views of portions of the display panel adjacent to the third round corners illustrated in FIG. 9.

[0023] Figure 12a is a plan view showing the connection configuration of the first and second initialization lines and pixels at the center of the display panel.

[0024] Figure 12b is a plan view showing the connection configuration of the first and second initialization lines and pixels adjacent to the first round corner.

[0025] FIG. 13 is a drawing showing a cross-section of a first vertical initialization line and a first horizontal initialization line corresponding to one of the contact holes illustrated in FIG. 9.

[0026] Fig. 14 is a drawing showing the configuration of a comparison display panel according to a comparative example.

[0027] FIGS. 15 to 17 are drawings showing configurations of common lines according to various embodiments of the present invention.

[0028] In this specification, when it is said that a component (or region, layer, portion, etc.) is “on,” “connected to,” or “coupled to” another component, it means that it can be directly disposed / connected / coupled to the other component, or a third component may be disposed between them.

[0029] Identical drawing numbers indicate identical components. Furthermore, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the purpose of effectively illustrating the technical content.

[0030] “And / or” includes any combination of one or more of the associated constructs that can be defined.

[0031] While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component." Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0032] Additionally, terms such as "below," "lower," "above," and "upper" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the relevant technical context, and unless explicitly defined herein, they should not be interpreted in an idealized or overly formal sense.

[0034] It should be understood that terms such as "include" or "have" are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0035] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0036] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0037] Referring to FIG. 1, a display device (DD) according to an embodiment of the present invention may have long sides extending parallel to a first direction (DR1) and short sides extending parallel to a second direction (DR2) intersecting the first direction (DR1). The corners of the display device (DD) connecting the long sides and the short sides may have a curved shape. The corners of the display device (DD) having a curved shape may be defined as rounded corners. The shape of the display device (DD) may be defined as a rounded corner rectangle.

[0038] Hereinafter, a direction substantially perpendicular to the plane defined by the first direction (DR1) and the second direction (DR2) is defined as a third direction (DR3). In addition, in this specification, the meaning of when viewed on a plane is defined as a state viewed from the third direction (DR3).

[0039] The front surface of the display device (DD) can be defined as a display surface (DS) and can have a plane defined by a first direction (DR1) and a second direction (DR2). Images (IM) generated in the display device (DD) can be provided to a user through the display surface (DS).

[0040] A display surface (DS) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The display area (DA) may display an image, and the non-display area (NDA) may not display an image. The non-display area (NDA) may define a border of the display device (DD) that surrounds the display area (DA) and is printed in a predetermined color.

[0041] The display area (DA) may have a rounded-corner rectangular shape, depending on the shape of the display device (DD). For example, the display area (DA) may include rectangular sides extending in a first direction (DR1) and a second direction (DR2) and rounded corners connecting the sides. Of the four sides, the sides extending in the first direction (DR1) may be defined as long sides, and of the four sides, the sides extending in the second direction (DR2) may be defined as short sides.

[0042] The display device (DD) can detect inputs applied from outside the display device (DD). For example, the display device (DD) can detect a first input by a touch pen (PEN) and a second input by a touch (TC). The touch pen (PEN) can be defined as an input device.

[0043] A touch pen (PEN) may be an active pen that outputs signals. The second input by touch (TC) may include various forms of external input, such as a part of the user's body, light, heat, or pressure.

[0044] The display device (DD) and the touch pen (PEN) can communicate bidirectionally. The display device (DD) can provide an uplink signal to the touch pen (PEN). For example, the uplink signal can include, but is not limited to, information such as panel information and protocol version.

[0045] The touch pen (PEN) can provide a downlink signal to the display device (DD). The downlink signal may include a synchronization signal or status information of the touch pen (PEN). For example, the downlink signal may include, but is not limited to, coordinate information of the touch pen (PEN), battery information of the touch pen (PEN), tilt information of the touch pen (PEN), and / or various information stored in the touch pen (PEN).

[0046] The display device (DD) can be used in large electronic devices such as televisions, monitors, or outdoor billboards. Furthermore, the display device (DD) can also be used in small and medium-sized electronic devices such as personal computers, laptop computers, personal digital assistants, car navigation systems, game consoles, smartphones, tablets, or cameras. However, these are presented as exemplary embodiments only, and the display device (DD) can be used in other electronic devices without departing from the scope of the present invention.

[0047] FIG. 2 is a drawing illustrating an example of a cross-section of the display device illustrated in FIG. 1.

[0048] For example, FIG. 2 shows a cross-section of the display device (DD) as viewed from the second direction (DR2).

[0049] Referring to FIG. 2, the display device (DD) may include a display panel (DP), an input sensing unit (ISP), an anti-reflection layer (RPL), a window (WIN), a panel protection film (PPF), and first and second adhesive layers (AL1, AL2).

[0050] The display panel (DP) according to one embodiment of the present invention may be an emissive display panel. For example, the display panel (DP) may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots, quantum rods, and the like. Hereinafter, the display panel (DP) is described as an organic light-emitting display panel.

[0051] An input sensing unit (ISP) may be arranged on a display panel (DP). The input sensing unit (ISP) may include a plurality of sensing units (e.g., a plurality of sensors or sensor electrodes) for sensing an external input in a capacitive manner. The input sensing unit (ISP) may be manufactured directly on the display panel (DP) during the manufacturing of the display device (DD). However, the present invention is not limited thereto, and the input sensing unit (ISP) may be manufactured as a separate panel from the display panel (DP) and attached to the display panel (DP) by an adhesive layer.

[0052] An anti-reflection layer (RPL) may be disposed on the input sensing portion (ISP). The anti-reflection layer (RPL) may be manufactured directly on the input sensing portion (ISP) during the manufacturing of the display device (DD). However, the present invention is not limited thereto, and the anti-reflection layer (RPL) may be manufactured as a separate panel and attached to the input sensing portion (ISP) by an adhesive layer.

[0053] An anti-reflection layer (RPL) can be defined as an external light anti-reflection film. The anti-reflection layer (RPL) can reduce the reflectance of external light incident from above the display device (DD) toward the display panel (DP). The external light can be prevented from being perceived by the user due to the anti-reflection layer (RPL).

[0054] When external light directed toward the display panel (DP) is reflected by the display panel (DP) and re-exposed to an external user, the user may perceive the external light, as if it were a mirror. To prevent this phenomenon, for example, the anti-reflection layer (RPL) may include a plurality of color filters that display the same color as the pixels of the display panel (DP).

[0055] Color filters can filter external light to the same color as the pixels. In this case, the external light may not be visible to the user. However, the present invention is not limited thereto, and the anti-reflection layer (RPL) may include a phase retarder and / or a polarizer to reduce the reflectance of external light.

[0056] The window (WIN) can be placed on an anti-reflection layer (RPL). The window (WIN) can protect the display panel (DP), the input sensing unit (ISP), and the anti-reflection layer (RPL) from external scratches and impacts.

[0057] A panel protection film (PPF) may be placed under the display panel (DP). The panel protection film (PPF) may protect the lower portion of the display panel (DP). The panel protection film (PPF) may include a flexible plastic material such as polyethylene terephthalate (PET).

[0058] A first adhesive layer (AL1) is disposed between a display panel (DP) and a panel protection film (PPF), and the display panel (DP) and the panel protection film (PPF) can be bonded to each other by the first adhesive layer (AL1). A second adhesive layer (AL2) is disposed between a window (WIN) and an anti-reflection layer (RPL), and the window (WIN) and the anti-reflection layer (RPL) can be bonded to each other by the second adhesive layer (AL2).

[0059] FIG. 3 is a drawing illustrating an example of a cross-section of the display panel illustrated in FIG. 2.

[0060] For example, FIG. 3 shows a cross-section of the display panel (DP) viewed from the second direction (DR2).

[0061] Referring to FIG. 3, the display panel (DP) may include a substrate (SUB), a circuit element layer (DP-CL) disposed on the substrate (SUB), a display element layer (DP-OLED) disposed on the circuit element layer (DP-CL), and a thin film encapsulation layer (TFE) disposed on the display element layer (DP-OLED).

[0062] The substrate (SUB) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The substrate (SUB) may include glass or a flexible plastic material such as polyimide (PI). A display element layer (DP-OLED) may be disposed on the display area (DA).

[0063] A plurality of pixels may be arranged on the circuit element layer (DP-CL) and the display element layer (DP-OLED). Each pixel may include a transistor arranged on the circuit element layer (DP-CL) and a light-emitting element arranged on the display element layer (DP-OLED) and connected to the transistor.

[0064] A thin film encapsulation layer (TFE) can be disposed on a circuit element layer (DP-CL) to cover a display element layer (DP-OLED). The thin film encapsulation layer (TFE) can protect pixels from moisture, oxygen, and external foreign substances.

[0065] Figure 4 is a block diagram of the display device shown in Figure 1.

[0066] Referring to FIG. 4, the display device (DD) may include a display panel (DP), a timing controller (TC), a scan driver (SDV), a data driver (DDV), a light emission driver (EDV), and a voltage generator (VG).

[0067] The display panel (DP) may include a plurality of scanning lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm), a plurality of light emitting lines (EML1 to EMLm), a plurality of data lines (DL1 to DLn), and a plurality of pixels (PX). m and n are natural numbers.

[0068] The pixels (PX) can be electrically connected to scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm), emission lines (EML1 to EMLm), and data lines (DL1 to DLn), respectively. Each of the pixels (PX) can be electrically connected to four corresponding scan lines, one corresponding data line, and one corresponding emission line.

[0069] The scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) may include a plurality of initialization scan lines (GIL1 to GILm), a plurality of compensation scan lines (GCL1 to GCLm), a plurality of write scan lines (GWL1 to GWLm), and a plurality of bias scan lines (GBL1 to GBLm).

[0070] Each of the pixels (PX) can be connected to a corresponding one of the initialization scan lines (GIL1 to GILm), a corresponding one of the compensation scan lines (GCL1 to GCLm), a corresponding one of the write scan lines (GWL1 to GWLm), and a corresponding one of the bias scan lines (GBL1 to GBLm).

[0071] The scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) are connected to the scan driver (SDV), extend in a first direction (DR1), and can be arranged in a second direction (DR2). The light emitting lines (EML1 to EMLm) are connected to the light emitting driver (EDV), extend in a first direction (DR1), and can be arranged in a second direction (DR2). The data lines (DL1 to DLn) are connected to the data driver (DDV), extend in a second direction (DR2), and can be arranged in the first direction (DR1).

[0072] The scanning driver (SDV), the emission driver (EDV), and the data driver (DDV) can be substantially arranged on the display panel (DP), and this configuration will be illustrated in FIG. 8 below.

[0073] The timing controller (TC) can receive a video signal (RGB) and a control signal (CTRL). The timing controller (TC) can generate a video data signal (DAS) by converting the data format of the video signal (RGB) to meet the interface specifications with the data driver (DDV). In response to the control signal (CTRL), the timing controller (TC) can output a scan control signal (SCS), a data control signal (DCS), and an emission control signal (ECS).

[0074] A voltage generator (VG) can generate voltages required for the operation of a display panel (DP). The voltage generator (VG) can generate a first driving voltage (ELVDD), a second driving voltage (ELVSS), a first initialization voltage (VINT), and a second initialization voltage (VAINT). The first driving voltage (ELVDD), the second driving voltage (ELVSS), the first initialization voltage (VINT), and the second initialization voltage (VAINT) can be applied to pixels (PX).

[0075] The scan driver (SDV) can receive a scan control signal (SCS) from a timing controller (TC). The scan driver (SDV) can output scan signals to scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) in response to the scan control signal (SCS). The scan signals can be applied to pixels (PX) through the scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm).

[0076] The data driver (DDV) can receive a data control signal (DCS) and an image data signal (DAS) from a timing controller (TC). The data driver (DDV) can convert the image data signal (DAS) into data signals and output them. The data signals can be defined as analog voltages corresponding to the grayscale levels of the image data signal (DAS). The data signals can be applied to the pixels (PX) through data lines (DL1 to DLn).

[0077] The emission driver (EDV) can receive an emission control signal (ECS) from a timing controller (TC). The emission driver (EDV) can output emission signals to the emission lines (EML1 to EMLm) in response to the emission control signal (ECS). The emission signals can be applied to the pixels (PX) through the emission lines (EML1 to EMLm).

[0078] Pixels (PX) can receive data voltages in response to scanning signals. Pixels (PX) can display images by emitting light with a brightness corresponding to the data voltages in response to light emission signals.

[0079] FIG. 5 is a diagram showing an equivalent circuit of one of the pixels illustrated in FIG. 4.

[0080] For example, FIG. 5 illustrates a pixel (PXij) connected to the jth data line (DLj), the ith scan lines (GWLi, GCLi, GILi, GBLi), and the ith emission line (EMLi). i and j are natural numbers.

[0081] Referring to FIG. 5, a pixel (PXij) may include a pixel circuit (PC) and a light-emitting element (OLED) connected to the pixel circuit (PC). The pixel circuit (PC) may drive the light-emitting element (OLED).

[0082] The pixel circuit (PC) may include a plurality of transistors (T1 to T8) and a capacitor (CST). The transistors (T1 to T8) and the capacitor (CST) may control the amount of current flowing to the light-emitting element (OLED). The light-emitting element (OLED) may generate light having a predetermined brightness depending on the amount of current supplied.

[0083] The ith write scan line (GWLi) can receive the ith write scan signal (GWi), the ith compensation scan line (GCLi) can receive the ith compensation scan signal (GCi), the ith initialization scan line (GILi) can receive the ith initialization scan signal (GIi), the ith bias scan line (GBLi) can receive the ith bias scan signal (GBi), and the ith emission line (EMLi) can receive the ith emission signal (EMi).

[0084] A pixel (PXij) can be connected to a j-th data line (DLj), an i-th write scan line (GWLi), an i-th compensation scan line (GCLi), an i-th initialization scan line (GILi), an i-th bias scan line (GBLi), an i-th emission line (EMLi), a first initialization line (VIL1), a second initialization line (VIL2), a bias line (VBL), and first and second power lines (PL1, PL2).

[0085] The first initialization line (VIL1) can receive the first initialization voltage (VINT), and the second initialization line (VIL2) can receive the second initialization voltage (VAINT). The bias line (VBL) can receive the bias voltage (VBIAS). The first power line (PL1) can receive the first driving voltage (ELVDD), and the second power line (PL2) can receive the second driving voltage (ELVSS).

[0086] Each of the transistors (T1 to T8) may include a source electrode, a drain electrode, and a gate electrode. Hereinafter, in FIG. 5, for convenience, one of the source electrode and the drain electrode is defined as the first electrode, and the other is defined as the second electrode. In addition, the gate electrode is defined as the control electrode.

[0087] The transistors (T1 to T8) may include first to eighth transistors (T1 to T8). The first, second, and fifth to eighth transistors (T1, T2, T5 to T8) may be PMOS transistors. The third and fourth transistors (T3, T4) may be NMOS transistors.

[0088] The first transistor (T1) may be defined as a driving transistor, the second transistor (T2) may be defined as a switching transistor, the third transistor (T3) may be defined as a compensation transistor, the fourth transistor (T4) and the seventh transistor (T7) may be defined as initialization transistors, the fifth transistor (T5) and the sixth transistor (T6) may be defined as light-emitting control transistors, and the eighth transistor (T8) may be defined as a bias transistor.

[0089] The light-emitting element (OLED) may be defined as an organic light-emitting element. The light-emitting element (OLED) may include an anode (AE) and a cathode (CE). The anode (AE) may receive a first driving voltage (ELVDD) through the fifth, first, and sixth transistors (T5, T1, T6). The first driving voltage (ELVDD) may be applied to the pixel circuit (PC) through the first power line (PL1).

[0090] The cathode (CE) can receive a second driving voltage (ELVSS) having a lower level than the first driving voltage (ELVDD). The second driving voltage (ELVSS) can be applied to the pixel circuit (PC) through a second power line (PL2).

[0091] A first transistor (T1) is disposed between a fifth transistor (T5) and a sixth transistor (T6), and can be connected to the fifth transistor (T5) and the sixth transistor (T6). The first transistor (T1) can be connected to a first power line (PL1) through the fifth transistor (T5), and to an anode (AE) through the sixth transistor (T6).

[0092] The first transistor (T1) may include a first electrode connected to the first power line (PL1) via a fifth transistor (T5), a second electrode connected to the anode (AE) via a sixth transistor (T6), and a control electrode connected to the first node (N1).

[0093] A first electrode of a first transistor (T1) may be connected to a fifth transistor (T5), and a second electrode of the first transistor (T1) may be connected to a sixth transistor (T6). The first transistor (T1) may control the amount of current flowing to the light-emitting element (OLED) according to the voltage of the first node (N1) applied to the control electrode of the first transistor (T1).

[0094] A second transistor (T2) may be disposed between the first transistor (T1) and the j-th data line (DLj) and may be connected to the first transistor (T1) and the j-th data line (DLj). The second transistor (T2) may include a first electrode connected to the j-th data line (DLj), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to the i-th write scan line (GWLi).

[0095] The second transistor (T2) can be turned on by the i-th write scan signal (GWi) applied through the i-th write scan line (GWLi) to electrically connect the j-th data line (DLj) and the first electrode of the first transistor (T1). The second transistor (T2) can perform a switching operation of providing the data voltage (VD) (corresponding to the aforementioned data signal) applied through the j-th data line (DLj) to the first electrode of the first transistor (T1).

[0096] A third transistor (T3) may be connected to the second electrode of the first transistor (T1) and the first node (N1). The third transistor (T3) may include a first electrode connected to the second electrode of the first transistor (T1), a second electrode connected to the first node (N1), and a control electrode connected to the ith compensation scan line (GCLi).

[0097] The third transistor (T3) can be turned on by the i-th compensation scan signal (GCi) applied through the i-th compensation scan line (GCLi) to electrically connect the second electrode of the first transistor (T1) and the control electrode of the first transistor (T1). When the third transistor (T3) is turned on, the first transistor (T1) and the third transistor (T3) can be connected in a diode form.

[0098] A fourth transistor (T4) may be connected to a first node (N1). The fourth transistor (T4) may include a first electrode connected to the first node (N1), a second electrode connected to a first initialization line (VIL1), and a control electrode connected to an ith initialization scan line (GILi). The fourth transistor (T4) may be turned on by an ith initialization scan signal (GIi) applied through the ith initialization scan line (GILi) and may provide a first initialization voltage (VINT) applied through the first initialization line (VIL1) to the first node (N1).

[0099] The fifth transistor (T5) may include a first electrode connected to the first power line (PL1), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to the ith light emitting line (EMLi).

[0100] The sixth transistor (T6) may include a first electrode connected to the second electrode of the first transistor (T1), a second electrode connected to the anode (AE), and a control electrode connected to the ith light emitting line (EMLi).

[0101] The fifth transistor (T5) and the sixth transistor (T6) can be turned on by the ith light-emitting signal (EMi) applied through the ith light-emitting line (EMLi). The first driving voltage (ELVDD) is provided to the light-emitting element (OLED) by the turned-on fifth transistor (T5) and sixth transistor (T6), so that a driving current can flow to the light-emitting element (OLED). Therefore, the light-emitting element (OLED) can emit light.

[0102] The seventh transistor (T7) may include a first electrode connected to the anode (AE), a second electrode connected to the second initialization line (VIL2), and a control electrode connected to the ith bias scan line (GBLi). The seventh transistor (T7) may be turned on by the ith bias scan signal (GBi) applied through the ith bias scan line (GBLi), and may provide the second initialization voltage (VAINT) received through the second initialization line (VIL2) to the anode (AE) of the light-emitting element (OLED).

[0103] In an embodiment of the present invention, the second initialization voltage (VAINT) may have a different level from the first initialization voltage (VINT), but is not limited thereto and may have the same level as the first initialization voltage (VINT).

[0104] The seventh transistor (T7) can improve the black expression capability of the pixel (PXij). When the seventh transistor (T7) is turned on, the parasitic capacitor (not shown) of the light-emitting element (OLED) can be discharged. Therefore, when implementing black luminance, the light-emitting element (OLED) does not emit light due to the leakage current of the first transistor (T1), and thus the black expression capability can be improved.

[0105] The capacitor (CST) may include a first electrode connected to a first power line (PL1) and a second electrode connected to a first node (N1). When the fifth transistor (T5) and the sixth transistor (T6) are turned on, the amount of current flowing to the first transistor (T1) may be determined according to the voltage stored in the capacitor (CST).

[0106] The eighth transistor (T8) may include a first electrode connected to a bias line (VBL), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to an i-th bias scan line (GBLi).

[0107] The eighth transistor (T8) is turned on by the i-th bias scan signal (GBi) and can provide a bias voltage (VBIAS) applied through the bias line (VBL) to the first electrode of the first transistor (T1).

[0108] FIG. 6 is a timing diagram of scanning signals and emission signals for explaining the operation of the pixel illustrated in FIG. 5.

[0109] Referring to FIGS. 5 and 6, the i-th emission signal (EMi) can have a high level during a non-emission period (NLP) and a low level during a emission period (LP).

[0110] The activation period of each of the ith write scan signal (GWi) and the ith bias scan signal (GBi) can be defined as the low level of each of the ith write scan signal (GWi) and the ith bias scan signal (GBi).

[0111] The activation period of each of the ith compensation injection signal (GCi) and the ith initialization injection signal (GIi) can be defined as the high level of each of the ith compensation injection signal (GCi) and the ith initialization injection signal (GIi).

[0112] After the ith initialization scan signal (GIi) is activated, the ith compensation scan signal (GCi) and the ith write scan signal (GWi) may be activated. Thereafter, the ith bias scan signal (GBi) may be activated.

[0113] During the non-luminous period (NLP), the activated ith initialization scan signal (GIi), the ith compensation scan signal (GCi), the ith write scan signal (GWi), and the ith bias scan signal (GBi) can be applied to the pixel (PXij).

[0114] The ith initialization scan signal (GIi) may be applied to the fourth transistor (T4), thereby turning on the fourth transistor (T4). The first initialization voltage (VINT) may be provided to the node (N1) through the fourth transistor (T4). Accordingly, the first initialization voltage (VINT) may be applied to the control electrode of the first transistor (T1), and the first transistor (T1) may be initialized by the first initialization voltage (VINT). This operation may be defined as an initialization operation.

[0115] The ith write scan signal (GWi) may be applied to the second transistor (T2) to turn on the second transistor (T2). In addition, the ith compensation scan signal (GCi) may be applied to the third transistor (T3) to turn on the third transistor (T3).

[0116] The first transistor (T1) and the third transistor (T3) may be connected to each other in a diode form. In this case, a compensation voltage (Vd-Vth) that is reduced by the threshold voltage (Vth) of the first transistor (T1) from the data voltage (VD) supplied through the data line (DLj) may be applied to the control electrode of the first transistor (T1). This operation may be defined as a write operation (or programming operation) and a compensation operation.

[0117] A first voltage (ELVDD) and a compensation voltage (Vd-Vth) can be applied to the first electrode and the second electrode of the capacitor (CST), respectively. A charge corresponding to a voltage difference between the first electrode of the capacitor (CST) and the second electrode of the capacitor (CST) can be stored in the capacitor (CST).

[0118] Thereafter, the i-th bias scan signal (GBi) may be applied to the seventh and eighth transistors (T7, T8), so that the seventh and eighth transistors (T7, T8) may be turned on. The second initialization voltage (VAINT) may be provided to the anode (AE) through the seventh transistor (T7), so that the anode (AE) may be initialized with the second initialization voltage (VAINT). The bias voltage (VBIAS) may be applied to the first electrode of the first transistor (T1) through the eighth transistor (T8).

[0119] Thereafter, during the emission period (LP), the ith emission signal (EMi) may be applied to the fifth transistor (T5) and the sixth transistor (T6) through the ith emission line (EMLi), so that the fifth transistor (T5) and the sixth transistor (T6) may be turned on. In this case, a driving current (Id) corresponding to a voltage difference between the voltage of the control electrode of the first transistor (T1) and the first voltage (ELVDD) may be generated. The driving current (Id) may be provided to the light-emitting element (OLED) through the sixth transistor (T6), so that the light-emitting element (OLED) may emit light.

[0120] During the light emission period (LP), the gate-source voltage (Vgs) of the first transistor (T1) by the capacitor (CST) can be defined as Vgs = ELVDD - (Vd-Vth). The current and voltage relationship of the first transistor (T1) is Id = (1 / 2)μCox(W / L)(Vgs-Vth) 2 can be defined as follows. This equation is the current and voltage relationship of a general transistor.

[0121] When Vgs is substituted into the current and voltage relationship, the threshold voltage (Vth) is removed, and the driving current (Id) is the square of the first voltage (ELVDD) minus the data voltage (VD) (ELVDD-Vd). 2 can be proportional to. Therefore, the driving current (Id) can be determined regardless of the threshold voltage (Vth) of the first transistor (T1). This operation can be defined as a threshold voltage compensation operation.

[0122] A bias voltage (VBIAS) can be applied to the first electrode of the first transistor (T1) through the eighth transistor (T8) before the light-emitting element (OLED) emits light after the threshold voltage of the first transistor (T1) is compensated. The shift of the hysteresis curve of the first transistor (T1) can be suppressed by the bias voltage (VBIAS). This operation can be defined as a bias operation.

[0123] FIG. 7 is a drawing exemplarily showing a cross-section of the light-emitting element, the first transistor, the fourth transistor, and the sixth transistor of the pixel illustrated in FIG. 5.

[0124] Referring to FIG. 7, the light emitting element (OLED) may include a first electrode (AE), a second electrode (CE), a hole control layer (HCL), an electron control layer (ECL), and an emission layer (EML). The first electrode (AE) may be the anode (AE) illustrated in FIG. 5, and the second electrode (CE) may be the cathode (CE) illustrated in FIG. 5. The second electrode (CE) may be disposed on the first electrode (AE), and the hole control layer (HCL), the electron control layer (ECL), and the emission layer (EML) may be disposed between the first electrode (AE) and the second electrode (CE).

[0125] The first, fourth, and sixth transistors (T1, T4, T6) and the light-emitting element (OLED) may be arranged on the substrate (SUB). The display area (DA) may include a light-emitting area (LEA) corresponding to the pixel (PXij) and a non-light-emitting area (NLEA) adjacent to the light-emitting area (LEA). The light-emitting element (OLED) may be arranged in the light-emitting area (LEA).

[0126] A lower metal layer (BML) may be disposed on a substrate (SUB). The lower metal layer (BML) may overlap a first transistor (T1). Although not illustrated, a constant voltage may be applied to the lower metal layer (BML). When a constant voltage is applied to the lower metal layer (BML), the threshold voltage (Vth) value of the first transistor (T1) disposed on the lower metal layer (BML) may be maintained without change.

[0127] The lower metal layer (BML) can block light incident on the first transistor (T1) from below the lower metal layer (BML). The lower metal layer (BML) can include a reflective metal. The lower metal layer (BML) can be omitted.

[0128] A buffer layer (BFL) is disposed on a substrate (SUB), and the buffer layer (BFL) may be an inorganic layer. The buffer layer (BFL) may cover a lower metal layer (BML). A semiconductor layer (S1, A1, D1) of a first transistor (T1) and a semiconductor layer (S6, A6, D6) of a sixth transistor (T6) may be disposed on the buffer layer (BFL). The semiconductor layers (S1, A1, D1, S6, A6, D6) may include polysilicon. However, the present invention is not limited thereto, and the semiconductor layers (S1, A1, D1, S6, A6, D6) may include amorphous silicon.

[0129] The semiconductor layers (S1, A1, D1, S6, A6, D6) may be doped with an N-type dopant or a P-type dopant. The semiconductor layers (S1, A1, D1, S6, A6, D6) may include a high-doping region and a low-doping region. The conductivity of the high-doping region is greater than that of the low-doping region, and may substantially function as a source electrode and a drain electrode of the first and sixth transistors (T1, T6). The low-doping region may substantially correspond to an active (or channel) of the first and sixth transistors (T1, T6).

[0130] The first source region (S1), the first channel region (A1), and the first drain region (D1) of the first transistor (T1) may be formed from semiconductor layers (S1, A1, D1). The sixth source region (S6), the sixth channel region (A6), and the sixth drain region (D6) of the sixth transistor (T6) may be formed from semiconductor layers (S6, A6, D6). The first channel region (A1) may be disposed between the first source region (S1) and the first drain region (D1). The sixth channel region (A6) may be disposed between the sixth source region (S6) and the sixth drain region (D6).

[0131] A first insulating layer (INS1) may be disposed on a buffer layer (BFL) to cover the semiconductor layers (S1, A1, D1, S6, A6, D6). A first gate electrode (G1) (or control electrode) of a first transistor (T1) and a sixth gate electrode (G6) (or control electrode) of sixth transistors (T6) may be disposed on the first insulating layer (INS1). When viewed in plan view, the first gate electrode (G1) may overlap the first channel region (A1), and the sixth gate electrode (G6) may overlap the sixth channel region (A6).

[0132] Although not shown, the structure of the source region, channel region, drain region, and gate electrode of each of the second, fifth, and seventh transistors (T2, T5, T7) may be substantially the same as that of the first and sixth transistors (T1, T6).

[0133] A second insulating layer (INS2) may be disposed on the first insulating layer (INS1) to cover the first and sixth gate electrodes (G1, G6). A dummy electrode (DME) may be disposed on the second insulating layer (INS2). The dummy electrode (DME) is disposed on the first gate electrode (G1) and may overlap the first gate electrode (G1) when viewed in a plan view. The dummy electrode (DME) may form the aforementioned capacitor (CST) together with the first gate electrode (G1).

[0134] A third insulating layer (INS3) may be disposed on the second insulating layer (INS2) to cover the dummy electrode (DME). A semiconductor layer (S4, A4, D4) of the fourth transistor (T4) may be disposed on the third insulating layer (INS3). The semiconductor layers (S4, A4, D4) may include an oxide semiconductor formed of a metal oxide. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor.

[0135] The semiconductor layer (S4, A4, D4) may include a plurality of regions that are distinguished depending on whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, referred to as the reduced region) may have higher conductivity than the region where the metal oxide is not reduced (hereinafter, referred to as the non-reduced region). The reduced region may substantially function as a source electrode or a drain electrode of the fourth transistor (T4). The non-reduced region may substantially correspond to the active (or channel) of the fourth transistor (T4).

[0136] The fourth source region (S4), the fourth channel region (A4), and the fourth drain region (D4) of the fourth transistor (T4) may be formed from semiconductor layers (S4, A4, D4). The fourth channel region (A4) may be positioned between the fourth source region (S4) and the fourth drain region (D4).

[0137] A fourth insulating layer (INS4) may be disposed on the third insulating layer (INS3) to cover the semiconductor layers (S4, A4, D4). A fourth gate electrode (G4) of a fourth transistor (T4) may be disposed on the fourth insulating layer (INS4). When viewed in plan view, the fourth gate electrode (G4) may overlap the fourth channel region (A4).

[0138] A fifth insulating layer (INS5) may be disposed on the fourth insulating layer (INS4) to cover the fourth gate electrode (G4). Although not illustrated, the structure of the source region, channel region, drain region, and gate electrode of the third transistor (T3) may be substantially the same as that of the fourth transistor (T4).

[0139] The buffer layer (BFL) and the first to fifth insulating layers (INS1 to INS5) may include inorganic layers. For example, the buffer layer (BFL), the first insulating layer (INS1), and the fourth insulating layer (INS4) may include a silicon oxide layer, and the second insulating layer (INS2) may include a silicon nitride layer.

[0140] The third and fifth insulating layers (INS3, INS5) may include a plurality of inorganic insulating layers including different materials and stacked on each other. For example, the third insulating layer (INS3) may include a silicon nitride layer and a silicon oxide layer stacked sequentially, and the fifth insulating layer (INS5) may include a silicon oxide layer and a silicon nitride layer stacked sequentially. The thickness of each of the third and fifth insulating layers (INS3, INS5) may be greater than the thickness of each of the buffer layer (BFL) and the first, second, and fourth insulating layers (INS1, INS2, INS4).

[0141] A connection electrode (CNE) may be disposed between the sixth transistor (T6) and the light-emitting element (OLED). The connection electrode (CNE) may electrically connect the sixth transistor (T6) and the light-emitting element (OLED). The connection electrode (CNE) may include a first connection electrode (CNE1) and a second connection electrode (CNE2) disposed on the first connection electrode (CNE1).

[0142] The first connection electrode (CNE1) may be disposed on the fifth insulating layer (INS5) and connected to the sixth drain region (D6) through the first contact hole (CH1) defined in the first to fifth insulating layers (INS1 to INS5). A sixth insulating layer (INS6) may be disposed on the fifth insulating layer (INS5) to cover the first connection electrode (CNE1).

[0143] The second connection electrode (CNE2) may be disposed on the sixth insulating layer (INS6). The second connection electrode (CNE2) may be connected to the first connection electrode (CNE1) through a second contact hole (CH2) defined in the sixth insulating layer (INS6).

[0144] A seventh insulating layer (INS7) may be disposed on the sixth insulating layer (INS6) to cover the second connecting electrode (CNE2). The sixth and seventh insulating layers (INS6, INS7) may include an inorganic layer or an organic layer.

[0145] A first electrode (AE) may be disposed on the seventh insulating layer (INS7). The first electrode (AE) may be electrically connected to the second connection electrode (CNE2) through a third contact hole (CH3) defined in the seventh insulating layer (INS7).

[0146] A pixel defining layer (PDL) exposing a predetermined portion of the first electrode (AE) may be disposed on the first electrode (AE) and the seventh insulating layer (INS7). An opening (PX_OP) for exposing a predetermined portion of the first electrode (AE) may be defined in the pixel defining layer (PDL).

[0147] A hole control layer (HCL) may be disposed on the first electrode (AE) and the pixel defining layer (PDL). The hole control layer (HCL) may be disposed commonly in the light emitting area (LEA) and the non-light emitting area (NLEA). The hole control layer (HCL) may include a hole transport layer and a hole injection layer.

[0148] The emission layer (EML) may be disposed on the hole control layer (HCL). The emission layer (EML) may be disposed in an area corresponding to the opening (PX_OP). The emission layer (EML) may include an organic material and / or an inorganic material. The emission layer (EML) may generate light of any one of red, green, and blue.

[0149] An electron control layer (ECL) may be disposed on the emissive layer (EML) and the hole control layer (HCL). The electron control layer (ECL) may be disposed commonly in the emissive area (LEA) and the non-emissive area (NLEA). The electron control layer (ECL) may include an electron transport layer and an electron injection layer.

[0150] The second electrode (CE) may be disposed on the electronic control layer (ECL). The second electrode (CE) may be disposed commonly on the pixels (PX). That is, the second electrode (CE) may be disposed commonly on the light-emitting layers (EML) of the pixels (PX).

[0151] The layer from the buffer layer (BFL) to the seventh insulating layer (INS7) can be defined as a circuit element layer (DP-CL). The layer on which the light-emitting element (OLED) is arranged can be defined as a display element layer (DP-OLED).

[0152] A thin film encapsulation layer (TFE) may be disposed on a light-emitting element (OLED). The TFE may include sequentially stacked inorganic layers, organic layers, and inorganic layers. The inorganic layers include inorganic materials and may protect pixels from moisture / oxygen. The organic layers include organic materials and may protect pixels (PX) from foreign substances such as dust particles.

[0153] A first voltage (ELVDD) may be applied to the first electrode (AE), and a second voltage (ELVSS) may be applied to the second electrode (CE). Holes and electrons injected into the light-emitting layer (EML) combine to form excitons, and when the excitons transition to the ground state, the light-emitting element (OLED) may emit light. The light-emitting element (OLED) emits light, and an image may be displayed.

[0154] Figure 8 is a plan view of the display panel illustrated in Figure 4.

[0155] Fig. 4 is a drawing mainly showing the functional blocks of the display device (DD), and Fig. 8 is a drawing mainly showing the planar structure of the display panel (DP).

[0156] Referring to FIG. 8, the display device (DD) may include a display panel (DP), a scan driver (SDV), a plurality of data drivers (DDV), an emission driver (EDV), and a plurality of pads (PD). The display panel (DP) may have a rounded corner rectangular shape corresponding to the shape of the display device (DD).

[0157] The border of the display panel (DP) may have long sides extending parallel to a first direction (DR1) and short sides extending parallel to a second direction (DR2). The long sides and short sides of the display panel (DP) may correspond to sides of a rectangle. The border of the display panel (DP) may include rounded corners connecting the long sides and short sides of the display panel (DP). Each of the rounded corners may connect adjacent long sides and short sides.

[0158] A display panel (DP) may include a display area (DA) and a non-display area (NDA) arranged around the display area (DA) and surrounding the display area (DA). The display area (DA) may have a rounded corner rectangular shape corresponding to the shape of the display panel (DP).

[0159] To have a rounded corner rectangle shape, the display area (DA) may include first to fourth sides (SI1 to SI4) and first to third rounded corners (CR1 to CR3). The first to fourth sides (SI1 to SI4) may define four sides of the rectangle. The first to third rounded corners (CR1 to CR3) may define four rounded corners of the rectangle.

[0160] The first side (SI1) and the fourth side (SI4) may extend parallel to the first direction (DR1) and face each other in the second direction (DR2). The second side (SI2) and the third side (SI3) may extend parallel to the second direction (DR2) and face each other in the first direction (DR1). The first side (SI1) and the fourth side (SI4) may extend longer than the second side (SI2) and the third side (SI3). The first side (SI1) and the fourth side (SI4) may be defined as long sides, and the second side (SI2) and the third side (SI3) may be defined as short sides.

[0161] The second side (SI2) and the third side (SI3) may be adjacent to both ends of the first side (SI1) and may extend in the second direction (DR2). The second side (SI2) may be disposed adjacent to one end of the first side (SI1) and may extend in the second direction (DR2). The third side (SI3) may be disposed adjacent to the other end of the first side (SI1) and may extend in the second direction (DR2). One end of the second side (SI2) may be adjacent to one end of the first side (SI1), and one end of the third side (SI3) may be adjacent to the other end of the first side (SI1).

[0162] The fourth side (SI4) can extend in the first direction (DR1) adjacent to the other end of the second side (SI2) and the other end of the third side (SI3). One end of the fourth side (SI4) can be adjacent to the other end of the second side (SI2), and the other end of the fourth side (SI4) can be adjacent to the other end of the third side (SI3).

[0163] One end and the other end of the first side (SI1) may be defined as the two ends of the first side (SI1) that are opposite to each other in the first direction (DR1). One end and the other end of the second side (SI2) may be defined as the two ends of the second side (SI2) that are opposite to each other in the second direction (DR2). One end and the other end of the third side (SI3) may be defined as the two ends of the third side (SI3) that are opposite to each other in the second direction (DR2). One end and the other end of the fourth side (SI4) may be defined as the two ends of the fourth side (SI4) that are opposite to each other in the first direction (DR1).

[0164] In the first direction (DR1), the distance between the second side (SI2) and the third side (SI3) may be greater than the length of the first side (SI1) and the length of the fourth side (SI4). In the second direction (DR2), the distance between the first side (SI1) and the fourth side (SI4) may be greater than the length of the second side (SI2) and the length of the third side (SI3).

[0165] When viewed from the second direction (DR2), the first side (SI1) and the fourth side (SI4) can be positioned between the second side (SI2) and the third side (SI3). When viewed from the first direction (DR1), the second side (SI2) and the third side (SI3) can be positioned between the first side (SI1) and the fourth side (SI4).

[0166] The first round corner (CR1) can connect the first side (SI1) and the second side (SI2). For example, the first round corner (CR1) can connect one end of the adjacent first side (SI1) and one end of the second side (SI2). The first round corner (CR1) can have a curved shape that is convexly bent toward the non-display area (NDA).

[0167] The second round corner (CR2) can connect the first side (SI1) and the third side (SI3). For example, the second round corner (CR2) can connect the other end of the adjacent first side (SI1) and one end of the third side (SI3). The second round corner (CR2) can have a curved shape that is convexly bent toward the non-display area (NDA).

[0168] The two third round corners (CR3) can connect the opposite ends of the fourth side (SI4) to the other ends of the second side (SI2) and the third side (SI3), respectively. One third round corner (CR3) can connect the other ends of the adjacent second sides (SI2) and one end of the fourth side (SI4). The other third round corner (CR3) can connect the other ends of the adjacent third sides (SI3) and the other end of the fourth side (SI4). The third round corners (CR3) can have a curved shape that is convexly bent toward the non-display area (NDA).

[0169] The first round corner (CR1) and the second round corner (CR2) may have shapes that are symmetrical to each other in the first direction (DR1). The third round corners (CR3) may have shapes that are symmetrical to each other in the first direction (DR1). The first and second round corners (CR1, CR2) and the third round corners (CR3) may have shapes that are symmetrical to each other in the second direction (DR2).

[0170] A display panel (DP) may include a plurality of pixels (PX), a plurality of scan lines (SL1 to SLm), a plurality of data lines (DL1 to DLn), and a plurality of emission lines (EML1 to EMLm). The pixels (PX) may be arranged within a display area (DA). The pixels (PX) may be connected to the scan lines (SL1 to SLm), the data lines (DL1 to DLn), and the emission lines (EML1 to EMLm).

[0171] The scan lines (SL1 to SLm) may include the scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) illustrated in FIG. 4. For example, the ith scan line among the scan lines (SL1 to SLm) may include the ith write scan line (GWLi), the ith compensation scan line (GCLi), the ith initialization scan line (GILi), and the ith bias scan line (GBLi). Accordingly, the scan signals described above may be applied to the pixels (PX) through the scan lines (SL1 to SLm).

[0172] The data lines (DL1 to DLn) and the light emitting lines (EML1 to EMLm) may be the same as the data lines (DL1 to DLn) and the light emitting lines (EML1 to EMLm) illustrated in FIG. 4.

[0173] A scanning driver (SDV) and an emission driver (EDV) may be arranged in non-display areas (NDAs) adjacent to opposite sides of a display panel (DP) in a first direction (DR1). The scanning driver (SDV) may be adjacent to a second side (SI2), a first round corner (CR1), and a third round corner (CR3) connected to the second side (SI2). The emission driver (EDV) may be adjacent to a third side (SI3), a second round corner (CR2), and a third round corner (CR3) connected to the third side (SI3).

[0174] A portion of the scanning driver (SDV) adjacent to the first round corner (CR1) and a portion of the scanning driver (SDV) adjacent to the third round corner (CR3) connected to the second side (SI2) may have a curved shape. A portion of the emission driver (EDV) adjacent to the second round corner (CR2) and a portion of the emission driver (EDV) adjacent to the third round corner (CR3) connected to the third side (SI3) may have a curved shape.

[0175] The data driving units (DDV) illustrated in FIG. 4 may be provided in multiple numbers on the display panel (DP), as illustrated in FIG. 8. The data driving units (DDV) may be arranged in a non-display area (NDA) adjacent to one of the two opposite sides of the display panel (DP) in the second direction (DR2). When viewed in a plan view, the data driving units (DDV) may be adjacent to the lower side of the display panel (DP). For example, the data driving units (DDV) may be adjacent to the first side (SI1).

[0176] The scan lines (SL1 to SLm) may extend in a first direction (DR1) and be connected to the pixels (PX) and the scan driver (SDV). The data lines (DL1 to DLn) may extend in a second direction (DR2) and be connected to the pixels (PX) and the data driver (DDV). The emission lines (EML1 to EMLm) may extend in the first direction (DR1) and be connected to the pixels (PX) and the emission driver (EDV).

[0177] The data driving units (DDV) may be spaced apart from each other in the first direction (DR1). A predetermined number of data lines may be connected to each of the data driving units (DDV). By way of example, two data driving units (DDV) are illustrated, but the number of data driving units (DDV) is not limited thereto. For example, as the left and right areas of the display panel (DP) increase, the number of data driving units (DDV) may also increase.

[0178] The pads (PD) are arranged in a non-display area (NDA) adjacent to the bottom of the display panel (DP) and may be closer to the bottom of the display panel (DP) than the data drivers (DDV). The data drivers (DDV) may be connected to the pads (PD). The data lines (DL1 to DLn) may be connected to the data drivers (DDV), and the data drivers (DDV) may be connected to the pads (PD) corresponding to the data lines (DL1 to DLn).

[0179] The timing controller (TC) and voltage generator (VG) illustrated in FIG. 4 can be mounted on a printed circuit board and connected to pads (PD) through the printed circuit board.

[0180] FIG. 9 is a separate drawing illustrating the configuration of the first initialization line arranged in the display panel illustrated in FIG. 8. FIG. 10 is a separate drawing illustrating the configuration of the second initialization line arranged in the display panel illustrated in FIG. 8. FIG. 11a is an enlarged view of a portion of the display panel adjacent to the first round corner illustrated in FIG. 9. FIG. 11b is an enlarged view of a portion of the display panel adjacent to the second round corner illustrated in FIG. 9. FIG. 11c and FIG. 11d are enlarged views of portions of the display panel adjacent to the third round corners illustrated in FIG.

[0181] For example, in FIGS. 9 and 10, a scan driver (SDV), data drivers (DDV), and an emission driver (EDV) are illustrated together with first and second initialization lines (VIL1, VIL2).

[0182] Referring to FIGS. 9 and 10, the first initialization line (VIL1) may include a plurality of first vertical initialization lines (VL1) and a plurality of first horizontal initialization lines (HL1). The second initialization line (VIL2) may include a plurality of second vertical initialization lines (VL2) and a plurality of second horizontal initialization lines (HL2).

[0183] Each of the first and second initialization lines (VIL1, VIL2) may be defined as an initialization line. In addition, the first and second vertical initialization lines (VL1, VL2) may be defined as vertical initialization lines, and the first and second horizontal initialization lines (HL1, HL2) may be defined as horizontal initialization lines.

[0184] The arrangement of the second vertical initialization lines (VL2) and the second horizontal initialization lines (HL2) may be substantially the same as the arrangement of the first vertical initialization lines (VL1) and the first horizontal initialization lines (HL1). Therefore, below, the configuration of the first vertical initialization lines (VL1) and the first horizontal initialization lines (HL1) will be mainly described, and the configuration of the second vertical initialization lines (VL2) and the second horizontal initialization lines (HL2) will be briefly described.

[0185] The structure in which the first vertical initialization lines (VL1) and the first horizontal initialization lines (HL1) and the second vertical initialization lines (VL2) and the second horizontal initialization lines (HL2) are connected to the pixels (PX) will be described below with reference to FIGS. 12a and 12b.

[0186] The display panel (DP) may include a common line (CL) connected to a first initialization line (VIL1) and a common line (CL') connected to a second initialization line (VIL2).

[0187] The common line (CL) may include a first common line (CL1), a second-first common line (CL2-1), and a second-second common line (CL2-2). The common line (CL') may include a first common line (CL1'), a second-first common line (CL2-1'), and a second-second common line (CL2-2').

[0188] The display panel (DP) may include first repair initialization lines (RVIL1) extending from opposite sides of a first common line (CL1) that are opposed to each other in a first direction (DR1), and second repair initialization lines (RVIL2) extending from opposite sides of a first common line (CL1') that are opposed to each other in the first direction (DR1).

[0189] The arrangement of the first common line (CL1'), the second-first common line (CL2-1'), the second-second common line (CL2-2'), and the first repair initialization lines (RVIL1) may be substantially the same as the arrangement of the first common line (CL1), the second-first common line (CL2-1), the second-second common line (CL2-2), and the second repair initialization lines (RVIL2).

[0190] Accordingly, below, the configurations of the first common line (CL1), the second-first common line (CL2-1), the second-second common line (CL2-2), and the first repair initialization lines (RVIL1) will be mainly described, and the configurations of the first common line (CL1'), the second-first common line (CL2-1'), the second-second common line (CL2-2'), and the second repair initialization lines (RVIL2) will be briefly described.

[0191] Referring to FIGS. 9 and 11A to 11D, first vertical initialization lines (VL1) and first horizontal initialization lines (HL1) may be arranged in the display area (DA). The first vertical initialization lines (VL1) may extend in the second direction (DR2) and be arranged in the first direction (DR1). The first horizontal initialization lines (HL1) may extend in the first direction (DR1) and be arranged in the second direction (DR2).

[0192] In the display area (DA), the first vertical initialization lines (VL1) and the first horizontal initialization lines (HL1) may extend to intersect each other. The first vertical initialization lines (VL1) and the first horizontal initialization lines (HL1) may be arranged to define a matrix shape.

[0193] The first vertical initialization lines (VL1) are arranged adjacent to the first side (SI1), the first round corner (CR1), and the second round corner (CR2), and can extend in the second direction (DR2). The first vertical initialization lines (VL1) can extend toward the third round corners (CR3) and the fourth side (SI4).

[0194] The first vertical initialization lines (VL1) may be arranged between a first round corner (CR1) and one third round corner (CR3) that face each other in the second direction (DR2). In addition, the first vertical initialization lines (VL1) may be arranged between a second round corner (CR2) and another third round corner (CR3) that face each other in the second direction (DR2).

[0195] The first vertical initialization lines (VL1) may be connected to the first horizontal initialization lines (HL1). Contact holes (CH') are defined at the intersections of the first vertical initialization lines (VL1) and the first horizontal initialization lines (HL1), and the first vertical initialization lines (VL1) may be electrically connected to the first horizontal initialization lines (HL1) through the contact holes (CH'). The configuration of the contact holes (CH') will be illustrated in FIG. 13 below.

[0196] The first vertical initialization lines (VL1) may be connected to the pixels (PX). For example, the first vertical initialization lines (VL1) may be connected to the pixels (PX) via the first horizontal initialization lines (HL1). This configuration will be illustrated in FIGS. 12A and 12B below.

[0197] The common line (CL) may be arranged adjacent to at least one adjacent side and at least one round corner. The first vertical initialization lines (VL1) may be arranged adjacent to at least one adjacent side and at least one round corner and may be connected to the common line (CL).

[0198] For example, the common line (CL) may be positioned in the non-display area (NDA) and adjacent to the first side (SI1), the first round corner (CR1), and the second round corner (CR2). The first vertical initialization lines (VL1) may be positioned adjacent to the first side (SI1), the first round corner (CR1), and the second round corner (CR2), and may extend to the non-display area (NDA) and be connected to the common line (CL).

[0199] The first vertical initialization lines (VL1) may extend from the common line (CL) in a second direction (DR2) and be connected to pixels (PX) within the display area (DA). The second direction (DR2) may be defined as a direction intersecting the extension direction of the first side (SI1) (e.g., the first direction (DR1)).

[0200] The first common line (CL1) may be positioned in the non-display area (NDA). The first common line (CL1) may be positioned adjacent to the first side (SI1). The first common line (CL1) may extend in the first direction (DR1).

[0201] The second-first common line (CL2-1) may be positioned in a non-display area (NDA). The second-first common line (CL2-1) may be adjacent to the first round corner (CR1) and may have a curved shape corresponding to the first round corner (CR1). However, the present invention is not limited thereto, and the second-first common line (CL2-1) may also have a linear shape.

[0202] The second common line (CL2-2) may be positioned in a non-display area (NDA). The second common line (CL2-2) may be adjacent to the second round corner (CR2) and may have a curved shape corresponding to the second round corner (CR2). However, the present invention is not limited thereto, and the second common line (CL2-2) may also have a straight shape.

[0203] Referring to FIGS. 11A and 11B , the second-first common line (CL2-1) may extend between the scan driver (SDV) and the first round corner (CR1). The second-first common line (CL2-1) may be positioned between the scan driver (SDV) and the first round corner (CR1). The second-first common line (CL2-1) may be closer to the first round corner (CR1) than to the scan driver (SDV).

[0204] The second common line (CL2-2) can extend between the emission driver (EDV) and the second round corner (CR2). The second common line (CL2-2) can be arranged between the emission driver (EDV) and the second round corner (CR2). The second common line (CL2-2) can be closer to the second round corner (CR2) than to the emission driver (EDV).

[0205] Referring to FIGS. 9 and 11A to 11D, the second-first common line (CL2-1) and the second-second common line (CL2-2) may extend from the first common line (CL1). The second-first common line (CL2-1) may extend in a curved shape from one side of the first common line (CL1), and the second-second common line (CL2-2) may extend in a curved shape from the other side of the first common line (CL1).

[0206] The first vertical initialization lines (VL1) can extend to the non-display area (NDA) and be connected to the first common line (CL1), the second-first common line (CL2-1), and the second-second common line (CL2-2).

[0207] Among the first vertical initialization lines (VL1), the first vertical initialization lines (VL1) adjacent to the first side (SI1) are connected to the first common line (CL1) and can extend in the second direction (DR2) from the first common line (CL1). The first vertical initialization lines (VL1) adjacent to the first side (SI1) can extend toward the fourth side (SI4).

[0208] Among the first vertical initialization lines (VL1), the first vertical initialization lines (VL1) adjacent to the first round corner (CR1) are connected to the second-first common line (CL2-1) and can extend in the second direction (DR2) from the second-first common line (CL2-1). The first vertical initialization lines (VL1) adjacent to the first round corner (CR1) can extend toward the third round corner (CR3) facing the first round corner (CR1) in the second direction (DR2).

[0209] Among the first vertical initialization lines (VL1), the first vertical initialization lines (VL1) adjacent to the second round corner (CR2) are connected to the second-second common line (CL2-2) and can extend in the second direction (DR2) from the second-second common line (CL2-2). The first vertical initialization lines (VL1) adjacent to the second round corner (CR2) can extend toward the third round corner (CR3) facing the second round corner (CR2) in the second direction (DR2).

[0210] The first horizontal initialization lines (HL1) can extend in the first direction (DR1) adjacent to the first round corner (CR1), the second side (SI2), and the third round corner (CR3) connected to the second side (SI2). The first horizontal initialization lines (HL1) can extend toward the second round corner (CR2), the third side (SI3), and the third round corner (CR3) connected to the third side (SI3).

[0211] The first common line (CL1) may be connected to the first pads (PD1). The first pads (PD1) may be adjacent to the lower side of the display panel (DP), and the data drivers (DDV) may be arranged between the first pads (PD1). However, the arrangement position of the first pads (PD1) is not limited thereto. The first pads (PD1) may receive a first initialization voltage (VINT).

[0212] The common line (CL) may not be placed in the non-display area (NDA) adjacent to the second side (SI2), the third side (SI3), the third round corners (CR3), and the fourth side (SI4).

[0213] Referring to FIG. 9, the first repair initialization lines (VIL1) may extend between the display area (DA) and the scan driver (SDV) and between the display area (DA) and the emission driver (EDV), respectively. The first repair initialization lines (VIL1) may be adjacent to the scan driver (SDV) and the emission driver (EDV), respectively. The first repair initialization lines (VIL1) may extend outward from the second-first common line (CL2-1) and the second-second common line (CL2-2), respectively.

[0214] A display panel (DP) may include a plurality of repair pixel circuits. For convenience of explanation, the repair pixel circuits are not illustrated in the reduced-scale drawing of FIG. 9, and the repair pixel circuits are illustrated in the enlarged drawings of FIGS. 11a to 11d.

[0215] Referring to FIGS. 11A to 11D , repair pixel circuits (RPC) may be disposed between the display area (DA) and the scan driver (SDV) and between the display area (DA) and the emission driver (EDV). The repair pixel circuits (RPC) may be adjacent to the scan driver (SDV) and the emission driver (EDV). The repair pixel circuits (RPC) may be disposed between the scan driver (SDV) and the first repair initialization line (VIL1) adjacent to the scan driver (SDV). In addition, the repair pixel circuits (RPC) may be disposed between the emission driver (EDV) and the first repair initialization line (VIL1) adjacent to the emission driver (EDV).

[0216] The first repair initialization lines (RVIL1) can be connected to repair pixel circuits (RPC). Each of the repair pixel circuits (RPC) can have the same configuration as the pixel circuit (PC) illustrated in FIG. 5.

[0217] Some pixel circuits (PC) of the pixels (PX) may be damaged. The damaged pixel circuits (PC) may be connected to some repair pixel circuits (RPC) via repair lines (not shown).

[0218] Since the repair pixel circuits (RPC) must be driven in the same manner as the pixel circuits (PC), the first initialization voltage (VINT) must also be applied to the repair pixel circuits (RPC). The first repair initialization lines (RVIL1) are connected to the repair pixel circuits (RPC) so that the first initialization voltage (VINT) can be applied to the repair pixel circuits (RPC).

[0219] Referring to FIG. 10, the second vertical initialization lines (VL2) may extend in the second direction (DR2), and the second horizontal initialization lines (HL2) may extend in the first direction (DR2). The second vertical initialization lines (VL2) and the second horizontal initialization lines (HL2) may be arranged in the display area (DA) and may intersect each other.

[0220] The second vertical initialization lines (VL2) may extend in the second direction (DR2) adjacent to the first side (SI1), the first round corner (CR1), and the second round corner (CR2). The second horizontal initialization lines (HL2) may extend in the first direction (DR1) adjacent to the first round corner (CR1), the second side (SI2), and the third round corner (CR3) connected to the second side (SI2).

[0221] The second vertical initialization lines (VL2) can be connected to the second horizontal initialization lines (HL2) through contact holes (CH') defined at the intersections of the second vertical initialization lines (VL2) and the second horizontal initialization lines (HL2). The second vertical initialization lines (VL2) can be connected to the pixels (PX) through the second horizontal initialization lines (HL2), and this configuration will be illustrated in FIGS. 12A and 12B below.

[0222] A first common line (CL1'), a second-first common line (CL2-1'), and a second-second common line (CL2-2') may be arranged in a non-display area (NDA). The first common line (CL1') may be adjacent to the first side (SI1) and may extend in the first direction (DR1). The second-first common line (CL2-1') may be adjacent to the first round corner (CR1) and may have a curved shape corresponding to the first round corner (CR1). The second-second common line (CL2-2') may be adjacent to the second round corner (CR2) and may have a curved shape corresponding to the second round corner (CR2).

[0223] The second-first common line (CL2-1') and the second-second common line (CL2-2') may extend from the first common line (CL1'). The second vertical initialization lines (VL2) may extend to the non-display area (NDA) and be connected to the first common line (CL1'), the second-first common line (CL2-1'), and the second-second common line (CL2-2'). The second vertical initialization lines (VL2) may extend in the second direction (DR2) from the first common line (CL1'), the second-first common line (CL2-1'), and the second-second common line (CL2-2') and be connected to the pixels (PX) within the display area (DA).

[0224] The first common line (CL1') may be arranged adjacent to the lower side of the display panel (DP) and connected to second pads (PD2) that receive the second initialization voltage (VAINT).

[0225] The common line (CL') may not be placed in the non-display area (NDA) adjacent to the second side (SI2), the third side (SI3), the third round corners (CR3), and the fourth side (SI4).

[0226] The second repair initialization lines (VIL2) may extend between the display area (DA) and the scan driver (SDV) and between the display area (DA) and the emission driver (EDV), respectively. The second repair initialization lines (VIL2) may be adjacent to the scan driver (SDV) and the emission driver (EDV), respectively. The second repair initialization lines (VIL2) may extend outward from the second-first common line (CL2-1') and the second-second common line (CL2-2'), respectively.

[0227] Although not illustrated in the enlarged view, the second repair initialization lines (VIL2) may also be connected to the repair pixel circuits (RPC) illustrated in FIGS. 11A to 11D, like the first repair initialization lines (VIL1). Accordingly, the repair pixel circuits (RPC) may receive the second initialization voltage (VAINT) through the second repair initialization lines (VIL2).

[0228] Fig. 12a is a plan view showing the connection configuration of the first and second initialization lines and pixels at the center of the display panel. Fig. 12b is a plan view showing the connection configuration of the first and second initialization lines and pixels adjacent to the first round corner.

[0229] Referring to FIGS. 12A and 12B , the display panel (DP) may include a plurality of pixel groups (PG). For example, the pixel groups (PG) may be arranged in a matrix form, with the pixel groups (PG) being arranged in a first direction (DR1) and a second direction (DR2). The first direction (DR1) may correspond to a row, and the second direction (DR2) may correspond to a column. Accordingly, the pixel groups (PG) may be arranged in a plurality of rows and a plurality of columns.

[0230] Each of the pixel groups (PG) may include a first pixel (PX1), a second pixel (PX2), and a third pixel (PX3). Each of the first, second, and third pixels (PX1, PX2, PX3) may correspond to a pixel (PXij) illustrated in FIGS. 5 and 7.

[0231] The first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) can display different colors. For example, the first pixel (PX1) can display red, the second pixel (PX2) can display green, and the third pixel (PX3) can display blue.

[0232] The first vertical initialization lines (VL1) and the second vertical initialization lines (VL2) may extend in the second direction (DR2) and may be alternately arranged in the first direction (DR1). The first and second vertical initialization lines (VL1, VL2) may be alternately arranged on one side of the pixel groups (PG) arranged in columns. For example, the first and second vertical initialization lines (VL1, VL2) may be alternately arranged on the right sides of the pixel groups (PG) arranged in columns, but the arrangement positions of the first and second vertical initialization lines (VL1, VL2) are not limited thereto.

[0233] The first horizontal initialization lines (HL1) and the second horizontal initialization lines (HL2) may be arranged adjacently in a pair. A pair of adjacent first horizontal initialization lines (HL1) and second horizontal initialization lines (HL2) may be arranged adjacent to the lower sides of the pixel groups (PG) arranged in the corresponding row, but the arrangement positions of the first and second horizontal initialization lines (HL1, HL2) are not limited thereto.

[0234] The first horizontal initialization lines (HL1) can be connected to the first, second, and third pixels (PX1, PX2, PX3) and the first vertical initialization lines (VL1). The first vertical initialization lines (VL1) can be connected to the first, second, and third pixels (PX1, PX2, PX3) via the first horizontal initialization lines (HL1).

[0235] The second horizontal initialization lines (HL2) can be connected to the first, second, and third pixels (PX1, PX2, PX3) and the second vertical initialization lines (VL2). The second vertical initialization lines (VL2) can be connected to the first, second, and third pixels (PX1, PX2, PX3) via the second horizontal initialization lines (HL2).

[0236] The first, second, and third pixels (PX1, PX2, PX3) adjacent to the first round corner (CR1) can be connected to the first and second vertical initialization lines (VL1, VL2) adjacent to the first round corner (CR1) via the first and second horizontal initialization lines (HL1, HL2).

[0237] FIG. 13 is a drawing showing a cross-section of a first vertical initialization line and a first horizontal initialization line corresponding to one of the contact holes illustrated in FIG. 9.

[0238] Referring to FIG. 13, the first horizontal initialization line (HL1) may be disposed on the fifth insulating layer (INS5), and the sixth insulating layer (INS6) may be disposed on the first horizontal initialization line (HL1). The first vertical initialization line (VL1) may be disposed on the sixth insulating layer (INS6), and the seventh insulating layer (INS7) may be disposed on the first vertical initialization line (VL1).

[0239] According to the above cross-sectional structure, the first vertical initialization line (VL1) and the first horizontal initialization line (HL1) may be arranged on different layers. The first vertical initialization line (VL1) may be arranged above the first horizontal initialization line (HL1).

[0240] The first horizontal initialization line (HL1) may be connected to the fourth drain region (D4) of the fourth transistor (T4) through a first contact hole (CH1') defined in the fourth and fifth insulating layers (INS4, INS5). The first vertical initialization line (VL1) may be connected to the first horizontal initialization line (HL1) through a second contact hole (CH2') defined in the sixth insulating layer (INS6). The contact hole (CH') illustrated in FIG. 9 may include the first and second contact holes (CH1', CH2') illustrated in FIG. 13.

[0241] A first vertical initialization line (VL1) can be connected to a fourth transistor (T4) via a first horizontal initialization line (HL1). A first initialization voltage (VINT) can be provided to the fourth transistor (T4) via the first vertical initialization line (VL1) and the first horizontal initialization line (HL1).

[0242] Although not shown, the second vertical initialization line (VL2) and the second horizontal initialization line (HL2) may be arranged on the same layer as the first vertical initialization line (VL1) and the first horizontal initialization line (HL1), respectively. In addition, the second vertical initialization line (VL2) and the second horizontal initialization line (HL2) may be connected in a substantially same connection structure as the first vertical initialization line (VL1) and the first horizontal initialization line (HL1). The second vertical initialization line (VL2) may be connected to the seventh transistor (T7) via the second horizontal initialization line (HL2).

[0243] Fig. 14 is a drawing showing the configuration of a comparison display panel according to a comparative example.

[0244] For example, FIG. 14 is illustrated as a plan view corresponding to FIG. 9, and below, the configurations illustrated in FIG. 14 will be described with a focus on a configuration different from the configuration illustrated in FIG. 9.

[0245] Referring to FIG. 14, the common line (CL1) may be positioned adjacent to the first edge (SI1). The first vertical initialization lines (VL1) may be connected to the common line (CL1). Unlike FIG. 9, the common line (CL1) connected to the first vertical initialization lines (VL1) may not be positioned adjacent to the first round corner (CR1) and the second round corner (CR2).

[0246] The first vertical initialization lines (VL1) may not be arranged adjacent to the first round corner (CR1) and the second round corner (CR2). The first vertical initialization lines (VL1) may not be arranged between the first round corner (CR1) and the third round corner (CR3) that are opposite to each other in the second direction (DR2), and between the second round corner (CR2) and the third round corner (CR3) that are opposite to each other in the second direction (DR2).

[0247] The areas between the first round corner (CR1) and the third round corner (CR3) that are opposite to each other in the second direction (DR2) and the areas between the second round corner (CR2) and the third round corner (CR3) that are opposite to each other in the second direction (DR2) may be defined as side areas (SA). The area between the side areas (SA) may be defined as a center area (CA), and the first vertical initialization lines (VL1) may be positioned in the center area (CA).

[0248] When the first vertical initialization lines (VL1) are not arranged in the side areas (SA) and the first vertical initialization lines (VL1) are arranged in the center area (CA), the line resistance for the pixels (PX) arranged in the center area (CA) may be different from the line resistance for the pixels (PX) arranged in the side areas (SA). In this case, a difference in image quality may occur between the pixels (PX) arranged in the center area (CA) and the pixels (PX) arranged in the side areas (SA), resulting in a deterioration in display quality.

[0249] Although not shown, in the comparison display panel (DP), the second initialization line (VIL2) and the common line connected to the second initialization line (VIL2) may also be arranged in substantially the same form as the first initialization line (VIL1) and the common line (CL1). Therefore, as described above, the display quality may be degraded.

[0250] Referring to FIGS. 9 and 10, in an embodiment of the present invention, first vertical initialization lines VL1 and second vertical initialization lines VL2 may also be arranged in the side areas SA illustrated in FIG. 14. In this case, the line resistance for the pixels PX arranged in the center area CA and the line resistance for the pixels PX arranged in the side areas SA may become more uniform. Accordingly, the difference in image quality between the pixels PX arranged in the center area CA and the pixels PX arranged in the side areas SA may be reduced, thereby improving the display quality.

[0251] FIGS. 15 to 17 are drawings showing configurations of common lines according to various embodiments of the present invention.

[0252] For example, FIGS. 15 to 17 are illustrated as planes corresponding to FIG. 9, and the configurations illustrated in FIGS. 15 to 17 will be described below, focusing on configurations different from those illustrated in FIG. 9.

[0253] In addition, although common lines (CL-1, CL-2, CL-3) connected to the first initialization line (VIL1) are shown in FIGS. 15 to 17, common lines connected to the second initialization line (VIL2) may also have substantially the same form as the common lines (CL-1, CL-2, CL-3).

[0254] Referring to FIG. 15, the common line (CL-1) can extend along the first, second, and third sides (SI1, SI2, SI3) and the first, second, and third round corners (CR1, CR2, CR3). The common line (CL-1) can be positioned adjacent to the first, second, and third sides (SI1, SI2, SI3) and the first, second, and third round corners (CR1, CR2, CR3).

[0255] The first vertical initialization lines (VL1) may be connected to the common line (CL-1). Compared to FIG. 9, the first vertical initialization lines (VL1) may be further connected to the common line (CL-1) adjacent to the third round corners (CR3).

[0256] Referring to FIG. 16, the common line (CL-2) can be arranged to surround the display area (DA). Accordingly, compared to FIG. 15, the common line (CL-2) can be further extended along the fourth side (SI4).

[0257] The first vertical initialization lines (VL1) may be connected to the common line (CL-2). Compared to FIG. 16, the first vertical initialization lines (VL1) may extend to the non-display area (NDA) and be further connected to the common line (CL-2) adjacent to the fourth side (SI4).

[0258] Referring to FIG. 17, the common line (CL-3) may be arranged to surround the display area (DA). The first vertical initialization lines (VL1) may extend to the non-display area (NDA) and be connected to the common line (CL-3). The first horizontal initialization lines (HL1) may extend to the non-display area (NDA) and be connected to the common line (CL-3).

[0259] Although the present invention has been described with reference to the above embodiments, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. Furthermore, the embodiments disclosed in the present invention are not intended to limit the technical idea of ​​the present invention, and all technical ideas falling within the scope of the following claims and equivalents thereof should be construed as being included within the scope of the rights of the present invention.

[0260] The present invention has high industrial applicability because a display device capable of improving display quality by uniformly forming line resistances for pixels in a display area can be provided to a user.

Claims

1. Multiple pixels arranged in a display area; A plurality of scanning lines connected to the above pixels; A plurality of data lines connected to the above pixels; a plurality of vertical initialization lines connected to the above pixels; and Includes a common line placed in a non-display area around the display area, The display area includes a first side extending in a first direction, a second side extending in a second direction intersecting the first direction adjacent to one end of the first side, and a first round corner connecting the one end of the first side to the one end of the second side adjacent to the one end of the first side, The above common line is adjacent to the first side and the first round corner, A display device wherein the vertical initialization lines are adjacent to the first side and the first round corner, connected to the common line, and extend in the second direction from the common line.

2. In paragraph 1, A display device in which the above common line is not placed in a non-display area adjacent to the second side.

3. In paragraph 1, The above common line is, a first common line disposed in the non-display area and adjacent to the first side; and A display device disposed in the non-display area and including a second-first common line adjacent to the first round corner.

4. In paragraph 3, A display device in which the first common line extends in the first direction, and the second-first common line extends from the first common line and has a curved shape corresponding to the first round corner.

5. In paragraph 3, The above first common line is a display device connected to a pad that receives an initialization voltage.

6. In paragraph 3, A display device further comprising a scanning driver disposed in the non-display area and connected to the scanning lines, adjacent to the second side and the first round corner.

7. In paragraph 6, The above 2-1 common line is a display device arranged between the injection driving unit and the first round corner.

8. In paragraph 6, A repair initialization line extending from the first common line between the display area and the scan lines; and Further comprising a repair pixel circuit disposed between the display area and the scan line and adjacent to the scan driver, The above repair initialization line is a display device connected to the above pixel circuit.

9. In paragraph 3, The display area further includes a third side extending in the second direction adjacent to the other end of the first side, and a second round corner connecting the other end of the first side to one end of the third side adjacent to the other end of the first side, The above common line is, further comprising a second-second common line disposed in the non-display area and adjacent to the second round corner, The display device wherein the vertical initialization lines are further arranged adjacent to the second round corner, further connected to the second-2 common line, and extend in the second direction from the second-2 common line.

10. In paragraph 9, A display device in which the above common line is not placed in a non-display area adjacent to the third side.

11. In paragraph 9, A display device in which the above-mentioned second-second common line extends from the above-mentioned first common line and has a curved shape corresponding to the above-mentioned second round corner.

12. In paragraph 9, a plurality of light-emitting lines connected to the above pixels; and A display device further comprising a light emitting driver connected to the light emitting lines, the light emitting driver being arranged in the non-display area and adjacent to the third side and the second round corner.

13. In paragraph 12, The above 2-2 common line is a display device arranged between the light emitting driver and the second round corner.

14. In paragraph 1, A display device further comprising a plurality of horizontal initialization lines arranged in the display area and extending to intersect the vertical initialization lines.

15. In paragraph 14, The above horizontal initialization lines are a display device connected to the above vertical initialization lines and the above pixels.

16. In paragraph 15, A display device in which the vertical initialization lines and the horizontal initialization lines are arranged on different layers.

17. In paragraph 16, A display device in which the vertical initialization lines are positioned above the horizontal initialization lines.

18. In paragraph 14, The above common line is arranged to surround the above display area, A display device in which the vertical initialization lines and the horizontal initialization lines extend into the non-display area and are connected to the common line.

19. Multiple pixels arranged within the display area; A plurality of scanning lines connected to the above pixels; A plurality of data lines connected to the above pixels; A common line placed in a non-display area around the display area; and comprising a plurality of vertical initialization lines connected to the above pixels, The above display area is, It includes a first side extending in a first direction, a second side and a third side extending in a second direction intersecting the first direction and adjacent to each end of the first side, a first round corner connecting the first side and the second side, and a second round corner connecting the first side and the second side, The above common line is adjacent to the first side, the first round corner, and the second round corner, A display device wherein the vertical initialization lines are adjacent to the first side, the first round corner, and the second round corner, are connected to the common line, and extend in the second direction from the common line.

20. In paragraph 19, A display device in which the above common line is not placed in a non-display area adjacent to the second side and the third side.

21. A plurality of pixels arranged within a display area including sides of a rectangle extending in a first direction and a second direction intersecting the first direction and round corners connecting the sides; A plurality of scanning lines connected to the above pixels; A plurality of data lines connected to the above pixels; A common line disposed in a non-display area around the display area, and adjacent to at least one side and at least one round corner among the sides and the round corners; and A plurality of vertical initialization lines are disposed adjacent to at least one edge and at least one round corner and connected to the pixels and the common line, A display device in which the above vertical initialization lines extend from the common line in a direction intersecting the extension direction of at least one side.

Images