Gate driving circuit and display panel

Abstract

Disclosed in the present application are a gate driving circuit and a display panel. The gate driving circuit comprises a shift register. By means of a newly added node control module, the shift register can pull down the potential of a pull-up node to the potential of a low-potential line on the basis of the potential of a first node, so as to reduce or prevent abnormal turning-on of a pull-up module, thereby mitigating or avoiding the risk of the number of pulses of a gate driving signal in one frame being abnormal, and thus improving the stability of the gate driving circuit.

Description

Gate drive circuit and display panel TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate drive circuit and a display panel. BACKGROUND

[0002] As a display component of electronic devices, display panels have been widely used, and the gate drive circuit is an important part of the display panel.

[0003] Therefore, the stability of the gate drive circuit is an important parameter for measuring reliability. However, the abnormality of the node potential inside the gate drive circuit will reduce the stability and cause display defects. SUMMARY

[0004] The present application provides a gate drive circuit and a display panel to alleviate the technical problem of low stability caused by abnormal pulse number of gate drive signals in a frame.

[0005] In a first aspect, the present application provides a gate drive circuit, which comprises a shift register, the shift register comprising an input module, a pull-up module, a pull-down module, a feedback module, a pull-down control module and a node control module, the input module being connected with a forward scanning control line, a first control line and a pull-up node; the pull-up module being connected with the pull-up node, a first clock line and a gate drive line; the pull-down module being connected with a pull-down node, the gate drive line and a low potential line; the feedback module being connected with the pull-down node, the low potential line and the pull-up node; the pull-down control module comprising a first transistor, a second transistor and a third transistor, the first transistor being connected with a second clock line, the forward scanning control line and a first node, the second transistor being connected with a third clock line, a reverse scanning control line and the first node, the third transistor being connected with the first node, a high potential line and the pull-down node; the node control module being connected with the pull-up node, the first node and the low potential line, and the node control module lowering the potential of the pull-up node to the potential of the low potential line according to the potential of the first node.

[0006] In a second aspect, the present application provides a display panel, which comprises the above-mentioned gate drive circuit. ADVANTAGEOUS EFFECTS

[0007] The gate drive circuit and the display panel provided by the present application can lower or prevent the abnormal opening of the pull-up module by the newly added node control module, so that the pulse number of the gate drive signals output by the pull-up module in a frame is consistent with the expectation, thereby improving or avoiding the risk of abnormal pulse number of the gate drive signals in a frame, and improving the stability of the gate drive circuit. BRIEF DESCRIPTION OF DRAWINGS

[0008] FIG. 1 is a circuit schematic diagram of a shift register in the related art.

[0009] FIG. 2 is a circuit schematic diagram of the shift register shown in FIG. 1.

[0010] FIG. 3 is a timing diagram of a gate drive circuit in the related art.

[0011] FIG. 4 is a schematic diagram of a cascade relationship between shift registers in the gate drive circuit in the related art.

[0012] FIG. 5 is a circuit schematic diagram of a tail shift register in the related art.

[0013] FIG. 6 is another timing diagram of a gate drive circuit in the related art.

[0014] FIG. 7 is a circuit schematic diagram of a shift register according to an embodiment of the present application.

[0015] FIG. 8 is a circuit schematic diagram of the shift register shown in FIG. 7.

[0016] FIG. 9 is another circuit schematic diagram of the shift register shown in FIG. 7.

[0017] FIG. 10 is a schematic diagram of a cascade relationship between shift registers in a gate drive circuit according to an embodiment of the present application.

[0018] FIG. 11 is another schematic diagram of a cascade relationship between shift registers in a gate drive circuit according to an embodiment of the present application.

[0019] FIG. 12 is a circuit schematic diagram of a tail shift register according to an embodiment of the present application.

[0020] FIG. 13 is a schematic diagram of a relationship between a start signal of a current frame and a start signal of a next frame according to an embodiment of the present application.

[0021] FIG. 14 is a timing simulation diagram of the shift register shown in FIG. 8 or FIG. 9. Embodiments of the present application

[0022] In order to make the objects, technical solutions and effects of the present application clearer and more explicit, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0023] Fig. 1 is a circuit schematic diagram of a shift register in the related art. Fig. 2 is a circuit schematic diagram of the shift register shown in Fig. 1. The shift register includes an input module 10, a pull-up module 20, a pull-down module 40, a feedback module 50, and a pull-down control module 30. The input module 10 is connected to the pull-up module 20 through a pull-up node Q1. The pull-down module 40 is connected to the pull-down module 40 through a pull-down node P. The feedback module 50 is connected to the pull-up node Q1 and the pull-down node P. A gate drive line is connected to the pull-up module 20 and the pull-down module 40.

[0024] The gate drive line is configured to transmit an Nth gate drive signal ST(N).

[0025] Exemplarily, the pull-down control module 30 includes a first transistor NT3, a second transistor NT4, and a third transistor NT8. The first electrode of the first transistor NT3 is connected to a second clock line. The second electrode of the first transistor NT3 is connected to a first node A. The gate of the first transistor NT3 is connected to a forward scan control line. The first electrode of the second transistor NT4 is connected to a third clock line. The second electrode of the second transistor NT4 is connected to the first node A. The gate of the second transistor NT4 is connected to a reverse scan control line. The gate of the third transistor NT8 is connected to the first node A. The first electrode of the third transistor NT8 is connected to a high potential line. The second electrode of the third transistor NT8 is connected to the pull-down node P.

[0026] The forward scan control line is configured to transmit a forward scan control signal U2D. The reverse scan control line is configured to transmit a reverse scan control signal D2U. The second clock line is configured to transmit an N+2th clock signal CKN+2. The third clock line is configured to transmit an N-2th clock signal CKN-2. The high potential line is configured to transmit a high potential signal VGH. The high potential signal VGH, when connected to the gate of a transistor, can turn on an N-channel transistor or turn off a P-channel transistor.

[0027] The first electrode is one of a source and a drain, and the second electrode is the other of the source and the drain. For example, when the first electrode is the source, the second electrode is the drain. Or, when the first electrode is the drain, the second electrode is the source.

[0028] Exemplarily, the pull-down module 40 includes a pull-down transistor NT10. The gate of the pull-down transistor NT10 is connected to the pull-down node P. The first electrode of the pull-down transistor NT10 is connected to a low potential line. The second electrode of the pull-down transistor NT10 is connected to the gate drive line.

[0029] The low potential line is configured to transmit a low potential signal VGL. The low potential signal VGL, when connected to the gate of a transistor, can turn on a P-channel transistor or turn off an N-channel transistor.

[0030] Exemplarily, the input module 10 comprises an input transistor NT1, a first electrode of the input transistor NT1 is connected with the positive scan control line, a second electrode of the input transistor NT1 is connected with the pull-up node Q1, and a gate of the input transistor NT1 is connected with the first control line.

[0031] The first control line is used for transmitting the N-2th gate driving signal ST(N-2) or the start signal STV_frame_n of the current frame.

[0032] Exemplarily, the pull-up module 20 comprises a first pull-up transistor NT7 and a second pull-up transistor NT9, a first electrode of the first pull-up transistor NT7 is connected with the pull-up node Q1, a gate of the first pull-up transistor NT7 is connected with the high potential line, a second electrode of the first pull-up transistor NT7 is connected with the second pull-up node Q2 and the gate of the second pull-up transistor NT9, a first electrode of the second pull-up transistor NT9 is connected with the first clock line, and a second electrode of the second pull-up transistor NT9 is connected with the gate driving line.

[0033] The first clock line is used for transmitting the Nth clock signal CKN.

[0034] Exemplarily, the feedback module 50 comprises a feedback transistor NT5, a first electrode of the feedback transistor NT5 is connected with the pull-up node Q1, a second electrode of the feedback transistor NT5 is connected with the low potential line, and a gate of the feedback transistor NT5 is connected with the pull-down node P.

[0035] Exemplarily, the shift register further comprises a fifth transistor NT2 and a sixth transistor NT6, a first electrode of the fifth transistor NT2 is connected with the reverse scan control line, a gate of the fifth transistor NT2 is connected with the second control line, and a second electrode of the fifth transistor NT2 is connected with the pull-up node Q1. A gate of the sixth transistor NT6 is connected with the second electrode of the fifth transistor NT2 and the pull-up node Q1, a first electrode of the sixth transistor NT6 is connected with the low potential line, and a second electrode of the sixth transistor NT6 is connected with the pull-down node P.

[0036] The second control line is used for transmitting the N+2th gate driving signal ST(N+2) or the start signal STV_frame_n+1 of the next frame.

[0037] Exemplarily, the shift register further comprises a first global transistor NT11, a second global transistor NT12, and a third global transistor NT13, a first electrode of the first global transistor NT11 is connected with the gate driving line, a second electrode of the first global transistor NT11 is connected with the gate of the first global transistor NT11 and the first global control line; a gate of the second global transistor NT12 is connected with the first global control line, a first electrode of the second global transistor NT12 is connected with the pull-down node P, and a second electrode of the second global transistor NT12 is connected with the low potential line; a first electrode of the third global transistor NT13 is connected with the gate driving line, a second electrode of the third global transistor NT13 is connected with the low potential line, and a gate of the third global transistor NT13 is connected with the second global control line.

[0038] The first global control line is used for transmitting a first global control signal GAS1. The second global control line is used for transmitting a second global control signal GAS2.

[0039] Exemplarily, the shift register further comprises a first capacitor C1 and a second capacitor C2, one end of the first capacitor C1 is connected with the low potential line, and the other end of the first capacitor C1 is connected with the pull-up node Q1. One end of the second capacitor C2 is connected with the low potential line, and the other end of the second capacitor C2 is connected with the pull-down node P.

[0040] FIG. 3 is a timing diagram of a gate driving circuit in the related art. The working stages in a frame thereof include a display stage, a touch stage, and a blank stage. The display stage and the touch stage can be alternated in the frame, and the blank stage is located at the end of the frame.

[0041] As can be seen, in the display stage, under the actions of the high potential signal VGH, the forward scanning control signal U2D, the low potential signal VGL, the reverse scanning control signal D2U, the start signal STV, the clock signal (for example, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4), the first global control signal GAS1, and the second global control signal GAS2, the first-stage gate driving signal ST(1), the second-stage gate driving signal ST(2), the third-stage gate driving signal ST(3), the fourth-stage gate driving signal ST(4), and the like can be generated, so as to realize the row-by-row scanning.

[0042] In the touch stage, under the actions of the above-mentioned corresponding signals, the first-stage gate driving signal ST(1), the second-stage gate driving signal ST(2), the third-stage gate driving signal ST(3), the fourth-stage gate driving signal ST(4), and the like stop outputting the corresponding pulses, and correspondingly, the row-by-row scanning process is also suspended; when entering the display stage again, the original row-by-row scanning or display is continued.

[0043] FIG. 4 is a schematic diagram of the cascade relationship between each shift register of a related art gate driving circuit. In the gate driving circuit, K shift registers are cascaded, for example, a first shift register for generating a first-stage gate driving signal ST(1), a second shift register for generating a second-stage gate driving signal ST(2), a (K-1)-th shift register for generating a (K-1)-th stage gate driving signal ST(K-1), and a K-th shift register for generating a K-th stage gate driving signal ST(K).

[0044] Each shift register is connected to a high potential line, a low potential line, and a corresponding clock line. For example, the first shift register is connected to a first clock line, a second clock line, and a fourth clock line, the second shift register is connected to the first clock line, the second clock line, and a third clock line, and so on, the (K-1)-th shift register is connected to the second clock line, the third clock line, and the fourth clock line, and the K-th shift register is connected to the first clock line, the third clock line, and the fourth clock line. The first clock line, the second clock line, the third clock line, and the fourth clock line are used to transmit a first clock signal CK1, a second clock signal CK2, a third clock signal CK3, and a fourth clock signal CK4, respectively.

[0045] The start line is connected to the first shift register and the K-th shift register to transmit a start signal STV_frame_n of a current frame and a start signal STV_frame_n+1 of a next frame, respectively. As shown in FIG. 5, compared with FIG. 2, the gate of the fifth transistor NT2 is connected to the start signal STV_frame_n+1 of the next frame.

[0046] Since the K-th shift register uses the (K-1)-th stage gate driving signal ST(K-1) output by the (K-1)-th shift register as a trigger signal and uses the start signal STV_frame_n+1 of the next frame as a pull-down signal, the pull-down signal is delayed for a certain time compared with the logic pull-down time. At this time, the potential of the pull-up node Q1 is not pulled down in time, which causes the N-th stage gate driving signal ST(N) to output multiple pulses in a frame, and macroscopically, the K-th shift register has a flicker.

[0047] Specifically, as shown in FIG. 6, in the continuous Nth frame (Frame_N) and the (N+1)th frame (Frame_N+1), both of which include a display stage and a blank stage. Under the control of the start signal STV, the first clock signal, the second clock signal, the third clock signal and the fourth clock signal, each shift register generates the corresponding first-stage gate drive signal ST(1), the second-stage gate drive signal ST(2), the third-stage gate drive signal ST(3), the fourth-stage gate drive signal ST(4)…and the Nth-stage gate drive signal ST(N).

[0048] Wherein, the Nth-stage gate drive signal ST(N) is generated by the tail shift register, and due to the problem of not timely pulling down the potential of the pull-up node Q1 in each frame, the Nth-stage gate drive signal ST(N) outputs multiple pulses in a frame, which macroscopically shows that there is a picture difference in the tail stage.

[0049] Based on this, please refer to FIGS. 7-14, the embodiment provides a gate drive circuit, which comprises a shift register, as shown in FIGS. 7 and 8, the shift register comprises an input module 10, a pull-up module 20, a pull-down module 40, a feedback module 50, a pull-down control module 30 and a node control module 60, the input module 10 is connected with the forward scanning control line, the first control line and the pull-up node Q1; the pull-up module 20 is connected with the pull-up node Q1, the first clock line and the gate drive line; the pull-down module 40 is connected with the pull-down node P, the gate drive line and the low potential line; the feedback module 50 is connected with the pull-down node P, the low potential line and the pull-up node Q1; the pull-down control module 30 comprises a first transistor NT3, a second transistor NT4 and a third transistor NT8, the first transistor NT3 is connected with the second clock line, the forward scanning control line and the first node A, the second transistor NT4 is connected with the third clock line, the reverse scanning control line and the first node A, and the third transistor NT8 is connected with the first node A, the high potential line and the pull-down node P; the node control module 60 is connected with the pull-up node Q1, the first node A and the low potential line, and the node control module 60 pulls down the potential of the pull-up node Q1 to the potential of the low potential line according to the potential of the first node A.

[0050] It can be understood that the gate drive circuit provided by the embodiment can pull down the potential of the pull-up node Q1 to the potential of the low potential line according to the potential of the first node A through the newly added node control module 60, so as to reduce or prevent the abnormal opening of the pull-up module 20, so that the number of pulses of the gate drive signal output by the pull-up module 20 in a frame is consistent with the expectation, thereby improving or avoiding the risk of abnormal number of pulses of the gate drive signal in a frame, and improving the stability of the gate drive circuit.

[0051] In one of the embodiments, as shown in FIG. 8, the node control module 60 comprises a fourth transistor NT14, the first electrode of the fourth transistor NT14 is connected with the pull-up node Q1, the second electrode of the fourth transistor NT14 is connected with the low potential line, the gate of the fourth transistor NT14 is connected with the first node A, and the fourth transistor NT14 is an N-channel transistor.

[0052] It should be noted that, in the case that the first node A is at high potential, the fourth transistor NT14 is turned on, the potential of the pull-up node Q1 is pulled down to the potential of the low potential signal VGL, and the second pull-up transistor NT9 can be controlled to be turned off, thereby avoiding the abnormal picture caused by the output of multiple pulses of the gate drive signal in a frame.

[0053] In one of the embodiments, as shown in FIG. 9, the node control module 60 comprises a fourth transistor NT14 and a seventh transistor NT15, the first electrode of the fourth transistor NT14 is connected with the pull-up node Q1, the second electrode of the fourth transistor NT14 is connected with the first electrode of the seventh transistor NT15, the second electrode of the seventh transistor NT15 is connected with the low potential line, and the first node A is connected with the gate of the fourth transistor NT14 and the gate of the seventh transistor NT15. The fourth transistor NT14 and the seventh transistor NT15 are both N-channel transistors.

[0054] It should be noted that, in the case that the first node A is at high potential, the fourth transistor NT14 and the seventh transistor NT15 are turned on, which not only can pull down the potential of the pull-up node Q1 to the potential of the low potential signal VGL, thereby controlling the second pull-up transistor NT9 to be turned off, and avoiding the abnormal picture caused by the output of multiple pulses of the gate drive signal in a frame, but also can reduce the leakage path of the pull-up node Q1 when the fourth transistor NT14 and the seventh transistor NT15 are turned off, especially in the touch phase with a long middle stop time.

[0055] In one of the embodiments, as shown in FIG. 9, the pull-up module 20 comprises a second pull-up transistor NT9, the gate of the second pull-up transistor NT9 is connected with the pull-up node Q1, the first electrode of the second pull-up transistor NT9 is connected with the first clock line, and the second electrode of the second pull-up transistor NT9 is connected with the gate drive line.

[0056] In one of the embodiments, the shift register further comprises a fifth transistor NT2 and a sixth transistor NT6, the fifth transistor NT2 is connected with the reverse scan control line, the second control line and the pull-up node Q1, and the sixth transistor NT6 is connected with the fifth transistor NT2, the pull-up node Q1, the low potential line and the pull-down node P.

[0057] The other structures in the shift register can refer to the related description of FIG. 2. In the figures, each transistor can be an N-channel thin film transistor.

[0058] In FIGS. 10 and 11, the gate drive circuit includes a plurality of shift registers connected in cascade, for example, a first shift register generating a first-stage gate drive signal ST(1), a second shift register generating a second-stage gate drive signal ST(2),..., a (K-1)-th shift register generating a (K-1)-th gate drive signal ST(K-1), and a K-th shift register (a last shift register) generating a K-th gate drive signal ST(K).

[0059] In the last shift register of the gate drive circuit, the second control line is a start line, as shown in FIG. 12, which is used to transmit a start signal STV_frame_n+1 of a next frame. In the non-last shift register of the gate drive circuit, the second control line is an (N+2)-th gate drive line, as shown in FIGS. 8 and 9, which is used to transmit an (N+2)-th gate drive signal ST(N+2).

[0060] In one embodiment, as shown in FIG. 10, the last shift register is provided with a node control module 60, and the non-last shift register is not provided with the node control module 60.

[0061] It should be noted that, in the last shift register, the node control module 60 can pull down the potential of the pull-up node Q1 to the potential of the low potential line according to the potential of the first node A, so as to reduce or prevent the abnormal opening of the pull-up module 20, so that the number of pulses of the last-stage gate drive signal in a frame is consistent with the expectation, thereby improving or avoiding the picture abnormality caused by the last-stage gate drive signal having multiple pulses in a frame, and improving the stability of the gate drive circuit.

[0062] In addition, since the node control module 60 is not provided in the non-last shift register, the bezel space of the non-last shift register can be reduced, thereby facilitating the realization of a narrower bezel.

[0063] In addition, the embodiment can be suitable for a driving scheme of only forward scanning.

[0064] In one embodiment, in the first shift register of the gate drive circuit, the first control line is a start line, which is used to transmit a start signal STV_frame_n of a current frame; and in the non-first shift register of the gate drive circuit, the first control line is an (N-2)-th gate drive line, which is used to transmit an (N-2)-th gate drive signal ST(N-2).

[0065] In one of the embodiments, as shown in FIG. 11, the tail-stage shift register and the head-stage shift register are each provided with the node control module 60, and the shift registers between the tail-stage shift register and the head-stage shift register are not provided with the node control module 60.

[0066] It should be noted that, by providing the node control module 60 in each of the head-stage shift register and the tail-stage shift register, the potential of the pull-up node Q1 can be pulled down to the potential of the low potential line according to the potential of the first node A, so as to reduce or prevent the abnormal opening of the pull-up module 20, so that the number of pulses of the gate drive signal of the first stage and the last stage in a frame is consistent with the expectation, thereby improving or avoiding the picture abnormality caused by the gate drive signal of the first stage and the last stage having multiple pulses in a frame, and improving the stability of the gate drive circuit.

[0067] In addition, since the shift registers between the tail-stage shift register and the head-stage shift register are not provided with the node control module 60, the bezel space of the non-tail-stage shift register can be reduced, thereby facilitating the realization of a narrower bezel.

[0068] In addition, the present embodiment can be suitable for a driving scheme of forward scanning and reverse scanning.

[0069] In one of the embodiments, each shift register in the gate drive circuit is provided with the node control module 60.

[0070] It should be noted that, by providing the node control module 60 in each of the shift registers, the potential of the pull-up node Q1 can be pulled down to the potential of the low potential line according to the potential of the first node A, so as to reduce or prevent the abnormal opening of the pull-up module 20, so that the number of pulses of the gate drive signal of each stage in a frame is consistent with the expectation, thereby improving or avoiding the picture abnormality caused by the gate drive signal of each stage having multiple pulses in a frame, and improving the stability of the gate drive circuit.

[0071] Especially in the display driving with a touch function or a touch stage, since the touch function is enabled or the touch stage is entered at any time, the gate drive circuit needs to suspend the line-by-line scanning at any time, and the last line of the suspended front scanning is also prone to picture abnormality. By providing the node control module 60 in each of the shift registers, the picture abnormality can be improved or avoided, and the stability of the gate drive circuit is improved.

[0072] Similarly, the present embodiment can be suitable for a driving scheme of at least one of forward scanning and reverse scanning.

[0073] Fig. 13 is a schematic diagram of the relationship between the start signal STV_frame_n of the current frame and the start signal STV_frame_n+1 of the next frame according to an embodiment of the present application. As shown in Fig. 13, the waveform of the start signal STV_frame_n of the current frame is the same as that of the start signal STV_frame_n+1 of the next frame, but the two signals appear in sequence, i.e., the start signal STV_frame_n of the current frame appears before the start signal STV_frame_n+1 of the next frame.

[0074] Fig. 14 is a schematic diagram of the timing simulation of the shift register shown in Fig. 8 or Fig. 9. As can be seen from Fig. 14, when the gate drive signal ST(N-2) of the N-2th stage is at a high level, the input transistor NT1 is turned on, the potential of the pull-up node Q1 is raised to a high level (the potential of the second pull-up node Q2 is also raised to a high level), the second pull-up transistor NT9 is turned on, and a pulse of the Nth clock signal CKN is output as a pulse of the gate drive signal ST(N) of the Nth stage. At this time, the potential of the pull-down node P is at a low level.

[0075] After the pulse output of the gate drive signal ST(N) of the Nth stage is completed, the potential of the pull-down node P is switched to a high level, and a pulse of the gate drive signal ST(N+2) of the N+2th stage also appears. The potential of the first node A alternately appears at a high level and a low level, and when the potential of the first node A is at a high level, the node control module 60 pulls down the potential of the pull-up node Q1 to avoid abnormal turning on of the second pull-up transistor NT9, thereby improving or avoiding the occurrence of abnormal pictures and improving the stability of the gate drive circuit.

[0076] In one embodiment, the present embodiment provides a display panel including the above-described gate drive circuit.

[0077] It can be understood that, since the display panel provided by the present embodiment includes the above-described gate drive circuit, the newly added node control module 60 can also pull down the potential of the pull-up node Q1 to the potential of the low potential line according to the potential of the first node A, so as to reduce or prevent abnormal turning on of the pull-up module 20, so that the number of pulses of the gate drive signal output by the pull-up module 20 in a frame is consistent with the expected number, thereby improving or avoiding the risk of abnormal number of pulses of the gate drive signal in a frame, and improving the stability of the gate drive circuit.

[0078] It should be noted that the above-described display panel can be a liquid crystal display panel or a self-luminous display panel. In the case of a liquid crystal display panel, the above-described gate drive circuit can perform row-by-row scanning on sub-pixels to control the writing of data signals to the corresponding sub-pixels. Alternatively, in the case of a self-luminous display panel, the above-described gate drive circuit can be used to drive the corresponding transistors in the pixel circuit.

[0079] The self-luminous display panel may be, for example, an organic light-emitting diode display panel, a mini light-emitting diode display panel, a micro light-emitting diode display panel, or a quantum dot light-emitting diode display panel.

[0080] In one of the embodiments, the display panel described above may also be a touch display panel, for example, an IN Cell Touch display panel or an ON Cell Touch display panel.

[0081] It can be understood that, for those skilled in the art, equivalent replacements or changes can be made according to the technical solutions and the inventive concept of the present application, and all these changes or replacements shall fall within the protection scope of the claims appended to the present application.

Claims

1. A gate drive circuit, wherein: The gate driving circuit includes a shift register, and the shift register includes: an input module connected to the forward scan control line, the first control line, and the pull-up node; a pull-up module connected to the pull-up node, the first clock line, and the gate drive line; a pull-down module connected to the pull-down node, the gate drive line, and the low potential line; a feedback module connected to the pull-down node, the low potential line, and the pull-up node; a pull-down control module, the pull-down control module comprising a first transistor, a second transistor, and a third transistor, the first transistor being connected to a second clock line, the forward scan control line, and a first node, the second transistor being connected to a third clock line, a reverse scan control line, and the first node, and the third transistor being connected to the first node, a high potential line, and the pull-down node; A node control module is connected to the pull-up node, the first node and the low potential line, and the node control module pulls down the potential of the pull-up node to the potential of the low potential line according to the potential of the first node.

2. The gate drive circuit according to claim 1, wherein: The node control module includes a fourth transistor, a first electrode of the fourth transistor is connected to the pull-up node, a second electrode of the fourth transistor is connected to the low potential line, a gate of the fourth transistor is connected to the first node, and the fourth transistor is an N-channel transistor.

3. The gate drive circuit according to claim 2, wherein: The shift register further includes: a fifth transistor connected to the reverse scan control line, the second control line, and the pull-up node; A sixth transistor is connected to the fifth transistor, the pull-up node, the low potential line, and the pull-down node.

4. The gate driving circuit according to claim 3, wherein: The gate drive line is used to transmit the Nth level gate drive signal; the gate of the fifth transistor is connected to the second control line; The gate drive circuit includes a plurality of cascaded shift registers, and in the tail-stage shift register of the gate drive circuit, the second control line is a start line, and the start line is used to transmit a start signal of a next frame; In the non-tail-stage shift register of the gate driving circuit, the second control line is an N+2-stage gate driving line, and the N+2-stage gate driving line is used to transmit an N+2-stage gate driving signal.

5. The gate driving circuit according to claim 4, wherein: The tail-stage shift register is provided with the node control module, while the non-tail-stage shift register is not provided with the node control module.

6. The gate driving circuit according to claim 4, wherein: The input module includes an input transistor, a first electrode of the input transistor is connected to the forward scanning control line, a second electrode of the input transistor is connected to the pull-up node, and a gate of the input transistor is connected to the first control line.

7. The gate driving circuit according to claim 6, wherein: In the first-stage shift register of the gate drive circuit, the first control line is the start line, which is used to transmit the start signal of this frame; in the non-first-stage shift register of the gate drive circuit, the first control line is the N-2th-stage gate drive line, which is used to transmit the N-2th-stage gate drive signal.

8. The gate driving circuit according to claim 7, wherein: The node control module is provided in both the tail-stage shift register and the first-stage shift register, but the shift register between the tail-stage shift register and the first-stage shift register is not provided with the node control module.

9. The gate driving circuit according to claim 3, wherein: The shift register further includes: a first global transistor, wherein a first electrode of the first global transistor is connected to the gate drive line, and a second electrode of the first global transistor is connected to the gate of the first global transistor and a first global control line; a second global transistor, wherein a gate of the second global transistor is connected to the first global control line, a first electrode of the second global transistor is connected to the pull-down node, and a second electrode of the second global transistor is connected to the low potential line; A third global transistor, wherein a first electrode of the third global transistor is connected to the gate drive line, a second electrode of the third global transistor is connected to the low potential line, and a gate of the third global transistor is connected to the second global control line.

10. The gate driving circuit according to claim 9, wherein: The gate driving circuit includes a plurality of cascaded shift registers, and each shift register in the gate driving circuit is provided with the node control module.

11. A display panel, wherein: The display panel includes a gate driving circuit, the gate driving circuit includes a shift register, and the shift register includes: an input module connected to the forward scan control line, the first control line, and the pull-up node; a pull-up module connected to the pull-up node, the first clock line, and the gate drive line; a pull-down module connected to the pull-down node, the gate drive line, and the low potential line; a feedback module connected to the pull-down node, the low potential line, and the pull-up node; a pull-down control module, the pull-down control module comprising a first transistor, a second transistor, and a third transistor, the first transistor being connected to a second clock line, the forward scan control line, and a first node, the second transistor being connected to a third clock line, a reverse scan control line, and the first node, and the third transistor being connected to the first node, a high potential line, and the pull-down node; A node control module is connected to the pull-up node, the first node and the low potential line, and the node control module pulls down the potential of the pull-up node to the potential of the low potential line according to the potential of the first node.

12. The display panel according to claim 11, wherein: The node control module includes a fourth transistor, a first electrode of the fourth transistor is connected to the pull-up node, a second electrode of the fourth transistor is connected to the low potential line, a gate of the fourth transistor is connected to the first node, and the fourth transistor is an N-channel transistor.

13. The display panel according to claim 12, wherein: The shift register further includes: a fifth transistor connected to the reverse scan control line, the second control line, and the pull-up node; A sixth transistor is connected to the fifth transistor, the pull-up node, the low potential line, and the pull-down node.

14. The display panel according to claim 13, wherein: The gate drive line is used to transmit the Nth level gate drive signal; the gate of the fifth transistor is connected to the second control line; The gate drive circuit includes a plurality of cascaded shift registers, and in the tail-stage shift register of the gate drive circuit, the second control line is a start line, and the start line is used to transmit a start signal of a next frame; In the non-tail-stage shift register of the gate driving circuit, the second control line is an N+2-stage gate driving line, and the N+2-stage gate driving line is used to transmit an N+2-stage gate driving signal.

15. The display panel according to claim 14, wherein: The tail-stage shift register is provided with the node control module, while the non-tail-stage shift register is not provided with the node control module.

16. The display panel according to claim 14, wherein: The input module includes an input transistor, a first electrode of the input transistor is connected to the forward scanning control line, a second electrode of the input transistor is connected to the pull-up node, and a gate of the input transistor is connected to the first control line.

17. The display panel according to claim 16, wherein: In the first-stage shift register of the gate drive circuit, the first control line is the start line, which is used to transmit the start signal of this frame; in the non-first-stage shift register of the gate drive circuit, the first control line is the N-2th-stage gate drive line, which is used to transmit the N-2th-stage gate drive signal.

18. The display panel according to claim 17, wherein: The node control module is provided in both the tail-stage shift register and the first-stage shift register, but the shift register between the tail-stage shift register and the first-stage shift register is not provided with the node control module.

19. The display panel according to claim 13, wherein: The shift register further includes: a first global transistor, wherein a first electrode of the first global transistor is connected to the gate drive line, and a second electrode of the first global transistor is connected to the gate of the first global transistor and a first global control line; a second global transistor, wherein a gate of the second global transistor is connected to the first global control line, a first electrode of the second global transistor is connected to the pull-down node, and a second electrode of the second global transistor is connected to the low potential line; A third global transistor, wherein a first electrode of the third global transistor is connected to the gate drive line, a second electrode of the third global transistor is connected to the low potential line, and a gate of the third global transistor is connected to the second global control line.

20. The display panel according to claim 19, wherein The gate driving circuit includes a plurality of cascaded shift registers, and each shift register in the gate driving circuit is provided with the node control module.

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