Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. The display panel comprises a plurality of data lines, a plurality of pixel circuits, and a plurality of adjusting circuits. The adjusting circuits are electrically connected to the data lines; each adjusting circuit comprises a first capacitor; when a first pixel circuit is in a data writing stage, m pixel circuits are in an adjusting stage; and when a second pixel circuit is in the data writing stage, n pixel circuits are in the adjusting stage. The first capacitors in at least some of the adjusting circuits are configured to be electrically connected to a target data line when the second pixel circuit is in the data writing stage.

Description

Display panel and display device

[0001] The present application claims priority to the Chinese patent application No. 202410437311.8, filed on April 11, 2024, and entitled "A display panel and display device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel and display device. BACKGROUND

[0003] In the current display technology, in order to improve the display effect of the display panel, the driving transistor in the pixel circuit is adjusted in the display of a frame of picture of the display panel, so as to ensure the driving effect. At the same time, in order to avoid the process of adjusting the driving transistor prolonging the working period of the pixel circuit and affecting the refresh frequency of the display panel, the adjustment stage of the driving transistor and the working stage of other parts of the pixel circuit are carried out at the same time. However, this will cause the display panel to have the problem of uneven display, mainly manifested as the display brightness of the first few rows of pixels or the last few rows of pixels of the display panel being too bright or too dark. SUMMARY

[0004] Therefore, the embodiments of the present application provide a display panel and display device.

[0005] In a first aspect, the embodiments of the present application provide a display panel, comprising: a plurality of data lines;

[0006] a plurality of pixel circuits, each pixel circuit comprising a driving transistor and a data writing module, a first end of the data writing module being electrically connected to a data line, and a second end of the data writing module being electrically connected to the driving transistor; a working period of the pixel circuit comprising a data writing stage and at least one adjustment stage, the data writing module in the pixel circuit being turned on in the data writing stage and writing a data voltage on the data line to the driving transistor, and the data writing module in the pixel circuit being turned on in the adjustment stage and writing an adjustment voltage on the data line to the driving transistor;

[0007] a plurality of adjustment circuits, at least one adjustment circuit being electrically connected to the same data line; the adjustment circuit comprising a first capacitor;

[0008] Among the plurality of pixel circuits electrically connected to the target data line, when the first pixel circuit is in the data writing stage, m pixel circuits are in the adjustment stage; when the second pixel circuit is in the data writing stage, n pixel circuits are in the adjustment stage, and m>n; the target data line is one of the plurality of data lines, and the first pixel circuit and the second pixel circuit are both pixel circuits electrically connected to the target data line;

[0009] The first capacitor in the at least partial adjustment circuit is electrically connected with the target data line when the second pixel circuit is in a data writing stage.

[0010] In a second aspect based on the same inventive concept, the embodiments of the present application provide a display device, comprising any one of the display panels provided in the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows.

[0012] FIG. 1 is a schematic diagram of a display panel provided by an embodiment of the present application;

[0013] FIG. 2 is an equivalent circuit diagram of a pixel circuit provided by an embodiment of the present application;

[0014] FIG. 3 is a timing diagram of a display panel provided by an embodiment of the present application;

[0015] FIG. 4 is a timing diagram of a display panel provided by an embodiment of the present application;

[0016] FIG. 5 is a schematic diagram of a multiplexing circuit provided by an embodiment of the present application;

[0017] FIG. 6 is a schematic diagram of the pixel circuit shown in FIG. 2;

[0018] FIG. 7 is a timing diagram of a pixel circuit provided by an embodiment of the present application;

[0019] FIG. 8 is a driving timing diagram of a display panel provided by an embodiment of the present application;

[0020] FIG. 9 is another driving timing diagram of a display panel provided by an embodiment of the present application;

[0021] FIG. 10 is a schematic diagram of the pixel circuit shown in FIG. 2;

[0022] FIG. 11 is another schematic diagram of the pixel circuit shown in FIG. 2;

[0023] FIG. 12 is another schematic diagram of the pixel circuit shown in FIG. 2;

[0024] FIG. 13 is another schematic diagram of the pixel circuit shown in FIG. 2;

[0025] FIG. 14 is a schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0026] FIG. 15 is a schematic diagram of another display panel provided by an embodiment of the present application;

[0027] FIG. 16 is a schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0028] FIG. 17 is a schematic diagram of another display panel according to an embodiment of the present application;

[0029] FIG. 18 is a schematic diagram of another pixel circuit according to an embodiment of the present application;

[0030] FIG. 19 is a driving timing diagram of another display panel according to an embodiment of the present application;

[0031] FIG. 20 is a schematic diagram of another pixel circuit according to an embodiment of the present application;

[0032] FIG. 21 is a driving timing diagram of another display panel according to an embodiment of the present application;

[0033] FIG. 22 is a schematic diagram of another display panel according to an embodiment of the present application;

[0034] FIG. 23 is a driving timing diagram of another display panel according to an embodiment of the present application;

[0035] FIG. 24 is a schematic diagram of another display panel according to an embodiment of the present application;

[0036] FIG. 25 is a driving timing diagram of another display panel according to an embodiment of the present application;

[0037] FIG. 26 is a schematic diagram of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to better understand the technical solutions of the present application, the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0039] FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present application, FIG. 2 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present application, FIG. 3 is a timing diagram of a display panel according to an embodiment of the present application, and FIG. 4 is a timing diagram of a display panel according to an embodiment of the present application.

[0040] As shown in FIG. 1, the present application provides a display panel 100, which includes a plurality of pixel circuits 200. The output end of the pixel circuit 200 is electrically connected to a light emitting device 300 in the display panel 100 and drives the light emitting device 300 to emit light. For example, the pixel circuit 200 can drive an organic light emitting diode (OLED), a micro light emitting diode (Micro-LED), or a submillimeter light emitting diode (Mini-LED) to emit light.

[0041] In addition, as shown in FIG. 2, the display panel 100 further includes a plurality of data lines SL1, which are electrically connected with the pixel circuit 200 and used for writing a data voltage Vdata into the pixel circuit 200. Different data voltages written into the pixel circuit 200 can result in different luminous brightness of the light emitting device 300 driven by the pixel circuit 200.

[0042] The pixel circuit 200 can include a driving transistor Md and a data writing module 10, the first end 101 of the data writing module 10 is electrically connected with the data line SL1, and the second end 102 of the data writing module 10 is electrically connected with the driving transistor Md. When the data writing module 10 is turned on, the voltage transmitted on the data line SL1 is written into the pixel circuit 200 through the turned-on data writing module 10.

[0043] The working period of the pixel circuit 200 includes a data writing stage T1 and at least one adjusting stage T2, and the data writing module 10 in the pixel circuit 200 is turned on in both the data writing stage T1 and the adjusting stage T2 to transmit the voltage transmitted on the data line SL1 to a specific node of the pixel circuit 200.

[0044] The data line SL1 can transmit a data voltage Vdata in the data writing stage T1, and the data writing module 10 can be turned on in the data writing stage T1 and write the data voltage Vdata on the data line SL1 into the driving transistor Md. Different data voltages Vdata can result in different light emitting driving currents generated by the pixel circuit 200, and further result in different luminous brightness of the light emitting device 300.

[0045] For example, as shown in FIG. 2, the pixel circuit 200 further includes a threshold writing module 20, the second end of the data writing module 10 is electrically connected with the first electrode of the driving transistor Md, the first end 201 of the threshold writing module 20 is electrically connected with the second electrode of the driving transistor Md, and the second end 202 of the threshold writing module 20 is electrically connected with the gate electrode of the driving transistor Md. In the data writing stage T1, the data writing module 10 and the threshold writing module 20 can be turned on, and the data voltage Vdata transmitted on the data line SL1 can be written into the gate electrode of the driving transistor Md through the data writing module 10 and the threshold writing module 20.

[0046] The data line SL1 transmits an adjusting voltage V1 in the adjusting stage T2, and the data writing module 10 of the pixel circuit 200 is turned on in the adjusting stage T2 and writes the adjusting voltage V1 on the data line SL1 into a specific node of the pixel circuit 200. The specific node of the pixel circuit 200 receives the adjusting voltage V1 in the adjusting stage T2 to ensure the performance of the light emitting driving current generated by the pixel circuit 200.

[0047] The timing diagrams shown in FIG. 3 and FIG. 4 are specifically for the timing diagram of the scan line SCi electrically connected to the control terminal 103 of the data write module 10 in the pixel circuit 200, the scan line SCi is electrically connected to the control terminal 103 of the data write module 10 in the pixel circuit 200 in the Si row, and i is an integer less than or equal to q and greater than or equal to 1. Taking the low level transmitted by the scan line SCi as an effective signal (i.e., the low level transmitted by the scan line SCi controls the data write module 10) as an example for description.

[0048] For example, in combination with FIG. 3, in order to improve the flicker problem when the display panel 100 emits light, a multi-pulse driving mode can be used to control the display panel 100 to emit light, that is, the display panel 100 includes multiple light emitting stages in the process of displaying a frame of picture. Further, in order to improve the bias problem of the driving transistor Md, a bias stage can be added after the data write stage T1 in the working period of the pixel circuit 200, the bias stage is a bias stage for adjusting the bias state of the driving transistor Md, wherein the bias stage can be the adjustment stage T2, and the bias voltage used to correct the bias state of the driving transistor Md can be the adjustment voltage V1. Then, in at least one adjustment stage T2, the adjustment voltage V1 is written into the pixel circuit 200 through the opened data write module 10 to correct the bias state of the driving transistor Md. It should be noted that when the second terminal of the data write module 10 is electrically connected to the first electrode of the driving transistor Md, the first terminal 201 of the threshold write module 20 is electrically connected to the second electrode of the driving transistor Md, and the second terminal 202 of the threshold write module 20 is electrically connected to the gate electrode of the driving transistor Md, the data write module 10 is opened in the bias stage and the threshold write module 20 is kept off in the bias stage, and the bias voltage is written into the first electrode of the driving transistor Md through the opened data write module 10.

[0049] For example, as shown in FIG. 4, in order to ensure that the luminous brightness of the display panel 100 meets the expectation and reduce the power consumption of the display panel 100, a pre-charge manner can be adopted, that is, a data voltage is pre-written to the pixel circuit 10 in the display panel 100 before the data writing stage T1. Then the working period of the pixel circuit 10 includes a pre-writing stage, the pre-writing stage can be regarded as the adjusting stage T2, and the pre-written pre-writing voltage of the driving transistor Md can be the adjusting voltage V1. Then in at least one adjusting stage T2, the adjusting voltage V1 is written to the pixel circuit 200 through the opened data writing module 10 to write the pre-writing voltage to the driving transistor Md. It should be noted that when the second end of the data writing module 10 is electrically connected with the first electrode of the driving transistor Md, the first end 201 of the threshold writing module 20 is electrically connected with the second electrode of the driving transistor Md, and the second end 202 of the threshold writing module 20 is electrically connected with the gate electrode of the driving transistor Md, the data writing module 10 is opened in the pre-writing stage, and the threshold writing module 20 is opened in the pre-writing stage, and the pre-writing voltage is written to the gate electrode of the driving transistor Md through the opened data writing module 10 and the threshold writing module 20.

[0050] In the display panel 100, as shown in FIG. 1, there are S1th row to Sqth row pixel circuits 200, and the pixel circuits 200 in the same column are electrically connected with the same data line SL1. In order to avoid the addition of the adjusting stage T2 to prolong the working period of the pixel circuit 200 and cause the refresh frequency of the display panel 100 to be reduced when displaying, the adjusting stage T2 of one pixel circuit 200 in the pixel circuits 200 electrically connected with the same data line SL1 can overlap with the data writing stage T1 of other pixel circuits 200, for example, the adjusting stage T2 of one pixel circuit 200 can completely coincide with the data writing stage T1 of other pixel circuits 200. Then in the pixel circuits 200 electrically connected with the same data line SL1, in the two pixel circuits 200 in which the adjusting stage T2 overlaps with the data writing stage T1, the adjusting voltage V1 received by the pixel circuit 200 in the adjusting stage T2 is actually the data voltage Vdata received by the pixel circuit 200 in the data writing stage T1, that is, the data voltage received by the pixel circuit 200 in the data writing stage T1 can be regarded as the adjusting voltage V1 of the pixel circuit 200 in the adjusting stage T2.

[0051] For example, as shown in FIG. 1 and FIG. 3, when the bias stage (adjustment stage T2) is performed after the data write stage T1, in terms of the plurality of pixel circuits 200 in the display panel 100 closest to the left side frame and connected to the same data line SL1, the fourth pixel circuit 2004 of the Sq-1th row is in the data write stage T1, and the fifth pixel circuit 2005 of the Sq-3th row is in the bias stage (adjustment stage T2). At this time, the electrical signal transmitted to the fourth pixel circuit 2004 of the Sq-1th row by the same data line SL1 in the same time period serves as the data voltage Vdata, and the electrical signal transmitted to the fifth pixel circuit 2005 of the Sq-3th row serves as the adjustment voltage V1.

[0052] For example, as shown in FIG. 1 and FIG. 4, when the pre-write stage (adjustment stage T2) is performed before the data write stage T1 in the display panel 100, in terms of the plurality of pixel circuits 200 in the display panel 100 closest to the left side frame and connected to the same data line SL1, the fifth pixel circuit 2005 of the Sq-3th row is in the data write stage T1, and the fourth pixel circuit 2004 of the Sq-1th row is in the pre-write stage (adjustment stage T2). At this time, the electrical signal transmitted to the fifth pixel circuit 2005 of the Sq-3th row by the same data line SL1 in the same time period serves as the data voltage Vdata, and the electrical signal transmitted to the fourth pixel circuit 2004 of the Sq-1th row serves as the adjustment voltage V1.

[0053] In the plurality of pixel circuits 200 electrically connected to the target data line SL1’, the first pixel circuit 2001 is in the data write stage T1, and the m pixel circuits 200 are in the adjustment stage T2. The second pixel circuit 2002 is in the data write stage T1, and the n pixel circuits are in the adjustment stage T2, and m>n; the target data line SL1’ is one of the plurality of data lines SL1, and the first pixel circuit 2001 and the second pixel circuit 2002 are both pixel circuits 200 electrically connected to the target data line SL1’.

[0054] Continuing to refer to FIG. 1 and FIG. 3, when the bias stage (adjustment stage T2) is performed after the data write stage T1, if the pixel circuit 200 of the Sqth row in the display panel 100 is the first pixel circuit 2001, the first pixel circuit 2001 is in the data write stage T1, and in addition, m pixel circuits 200 are in the bias stage (adjustment stage T2), at this time, m=1. If the pixel circuit 200 of the S1th row in the display panel 100 connected to the target data line SL1’ simultaneously with the first pixel circuit 2001 is the second pixel circuit 2002, in addition, n pixel circuits 200 are in the bias stage (adjustment stage T2), at this time, n=0.

[0055] Continuing to refer to FIG. 1 and FIG. 4, when the pre-writing stage (adjustment stage T2) is performed before the data writing stage T1, if the pixel circuit 200 in the S1th row of the display panel 100 is the first pixel circuit 2001, the first pixel circuit 2001 is in the data writing stage T1, and m pixel circuits 200 are in the pre-writing stage (adjustment stage T2) at the same time, where m = 1. If the pixel circuit 200 in the (Sq-1)th row of the display panel 100 connected to the target data line SL1' at the same time as the first pixel circuit 2001 is the second pixel circuit 2002, n pixel circuits 200 are in the pre-writing stage (adjustment stage T2) at the same time, where n = 0.

[0056] In summary, it can be seen that when the bias stage (adjustment stage T2) is performed after the data writing stage T1, the number of pixel circuits in the adjustment stage T2 at the same time is less than the number of pixel circuits in the last few rows of the display panel 100 when the first few rows of pixel circuits 200 in the display panel 100 are in the data writing stage T1. It can be seen that when the pre-writing stage (adjustment stage T2) is performed before the data writing stage T1, the number of pixel circuits in the adjustment stage T2 at the same time is greater than the number of pixel circuits in the last few rows of the display panel 100 when the first few rows of pixel circuits 200 in the display panel 100 are in the data writing stage T1. Therefore, the load connected to the target data line SL1' during the period when the first pixel circuit 2001 is in the data writing stage T1 is obviously different from the load connected to the target data line SL1' during the period when the second pixel circuit 2002 is in the data writing stage T1.

[0057] From the above analysis, it can be seen that the load of the same data line SL1 when writing voltage to the pixel circuit 100 at different times may be different, which leads to different deviations of the data voltage received by the gate of the drive transistor Md in some pixel circuits 200 due to different data line loads, and further affects the luminous brightness of the light emitting device 300, mainly manifested as the brightness of the area near the upper and / or lower frame of the display panel 100 being brighter or darker.

[0058] A plurality of adjustment circuits 400 are arranged in the display panel 100, and at least one adjustment circuit 400 is electrically connected to the same data line SL1; the adjustment circuit 400 is used to balance the load of the data line SL1 at different working periods, so that the load connected to the data line SL1 is approximately level when the data line SL1 transmits electrical signals to different numbers of pixel circuits 200, thereby avoiding different deviations of the data voltage Vdata received by the pixel circuit 200 in part of the data writing stage T1.

[0059] The adjusting circuit 400 includes a first capacitor C1, and the first capacitor C1 can be used as a load of the adjusting circuit 400. At least part of the first capacitors C1 in the adjusting circuit 400 are used to be electrically connected with the target data line SL1' when the second pixel circuit 2002 is in the data writing stage T1.

[0060] When the target data line SL1' transmits the data voltage Vdata for the second pixel circuit 2002 in the data writing stage T1, the target data line SL1' is electrically connected with at least part of the first capacitors C1 in the adjusting circuit 400, and the first capacitors C1 increase the load of the target data line SL1'. The load of the target data line SL1' in the first pixel circuit 2001 in the data writing stage T1 is substantially the same as the load of the target data line SL1' in the second pixel circuit 2002 in the data writing stage T1. When the load of the target data line SL1' in different working periods is substantially the same, the display area of the display panel 100 can have a more uniform luminous brightness.

[0061] In the embodiment of the present application, since the capacitor can keep the stability of the potential of the node electrically connected thereto, by using the first capacitors C1 included in the adjusting circuit 400 as a device for balancing the load of the target data line SL1' in different working periods, the load connected to the target data line SL1' can be avoided from having a large difference at different times.

[0062] FIG. 5 is a schematic diagram of a multiplexing circuit provided in an embodiment of the present application.

[0063] In an embodiment of the present application, as shown in FIG. 5, the display panel 100 further includes a multiplexing circuit 500, and the multiplexing circuit 500 is used to transmit a voltage signal to different data lines SL1. The multiplexing circuit 500 includes a plurality of selection switches 500A. In the same multiplexing circuit 500, the input ends of the plurality of selection switches 500A are electrically connected, and the output ends of the plurality of selection switches 500A are respectively electrically connected with different data lines SL1, and the plurality of (two or more) selection switches 500A are opened at different times. When the plurality of selection switches 500A of the multiplexing circuit 500 are opened at different times, the data lines SL1 respectively electrically connected with the output ends of the plurality of selection switches 500A receive the data voltage provided by the IC. The multiplexing circuit 500 is electrically connected with the data lines SL1, and the mode of writing the data voltage Vdata to the pixel circuit 200 is a line charging mode. That is, the IC first writes the data voltage Vdata to the data lines SL1 through the selection switches 500A of the multiplexing circuit 500 opened at different times, and the data lines SL1 keep the data voltage Vdata and write the data voltage Vdata to the corresponding pixel circuit 200 in the data writing stage T1.

[0064] Correspondingly, among the plurality of pixel circuits 200 electrically connected to the same data line SL1, if the time period when at least one pixel circuit 200 receives the adjusting voltage V1 in the adjusting stage T2 overlaps with the time period when another pixel circuit 200 receives the data voltage Vdata in the data writing stage T1, the adjusting voltage V1 and the data voltage Vdata are voltage signals written into the data line SL1 at the same time and in the same way, i.e., the way of writing the adjusting voltage V1 into the pixel circuit 200 is also the line charging way.

[0065] When the data line SL1 in the display panel 100 is electrically connected to the multiplexing circuit 500, i.e., the way of writing the data voltage Vdata into the pixel circuit 200 is the line charging way, the pixel circuit 200 as a load shares the data voltage Vdata on the data line SL1, and thus, when the number of pixel circuits 200 as loads on the same data line SL1 is different in different working time periods, the data voltage Vdata received by the pixel circuit 200 in the data writing stage T1 in different working time periods is obviously different. Thus, the display brightness of the display area of the display panel 100 close to the upper and / or lower frame is obviously different from the display brightness of other positions. Therefore, by using the technical solution of the embodiment of the present application, a certain number of adjusting circuits 400 are also connected to the same data line SL1 in addition to the pixel circuits 200, and when the load connected to a data line SL1 in a working time period is obviously smaller than the load connected to the data line SL1 in other working time periods, at least part of the adjusting circuits 400 connected to the data line SL1 are also adjusted as the load of the data line SL1, so that the load levels of the data line SL1 in different working time periods are similar, thereby effectively improving the display unevenness problem in the display panel 100 using the line charging way.

[0066] FIG. 6 is a schematic diagram of the pixel circuit shown in FIG. 2.

[0067] In an embodiment of the present application, as shown in FIG. 2 and FIG. 6, the pixel circuit 200 further includes a threshold writing module 20, the second electrode of the data writing module 10 is electrically connected to the first electrode of the driving transistor Md, the first end 201 of the threshold writing module 20 is electrically connected to the second electrode of the driving transistor Md, and the second end 202 of the threshold writing module 20 is electrically connected to the gate electrode of the driving transistor Md. The threshold writing module 20 can be used to compensate the threshold voltage of the driving transistor Md.

[0068] The data writing module 10 can include a first transistor M1, a first electrode of the first transistor M1 receiving a data voltage Vdata, a second electrode electrically connected with a first electrode of the driving transistor Md, and a gate electrode electrically connected with a scan line SCi (i is an integer, and represents the i-th scan line, for example, the first scan line is SC1 or the q-th scan line is SCq, etc.). The threshold value writing module 20 can include a second transistor M2, a first electrode of the second transistor M2 electrically connected with a second electrode of the driving transistor Md, a second electrode electrically connected with a gate electrode of the driving transistor Md, and a gate electrode electrically connected with a scan line.

[0069] In the working period T of the pixel circuit 200, at least part of the adjustment phase T2 is located before the data writing phase T1, and the threshold value writing module 20 is turned on in the data writing phase T1 and the adjustment phase T2 located before the data writing phase T1. At this time, the control signal received by the threshold value writing module 20 can be the same as that received by the data writing module 10. When the data writing module 10 receives the control signal and is turned on to receive the data voltage Vdata or the adjustment voltage V1, the threshold value writing module 20 is also turned on to write the data voltage Vdata or the adjustment voltage V1 to the gate electrode of the driving transistor Md.

[0070] When part of the adjustment phase T2 is located after the data writing phase T1, the threshold value writing module 20 is turned off in the adjustment phase T2 located after the data writing. At this time, the threshold value writing module 20 is turned off to avoid the adjustment voltage V1 received by the driving transistor Md from changing the gate potential thereof.

[0071] The pixel circuit 200 further includes a power voltage writing module 50 and a light emitting control module 60. The power voltage writing module 50 is configured to transmit a power voltage to the driving transistor Md, so that the driving transistor Md generates a light emitting driving current. The power voltage writing module 50 includes a fifth transistor M5, a first electrode of the fifth transistor M5 receiving the power voltage, a second electrode electrically connected with a first electrode of the driving transistor Md, and a gate electrode electrically connected with a light emitting control signal line EMIT. The light emitting control module 60 is configured to transmit the light emitting driving current to a first electrode 3001 of the light emitting device 300, so that the light emitting device 300 emits light. The light emitting control module 60 includes a sixth transistor M6, a first electrode of the sixth transistor M6 receiving the light emitting driving current, a second electrode electrically connected with the first electrode 3001 of the light emitting device 300, and a gate electrode electrically connected with the light emitting control signal line EMIT.

[0072] FIG. 7 is a timing diagram of a pixel circuit according to an embodiment of the present application.

[0073] In an embodiment of the present application, as shown in FIG. 7, in the working period of the pixel circuit 200, at least part of the adjustment phase T2 is located after the data writing phase T1.

[0074] As shown in FIG. 7, the working period T of the pixel circuit 200 further includes a plurality of light emitting stages T3, and the adjusting stage T2 after the data writing stage T1 is located between adjacent light emitting stages T3. In addition, the adjusting stage T2 can also be included between the light emitting stage T3 and the data writing stage T1.

[0075] When the display panel 100 includes a plurality of light emitting stages T3 in a frame display process, the power consumption of the display panel 100 can be reduced. When one light emitting stage T3 is performed after the data writing stage T1, the bias state of the driving transistor Md will be different before the next light emitting stage T3 is performed. Therefore, the data writing module 10 of the pixel circuit 200 needs to be turned on again to perform the adjusting stage T2 to correct the bias state of the driving transistor Md.

[0076] In this process, due to the participation of the adjusting stage T2, the data line SL1 connected to a plurality of pixel circuits 200 can have uneven load at different time periods. Therefore, the adjusting circuit 400 including the first capacitor C1 is added to the display panel 100 to balance the load on the data line SL1, which is more conducive to reducing the power consumption of the display panel 100 while ensuring that the light emitting brightness of the display panel 100 is more uniform.

[0077] In an embodiment of the present application, the output end of the pixel circuit 200 is electrically connected to the light emitting device 300, and the adjusting circuit 400 is electrically insulated from the light emitting device 300. That is, the light emitting device 300 is electrically connected to the pixel circuit 200 and is driven by the pixel circuit 200 to emit light, and the light emitting of the light emitting device 300 is not driven by the adjusting circuit 400. Alternatively, the circuit structure of the adjusting circuit 400 is different from that of the light emitting device 300. Alternatively, if part of the light emitting device 300 is driven by the adjusting circuit 400 to emit light, and part of the light emitting device 300 is driven by the pixel circuit 200 to emit light, the light emitting brightness will be different, which will cause uneven light emitting. In the present application, the adjusting circuit 400 is arranged to be electrically insulated from the light emitting device 300, which can effectively avoid the problem of uneven light emitting caused by the above reasons, and on the other hand, will not increase the power consumption.

[0078] FIG. 8 is a driving timing diagram of a display panel according to an embodiment of the present application, and FIG. 9 is another driving timing diagram of a display panel according to an embodiment of the present application.

[0079] In an embodiment of the present application, as shown in FIG. 2, the adjusting circuit 400 further includes a control module 410, a first end of the control module 410 is electrically connected to the data line SL1, and a second end of the control module 410 is electrically connected to the first plate of the first capacitor C1. The control module 410 is used to control the first capacitor C1 to be electrically connected to the data line SL1 when the control module 410 is turned on, and to control the first capacitor C1 to be electrically disconnected from the data line SL1 when the control module 410 is turned off.

[0080] As shown in Fig. 2, the data writing module 10 in the pixel circuit 200 is controlled by the signal transmitted by the scan line SCi. In combination with Fig. 1, there are q scan lines in the display panel 100 for controlling the working of the pixel circuit 200, wherein 1≤i≤q, and the scan line SCi is one of the scan lines SC1-SCq. In addition, when the adjusting circuit 400 is added in the display panel 100, for controlling the working of the adjusting circuit 400, as shown in Fig. 8, the scan lines SC00, SC01, … SCq+1, SCq+2, … are added, wherein one scan line can control one row of the adjusting circuit 400, and the number of the adjusting circuit 400 added is determined according to the actual working requirement of the display panel 100.

[0081] For example, in combination with Fig. 8, when the bias stage (adjusting stage T2) is performed after the data writing stage T1 in the display panel 100, there is the pixel circuit 200 in the S1th row performing the data writing stage T2, and there is no other pixel circuit 200 performing the bias stage (adjusting stage T2). However, the pixel circuit 200 after the S3th row is performing the data writing stage T1, and all of them have one pixel circuit 200 performing the adjusting stage T2 in the same period. Therefore, the load compensation is needed for the data line SL1 transmitting the data voltage Vdata in the period when the pixel circuit 200 in the S1th row is performing the data writing stage T1. The load compensation working can be completed by electrically connecting the first capacitor C1 to the data line SL1, and the compensation working process is as follows: when the pixel circuit 200 in the S1th row is performing the data writing stage T1, the scan line SC00 transmits the enable signal to the control module 410 in the adjusting circuit 400, and the control module 410 is opened to control the first capacitor C1 to be electrically connected to the data line SL1, so as to realize the load compensation in the period.

[0082] For example, in combination with Fig. 9, in the display panel 100, when the pre-writing stage (adjustment stage T2) is performed before the data writing stage T1, there is one pixel circuit 200 of the (Sq-1)th row performing the data writing stage T1, and there is no other pixel circuit 200 performing the pre-writing stage (adjustment stage T2). When the pixel circuits 200 of the (S1)th to (Sq-2)th rows are performing the data writing stage T1, each of the pixel circuits 200 has one pixel circuit 200 performing the adjustment stage T2 at the same time. Therefore, the data line SL1 transmitting the data voltage Vdata at the time when the pixel circuit 200 of the (Sq-1)th row is performing the data writing stage T1 needs to be load compensated. The load compensation can be achieved by electrically connecting the first capacitor C1 to the data line SL1. The compensation process is as follows: when the pixel circuit 200 of the (Sq-1)th row is performing the data writing stage T1, the scan line SCq+1 transmits an enable signal to the control module 410 in the adjustment circuit 400 at the (Sq+1)th row, and the control module 410 is turned on to electrically connect the first capacitor C1 to the data line SL1 to achieve the load compensation at the time.

[0083] Fig. 10 is a schematic diagram of the pixel circuit shown in Fig. 2, and Fig. 11 is another schematic diagram of the pixel circuit shown in Fig. 2.

[0084] In an embodiment of the present application, as shown in Figs. 10-11, the control module 410 includes a first switch 420 and a diode C2, a first end 421 of the first switch 420 is electrically connected to the data line SL1, and a second end 422 of the first switch 420 is electrically connected to an anode of the diode C2, and a cathode of the diode C2 is electrically connected to a first plate of the first capacitor C1.

[0085] In the embodiment of the present application, the first switch 420 is provided to control whether the control module 410 is turned on or not, and when the first switch 420 is turned on, the control module 410 is turned on. The control end of the first switch 420 can be the control end of the control module 410. In addition, the first switch 420 can be a transistor as shown in Figs. 10 and 11, and in the corresponding transistor of the first switch 420, the first pole is electrically connected to the data line SL1, the second pole is electrically connected to the anode of the diode C2, and the gate is electrically connected to the control end of the control module 410.

[0086] When the first switch 420 is turned on, the anode of the diode C2 receives the data voltage Vdata transmitted by the data line SL1 and charges the first capacitor C1, which is beneficial to realize the first capacitor C1 as a load of the data line SL1. In addition, the cathode of the diode C2 is electrically connected to the first plate of the first capacitor C1, which is beneficial to avoid that the potential on the first plate of the first capacitor C1 affects the voltage signal transmitted by the data line SL1 through the diode C2.

[0087] In an implementation form of the embodiment, the diode C2 is formed by electrically connecting one pole of a transistor with a gate. For example, as shown in FIG. 11, the transistor constituting the diode C2 is a P-channel transistor, the source of the P-channel transistor is electrically connected with the first switch 420, the drain is electrically connected with the first capacitor C1, and the gate is electrically connected with the drain. In this implementation form, the diode C2 can be prepared at the same time as the transistor corresponding to the first switch 420 and the transistor included in the pixel circuit 200, thereby simplifying the process flow and reducing the preparation cost.

[0088] FIG. 12 is another schematic diagram of the pixel circuit shown in FIG. 2.

[0089] In an implementation form of the present application, as shown in FIG. 12, the adjusting circuit 400 further includes an adjusting reset module 420, the first end 421 of the adjusting reset module 420 is electrically connected with the reset signal line, and the second end 422 of the adjusting reset module 420 is electrically connected with the first plate of the first capacitor C1.

[0090] In the embodiment of the present application, the adjusting reset module 420 is provided to reset the first plate of the first capacitor C1, which is beneficial to quickly and effectively share the voltage on the data line SL by the first capacitor C1 when the control module 410 is turned on, i.e., the first capacitor C1 can quickly become a useful load on the data line SL. This avoids the situation that the potential of the first capacitor C1 is low or high at the moment of electrical connection with the data line SL, thereby avoiding affecting the charging charge amount of the first capacitor C1 and avoiding the inaccurate load exerted by the first capacitor C1 on the data line SL1. In this way, it is beneficial to make the load exerted by the first capacitor on the data line SL1 more accurate, further ensure the uniform luminous brightness of the light emitting device 300 in the display panel 100, and improve the display effect.

[0091] FIG. 13 is another schematic diagram of the pixel circuit shown in FIG. 2.

[0092] In an implementation form of the present application, as shown in FIG. 13, the pixel circuit 200 further includes a first reset module 30, the first end 301 of the first reset module 30 is electrically connected with the reset signal line SL2, and the second end 302 of the first reset module 30 is electrically connected with the gate of the driving transistor Md; and / or,

[0093] The pixel circuit 200 further includes a second reset module 40, the first end 401 of the second reset module 40 is electrically connected with the reset signal line SL2, and the second end 402 of the second reset module 40 is electrically connected with the first pole 3001 of the light emitting device 300, and the output end of the pixel circuit 200 is electrically connected with the first pole 3001 of the light emitting device 300.

[0094] In an implementation, the pixel circuit 200 includes the first reset module 30 and the second reset module 40, and the first reset module 30 and the second reset module 40 are electrically connected to the same reset signal line SL2 of the adjusting reset module 420.

[0095] In an implementation, the pixel circuit 200 includes the first reset module 30, and the first reset module 30 is electrically connected to the same reset signal line SL2 of the adjusting reset module 420. Even if the pixel circuit 200 includes the second reset module 40, the reset signal line SL2 electrically connected to the second reset module 40 is not the same as the reset signal line SL2 electrically connected to the adjusting reset module 420.

[0096] In an implementation, the pixel circuit 200 includes the second reset module 40, and the second reset module 40 is electrically connected to the same reset signal line SL2 of the adjusting reset module 420. Even if the pixel circuit 200 includes the first reset module 30, the reset signal line SL2 electrically connected to the first reset module 30 is not the same as the reset signal line SL2 electrically connected to the adjusting reset module 420.

[0097] When the pixel circuit 200 includes the first reset module 30, the first reset module 30 is turned on, receives the reset voltage Vref1 transmitted by the reset signal line SL2, and transmits the reset voltage Vref1 to the gate of the driving transistor Md to reset the gate of the driving transistor Md. Optionally, the adjusting reset module 420 in the adjusting circuit 400 for resetting the first capacitor C1 is electrically connected to the same reset signal line as the first reset module 30 in the pixel circuit 200 for resetting the gate of the driving transistor Md, so as to avoid introducing too many wirings in the display panel 100 and reduce the wiring difficulty of the display panel 100.

[0098] When the pixel circuit 200 includes the second reset module 40, the second reset module 40 is turned on, receives the reset voltage Vref2 transmitted by the reset signal line, and transmits the reset voltage Vref2 to the first electrode 3001 of the light emitting device 300 to reset the first electrode 3001 of the light emitting device 300. Optionally, the adjusting reset module 420 in the adjusting circuit 400 for resetting the first capacitor C1 is electrically connected to the same reset signal line as the second reset module 40 in the pixel circuit 200 for resetting the gate of the driving transistor Md, so as to avoid introducing too many wirings in the display panel 100 and reduce the wiring difficulty of the display panel 100.

[0099] In addition, the first reset module 30 and the second reset module 40 can be electrically connected to the same reset signal line, or can be electrically connected to different reset signal lines. When the first reset module 30 and the second reset module 40 are electrically connected to the same reset signal line, the adjusting reset module 420, the first reset module 30 and the second reset module 40 are electrically connected to the same reset signal line SL2.

[0100] In combination with FIG. 6 and FIG. 13, the first reset module 30 can include a third transistor M3, the first electrode of the third transistor M3 receiving a reset voltage Vref1, the second electrode of the third transistor M3 being electrically connected to the gate electrode of the driving transistor Md, and the gate electrode of the third transistor M3 being electrically connected to the control line. The second reset module 40 can include a fourth transistor M4, the first electrode of the fourth transistor M4 receiving a reset voltage Vref2, the second electrode of the fourth transistor M4 being electrically connected to the first electrode 3001 of the light emitting device 300, and the gate electrode of the fourth transistor M4 being electrically connected to the control line.

[0101] When the first reset module 30, the second reset module 40 and the adjusting reset module 420 are electrically connected to the same reset signal line SL2, the reset voltage Vref1 and the reset voltage Vref2 can be equal.

[0102] FIG. 14 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.

[0103] In an embodiment of the present application, as shown in FIG. 14, the display panel 100 further includes a plurality of first scan lines and a shift register circuit 600.

[0104] The plurality of first scan lines include a first sub-scan line SCA and a second sub-scan line SCB, the first sub-scan line SCA being electrically connected to the control end 103 of the data writing module 10, and the second sub-scan line SCB being electrically connected to the control end of the control module 410. That is, the first sub-scan line SCA can be used to transmit a control signal for the operation of the pixel circuit 200, and the second sub-scan line SCB can be used to control the operation of the adjusting circuit 400.

[0105] As shown in FIG. 14, the shift register circuit 600 includes a plurality of cascaded shift registers 601, the first scan lines being electrically connected to the output ends of the shift registers 601, and the control signals output by the shift registers 601 being transmitted to the control end 103 of the data writing module 10 in the pixel circuit 200 and the control module 410 in the adjusting circuit 400 by the first scan lines. That is, the scan signals transmitted by the first sub-scan line SCA to the pixel circuit 200 and the scan signals transmitted by the second sub-scan line SCB to the adjusting circuit 400 are provided by the cascaded shift registers 601. In this way, the problem of increased computing power and increased output ports of the IC caused by the addition of the adjusting circuit 400 can be avoided, and the number of signal lines on the display panel 100 will not be excessively increased.

[0106] In an embodiment of the present application, as shown in FIG. 1, FIG. 9 and FIG. 14, in a working cycle T of the pixel circuit 200, the pre-writing stage (adjustment stage T2) is located before the data writing stage T1. The shift register 601 connected to the second sub scanning line SCB is cascaded after the shift register 601 connected to the first sub scanning line SCA.

[0107] From the above analysis, when the pre-writing stage (adjustment stage T2) is located before the data writing stage T1, the pixel circuits 200 in the later rows of the display panel 100 will have a reduced load on the data line SL1 when performing the data writing stage T1. In this case, the shift register 601 providing the control signal for the adjustment circuit 400 is cascaded after the shift register 601 providing the control signal for the data writing module 10 of the pixel circuit 200, so that the adjustment circuit 400 can be turned on when the pixel circuits 200 in the later rows perform the data writing stage T2, thereby balancing the load on the data line SL1.

[0108] For example, when the pixel circuit 200 in the Sq-1 row receives the enable signal for starting the data writing stage T1 transmitted by the scanning line SCA / SCq-1, the adjustment circuit 400 in the Sq+1 row located behind the pixel circuit 200 in the display panel 100 also receives the enable signal for starting the control module 410 transmitted by the scanning line SCB / SCq+1 under the cascading effect of the shift registers 601. At this time, the pixel circuit 400 in the Sq-1 row and the adjustment circuit 400 in the Sq+1 row are electrically connected to the same data line SL1.

[0109] In the embodiment of the present application, the pre-writing stage (adjustment stage T2) is located before the data writing stage T1, and the shift register 601 connected to the second sub scanning line SCB is cascaded after the shift register 601 connected to the first sub scanning line SCA. This is beneficial to avoid the problem that the pixel circuits 200 in the later rows have a reduced load on the data line SL1 when performing the data writing stage T1 during the adjustment stage T2, and is beneficial to balance the load of the data line SL1 in each period and avoid the output data voltage Vdata from having a significant deviation.

[0110] FIG. 15 is a schematic diagram of another display panel provided by an embodiment of the present application, and FIG. 16 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.

[0111] In an embodiment of the present application, as shown in FIG. 8, FIG. 15 and FIG. 16, in a working cycle T of the pixel circuit 200, the bias stage (adjustment stage T2) is located after the data writing stage T1.

[0112] The shift register 601 electrically connected to the first sub scanning line SCA is cascaded after the shift register 601 electrically connected to the second sub scanning line SCB.

[0113] From the above analysis, it can be seen that when the bias stage (adjustment stage T2) is located after the data writing stage T1, the pixel circuit 200 in the front rows of the display panel 100 will have a reduced load on the data line SL1 when performing the data writing stage T1. At this time, the shift register 601 providing the control signal for the adjustment circuit 400 is cascaded before the shift register 601 providing the control signal for the data writing module 10 of the pixel circuit 200. Therefore, the adjustment circuit 400 can be turned on when the pixel circuit 200 in the front rows performs the data writing stage T2, so as to balance the load on the data line SL1.

[0114] For example, when the adjustment circuit 400 in the S00th row of the display panel 100 receives the enable signal transmitted by the scanning line SCB / SC00 to turn on the control module 410, the first capacitor C1 is electrically connected to the data line SL1. At the same time, under the cascading effect of the shift registers 601, the pixel circuit 200 in the S1th row of the display panel 100 located after the adjustment circuit 400 also receives the enable signal transmitted by the scanning line SCA / SC1 to turn on the data writing module 10, and the pixel circuit 200 in the S1th row performs the data writing stage T1. At this time, the pixel circuit 400 in the S1th row and the adjustment circuit 400 in the S00th row are electrically connected to the same data line SL1 as loads.

[0115] In the embodiment of the present application, the bias stage (adjustment stage T2) is located after the data writing stage T1, and the shift register 601 electrically connected to the second sub scanning line SCB is cascaded before the shift register 601 electrically connected to the first sub scanning line SCA. This is beneficial to avoid the problem that the pixel circuit 200 in the front rows has a reduced load on the data line SL1 when performing the data writing stage T1 during the subsequent adjustment stage T2, and is beneficial to balance the load of the data line SL1 during each period, so as to avoid the data voltage Vdata output by the data line SL1 from having a significant deviation.

[0116] FIG. 17 is a schematic diagram of another display panel provided by an embodiment of the present application, FIG. 18 is a schematic diagram of another pixel circuit provided by an embodiment of the present application, and FIG. 19 is a driving timing diagram of another display panel provided by an embodiment of the present application.

[0117] In one embodiment of the present application, as shown in FIGS. 17-19, in one working cycle of the pixel circuit 200, part of the adjustment stage T2 is located before the data writing stage T1, and part of the adjustment stage T2 is located after the data writing stage T1.

[0118] Part of the second sub-scan line SCB electrically connected shift register 601 cascade in the first sub-scan line SCA electrically connected shift register 601, and part of the second sub-scan line SCB electrically connected shift register 601 cascade in the first sub-scan line SCA electrically connected shift register 601.

[0119] From the above analysis, when the pre-write stage (adjustment stage T2) in the working cycle of the pixel circuit 200 is located before the data write stage T1, the data line SL1 connected to the pixel circuit 200 in the later rows of the pixel circuit 200 needs to be load compensated. When the bias stage (adjustment stage T2) in the working cycle of the pixel circuit 200 is located after the data write stage T1, the data line SL1 connected to the pixel circuit 200 in the front rows of the pixel circuit 200 needs to be load compensated. Therefore, when the working cycle of the pixel circuit 200 includes both the pre-write stage and the bias stage, the pixel circuit 200 in the front rows needs to turn on at least part of the control module in the adjustment circuit 400 when entering the data write stage T1, and the pixel circuit 200 in the later rows also needs to turn on at least part of the control module in the adjustment circuit 400 when entering the data write stage T1.

[0120] For example, when the pixel circuit 200 in the Sq-1 row is in the data write stage T1, the scan line SCB / SCq+1 also transmits an enable signal to control the control module 410 in the adjustment circuit 400 to be turned on, at this time, the same data line SL1 is electrically connected to the pixel circuit 200 in the Sq-1 row and the adjustment circuit 400 in the Sq+1 row; and when the pixel circuit 200 in the S2 row is in the data write stage T1, the scan line SCB / SC00 also transmits an enable signal to control the control module 410 in the adjustment circuit 400 to be turned on, at this time, the same data line SL1 is electrically connected to the pixel circuit 200 in the S2 row and the adjustment circuit 400 in the S00 row.

[0121] In the embodiment of the present application, when the pixel circuit 200 in the display panel 100 includes both the bias stage (adjustment stage T2) and the pre-write stage (adjustment stage T2), part of the second sub-scan line SCB electrically connected shift register 601 is cascaded before the first sub-scan line SCA electrically connected shift register 601, and part of the second sub-scan line SCB electrically connected shift register 601 is cascaded after the first sub-scan line SCA electrically connected shift register 601. Under the premise of alleviating the problem of uneven luminance of the light emitting device 300 driven by the pixel circuit 200 in the front rows or the later rows of the display panel 100, it is beneficial to avoid the problem of increasing the computing power of the IC and the output port caused by increasing the adjustment circuit 400, and it will not excessively increase the signal lines on the display panel 100.

[0122] FIG. 20 is a schematic diagram of another pixel circuit according to an embodiment of the present application.

[0123] In one embodiment of the present application, as shown in FIG. 20, the display panel 100 further includes a control line SL2 and a pin C3, and the control line SL2 is electrically connected to the control end of the control module 410. One end SL2 of the control line SL2 is electrically connected to the pin C3.

[0124] The pin C3 can be electrically connected to a control chip to receive a signal transmitted by the control chip to individually control the adjusting circuit 400. The control signal received by the pin C3 is transmitted to the control end of the control module 410 by the control line SL2.

[0125] In the embodiment of the present application, the control line SL2 and the pin C3 in the display panel 100 individually receive the control signal of the control module 410 in the controllable adjusting circuit 400. This is conducive to more flexibly turning on the control module 410 to electrically connect the first capacitor C1 to the corresponding data line SL1. Moreover, this is conducive to flexibly controlling the number of the first capacitors C1 electrically connected to the data line SL1 to adaptively adjust the load connected to the data line SL1.

[0126] In one embodiment of the present application, the working period T of the pixel circuit 200 includes a data writing stage T1 and k adjusting stages T2. The data line SL1 is electrically connected to (2*k-x) adjusting circuits 400, 2*k>x≥0, and x is an integer. The same data line SL1 is electrically connected to at least one adjusting circuit 400 and at most 2k adjusting circuits 400. The electrical connection of the data line SL1 to at least one adjusting circuit 400 can ensure that the data line SL1 is compensated for load, and the electrical connection of the data line SL1 to at most 2k adjusting circuits 400 can avoid excessively increasing the adjusting circuit 400 to affect the width of the non-display area of the display panel 100.

[0127] In one embodiment of the present application, x=1 or x=0.

[0128] In the embodiment of the present application, when x=1, that is, (2*k-1) adjusting circuits 400 are arranged on the data line SL1, the number of circuits loaded by the pixel circuits 200 other than the last row of pixel circuits 200 during the data writing stage T1 is basically the same.

[0129] FIG. 21 is a driving timing diagram of another display panel according to an embodiment of the present application. For example, when k = 2, and x = 1, three adjusting circuits 400 are arranged on the data line SL1, as shown in FIG. 21. At this time, the second sub scanning lines to which the three adjusting circuits 400 are respectively connected are SCq+1, SCq+2 and SCq+3 respectively. As shown in FIG. 21, the number of circuits loaded by the pixel circuits 200 except the last row of pixel circuits 200 in the data writing stage T1 is basically the same.

[0130] In the embodiment of the present application, when x = 0, that is, (2*k) adjusting circuits 400 are arranged on the data line SL1, the number of circuits loaded by the data line SL1 in any data writing stage T1 is basically the same.

[0131] In an embodiment of the present application, x = 2*k-1, and one adjusting circuit 400 is arranged on the data line SL1. Arranging one adjusting circuit 400 is beneficial to save the space of the display panel 100 and avoid the influence of arranging multiple adjusting circuits 400 on the placement of other circuits.

[0132] For example, the working period T of the pixel circuit 200 includes the data writing stage T1 and two adjusting stages T2. At this time, k = 2 and x = 3, that is, 2*k-3 adjusting circuits 400 are arranged on the data line SL1, that is, one adjusting circuit 400 is arranged.

[0133] FIG. 22 is a schematic diagram of another display panel according to an embodiment of the present application, FIG. 23 is a driving timing diagram of another display panel according to an embodiment of the present application, FIG. 24 is a schematic diagram of another display panel according to an embodiment of the present application, and FIG. 25 is a driving timing diagram of another display panel according to an embodiment of the present application.

[0134] In an embodiment of the present application, the data line SL1 is electrically connected with multiple adjusting circuits 400.

[0135] In combination with FIGS. 22 and 24, among the multiple pixel circuits 200 electrically connected with the target data line SL1', when the third pixel circuit 2003 is in the data writing stage T1, p pixel circuits 200 are in the adjusting stage T2; n > p; the third pixel circuit is the pixel circuit 200 electrically connected with the target data line SL1'.

[0136] Among the multiple pixel circuits 200 electrically connected with the same data line SL, compared with the first pixel circuit 2001 in the data writing stage T1 and the second pixel circuit 2002 in the data writing stage T1, the number of pixel circuits 200 in the adjusting stage T2 when the third pixel circuit is in the data writing stage T1 is less.

[0137] For example, as shown in FIGS. 22 and 23, when the bias stage (adjustment stage T2) is after the data writing stage T1, the first pixel circuit 2001 located in the S5th row has m pixel circuits 200 in the adjustment stage T2 in the pixel circuits 200 connected to the target data line SL1' when the data writing stage T1 is performed, where m = 2. The second pixel circuit 2002 located in the S3rd row has n pixel circuits 200 in the adjustment stage T2 in the pixel circuits 200 connected to the target data line SL1' when the data writing stage T2 is performed, where n = 1. The third pixel circuit 2003 located in the S2nd row has p pixel circuits 200 in the adjustment stage T2 in the pixel circuits 200 connected to the target data line SL1' when the data writing stage T2 is performed, where p = 0. At this time, the third pixel circuit 2003 is closer to the upper frame of the display panel 100. According to the above example, it can be deduced that when the bias stage (adjustment stage T2) is after the data writing stage T1, the data voltage Vdata received by the pixel circuit 200 closer to the upper frame of the display panel 100 has a larger deviation.

[0138] For example, as shown in FIGS. 24 and 25, when the pre-writing stage (adjustment stage T2) is before the data writing stage T1. The first pixel circuit 2001 located in the Sq-5th row has m pixel circuits 200 in the adjustment stage T2 in the pixel circuits 200 connected to the target data line SL1' when the data writing stage T1 is performed, where m = 2. The second pixel circuit 2002 located in the Sq-3rd row has n pixel circuits 200 in the adjustment stage T2 in the pixel circuits 200 connected to the target data line SL1' when the data writing stage T2 is performed, where n = 1. The third pixel circuit 2003 located in the Sqth row has p pixel circuits 200 in the adjustment stage T2 in the pixel circuits 200 connected to the target data line SL1' when the data writing stage T2 is performed, where p = 0. At this time, the third pixel circuit 2003 is closer to the upper frame of the display panel 100. According to the above example, it can be deduced that when the pre-writing stage (adjustment stage T2) is before the data writing stage T1, the data voltage Vdata received by the pixel circuit 200 closer to the lower frame of the display panel 100 has a larger deviation.

[0139] In summary, the third pixel circuit 2003 is closer to the upper frame and / or the lower frame of the display panel 100. When the display brightness closer to the upper frame and the lower frame of the display panel 100 is obviously different from other positions, it is not easy to be observed by the human eye, and therefore, the brightness compensation requirement close to the upper frame and the lower frame can be reduced.

[0140] In the embodiment, the number of the first capacitors C1 electrically connected with the target data line SL1' is a when the second pixel circuit 2002 is in the data writing stage T1, and the number of the first capacitors C1 electrically connected with the target data line SL1' is b when the third pixel circuit 2003 is in the data writing stage T1, and a > b. For example, as shown in FIG. 23, the second pixel circuit 2002 is the pixel circuit 200 in the S3th row, and a = 1, and the third pixel circuit 2003 is the pixel circuit 200 in the S2th row, and b = 0. For example, as shown in FIG. 25, the second pixel circuit 2002 is the pixel circuit 200 in the Sq-3th row, and a = 1, and the third pixel circuit 2003 is the pixel circuit 200 in the qth row, and b = 0. In the plurality of pixel circuits 200 electrically connected with the same data line SL, compared with the load compensation when the first pixel circuit 2001 is in the data writing stage T1 and the second pixel circuit 2002 is in the data writing stage T1, the load compensation when the third pixel circuit 2003 is in the data writing stage T1 can be less, and the number of the adjustment modules 400 can be avoided from being excessively increased.

[0141] In one embodiment of the present application, as shown in FIG. 22 and FIG. 23, and FIG. 24 and FIG. 25, b = 0.

[0142] In the embodiment, the third pixel circuit 2003 is closer to the upper or lower edge of the display panel 100, and even if there is some difference in the luminous brightness of the light emitting device 300 driven by the third pixel circuit 2003, it is not easy to be perceived by the human eye, and the target data line SL1' connected with the third pixel circuit 2003 in the data writing stage T1 can not be compensated, which is beneficial to reduce the complexity of the circuit operation.

[0143] FIG. 26 is a schematic diagram of a display device provided in an embodiment of the present application.

[0144] The display device 700 provided in the embodiment of the present application can be a mobile phone, and in addition, the display device 700 can also be a computer, a television or other electronic device.

[0145] In the display device 700, since the capacitor can keep the stability of the electric potential of the node electrically connected therewith, by taking the first capacitor C1 included in the adjustment circuit 400 as a device for balancing the load of the target data line SL1' at different working time periods, the load connected with the target data line SL1' can be avoided from having a large difference at different time.

[0146] The above only is the preferred embodiment of the present application, and is not used to limit the present application, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: include: Multiple data lines; A plurality of pixel circuits, each pixel circuit comprising a driving transistor and a data writing module, wherein a first end of the data writing module is electrically connected to the data line, and a second end of the data writing module is electrically connected to the driving transistor; a working cycle of the pixel circuit comprises a data writing phase and at least one adjustment phase, wherein the data writing module in the pixel circuit is turned on in the data writing phase and writes the data voltage on the data line to the driving transistor, and the data writing module in the pixel circuit is turned on in the adjustment phase and writes the adjustment voltage on the data line to the driving transistor; a plurality of regulating circuits, at least one of which is electrically connected to the same data line; the regulating circuit comprising a first capacitor; Among the multiple pixel circuits electrically connected to the target data line, when the first pixel circuit is in the data writing phase, m pixel circuits are in the adjustment phase; when the second pixel circuit is in the data writing phase, n pixel circuits are in the adjustment phase, m>n; the target data line is one of the multiple data lines, and the first pixel circuit and the second pixel circuit are both the pixel circuits electrically connected to the target data line; At least part of the first capacitors in the regulating circuit are configured to be electrically connected to the target data line when the second pixel circuit is in a data writing phase.

2. The display panel according to claim 1, wherein: The display panel also includes a multi-way selection circuit, which includes multiple selection switches. In the same multi-way selection circuit, the input ends of the multiple selection switches are electrically connected, and the output ends are electrically connected to the data lines respectively, and the multiple selection switches are turned on in a time-sharing manner.

3. The display panel according to claim 1 or 2, wherein: The display panel includes a plurality of light emitting devices, the output end of the pixel circuit is electrically connected to the light emitting devices, and the regulating circuit is electrically insulated from the light emitting devices.

4. The display panel according to claim 1 or 2, wherein: The regulation circuit also includes a control module, a first end of the control module is electrically connected to the data line and a second end of the control module is electrically connected to the first plate of the first capacitor, and the control module is used to control the first capacitor to be electrically connected to the data line when turned on, and to control the first capacitor to be electrically disconnected from the data line when turned off.

5. The display panel according to claim 4, wherein: The control module includes a first switch and a diode, wherein a first end of the first switch is electrically connected to the data line and a second end of the first switch is electrically connected to an anode of the diode, and a cathode of the diode is electrically connected to a first plate of the first capacitor.

6. The display panel according to claim 4, wherein: The regulating circuit further includes a regulating reset module, a first end of the regulating reset module is electrically connected to the reset signal line, and a second end of the regulating reset module is electrically connected to the first plate of the first capacitor.

7. The display panel according to claim 6, wherein: The pixel circuit further includes a first reset module, a first end of the first reset module is electrically connected to the reset signal line and a second end of the first reset module is electrically connected to the gate of the driving transistor; and / or, The pixel circuit also includes a second reset module, a first end of the second reset module is electrically connected to the reset signal line and a second end of the second reset module is electrically connected to the first electrode of the light-emitting device, and an output end of the pixel circuit is electrically connected to the first electrode of the light-emitting device.

8. The display panel according to claim 4, wherein: The display panel further includes: a plurality of first scan lines, wherein the plurality of first scan lines include a first sub-scan line and a second sub-scan line, the first sub-scan line is electrically connected to the control end of the data writing module, and the second sub-scan line is electrically connected to the control end of the control module; The shift register circuit includes a plurality of cascaded shift registers; the first scan line is electrically connected to the output end of the shift register.

9. The display panel according to claim 8, wherein: In a working cycle of the pixel circuit, the adjustment phase is located before the data writing phase; The shift register electrically connected to the second sub-scan line is cascaded behind the shift register electrically connected to the first sub-scan line.

10. The display panel according to claim 8, wherein In a working cycle of the pixel circuit, the adjustment phase is located after the data writing phase; The shift register electrically connected to the first sub-scan line is cascaded behind the shift register electrically connected to the second sub-scan line.

11. The display panel according to claim 8, wherein In one working cycle of the pixel circuit, part of the adjustment phase is located before the data writing phase and part of the adjustment phase is located after the data writing phase; Part of the shift registers electrically connected to the second sub-scan lines are cascaded before the shift registers electrically connected to the first sub-scan lines, and part of the shift registers electrically connected to the second sub-scan lines are cascaded after the shift registers electrically connected to the first sub-scan lines.

12. The display panel according to claim 4, wherein: The display panel further includes a control line and a pin. The control line is electrically connected to the control end of the control module; one end of the control line is electrically connected to the pin.

13. The display panel according to claim 1 or 2, characterized in that: The working cycle of the pixel circuit includes a data writing phase and k adjustment phases; The data line is electrically connected to (2*kx) regulating circuits, 2*k>x≥0.

14. The display panel according to claim 13, wherein: x=1 or x=0.

15. The display panel according to claim 13, wherein: x=2*k-1.

16. The display panel according to claim 1, wherein The data line is electrically connected to a plurality of regulating circuits; Among the plurality of pixel circuits electrically connected to the target data line, when the third pixel circuit is in the data writing phase, p pixel circuits are in the adjustment phase; n>p; the third pixel circuit is the pixel circuit electrically connected to the target data line; When the second pixel circuit is in the data writing stage, the number of the first capacitors electrically connected to the target data line is a; when the third pixel circuit is in the data writing stage, the number of the first capacitors electrically connected to the target data line is b, a>b.

17. The display panel according to claim 16, wherein: b＝0。 18. The display panel according to claim 1 or 2, characterized in that: The pixel circuit further includes a threshold value writing module; a second terminal of the data writing module is electrically connected to a first terminal of the driving transistor, a first end of the threshold value writing module is electrically connected to a second terminal of the driving transistor, and a second end of the threshold value writing module is electrically connected to a gate of the driving transistor; In a working cycle of the pixel circuit, at least part of the adjustment phase is located before the data writing phase, and the threshold writing module is turned on during the data writing phase and the adjustment phase located before the data writing phase.

19. The display panel according to claim 1 or 2, characterized in that: In a working cycle of the pixel circuit, at least part of the adjustment phase is located after the data writing phase; The working cycle of the pixel circuit further includes a plurality of light-emitting phases, and at least a portion of the adjustment phase located after the data writing phase is located between adjacent light-emitting phases.

20. A display device, characterized in that: Comprising the display panel according to any one of claims 1-19.

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