Iii-v compound semiconductor structure and manufacturing method

Abstract

A method (60) for forming a III-V compound semiconductor structure comprises: providing a GaSb substrate layer having an outer surface (61); and subjecting the outer surface to liquid hot water H2O, HW, at a temperature of the HW in the range of 90 ᵒC to 110 ᵒC, for example, in the range of 95 ᵒC to 105 ᵒC, for example, about 100 ᵒC, for an HW treatment period of at least 30 minutes, for example, 40 to 80 minutes, for example, about 50 minutes, about 60 minutes, or about 75 minutes.

Description

[0001] III-V COMPOUND SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD

[0002] FIELD OF TECHNOLOGY

[0003] This disclosure concerns semiconductor technology, in particular, I I I -V compound semiconductor structures comprising gallium antimony GaSb and methods for forming the same . At least some aspects of the disclosure relate to structures suitable for passivating GaSb semiconductor structures and / or devices .

[0004] BACKGROUND

[0005] Properties of various I I I -V compound semiconductor materials make them useful for optoelectronic applications . An example of versatile I I I -V compound semiconductor materials is gallium antimony GaSb .

[0006] The efficiency of photovoltaic and light emitting devices may be improved by providing a passivation of the active surface ( s ) of the device structure . A proper passivation may decrease the defect density within the device structure , thereby reducing the loss of charge carriers on the active area of the device such as a solar cell , LED, or some other light emitting or receiving device . This may result in improvements in the radiation detection or emission efficiency . Passivation may also be useful to enhance the electrical properties of various device structures .

[0007] One method to produce a passivation is to deposit a passivating layer structure onto the surface to be passivated . However, from manufacturing process complexity and cost points of view, providing the passivation should not comprise several demanding process steps.

[0008] SUMMARY

[0009] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0010] According to a first aspect, a III-V compound semiconductor structure may be implemented, the semiconductor substrate comprising a crystalline III-V compound semiconductor substrate layer, wherein the group III element comprises gallium Ga, and the group V element comprises Sb; the substrate layer having an outer surface; and an oxide layer of oxide (s) of the III-V semiconductor substrate layer on the outer surface, the oxide layer comprising a plurality of crystalline nanoparticles (121) .

[0011] A majority of more than 50 % , for example, more than 65%, for example, more than 80 % , for example, more than 90 % , for example, more than 95 % , for example, more than 99 % of the plurality of nanoparticles has a maximum diameter in the range of 5 to 120 nm, for example, 10 to 110 nm, for example, 15 to 105 nm, for example, 20 to 100 nm.

[0012] In an embodiment, the plurality of nanoparticles further comprises elongate nanoparticles having a maximum width of at least 100 nm, for example, in the range of 100 nm to 200 nm, for example, in the range of 100 nm to 150 nm, and a maximum length of at least 500 nm, for example, in the range of 500 nm to 2000 nm, for example, in the range of 600 nm to 1800 nm, for example, in the range of 700 nm to 1650 nm, for example, in the range of 900 nm to 1500 nm.

[0013] In an embodiment, which may be in accordance with the previous embodiment, III-V compound semiconductor structure as defined in claim 1 or 2, wherein the oxide layer has a thickness of 5 to 100 nm, for example, 10 to 90 nm, for example, 20 to 80 nm, for example, 30 to 70 nm, for example, 40 to 60 nm.

[0014] In an embodiment, which may be in accordance with any of the previous embodiments, the oxide layer comprises gallium oxide GaOxand antimony oxide SbOx.

[0015] In an embodiment, which may be in accordance with any of the previous embodiments, the oxide layer comprises gallium oxide hydroxide GaHCy .

[0016] In an embodiment, which may be in accordance with any of the previous embodiments, at least some of the plurality of nanoparticles are chemically bonded to the outer surface.

[0017] In an embodiment, which may be in accordance with any of the previous embodiments, the semiconductor structure is obtainable by a method according to the second aspect discussed below.

[0018] In an embodiment, a semiconductor device comprises a III-V compound semiconductor structure in accordance with any of those specified above. The semiconductor device may be a solar cell, a photodetector, a Schottky detector, a metal-semiconductor-metal (MSM) photodetector, a single photon detector (SPAD) , a high-electron- mobility transistors (HEMT) , a light emitting diode LED, or a laser, such as a vertical-cavity surface-emitting laser .

[0019] In a second aspect, a method may be implemented for forming a III-V compound semiconductor structure, the method comprising: providing a crystalline III-V compound semiconductor substrate layer, wherein the group III element comprises gallium Ga, and the group V element comprises antimony Sb, the substrate layer having an outer surface; subjecting the outer surface to liquid hot water H2O, HW, at a temperature of the HW of at least 80 °C, for an HW treatment period of at least 30 minutes, for example, 40 to 80 minutes, for example, about 50 minutes, about 60 minutes, or about 75 minutes. The temperature of the HW may be, for example, in the range of 80 °C to 120 °C, for example, in the range of 90 °C to 110 °C, for example, in the range of 95 °C to 105 °C, for example, at about 100 °C. In some embodiments, it may be even much higher, up to the critical point of water at 373.946 °C. For example, temperatures of 100, 101, 103, 105, 107, 110, 115, 120, 130, 150, 170, 200, 250, 300, and 373.946 °C may be used. At or above 100 °C, appropriately pressurized conditions may be used to keep the water in liquid form.

[0020] In an embodiment, the duration of the HW treatment period is less than or equal to 120 minutes, less than or equal to 90 minutes.

[0021] In an embodiment, which may be in accordance with the previous embodiment, the water is deionized water or distilled water. In an embodiment, which may be in accordance with any of the previous embodiments of the second aspect, the method comprises cleaning the outer surface for removing native oxide (s) therefrom. The cleaning may comprise: a first cleaning step of subjecting the outer surface to a solution of hydrogen chloride HC1, and isopropyl alcohol CH3CHOHCH3, with a ratio of (1:3) ; and a second cleaning step, following the first cleaning step, of subjecting the outer surface to isopropyl alcohol CH3CHOHCH3. The duration of the first cleaning step may be in the range of 1 to 5 minutes, for example, about 3 minutes, and the duration of the second cleaning step may be in the range of 30 seconds to 2 minutes, for example, about 1 minute.

[0022] The HW treatment may take place, thus the outer surface may be subjected to HW, before the outer surface has been treated by or subjected to any other hot liquid, the temperature of which exceeds 50 °C. The outer surface may thus be an untreated, as-grown, or initial surface of the substrate layer. Especially, the HW treatment may take place without the outer surface having been treated by or subjected to liquid hot hydrogen peroxide HHP, the temperature od which exceeds 50 °C, being, for example, in the range of 60 °C to 99 °C.

[0023] Further embodiments of the above aspects may be implemented within the scope of the claims.

[0024] BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present disclosure will be better understood from the following detailed description read in light of the accompanying drawings, wherein: FIG. 1 shows a part of a GaSb semiconductor structure in different stages of its manufacturing process;

[0026] FIG. 2 shows a scanning electron microscope SEM image of a III-V compound semiconductor structure comprising a GaSb substrate layer with an oxide layer thereon;

[0027] FIG. 3 shows photoluminescence measurement results of various III-V semiconductor structure samples;

[0028] FIGs . 4 and 5 show GaSb semiconductor devices with a passivation layer thereon;

[0029] FIG. 6 shows a flow chart of a method for forming a III-

[0030] V compound semiconductor structure; and

[0031] FIG. 7 shows EDS results of the III-V compound semiconductor substrate of FIG. 2.

[0032] Unless specifically stated to the contrary, any drawing of the aforementioned drawings may be schematic and drawn not to scale such that any element in said drawing may be drawn with inaccurate proportions with respect to other elements in said drawing in order to emphasize certain structural aspects of the embodiment of said drawing .

[0033] Moreover, corresponding elements in the embodiments of any two drawings of the aforementioned drawings may be disproportionate to each other in said two drawings in order to emphasize certain structural aspects of the embodiments of said two drawings.

[0034] DETAILED DESCRIPTION

[0035] The uppermost drawing of FIG. 1 shows a crystalline III-

[0036] V compound semiconductor substrate layer 110, the III- V compound semiconductor comprising gallium antimony Ga Sb .

[0037] "III-V compound semiconductor" refers to a semiconductor material of an alloy containing elements of groups III and V in the periodic table. In the example of FIG. 1, of the group III element thus comprises gallium Ga, and the group V element comprises antimony Sb.

[0038] "Crystalline" layer or element of a material may refer to constituents, such as atomic nuclei, of said material forming an ordered, three-dimensional crystal lattice.

[0039] A "layer" refers to a structural entity which may extend substantially along, or parallel to, a fictional base surface or plane (not illustrated in the FIGs.) , and have a thickness in a direction perpendicular to said surface or plane substantially smaller than the dimensions of the layer along or parallel to said surface. Such base surface or plane may be planar or curved. In thecae of a curved base surface or plane, the perpendicular thickness direction may be defined, at each observation point of the base surface or plane, as a direction perpendicular to a planar reference surface or plane tangential to the base surface or plane at the observation point.

[0040] A "substrate layer" refers to a layer capable of serving as a substrate in the sense that further layer (s) or element (s) may be formed on or attached to one or more of the surfaces of the substrate layer.

[0041] The substrate layer 110 has an outer surface 111. "Outer" refers in this example to that surface being defined to form the "uppermost" main surface of the substrate layer when observed in a fictitious coordinate system fixed to the semiconductor structure with the hori zontal directions defined by the fictitious base surface or plane , and the upwards / downwards directions directed along the thickness direction of the substrate layer . That surface may therefore be called also a top surface . Further, that surface may also be called a deposition surface , "deposition" referring to a possibi lity to deposit , or to have deposited, some material on the deposition surface . Yet further, that surface may also be called a treatment surface , "treatment" referring to a possibility to carry out a treatment on or of the treatment surface , for example , to form a passivation layer thereon .

[0042] In other embodiments or examples , an outer surface of a semiconductor structure may comprise a bottom surface of a substrate layer . In yet other embodiments or examples , an outer surface may comprise a side surface of a semiconductor substrate layer, or a side surface of a three-dimensional structure formed in a substrate layer . Such three-dimensional structure may be , for example , a mesa structure formed in a semiconductor substrate layer, for example , by etching . An example is illustrated in FIG . 5 .

[0043] The I I I -V semiconductor structure 100 illustrated in FIG . 1 may form an integral or inseparable part of a complete , operable semiconductor device , the other layers , parts , and / or members of the semiconductor device being not i llustrated in the drawing of FIG . 1 . Alternatively, it may be a discrete or stand-alone structure possibly attached to or formed on a semiconductor device . In the case of the III-V semiconductor structure 100 being attached to or formed on, or forming a part of, another structure or layer of e.g. a complete semiconductor device, the underlying structure or layer may be formed of or comprise the same or different material as the III-V semiconductor layer. Especially, the underlying structure or layer may be formed of a different III- V semiconductor material. For example, a III-V semiconductor structure with a substrate layer of GaSb may lie on an underlying structure or layer of InP.

[0044] As marked adjacent to the arrow between the uppermost and the lowermost drawings of FIG. 1, the lowermost drawing illustrates the semiconductor structure 100 after subjection of the outer surface 111 of the substrate layer 110 to hot water H2O, hereinafter referred to as "HW". It may be preferable to use deionized water. In some embodiments, distilled water may be used.

[0045] The HW subjection or treatment may be carried out in accordance with the below disclosure the method aspects with reference to FIG. 6.

[0046] In result of the HW treatment, the semiconductor structure 100 comprises an oxide layer 120 on the outer surface 111 of the substrate layer 110.

[0047] The oxide layer 120 is formed as a substantially continuous layer extending all over the part of the outer surface 111 illustrated in FIG. 1.

[0048] The oxide layer 120 may comprise oxide of at least one of the III-V compound semiconductor elements. For example, the oxide layer 120 may comprise at least gallium oxide GaOx, and possibly also antimony oxide SbOx. "X" in those molecular formula denotes that the oxide layer may comprise different stoichiometric or non-stochio- metric oxide composition ( s ) . For example, for gallium oxide, the stoichiometric composition if Ga2Os, but the oxide layer may comprise also, or alternatively, non- stoichiometric gallium oxide (s) .

[0049] In addition to, or instead of, oxide (s) of the III-V compound semiconductor elements, the oxide layer 120 may comprise oxide hydroxide of at least one of the III-V compound semiconductor elements. For example, the oxide layer may comprise gallium oxide hydroxide GaHCy .

[0050] The oxide layer 120 comprises, and may be substantially formed of, a plurality of crystalline nanoparticles 121.

[0051] "Nanoparticle" refers to a particle with its maximum diameter in the nanometer range, i.e. substantially below 1 pm, for example, less than or equal to 500 nm.

[0052] "Maximum diameter" Dparticie of a nanoparticle refers to a longest distance, measured along a straight line, between two points of the three-dimensional nanoparticle. The maximum diameter of one nanoparticle is marked in the lowermost drawing of FIG. 1.

[0053] The nanoparticles 121 of the oxide layer 120 may have different sizes. A majority of the plurality of nanoparticles may have a maximum diameter in the range of 5 to 120 nm, for example, 10 to 110 nm, for example, 15 to 105 nm, for example, 20 to 100 nm.

[0054] Analyses of various sample structures have shown the nanoparticles comprising ones with maximum diameters, for example, of 20 nm, 28 nm, 40 nm, and 100 nm.

[0055] The "majority" may refer to a portion of higher than 50 % , for example, higher than 80 % , of the nanoparticles having their maximum diameter falling within such range . The maj ority may alternatively refer to any other appropriate percentage , such as more than 65 , 90 , 95 , or

[0056] 99 % .

[0057] Maximum diameter of the at least part of the nanoparticles lying in a specific range may refer to those nanoparticles comprising nanoparticles of different si zes , thus with different maximum diameters within the specific range . Alternatively, it may refer to those nanoparticles comprising substantially equally dimensioned nanoparticles having their maximum diameters within a narrower sub-range of the specific range .

[0058] In addition to the plurality of nanoparticles with di mensions as discussed above , the oxide layer may comprise also larger and / or smaller nanoparticles .

[0059] For example , the nanoparticles may also comprise elongate nanoparticles having a maximum width of at least

[0060] 100 nm, for example , in the range of 100 nm to 200 nm, for example , in the range of 100 nm to 150 nm, and a maximum length of at least 500 nm, for example , in the range of 500 nm to 2000 nm, for example , in the range of 900 nm to 1500 nm . One such larger, elongated nanoparticle is visible in the SEM image of FIG . 2 .

[0061] The thickness of the oxide layer t0Xide layer may depend on the si ze range of the nanoparticles . The thickness may lie , for example , in the range of about of 5 to 100 nm, for example , 20 to 80 nm, for example , 40 to 60 nm .

[0062] The nanoparticles may have various shapes . At least some of them may be substantially elongate . At least some of them may be roughly cubic or roundish . The crystal structure of the oxide a nanoparticle is formed of may affect the three-dimensional shape thereof.

[0063] At least some, possibly substantially all, of the plurality of nanoparticles 121 may be chemically bonded to the outer surface 111 of the substrate layer 110.

[0064] The drawings of FIG. 1 are partial illustrations of the semiconductor structure 100 and its substrate layer 110 and oxide layer 120. This means that the semiconductor structure 100 with its layers may continue, in the horizontal directions outside the cut off part thereof shown in the illustrations of FIG. 1. On the other hand, a plurality of semiconductor substrates may be formed on, or belong to, a larger carrier such as a semiconductor wafer or a piece or die of such.

[0065] As mentioned above, "horizontal" refers, in the context of the FIGs., to the directions along or parallel to the fictitious base plane or surface along or parallel to which the substrate layer extends.

[0066] FIG. 2 illustrates a SEM image of a semiconductor structure 200 with a GaSb substrate layer treated by HW. The semiconductor structure 200 had the following layer structure formed on a 5 x 5 mm n-type GaSb (100) substrate having a thickness of 500 pm: a GaSb buffer layer of 100 nm; an AlAsSb diffusion barrier layer of 250 nm; an unintentionally doped UID GaSb substrate layer of 1000 nm.

[0067] Before exposing the substrate layer to HW, the outer surface thereof was cleaned by subjecting it to a solution of hydrogen chloride, HC1, and isopropyl alcohol IPA, CH3CHOHCH3, with a ratio of (1:3) ; and then to isopropyl alcohol IPA, CH3CHOHCH3. The durations of the first and second cleaning step were 3 and 1 minutes , respectively .

[0068] After cleaning, the outer surface of the GaSb substrate layer was exposed to HW of 100 °C for an HW treatment period of 75 minutes .

[0069] In result of the HW treatment , an oxide layer 220 comprising crystalline nanoparticles 221 , 222 was formed on the outer surface . The formation of the oxide layer of oxides of Ga and Sb was confirmed by energy dispersive spectroscopy EDS and X-ray photoelectron spectroscopy XPS measurements . EDS images of the sample are presented in FIG 7 .

[0070] The SEM image of FIG 2 shows the hazy appearance of the oxide layer 220 , resulting from the oxide layer comprising a plurality of nanoparticles instead of being formed as a solid, single crystal layer .

[0071] In addition to smaller nanoparticles , FIG . 2 also shows the oxide layer 220 compris ing an elongated larger nanoparticle 222 having a length of about 1 pm .

[0072] The images of FIG . 7 represent a location of the sample different from that of the SEM image of FIG . 2 . The images are the following : a) the SEM image used for analysis ; b) constructed compositional map of the surface based on EDS results ; and c) , d) , and e ) represent Ga , 0, and Sb concentration, respectively, on the surface . The EDS images show that the larger nanoparticles comprise gallium and oxygen, thus forming gallium oxide , and the smaller nanoparticles comprise gallium, antimony, and oxide , thus forming gallium oxide and antimony oxide . It has been surprisingly found that I I I -V semiconductor structures in accordance with the above examples may possess advantageous properties , especially in terms of their capability to serve for surface passivation of semiconductor devices .

[0073] FIG . 3 shows laser-induced photoluminescence intensity measurements carried out for sample semiconductor structures in accordance with that of FIG . 2 . Measured samples comprise 1 ) a reference sample semiconductor structure without any HW treatment , 2 ) a sample semiconductor structure with an oxide layer formed by a method in accordance with that discussed above with reference to FIG . 2 , and 3 ) a sample semiconductor structure in accordance with the sample semiconductor structure 2 ) further comprising an anti-reflection coating ARC comprising Si02 formed on the oxide layer . The PL spectra of the sample semiconductor structures 1 ) and 2 ) show that the PL intensity increases strongly in result of the oxide layer formed by the HW treatment . This may indicate a reduction in the defect density in the crystalline substrate layer which may improve the light receiving or light emitting performance of an optoelectronic or photonic semiconductor device incorporating a semiconductor structure as defined above . For example , in a light emitting device such as a LED or a laser, this may result in higher intensity of the light output . To summary, the oxide layer formed by the HW treatment may be used as an efficient passivation for various GaSb device layers .

[0074] Another advantageous effect can be seen by comparing the PL spectra of the sample semiconductor structures 2 ) and 3 ) . Those spectra indicate the additional AR coating having practically no effect on the PL intens ity . This proves the passivation in the form of the oxide layer formed by the HW treatment being compatible with the AR coating .

[0075] The cross-sectional image of FIG. 4 shows a III-V compound semiconductor device 40 where at least some of the operational layers are formed of GaSb.

[0076] The semiconductor device illustrated in a simplified and schematic form in the drawing of FIG. 4 may comprise any appropriate device layers, structures, and elements. In the drawing of FIG. 4, only a device layer part 41 denoting the device layer (s) , an upper contact structure 42, and a semiconductor structure 400 with a III-V compound semiconductor substrate layer 410 and an oxide layer 420 with nanoparticles thereon are illustrated. The semiconductor structure 400 may be in accordance with any of those discussed above with reference to FIGs. 1 to 3.

[0077] In the example of FIG. 4, the III-V compound semiconductor structure 400 is illustrated as an additional structure formed on the other part(s) of the semiconductor device. In other embodiments, a III-V compound semiconductor structure may be formed in or on an existing structure of the semiconductor device. Then, any appropriate existing GaSb layer may serve as a substrate layer on which an oxide layer is formed.

[0078] The III-V compound semiconductor device 40 may be of any appropriate device type. Especially, it may be any of a solar cell, a photodetector, a light emitting diode LED, or a laser such as vertical-cavity surface-emitting laser, or any other light receiving and / or emitting device. Then, the III-V compound semiconductor structure may serve in the device as an anti-reflection structure , coating, or element . Thereby, it may improve light capture into , or light output out of , the I I I -V compound semiconductor device 40 .

[0079] In other embodiments , a compound semiconductor device with a GaSb substrate layer and an oxide layer thereon may be implemented as , for example , a Schottky detector . Further examples of electrical devices comprise a metalsemiconductor-metal (MSM) photodetector, a single photon detector ( SPAD) , and a high-electron-mobility transistors (HEMT ) .

[0080] Any of those devices mentioned above may be designed for and / or operate at parts of the electromagnetic spectrum corresponding to the bandgap of GaSb . At least in some embodiments , the operating wavelength range may lie in infrared wavelengths 1 . 4 to 21 pm .

[0081] The cross-sectional image of FIG . 5 shows a I I I -V compound semiconductor device 50 with a mesa-like semiconductor structure 500 rising from a substrate 501 . The semiconductor structure 500 comprises a plurality of device layers 510 , each of which comprises GaSb . Each of the device layers 510 have a side surface 512 . In the terminology used herein, the device layers serve as substrate layers , and the top surface 511 of the uppermost device layer and the side surfaces 512 of the device layers serve as outer surfaces of those substrate layers .

[0082] The mesa-like semiconductor structure 500 has been treated by a HW treatment to form an oxide layer 520 of oxide ( s ) of Ga and / or Sb on parts thereof comprising GaSb . The oxide layer covers both the top surface 511 of the uppermost device layer and the side surfaces 512 of the GaSb device layers. In addition to passivation function, the oxide layer may prevent or decrease unwanted leakage of electric current along the side surfaces 512 of the device layers 51.

[0083] The oxide layer 520 may be in accordance with any of those discussed above with reference to FIGs. 1 to 4. It may be formed in accordance with any of the treatments discussed above with reference to FIGs. 1 to 4 or hereinafter with reference to FIG. 6.

[0084] Above, mainly structural and material features of III- V compound semiconductor structures and semiconductor devices are discussed. In the following, more emphasis will lie on methods for forming III-V compound semiconductor structures. The III-V semiconductor structures discussed above may be formed by methods discussed hereinafter. Respectively, the methods hereinafter discussed may be used to manufacture III-V semiconductor structures in accordance with those discussed above.

[0085] The method 60 of FIG. 6 starts, in first operation 81, by providing a crystalline III-V compound semiconductor substrate having an outer surface. The group III element comprises gallium, Ga, and the group V element comprises antimony Sb.

[0086] An "operation" may refer to a single action, or it may comprise a series of sub-operations or steps.

[0087] As discussed above with reference to FIGs. 1 to 5, the semiconductor substrate may be a stand-alone structure. Alternatively, it may be attached to another semiconductor structure such as a III-V compound semiconductor device, or form an integral, inseparable part of such device .

[0088] In second operation 62, the outer surface is cleaned. This may be carried out, for example, by subjecting the outer surface in a first cleaning step to a solution of hydrogen chloride, HC1, and isopropyl alcohol IPA, CH3CHOHCH3, with a ratio of (1:3) ; and then subjecting the outer surface in a second cleaning step to isopropyl alcohol, CH3CHOHCH3. Duration of one or both of the subjection steps may be, for example, 0.5 to 5 minutes, for example, about 1 to 3 minutes. In one embodiment, the duration of the first cleaning step is 1 minute, and the duration of the second cleaning step is about 3 minutes.

[0089] In other embodiments, different cleaning operation (s) or methods, possibly utilizing different agents may be carried out. In yet other embodiments, methods without cleaning operation may be implemented, as indicated by the operation 62 being marked as optional in FIG. 6. For example, in some embodiments, a pre-cleaned semiconductor substrate may be used.

[0090] In third operation 63, the outer surface is subjected to liquid hot water HW, H2O, at a temperature of the HW in the range of 90 °C to 110 °C, for example, in the range of 95 °C to 105 °C, for example, about 100 °C, for an HW treatment period of at least 30 minutes. In other embodiments, the temperature of the liquid HW may be anything of at least 80 °C, the upper limit being the critical point of water at 373.946 °C. In the case of the temperature lying at or exceeding 100 °C, the HW treatment may be carried out in pressurized conditions, i.e. in an elevated pressure higher than the atmospheric pressure, to maintain the hot water in liquid form. Then, temperatures, for example, of 100, 101, 103, 105, 107, 110, 115, 120, 130, 150, 170, 200, 250, 300, or 373.946 °C can be used.

[0091] The HW treatment period may have a duration of at least 30 minutes, 40 to 80 minutes, for example, about 50 minutes, about 60 minutes, or about 75 minutes.

[0092] The third operation 63 may follow the second operation 62, or start the method in the case of no cleaning operation carried out, directly such that that there is no preceding subjection of the outer surface to any hot liquid such as Hot Hydrogen Peroxide HHP before subjection thereof to HW.

[0093] Water used in the HW treatment may be deionized water. In other embodiments, it may be distilled water. It may also be possible to use regular water, such as tap water, without any further treatment needed to be applied to the water. Further, in some embodiments, heavy water may be used.

[0094] As discussed above with reference to FIGs. 1 to 5, the HW treatment results in an oxide layer being formed on the outer surface.

[0095] An HW treatment period refers to the time the deposition is subjected to HW, respectively. As specified above, the durations of that time period may vary.

[0096] "Subjecting" the outer surface to HW refers to treating the outer surface by HW. Then, the outer surface is arranged into contact with liquid HW so that physical and / or chemical interaction between the outer surface and HHP or HW is possible. Said arranging may be carried out in any appropriate manner, using any appropriate means . For example , a beaker containing liquid HW may be used . Then, the outer surface of the semiconductor structure may be simply dipped into the liquid HW contained in the beaker . A large number of semiconductor structures may be formed, for example , on a single wafer . Then, dipping the wafer to the beaker enables AR semiconductor structures to be produced by an efficient batch process . Thereby, the method may be scaled for industrial purposes .

[0097] Various embodiments of the method may advantageously provide an efficient , simple , and low-cost way to produce I I I -V compound semiconductor structures with an oxide layer thereon suitable for serving as passivation .

[0098] It is obvious to a person ski lled in the art that with the advancement of technology, the basic idea of the invention may be implemented in various ways . The invention and its embodiments are thus not limited to the examples described above , instead they may vary within the scope of the claims .

[0099] It wi ll be understood that any benef its and advantages described above may relate to one embodiment or may relate to several embodiments . The embodiments are not limited to those that solve any or all of the stated problems or those that have any or all of the stated benefits and advantages .

[0100] The term "compris ing" i s used in thi s specification to mean including the feature ( s ) or act ( s ) followed thereafter, without excluding the presence of one or more additional features or acts. It will further be understood that reference to 'an' item refers to one or more of those items.

Claims

CLAIMS1. A III-V compound semiconductor structure (100) , comprising: a crystalline III-V compound semiconductor substrate layer (110) , wherein the group III element comprises gallium Ga, and the group V element comprises Sb; the substrate layer (110) having an outer surface (111) ; and an oxide layer (120) of oxide (s) of the III-V semiconductor substrate layer on the outer surface, the oxide layer comprising a plurality of crystalline nanoparticles (121) , a majority of more than 50 % , for example, more than 65%, for example, more than 80 % , for example, more than 90 % , for example, more than 95 % , for example, more than 99 % of the nanoparticles having a maximum diameter in the range of 5 to 120 nm, for example, 10 to 110 nm, for example, 15 to 105 nm, for example, 20 to 100 nm.

2. A III-V compound semiconductor structure (100) as defined in claim 1, wherein the nanoparticles (121) further comprise elongate nanoparticles having a maximum width of at least 100 nm, for example, in the range of 100 nm to 200 nm, for example, in the range of 100 nm to 150 nm, and a maximum length of at least 500 nm, for example, in the range of 500 nm to 2000 nm for example, in the range of 900 nm to 1500 nm.

3. A III-V compound semiconductor structure (100) as defined in claim 1 or 2, wherein the oxide layer (120) has a thickness of 5 to 100 nm, for example, 20 to 80 nm, for example, 40 to 60 nm.

4. A III-V compound semiconductor structure (100) as defined in any of claims 1 to 3, wherein the oxide layer (120) comprises gallium oxide GaOxand antimony oxide SbOx.

5. A III-V compound semiconductor structure (100) as defined in any of claims 1 to 4, wherein the oxide layer (120) comprises gallium oxide hydroxide GaHO2•6. A III-V compound semiconductor structure (100) as defined in any of claims 1 to 5, wherein at least some of the plurality of nanoparticles (121) are chemically bonded to the outer surface (Illa, 111b) .

7. A III-V compound semiconductor structure (100) as defined in any of the preceding claims, wherein the semiconductor structure is obtainable by a method according to any of claims 10 to 14.

8. A semiconductor device (40, 50) comprising a III-V compound semiconductor structure (400, 500) as defined in any of claims 1 to 7.

9. A semiconductor device (40, 50) as defined in claim 8, wherein the semiconductor device is a solar cell, a photodetector, a Schottky detector, a metalsemiconductor-metal (MSM) photodetector, a single photon detector (SPAD) , a high-electron-mobility transistors (HEMT) , a light emitting diode LED, or a laser, such as a vertical-cavity surface-emitting laser.

10. A method (60) for forming a III-V compound semiconductor structure, the method comprising: providing a crystalline III-V compound semiconductor substrate layer, wherein the group III element comprises gallium Ga, and the group V element comprisesantimony Sb, the substrate layer having an outer surface (61) ; subjecting the outer surface to liquid hot water H2O, HW, at a temperature of the HW of at least 80 °C, for an HW treatment period of at least 30 minutes, for example, 40 to 80 minutes, for example, about 50 minutes, about 60 minutes, or about 75 minutes (63) .

11. A method as defined in claim 10, wherein the temperature of the HW lies in the range of 80 °C to 120 °C, for example, 90 °C to 110 °C, for example, in the range of 95 °C to 105 °C, for example, at about 100 °C.

12. A method (60) as defined in claim 11, wherein the duration of the HW treatment period is less than or equal to 120 minutes, for example, less than or equal to 90 minutes.

13. A method (60) as defined in any of claims 10 to 12, wherein the water is deionized water or distilled water.

14. A method (60) as defined in any of claims 10 to 13, wherein before the subjection to HW, the method comprises cleaning the outer surface for removing native oxide (s) therefrom (62) .

15. A method (60) as defined in claim 14, wherein the cleaning (62) comprises: a first cleaning step of subjecting the outer surface to a solution of hydrogen chloride HC1, and isopropyl alcohol CH3CHOHCH3, with a ratio of (1:3) ; and a second cleaning step, following the first cleaning step, of subjecting the outer surface to isopropyl alcohol CH3CHOHCH3.

16. A method (60) as defined in claim 15, wherein the duration of the first cleaning step is in the range of 1 to 5 minutes, for example, about 3 minutes, and the duration of the second cleaning step is in the range of 30 seconds to 2 minutes, for example, about 1 minute.

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