Semiconductor device

Abstract

Provided is a semiconductor device having a small footprint. This semiconductor device has a transistor and a first insulating layer. The transistor has an electroconductive layer and a metal oxide layer. The first insulating layer is positioned on the electroconductive layer. The first insulating layer has an end portion in contact with the upper surface of the electroconductive layer. The first insulating layer has a second insulating layer, and a third insulating layer located on the second insulating layer. The metal oxide layer has an end portion in contact with the upper surface of the electroconductive layer, an end portion in contact with the side surface of the second insulating layer, an end portion in contact with the side surface of the third insulating layer, and an end portion in contact with the upper surface of the third insulating layer. The third insulating layer has a region in which the hydrogen content is greater than that in the second insulating layer.

Description

Semiconductor Devices

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. 2. Description of the Related Art One embodiment of the present invention relates to a transistor and a manufacturing method thereof.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] Semiconductor devices including transistors are widely used in electronic devices. For example, in display devices, pixel size can be reduced by reducing the area occupied by a transistor, and resolution can be increased. Therefore, miniaturized transistors are in demand.

[0005] As devices requiring high-definition display devices, devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR) are being actively developed.

[0006] 2. Description of the Related Art As display devices, for example, light-emitting devices having organic electroluminescence (EL) elements or light-emitting diodes (LEDs) have been developed.

[0007] Patent Document 1 discloses a high-definition display device using organic EL elements.

[0008] International Publication No. 2016 / 038508

[0009] An object of one embodiment of the present invention is to provide a semiconductor device including a micro-sized transistor. Another object is to provide a semiconductor device including a transistor with a short channel length. Another object is to provide a semiconductor device including a transistor with high on-state current. Another object is to provide a semiconductor device including a transistor with high field-effect mobility. Another object is to provide a semiconductor device including a transistor with favorable electrical characteristics. Another object is to provide a semiconductor device that operates at high speed. Another object is to provide a semiconductor device with a small occupation area. Another object is to provide a semiconductor device with low wiring resistance. Another object is to provide a semiconductor device or display device with low power consumption. Another object is to provide a highly reliable transistor, semiconductor device, or display device. Another object is to provide a high-resolution display device. Another object is to provide a method for manufacturing a semiconductor device or display device with high productivity. Another object is to provide a novel transistor, semiconductor device, or display device, or a manufacturing method thereof.

[0010] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0011] One embodiment of the present invention is a semiconductor device including a transistor and a first insulating layer. The transistor includes a conductive layer and a metal oxide layer. The first insulating layer is located over the conductive layer. The first insulating layer has an end portion in contact with a top surface of the conductive layer. The first insulating layer includes a second insulating layer and a third insulating layer over the second insulating layer. The metal oxide layer has an end portion in contact with a top surface of the conductive layer, an end portion in contact with a side surface of the second insulating layer, an end portion in contact with a side surface of the third insulating layer, and an end portion in contact with a top surface of the third insulating layer. The third insulating layer has a region with a higher hydrogen content than the second insulating layer.

[0012] In the semiconductor device, the transistor preferably includes a gate electrode and a gate insulating layer. The gate insulating layer preferably has a region in contact with an upper surface and a side surface of the metal oxide layer. The gate electrode preferably has a region facing a side surface of the first insulating layer with the gate insulating layer and the metal oxide layer interposed therebetween.

[0013] One embodiment of the present invention is a semiconductor device including a transistor and a first insulating layer. The transistor includes a conductive layer, a metal oxide layer, a gate insulating layer, and a gate electrode. The first insulating layer is located over the conductive layer. The first insulating layer has an edge portion in contact with a top surface of the conductive layer. The first insulating layer includes a second insulating layer and a third insulating layer over the second insulating layer. The metal oxide layer has a region in contact with a top surface of the conductive layer, a side surface of the second insulating layer, and a top surface and a side surface of the third insulating layer. The gate insulating layer has a region in contact with a top surface and a side surface of the metal oxide layer and a side surface of the first insulating layer. The gate electrode has a region facing a side surface of the first insulating layer with the gate insulating layer and the metal oxide layer interposed therebetween. The third insulating layer has a region having a higher hydrogen content than the second insulating layer.

[0014] In the semiconductor device, the first insulating layer preferably has an opening that reaches the conductive layer, and the metal oxide layer, the gate insulating layer, and the gate electrode preferably each have a region located within the opening.

[0015] In the semiconductor device, the second insulating layer preferably contains silicon and oxygen, and the third insulating layer preferably contains silicon and nitrogen.

[0016] In the semiconductor device described above, the first insulating layer preferably has a fourth insulating layer between the second insulating layer and the third insulating layer. The fourth insulating layer preferably contains silicon and nitrogen. The third insulating layer preferably has a region having a higher hydrogen content than the fourth insulating layer.

[0017] The aforementioned semiconductor device preferably has a fifth insulating layer. The fifth insulating layer preferably has a region in contact with the lower surface of the conductive layer. The first insulating layer preferably has a sixth insulating layer. The sixth insulating layer is preferably located between the second insulating layer and the conductive layer. The fifth insulating layer preferably contains silicon and nitrogen. The sixth insulating layer preferably contains silicon and nitrogen. The fifth insulating layer preferably has a region having a higher hydrogen content than the sixth insulating layer.

[0018] In the semiconductor device described above, the first insulating layer preferably has a fourth insulating layer between the second insulating layer and the third insulating layer. The fourth insulating layer preferably contains aluminum and oxygen. The third insulating layer preferably has a region with a higher hydrogen content than the fourth insulating layer.

[0019] The aforementioned semiconductor device preferably has a fifth insulating layer. The fifth insulating layer preferably has a region in contact with the lower surface of the conductive layer. The first insulating layer preferably has a sixth insulating layer between the second insulating layer and the conductive layer. The fifth insulating layer preferably contains silicon and nitrogen. The sixth insulating layer preferably contains silicon and nitrogen. The fifth insulating layer preferably has a region having a higher hydrogen content than the sixth insulating layer.

[0020] In the above-described semiconductor device, the metal oxide layer preferably contains indium.

[0021] In the above-described semiconductor device, the conductive layer preferably contains indium and oxygen.

[0022] According to one embodiment of the present invention, a semiconductor device including a micro-sized transistor can be provided. Alternatively, a semiconductor device including a transistor with a short channel length can be provided. Alternatively, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with high field-effect mobility can be provided. Alternatively, a semiconductor device including a transistor with favorable electrical characteristics can be provided. Alternatively, a semiconductor device that operates at high speed can be provided. Alternatively, a semiconductor device with a small occupation area can be provided. Alternatively, a semiconductor device with low wiring resistance can be provided. Alternatively, a semiconductor device or display device with low power consumption can be provided. Alternatively, a highly reliable transistor, semiconductor device, or display device can be provided. Alternatively, a high-resolution display device can be provided. Alternatively, a method for manufacturing a semiconductor device or display device with high productivity can be provided. Alternatively, a novel transistor, semiconductor device, or display device, or a manufacturing method thereof can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0024] FIG. 1A is a top view showing an example of a semiconductor device. FIGS. 1B and 1C are cross-sectional views showing an example of a semiconductor device. FIGS. 2A and 2B are perspective views showing an example of a semiconductor device. FIG. 3 is a cross-sectional view showing an example of a semiconductor device. FIG. 4 is a cross-sectional view showing an example of a semiconductor device. FIG. 5A is a cross-sectional view showing an example of a semiconductor device. FIG. 5B is a top view showing an example of a semiconductor device. FIGS. 6A and 6B are cross-sectional views showing an example of a semiconductor device. FIGS. 7A and 7B are cross-sectional views showing an example of a semiconductor device. FIGS. 8A and 8B are cross-sectional views showing an example of a semiconductor device. FIGS. 9A is a top view showing an example of a semiconductor device. FIGS. 9B and 9C are cross-sectional views showing an example of a semiconductor device. FIGS. 10A and 10B are perspective views showing an example of a semiconductor device. FIG. 11A is a top view showing an example of a semiconductor device. FIG. 11B is a cross-sectional view showing an example of a semiconductor device. FIG. 12A is a top view showing an example of a semiconductor device. FIG. 12B is an equivalent circuit diagram of the semiconductor device. FIG. 12C is a cross-sectional view showing an example of a semiconductor device. FIG. 13 is a cross-sectional view showing an example of a semiconductor device. 14A and 14B are perspective views showing an example of a semiconductor device. FIG. 15 is a cross-sectional view showing an example of a semiconductor device. FIG. 16A is a cross-sectional view showing an example of a semiconductor device. FIG. 16B is a top view showing an example of a semiconductor device. FIG. 17A is a top view showing an example of a semiconductor device. FIG. 17B is a cross-sectional view showing an example of a semiconductor device. FIGS. 18A and 18B are perspective views showing an example of a semiconductor device. FIG. 19A is a top view showing an example of a semiconductor device. FIG. 19B is an equivalent circuit diagram of the semiconductor device. FIG. 19C is a cross-sectional view showing an example of a semiconductor device. FIG. 20 is a cross-sectional view showing an example of a semiconductor device. FIGS. 21A and 21B are perspective views showing an example of a semiconductor device. FIG. 22 is a cross-sectional view showing an example of a semiconductor device. FIG. 23A is a top view showing an example of a semiconductor device. FIG. 23B is an equivalent circuit diagram of the semiconductor device. FIG. 23C is a cross-sectional view showing an example of a semiconductor device. FIG. 24 is a cross-sectional view showing an example of a semiconductor device. FIG. 25A is a top view showing an example of a semiconductor device. FIG. 25B is an equivalent circuit diagram of the semiconductor device. FIG. 25C is a cross-sectional view showing an example of a semiconductor device.FIG. 26A is a top view showing an example of a semiconductor device. FIG. 26B is an equivalent circuit diagram of the semiconductor device. FIG. 26C is a cross-sectional view showing an example of a semiconductor device. FIGS. 27A and 27B are equivalent circuit diagrams of a semiconductor device. FIG. 28A is a top view showing an example of a semiconductor device. FIG. 28B is a cross-sectional view showing an example of a semiconductor device. FIGS. 29A and 29B are perspective views showing an example of a semiconductor device. FIG. 30A is a top view showing an example of a semiconductor device. FIG. 30B is a cross-sectional view showing an example of a semiconductor device. FIG. 31A is a top view showing an example of a semiconductor device. FIG. 31B is a cross-sectional view showing an example of a semiconductor device. FIGS. 32A and 32B are cross-sectional views showing an example of a semiconductor device. FIGS. 33A and 33B are perspective views showing an example of a semiconductor device. FIG. 34A is a top view showing an example of a semiconductor device. FIG. 34B is a perspective view showing an example of a semiconductor device. FIG. 35A is a top view showing an example of a semiconductor device. FIG. 35B is a cross-sectional view showing an example of a semiconductor device. FIGS. 36A and 36B are cross-sectional views showing an example of a semiconductor device. 37A and 37B are perspective views showing an example of a semiconductor device. FIG. 38A is a top view showing an example of a semiconductor device. FIG. 38B is a cross-sectional view showing an example of a semiconductor device. FIGS. 39A to 39E are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 40A to 40D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 41 is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. FIGS. 42A to 42C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 43 is a perspective view showing an example of a display device. FIGS. 44A and 44B are cross-sectional views showing an example of a display device. FIG. 45 is a cross-sectional view showing an example of a display device. FIGS. 46A to 46C are cross-sectional views showing an example of a display device. FIGS. 47A and 47B are cross-sectional views showing an example of a display device. FIG. 48 is a cross-sectional view showing an example of a display device. FIGS. 49A to 49C are cross-sectional views showing an example of a display device. FIG. 50 is a cross-sectional view showing an example of a display device. FIG. 51 is a cross-sectional view showing an example of a display device. FIGS. 52A to 52D are diagrams showing examples of electronic devices. 53A to 53F are diagrams showing an example of an electronic device.54A to 54G are diagrams showing an example of an electronic device.

[0025] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0026] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0027] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0028] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0029] The terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0030] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0031] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. The source and drain of a transistor may be appropriately referred to as the source terminal and drain terminal, or the source electrode and drain electrode, depending on the situation.

[0032] The terms "gate" and "back gate" can be used interchangeably. Therefore, in this specification and the like, the terms "gate" and "back gate" can be used interchangeably. Note that the names of the gate and back gate of a transistor can be appropriately changed to gate electrode and back gate electrode, etc., depending on the situation.

[0033] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0034] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0035] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0036] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0037] In this specification, unless otherwise specified, the on-state current refers to the drain current (also referred to as Id) when a transistor is in an on state (also referred to as a conductive state). Unless otherwise specified, the on state refers to a state in which the voltage between the gate and the source (also referred to as gate voltage, Vg or Vgs) is equal to or higher than a threshold voltage (also referred to as Vth) for an n-channel transistor, or a state in which the voltage is equal to or lower than the threshold voltage for a p-channel transistor.

[0038] In this specification and the like, unless otherwise specified, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage between the gate and the source is lower than the threshold voltage in an n-channel transistor, and higher than the threshold voltage in a p-channel transistor.

[0039] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0040] In this specification, the top surface shape of a component refers to the contour shape of the component as viewed from above (also referred to as a plan view). The top surface view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0041] In this specification, the phrase "top surface shapes that match or approximately match" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes that match or approximately match" may also be used. Furthermore, when the top surface shapes match or approximately match, it can also be said that "edges match or approximately match" or "edges are aligned or approximately aligned."

[0042] In this specification and the like, a tapered shape refers to a shape in which at least a part of a side surface of a structure is inclined with respect to a substrate surface or a surface to be formed. The angle formed between the inclined side surface and the substrate surface or the surface to be formed is sometimes referred to as a taper angle.

[0043] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure. Because devices with an MML structure can be manufactured without using a metal mask, they can exceed the upper limit of resolution due to the alignment accuracy of the metal mask. Furthermore, devices with an MML structure can eliminate the need for equipment for manufacturing metal masks and a metal mask cleaning process. Furthermore, devices with an MML structure are suitable for mass production because they can keep manufacturing costs low.

[0044] In this specification and the like, a structure in which different light-emitting layers are formed for light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and making it easier to improve brightness and reliability.

[0045] In this specification and the like, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0046] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.

[0047] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0048] In this specification and the like, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0049] In this specification and the like, the sacrificial layer (which may also be referred to as a mask layer) is located above at least the light-emitting layer (more specifically, a layer that is processed into an island shape among the layers that make up the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0050] In this specification and the like, flexibility refers to the property of an object being soft and bendable, i.e., the property of an object being able to deform in response to an external force applied to the object, regardless of whether or not the object has elasticity or the ability to return to its original shape before deformation.

[0051] For example, a flexible electronic device can deform in response to an external force. A flexible electronic device can be used while fixed in a deformed state, or can be used after repeatedly deforming. A flexible display device (also referred to as a flexible display device, flexible display device, flexible display, etc.) can deform in response to an external force. A flexible display device can be used while fixed in a deformed state, or can be used after repeatedly deforming, or can be used in an undeformed state. A flexible battery (also referred to as a flexible battery, flexible battery, flexible battery, etc.) can deform in response to an external force. A flexible battery can be used while fixed in a deformed state, or can be used after repeatedly deforming, or can be used in an undeformed state. A flexible substrate (also referred to as a flexible substrate, flexible substrate, etc.) can deform in response to an external force. A flexible substrate can be used while fixed in a deformed state, or can be used after repeatedly deforming, or can be used in an undeformed state. Note that the above phrase "deform in response to an external force" refers to deformation by an average adult's hand without requiring excessive force. Flexibility can be quantified as deformation of an object due to an external force using a testing machine (such as a tensile testing machine or a compression testing machine) capable of measuring stress-strain.

[0052] In this specification, when an object is described as having flexibility, it means that at least a part of the object has flexibility. In other words, a flexible object may have a non-flexible part (also called a hard part).

[0053] In this specification, when two objects are deformed by the same external force, the object that deforms more is said to be the object with higher flexibility. Also, when a first part and a second part of an object are deformed by the same external force, the part that deforms more is said to be the part with higher flexibility.

[0054] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 1A to 11B. FIG.

[0055] One embodiment of the present invention is a semiconductor device including a transistor and a first insulating layer.

[0056] The transistor includes a conductive layer and a metal oxide layer, the conductive layer functions as one of a source electrode and a drain electrode, and the metal oxide layer includes a channel formation region and a region functioning as the other of the source electrode and the drain electrode.

[0057] The first insulating layer is located on the conductive layer. The first insulating layer has an end portion contacting the top surface of the conductive layer. The first insulating layer has a second insulating layer and a third insulating layer on the second insulating layer. The metal oxide layer has an end portion contacting the top surface of the conductive layer, an end portion contacting a side surface of the second insulating layer, an end portion contacting a side surface of the third insulating layer, and an end portion contacting the top surface of the third insulating layer.

[0058] In the transistor of one embodiment of the present invention, the channel length can be controlled by the thickness of the second insulating layer. That is, the channel length of the transistor is not affected by the exposure performance of an exposure apparatus used for manufacturing the transistor. Therefore, the channel length of the transistor can be made shorter than the minimum value of the dimension that can be exposed by an exposure apparatus (hereinafter also referred to as the minimum dimension). By shortening the channel length, the transistor can have a large on-state current. Therefore, a semiconductor device that operates at high speed can be provided. Furthermore, because a conductive layer that functions as one of a source electrode and a drain electrode and a metal oxide layer having a channel formation region and a region that functions as the other of the source electrode and the drain electrode can be provided in an overlapping manner, the area occupied by the transistor can be reduced. Therefore, the area occupied by a semiconductor device including the transistor can be reduced.

[0059] The third insulating layer has a region with a higher hydrogen content than the second insulating layer. Hydrogen is released from the third insulating layer to a region of the metal oxide layer in contact with the third insulating layer, increasing the carrier concentration in the region and increasing the conductivity. This region functions as the other of the source and drain electrodes of the transistor. Because a portion of the metal oxide layer functions as the other of the source and drain electrodes, there is no need to provide a separate conductive layer functioning as the other of the source and drain electrodes. Therefore, the number of layers constituting the transistor can be reduced, thereby shortening the manufacturing process of the semiconductor device and reducing manufacturing costs. Furthermore, because a process related to the conductive layer is unnecessary, manufacturing yield can be increased.

[0060] <Configuration Example 1> A semiconductor device according to one embodiment of the present invention will be described. FIG. 1A shows a top view (also referred to as a plan view) of a semiconductor device 10. FIG. 1B shows a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 1A, and FIG. 1C shows a cross-sectional view of a cut surface taken along dashed dotted line B1-B2 in FIG. 1A. Note that some of the components of the semiconductor device 10 (such as a gate insulating layer) are omitted in FIG. 1A. As with FIG. 1A, some of the components are also omitted in the top views of the semiconductor device in the following drawings.

[0061] The semiconductor device 10 includes a transistor 100, an insulating layer 110, and an insulating layer 109. The insulating layer 109 is provided over a substrate 102, and the transistor 100 is provided over the insulating layer 109.

[0062] The transistor 100 includes a conductive layer 104, an insulating layer 106, a layer 108, and a conductive layer 112a. In the transistor 100, the conductive layer 104 functions as a gate electrode, the insulating layer 106 functions as a gate insulating layer, and the conductive layer 112a functions as one of a source electrode and a drain electrode. The layer 108 includes a semiconductor material. The layer 108 includes a channel formation region and a region functioning as the other of the source electrode and the drain electrode.

[0063] A perspective view of the semiconductor device 10 is shown in FIG. 2A. A perspective view in which the conductive layer 104 and the insulating layer 106 are omitted from FIG. 2A is shown in FIG. 2B. In FIGS. 2A and 2B, some of the insulating layers are shown transparently and their outlines are indicated by dashed lines. In the perspective views of the semiconductor device in the following drawings, like FIGS. 2A and 2B, some of the insulating layers are shown transparently and their outlines are indicated by dashed lines.

[0064] A conductive layer 112a is provided over the insulating layer 109, and an insulating layer 110 is provided over the conductive layer 112a. The conductive layer 112a has a region in contact with the insulating layer 109. The insulating layer 110 has a region in contact with the conductive layer 112a.

[0065] 1B , the insulating layer 110 has an end 31 that contacts the upper surface of the conductive layer 112a. In the insulating layer 110, the region where the side surface of the insulating layer 110 contacts the upper surface of the conductive layer 112a corresponds to the end 31. The conductive layer 112a has a region where the insulating layer 110 is provided and a region where the insulating layer 110 is not provided. The insulating layer 110 also has a side surface 77 on the conductive layer 112a. The lower end of the side surface 77 corresponds to the end 31.

[0066] A layer 108 is provided over the conductive layer 112a and the insulating layer 110. The layer 108 has regions in contact with the top surface of the conductive layer 112a and the top surface and side surface (here, the side surface 77) of the insulating layer 110. The layer 108 is connected to the conductive layer 112a. The layer 108 has a shape that follows the shapes of the top surface of the conductive layer 112a and the top surface and side surface 77 of the insulating layer 110. The layer 108 is provided across a region over the conductive layer 112a where the insulating layer 110 is not provided and a region over the conductive layer 112a where the insulating layer 110 is provided.

[0067] The layer 108 has a first region in contact with the conductive layer 112a, a second region in contact with the side surface 77, and a third region in contact with the top surface of the insulating layer 110. The first region is in contact with the second region, and the second region is in contact with the third region. It can also be said that the first region, the second region, and the third region are continuous in this order. A channel formation region is located in the second region.

[0068] The semiconductor material used for the layer 108 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS: oxide semiconductors). Note that these semiconductor materials may contain impurities as dopants.

[0069] The crystallinity of the semiconductor material used for the layer 108 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) can be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0070] The layer 108 can be made of, for example, silicon. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS). A transistor using amorphous silicon for its channel formation region can be formed on a large glass substrate and manufactured at low cost. A transistor using polycrystalline silicon for its channel formation region has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for its channel formation region has higher field-effect mobility than a transistor using amorphous silicon and can operate at high speed. Note that a transistor using silicon for its channel formation region may be referred to as a Si transistor, and a transistor using LTPS for its channel formation region may be referred to as an LTPS transistor.

[0071] The layer 108 preferably contains a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics. A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has extremely high field-effect mobility compared to a transistor using amorphous silicon. Furthermore, an OS transistor has an extremely low off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device. When a metal oxide is used for the layer 108, the layer 108 can be referred to as a metal oxide layer.

[0072] The insulating layer 110 can be an inorganic insulating layer, an organic insulating layer, or both. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. The insulating layer 110 preferably includes one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.

[0073] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0074] The insulating layer 110 has a region in contact with the layer 108. When a metal oxide is used for the layer 108, at least a part of the region of the insulating layer 110 in contact with the layer 108 preferably contains oxygen in order to improve the interfacial characteristics between the layer 108 and the insulating layer 110. Specifically, the region in contact with the channel formation region of the insulating layer 110 preferably contains oxygen. One or more of an oxide and an oxynitride can be suitably used for the region in contact with the channel formation region of the insulating layer 110.

[0075] When a metal oxide is used for the layer 108, it is preferable that at least a part of the region of the insulating layer 110 in contact with the layer 108 releases oxygen when heat is applied. As a result, oxygen is supplied from the insulating layer 110 to the layer 108, and oxygen vacancies (V Ｏ : Oxygen Vacancy), and defects in which hydrogen enters an oxygen vacancy (hereinafter referred to as V Ｏ This can reduce the threshold voltage of the transistor 100, thereby suppressing a shift in the threshold voltage of the transistor 100 and reducing the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V. This allows a semiconductor device with low power consumption. Furthermore, a highly reliable transistor and semiconductor device can be provided.

[0076] The insulating layer 110 preferably has a stacked structure. Figure 1B and other figures show an example in which the insulating layer 110 includes an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110d on the insulating layer 110c. The insulating layers 110a, 110b, 110c, and 110d can each be made of the materials listed for the insulating layer 110.

[0077] FIG. 3 shows a cross-sectional view of the cut surface taken along dashed dotted line C1-C2 in FIG. 1B . FIG. 3 is a cross-sectional view of a plane including the insulating layer 110. As shown in FIGS. 1C and 3 , the layer 108 has an end 33 in contact with the top surface of the conductive layer 112a, an end 37 in contact with the side surface 77, and an end 35 in contact with the top surface of the insulating layer 110. The end 33 is an end on the surface of the layer 108 in contact with the top surface of the conductive layer 112a. The end 37 is an end on the surface of the layer 108 in contact with the side surface 77. The end 35 is an end on the surface of the layer 108 in contact with the top surface of the insulating layer 110d. Note that when the insulating layer 110 has a stacked structure, the layer 108 has ends in contact with the side surfaces of each layer of the insulating layer 110 (see the insulating layer 110 and end 37 in FIG. 3 ). Specifically, layer 108 has an end that contacts the side surface of insulating layer 110a, an end that contacts the side surface of insulating layer 110b, an end that contacts the side surface of insulating layer 110c, and an end that contacts the side surface of insulating layer 110d.

[0078] The top layer of the insulating layer 110 (here, the insulating layer 110d) preferably contains impurities that reduce the electrical resistance of the layer 108 and is made of a material that releases the impurities. When a metal oxide is used for the layer 108, the elements contained in the impurities (hereinafter also referred to as impurity elements) can be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases. Typical examples of noble gases include helium, neon, argon, krypton, and xenon. The impurity element is preferably one or more of hydrogen, boron, phosphorus, aluminum, magnesium, and silicon, and particularly preferably hydrogen. For example, the insulating layer 110d is preferably made of a material that releases one or both of hydrogen and water. The insulating layer 110d preferably contains, for example, silicon and hydrogen. Typically, silicon nitride containing hydrogen can be suitably used for the insulating layer 110d. Note that in this specification and the like, hydrogen may be used as an example of the impurity.

[0079] The oxygen bonded to the metal atoms in the metal oxide reacts with hydrogen to form water, leaving oxygen vacancies (V Ｏ ) is formed. Furthermore, oxygen vacancies (V Ｏ) with hydrogen in it. Ｏ H functions as a donor, generating electrons as carriers. Furthermore, some of the hydrogen bonds with oxygen, which bonds with metal atoms, generating electrons as carriers. This allows the metal oxide to exhibit electrical conductivity and function as a conductor. A metal oxide that functions as a conductor can be called an oxide conductor (OC). Generally, metal oxides have a large band gap, allowing them to transmit visible light (or they can be said to be translucent to visible light). An oxide conductor is a metal oxide that has a donor level near the conduction band. Therefore, oxide conductors are less affected by absorption due to the donor level, and have the same level of translucency to visible light as metal oxides.

[0080] The insulating layer 110d can be formed using a gas containing an impurity. When hydrogen is used as the impurity element, the insulating layer 110d can be formed using a gas containing a hydrogen element. For example, silane (SiH ４ ), disilane (Si ２ H ６ ), trisilane (Si ３ H ８ ), TEOS (Tetraethoxysilane, Si(OC ２ H ５ ) ４ ), hydrogen (H ２ ), and ammonia (NH ３ When a silicon nitride film is formed as the insulating layer 110d by using a plasma enhanced chemical vapor deposition (PECVD) method, silane (SiH ４ ), nitrogen (N ２ ) and ammonia (NH ３) can be used. At this time, the amount of hydrogen released from the insulating layer 110d can be adjusted by changing the ratio of the flow rate of the ammonia gas to the total film formation gas (hereinafter also referred to as the ammonia flow rate ratio). For example, by increasing the ammonia flow rate ratio, the amount of hydrogen contained in the insulating layer 110d can be increased, and the amount of hydrogen released by heat applied to the insulating layer 110d can be increased.

[0081] FIG. 4 shows an enlarged view of FIG. 1B . The layer 108 has a region 108P in contact with the top layer of the insulating layer 110 (here, the insulating layer 110d). The region 108P is in contact with the top surface and side surfaces of the insulating layer 110d. The region 108P is conductive due to the presence of impurities emitted from the insulating layer 110d. The region 108P can be referred to as an oxide conductor (OC). As a result, the region 108P functions as the other of the source and drain electrodes of the transistor 100. The region 108Q in contact with the conductive layer 112a functions as one of the source and drain regions of the transistor 100. In the layer 108, a channel formation region is located between the region 108P and the region 108Q. For example, the region 108R of the layer 108 in contact with the insulating layer 110b functions as the channel formation region.

[0082] Since a part of the layer 108 (here, the region 108P) functions as the other of the source electrode and the drain electrode, there is no need to separately provide a conductive layer that functions as the other of the source electrode and the drain electrode. Therefore, the number of layers constituting the transistor 100 can be reduced, thereby shortening the manufacturing process of the semiconductor device and reducing manufacturing costs. Furthermore, since a process related to the conductive layer is not necessary, the manufacturing yield can be increased.

[0083] By reducing the number of layers constituting the transistor 100, unevenness caused by the transistor 100 can be reduced. Here, if the unevenness of the surface on which a layer is formed is large, defects such as discontinuities or voids due to reduced coverage of the layer, or etching residues when processing the layer, may occur. By reducing the unevenness caused by the transistor 100, defects (e.g., discontinuities, voids, and etching residues) in the formation of layers provided on the transistor 100 can be suppressed, and the manufacturing yield can be increased.

[0084] The region 108P functioning as the other of the source and drain electrodes preferably has a higher impurity concentration than the region 108R functioning as a channel formation region. For example, the region 108P preferably has a higher hydrogen concentration than the region 108R.

[0085] An enlarged view of FIG. 1B is shown in FIG. 5A. If the thickness T108 of the region 108P is thin, the electrical resistance of the region 108P, which functions as one of the source electrode and the drain electrode, may become high. On the other hand, if the thickness T108 is thick, the thickness of the region 108R also becomes thick, and oxygen vacancies (V Ｏ ) may become large. As shown in FIG. 5A , the thickness T108 can be the shortest distance between the top surface of the insulating layer 110 (specifically, the top surface of the insulating layer 110d) and the top surface of the layer 108 in a cross-sectional view. The thickness T108 of the region 108P is preferably 5 nm to 150 nm, more preferably 5 nm to 100 nm, even more preferably 10 nm to 100 nm, still more preferably 20 nm to 100 nm, and even more preferably 20 nm to 50 nm. By setting the thickness T108 within the above range, the electrical resistance of one of the source electrode and the drain electrode can be reduced, and a transistor having good electrical characteristics can be obtained. Note that the thickness T108 is not limited to the above range.

[0086] The sheet resistance (also referred to as surface resistivity or sheet resistivity) of region 108P is preferably 1000 Ω / □ (also written as Ω / sq) or less, more preferably 500 Ω / □ or less, even more preferably 300 Ω / □ or less, even more preferably 200 Ω / □ or less, and even more preferably 100 Ω / □ or less. Note that, since it is preferable that the electrical resistance of region 108P is low, there is no lower limit for the sheet resistance.

[0087] The amount of impurities released from the insulating layer 110d can be adjusted by adjusting the thickness of the insulating layer 110d. Specifically, increasing the thickness of the insulating layer 110d increases the amount of impurities released from the insulating layer 110d, thereby reducing the electrical resistance of the region 108P. As shown in FIG. 5A , the thickness T110d of the insulating layer 110d can be defined as the shortest distance between the surface on which the insulating layer 110d is formed (here, the upper surface of the insulating layer 110c) and the upper surface of the insulating layer 110d in a cross-sectional view. The thickness T110d is preferably 10 nm to 500 nm, more preferably 20 nm to 400 nm, even more preferably 50 nm to 300 nm, even more preferably 70 nm to 200 nm, even more preferably 70 nm to 150 nm, and even more preferably 70 nm to 120 nm. Note that the thickness T110d is not limited to the aforementioned range.

[0088] The insulating layer 110b in contact with the region 108R preferably contains oxygen, and is preferably made of one or more of the above-described oxides and oxynitrides. The insulating layer 110b preferably contains, for example, silicon and oxygen. Typically, the insulating layer 110b can be made of one or both of silicon oxide and silicon oxynitride.

[0089] It is more preferable to use a material that releases oxygen when heat is applied to the insulating layer 110b. When heat is applied during the manufacturing process of the semiconductor device 10, the insulating layer 110b releases oxygen, which allows oxygen to be supplied to the layer 108. By supplying oxygen from the insulating layer 110b to the layer 108, particularly to the channel formation region, oxygen vacancies (V Ｏ ) is repaired, and oxygen vacancies (V Ｏ ) can be reduced. ＯH can be reduced. Therefore, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0090] For example, oxygen can be supplied to the insulating layer 110b by heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer 110b by forming a film on the top surface of the insulating layer 110b by sputtering in an oxygen-containing atmosphere. The film can then be removed. Note that a method for supplying oxygen to the insulating layer 110b will be specifically described in Embodiment 3.

[0091] The insulating layer 110b is preferably formed by a sputtering method or a PECVD method. In particular, by using a sputtering method without using a gas containing hydrogen (e.g., hydrogen gas or ammonia gas) in the film formation gas, a film with an extremely low hydrogen content can be obtained. Therefore, hydrogen can be prevented from being supplied to the channel formation region, and the electrical characteristics of the transistor can be stabilized.

[0092] The insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112a. The insulating layer 110c is provided between the insulating layer 110b and the insulating layer 110d. The insulating layer 110a and the insulating layer 110c preferably release small amounts of impurities (e.g., hydrogen and water) from themselves. Furthermore, the insulating layer 110a and the insulating layer 110c preferably have barrier properties. The insulating layer 110a and the insulating layer 110c can also be said to function as barrier films. Specifically, the insulating layer 110a and the insulating layer 110c preferably have low impurity permeability. This can prevent impurities contained in the insulating layer 110a and the insulating layer 110c from diffusing into the channel formation region. Therefore, a highly reliable transistor can be obtained, exhibiting favorable electrical characteristics.

[0093] In this specification and the like, a barrier film refers to a film having barrier properties. The barrier properties refer to one or both of a function of making it difficult for a target substance to diffuse and thereby suppressing the substance from permeating the film (also referred to as low permeability) and a function of capturing or fixing the substance (also referred to as gettering). For example, an insulating layer having barrier properties can be referred to as a barrier insulating layer.

[0094] The barrier film can be made of, for example, one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing aluminum, a nitride containing silicon, and a nitride oxide containing silicon.Typically, the barrier film can be made of, for example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0095] The insulating layer 110c provided between the insulating layer 110d and the insulating layer 110b is preferably made of a material that is difficult for impurities contained in the insulating layer 110d to penetrate, thereby preventing the impurities contained in the insulating layer 110d from diffusing into the channel formation region through the insulating layer 110c and the insulating layer 110b.

[0096] It is preferable that the insulating layer 110a and the insulating layer 110c are made of a material that is difficult for oxygen to permeate. This can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112a side through the insulating layer 110a. Similarly, it can prevent oxygen contained in the insulating layer 110b from diffusing upward through the insulating layer 110c and the insulating layer 110d. This increases the amount of oxygen supplied to the channel formation region from the insulating layer 110b, and reduces oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0097] By using a material that is difficult for oxygen to permeate for the insulating layer 110c, it is possible to prevent oxygen contained in the insulating layer 110b from diffusing into the region 108P via the insulating layer 110c and the insulating layer 110d. When oxygen is supplied to the region 108P, oxygen vacancies (V Ｏ ) and V Ｏ H may decrease, resulting in an increase in the electrical resistance of the region 108P. By providing the insulating layer 110c between the region 108P and the insulating layer 110b, oxygen diffusion into the region 108P is suppressed, and an increase in the electrical resistance of the region 108P can be suppressed. Similarly, by using a material that is difficult for oxygen to permeate for the insulating layer 110a, oxygen contained in the insulating layer 110b can be suppressed from diffusing into the conductive layer 112a via the insulating layer 110a. Therefore, oxidation of the conductive layer 112a and an increase in the electrical resistance of the conductive layer 112a can be suppressed. This allows a transistor with a large on-current.

[0098] The insulating layer 110a and the insulating layer 110c can each be made of the materials listed for the barrier film. For example, the insulating layer 110a and the insulating layer 110c can each be made of one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide. The insulating layer 110a and the insulating layer 110c can each be made of the same material. Alternatively, the insulating layer 110a and the insulating layer 110c can each be made of different materials.

[0099] In this specification and the like, different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0100] One or more of the insulating layers 110a and 110c can have a stacked structure. For example, the insulating layer 110c can have a stacked structure of an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0101] The insulating layer 110d preferably has a region with a higher impurity content than the insulating layer 110c. The insulating layer 110d preferably has a region with a higher impurity content than the insulating layer 110b. Furthermore, the insulating layer 110d preferably has a region with a higher impurity content than the insulating layer 110a.

[0102] For example, the insulating layer 110d preferably has a region with a higher hydrogen content than the insulating layer 110c. The insulating layer 110d preferably has a region with a higher hydrogen content than the insulating layer 110b. The insulating layer 110d preferably has a region with a higher hydrogen content than the insulating layer 110a. The hydrogen content of the insulating layer 110 can be analyzed by, for example, secondary ion mass spectrometry (SIMS).

[0103] For example, the amount of released hydrogen can be adjusted by differentiating the deposition conditions for the insulating layer 110d and the insulating layer 110c. Specifically, the deposition conditions for the insulating layer 110d and the insulating layer 110c can be made different from each other by varying one or more of the deposition power (deposition power density), deposition pressure, deposition gas type, deposition gas flow rate ratio, deposition temperature, and the distance between the substrate and the electrode. For example, by lowering the deposition power density for the insulating layer 110d compared to the deposition power density for the insulating layer 110c, the hydrogen content in the insulating layer 110d can be made higher than the hydrogen content in the insulating layer 110c. This increases the amount of hydrogen released from the insulating layer 110d due to heat applied to the insulating layer 110d.

[0104] The deposition gas used to deposit the insulating layer 110d preferably contains more hydrogen than the deposition gas used to deposit the insulating layer 110c. Specifically, when a silicon nitride film or a silicon nitride oxide film is deposited by PECVD for each of the insulating layer 110 and the insulating layer 110c, the ratio of the flow rate of ammonia gas to the total flow rate of the deposition gas used to deposit the insulating layer 110d (hereinafter also referred to as the ammonia flow rate ratio) is preferably higher than the ammonia flow rate ratio of the deposition gas used to deposit the insulating layer 110c. By depositing the insulating layer 110d under conditions with a high ammonia flow rate ratio, the hydrogen content in the insulating layer 110d can be increased. Furthermore, the amount of hydrogen released from the insulating layer 110d due to heat applied to the insulating layer 110d can be increased.

[0105] It is more preferable that the film density of the insulating layer 110c be higher than that of the insulating layer 110d. This can prevent impurities contained in the insulating layer 110d from diffusing into the channel formation region via the insulating layers 110c and 110b. The film density can be evaluated by, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflectivity (XRR). The difference in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a faint (bright) transmission electron (TE) image. Therefore, in a TE image, the insulating layer 110c may appear denser (darker) than the insulating layer 110d. Even when the same material is used for the insulating layers 110d and 110c, the film densities are different, and therefore the boundary between them may be observed as a difference in contrast in a cross-sectional TEM image.

[0106] The thickness T110c is preferably a value that functions as a barrier film. If the thickness T110c is small, the barrier properties are reduced, and impurities contained in the insulating layer 110d may diffuse into the channel formation region via the insulating layers 110c and 110d. Furthermore, oxygen contained in the insulating layer 110b may diffuse into the region 108P via the insulating layers 110c and 110d, increasing the electrical resistance of the region 108P. Furthermore, the amount of oxygen supplied to the channel formation region may decrease. On the other hand, if the thickness T110c is large, the amount of impurities released from the insulating layer 110c may increase, resulting in an increased amount of impurities diffusing into the channel formation region.

[0107] The thickness T110c of the insulating layer 110c is preferably 3 nm or more and 500 nm or less, more preferably 5 nm or more and 400 nm or less, even more preferably 10 nm or more and 300 nm or less, even more preferably 20 nm or more and 300 nm or less, even more preferably 50 nm or more and 300 nm or less, even more preferably 100 nm or more and 300 nm or less, even more preferably 100 nm or more and 200 nm or less. As shown in FIG. 5A , the thickness T110c can be the shortest distance between the surface on which the insulating layer 110c is to be formed (here, the top surface of the insulating layer 110b) and the top surface of the insulating layer 110c in a cross-sectional view. By setting the thickness T110c within the above range, the amount of oxygen supplied to the channel formation region can be increased, and oxygen vacancies (V) in the channel formation region can be reduced. Ｏ ) and V Ｏ H can be reduced. In addition, it is possible to prevent the electrical resistance of the region 108P from increasing due to oxygen contained in the insulating layer 110b. The thickness T110c is not limited to the above range.

[0108] The thickness T110a is preferably a value that allows the film to function as a barrier film. If the thickness T110a is small, the barrier properties are reduced, and oxygen contained in the insulating layer 110b may diffuse into the conductive layer 112a through the insulating layer 110a, resulting in an increase in the electrical resistance of the conductive layer 112a. Furthermore, the amount of oxygen supplied to the channel formation region may be reduced. On the other hand, if the thickness T110a is large, the amount of impurities released from the insulating layer 110a may increase, resulting in an increase in the amount of impurities diffusing into the channel formation region.

[0109] The thickness T110a of the insulating layer 110a is preferably 3 nm to 500 nm, more preferably 5 nm to 400 nm, even more preferably 10 nm to 300 nm, even more preferably 20 nm to 300 nm, even more preferably 50 nm to 300 nm, even more preferably 100 nm to 300 nm, even more preferably 100 nm to 250 nm, even more preferably 150 nm to 250 nm. As shown in FIG. 5A , the thickness T110a can be the shortest distance between the surface on which the insulating layer 110a is to be formed (e.g., the top surface of the conductive layer 112a) and the top surface of the insulating layer 110a in a cross-sectional view. By setting the thickness T110a within the above range, the amount of oxygen supplied to the channel formation region can be increased, and oxygen vacancies (V Ｏ ) and V Ｏ This can reduce the thickness H. Furthermore, it is possible to prevent the electrical resistance of the conductive layer 112a from increasing due to oxygen contained in the insulating layer 110b. Note that the thickness T110a is not limited to the above range.

[0110] The thickness T110a can be greater than the thickness T110c. If the region of the layer 108 in contact with the insulating layer 110a functions as a source region or a drain region, increasing the thickness T110a can make the distance from the source region or the drain region to the gate electrode more uniform. This can make the electric field of the gate electrode applied to the channel formation region more uniform.

[0111] At least one of the region of the layer 108 in contact with the insulating layer 110a and the region of the layer 108 in contact with the insulating layer 110c can be a region with lower electrical resistance than the channel formation region (hereinafter also referred to as a low-resistance region). This region can also be referred to as a region with a higher carrier concentration or a higher oxygen defect density than the channel formation region. By using a material that releases impurities (e.g., water and hydrogen) for the insulating layer 110a, the region of the layer 108 in contact with the insulating layer 110a contains impurities, and this region can be a low-resistance region. The layer 108 can have a low-resistance region between one of the source and drain regions (region 108Q) and the channel formation region (region 108R). Similarly, by using a material that releases impurities for the insulating layer 110c, the region of the layer 108 in contact with the insulating layer 110c contains impurities, and this region can be a low-resistance region. The layer 108 may have a low-resistance region between the other of the source and drain electrodes (region 108P) and the channel formation region (region 108R). The low-resistance region may function as a buffer region for alleviating the drain electric field. Note that these low-resistance regions may also function as source or drain regions.

[0112] Impurities released from the insulating layer 110a and the insulating layer 110c may diffuse into the channel formation region via the insulating layer 110b or via the region of the layer 108 that is in contact with the insulating layer 110a and the insulating layer 110c. However, oxygen is supplied from the insulating layer 110b to at least the region 108R of the layer 108 that is in contact with the insulating layer 110b, and therefore oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. This suppresses a shift in threshold voltage, enabling a transistor with both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0113] However, if the amount of impurities released from the insulating layer 110a and the insulating layer 110c becomes too large, the impurities contained in the layer 108 will increase. As a result, oxygen vacancies (V Ｏ ) and VＯ The amount of H is the oxygen vacancy (V Ｏ ) and V Ｏ The amount of H may be greater than the amount of H. Even when a material that releases impurities is used for the insulating layer 110a and the insulating layer 110c, it is more preferable that the amount of released impurities is small.

[0114] The insulating layer 106, which functions as a gate insulating layer of the transistor 100, is provided to cover the layer 108. The insulating layer 106 has regions in contact with the top surface and side surface of the layer 108 and the side surface 77. The insulating layer 106 also has regions in contact with the top surface and side surface of the conductive layer 112a, the top surface and side surface of the insulating layer 110, and the top surface of the insulating layer 109.

[0115] 3 , the insulating layer 110 has, on the side surface 77, a region 70 where the layer 108 is provided and a region 72 where the layer 108 is not provided. In the region 70, the layer 108 contacts the insulating layer 110. The insulating layer 106 has a region facing the side surface 77 with the layer 108 interposed therebetween. On the other hand, in the region 72, the insulating layer 106 contacts the insulating layer 110.

[0116] The conductive layer 104, which functions as a gate electrode of the transistor 100, is provided over the insulating layer 106 and has a region in contact with the top surface of the insulating layer 106. The conductive layer 104 has a region overlapping with the layer 108 with the insulating layer 106 interposed therebetween. The conductive layer 104 also has a region facing the side surface 77 with the insulating layer 106 and the layer 108 interposed therebetween. The conductive layer 104 is provided to cover at least the region of the layer 108 that is in contact with the side surface 77. This allows the region to function as a channel formation region of the transistor 100.

[0117] Note that the conductive layer 104 can also cover the entire layer 108. Covering the layer 108 with the conductive layer 104 can prevent the layer 108 from being damaged when layers are formed over the transistor 100.

[0118] A step is formed between a region on the conductive layer 112a where the insulating layer 110 is provided and a region where the insulating layer 110 is not provided, and the layer 108, the insulating layer 106, and the conductive layer 104 are provided along the step.

[0119] In the transistor 100, a source electrode and a drain electrode are located at different heights with respect to the surface of the substrate 102, and a drain current flows perpendicular to or approximately perpendicular to the surface of the substrate 102. In other words, the drain current flows vertically in the transistor 100. Therefore, the transistor of one embodiment of the present invention can be called a vertical channel transistor, a vertical transistor, or a vertical field effect transistor (VFET).

[0120] The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 provided on the conductive layer 112a. Therefore, a transistor having a channel length shorter than the minimum exposure dimension of an exposure device used to manufacture the transistor can be manufactured with high precision. Furthermore, the characteristic variation among multiple transistors is also reduced. Therefore, the operation of the semiconductor device 10 can be stabilized and the reliability can be improved. Furthermore, the reduced characteristic variation of transistors increases the degree of freedom in circuit design, and the operating voltage of the semiconductor device can be reduced. Therefore, the power consumption of the semiconductor device can be reduced.

[0121] In the transistor of one embodiment of the present invention, a conductive layer functioning as one of a source electrode and a drain electrode, a region functioning as the other of the source electrode and the drain electrode, and a layer having a channel formation region can be provided so as to overlap with each other. Therefore, the area occupied by the transistor can be significantly reduced compared to a so-called planar transistor in which these are arranged in a planar shape.

[0122] The conductive layer 112a and the region 108P can each function as a wiring. The transistor 100 can be provided in a region where these wirings overlap. That is, in a circuit including the transistor 100 and the wiring, the area occupied by the transistor 100 and the wiring can be reduced. Therefore, a semiconductor device with a small area can be provided.

[0123] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-resolution display device can be obtained.Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (for example, one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.

[0124] The insulating layer 109 is provided between the transistor 100 and the insulating layer 110 and the substrate 102. The insulating layer 109 has a region in contact with the conductive layer 112a, the insulating layer 110, and the insulating layer 106.

[0125] The insulating layer 109 preferably has a barrier property. The insulating layer 109 is preferably made of a material through which impurities (e.g., water and hydrogen) contained in the substrate 102 do not easily diffuse. This can suppress diffusion of impurities from the substrate 102 to the transistor 100. The insulating layer 109 can be made of, for example, one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing aluminum, a nitride containing silicon, and a nitride oxide containing silicon. Specifically, the insulating layer 109 can be made of, for example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0126] The insulating layer 109 preferably has a region in contact with the bottom surface of the conductive layer 112a. The insulating layer 109 preferably contains impurities (e.g., water and hydrogen) that reduce the electrical resistance of the layer 108 and is made of a material that releases the impurities. The impurities released from the insulating layer 109 diffuse into the region of the conductive layer 112a that is in contact with the insulating layer 109. The impurities diffused into the conductive layer 112a diffuse into the region 108Q, whereby the region 108Q contains the impurities and the electrical resistance of the region 108Q can be reduced. That is, the electrical resistance of one of the source region and the drain region of the transistor 100 can be reduced. Therefore, a transistor with a large on-state current can be obtained, and a semiconductor device that operates at high speed can be obtained.

[0127] When a metal oxide is used for the layer 108, the impurities released by the insulating layer 109 preferably contain hydrogen. When hydrogen contained in the insulating layer 109 diffuses into the layer 108 through the conductive layer 112a, the region 108Q contains hydrogen, and the carrier concentration of the region 108Q increases. That is, the electrical resistance of one of the source region and the drain region of the transistor 100 can be reduced. The insulating layer 109 can be made of any of the materials listed for the insulating layer 110d. The insulating layer 109 preferably contains, for example, silicon and hydrogen. Typically, the insulating layer 109 can be made of silicon nitride containing hydrogen.

[0128] It is more preferable that the insulating layer 109 be made of a material that releases impurities that reduce the electrical resistance of the conductive layer 112a, thereby reducing the electrical resistance of the conductive layer 112a.

[0129] The conductive layer 112a can be formed using, for example, a conductive metal oxide (also referred to as an oxide conductor). Examples of oxide conductors (OC) include indium oxide, zinc oxide, In—Sn oxide (ITO), In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide (also referred to as ITO containing silicon, ITSO), zinc oxide to which gallium is added, and In—Ga—Zn oxide. In particular, oxide conductors containing indium have high conductivity and can be suitably used for the conductive layer 112a.

[0130] When a metal oxide is used for the conductive layer 112a, the impurities released from the insulating layer 109 preferably contain hydrogen. The impurities released from the insulating layer 109 diffuse into the conductive layer 112a, and the conductive layer 112a contains the impurities. This increases the carrier concentration of the conductive layer 112a, thereby reducing the electrical resistance. The conductive layer 112a can function as a wiring, and a semiconductor device with low wiring resistance can be obtained. Note that the impurities that reduce the electrical resistance of the conductive layer 112a can be the same as the impurities that reduce the electrical resistance of the layer 108. Alternatively, these impurities can be different from each other. The conductive layer 112a is more preferably permeable to impurities. The conductive layer 112a is more preferably less susceptible to adsorption of impurities.

[0131] When the thickness T109 of the insulating layer 109 is large and the amount of impurities released from the insulating layer 109 is too large, the amount of impurities diffusing into the channel forming region increases, and oxygen vacancies (V Ｏ ) and V Ｏ The amount of H is the oxygen vacancy (V Ｏ ) and V ＯThe amount of H may be greater than the amount of H. On the other hand, if the thickness T109 is small, the amount of impurities diffused into the conductive layer 112a and the region 108Q may be small, which may increase the electrical resistance of the conductive layer 112a and the region 108Q. The thickness T109 is preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, further preferably 20 nm or more and 100 nm or less, and further preferably 20 nm or more and 50 nm or less. As shown in FIG. 5A , the thickness T109 can be the shortest distance between the surface on which the insulating layer 109 is to be formed (here, the upper surface of the substrate 102) and the upper surface of the insulating layer 109 in a cross-sectional view. By setting the thickness T109 within the above range, oxygen vacancies (V Ｏ ) and V Ｏ It is possible to suppress an increase in H and to lower the electrical resistance of these. The thickness T109 is not limited to the above range.

[0132] Note that impurities released from the insulating layer 109 may diffuse into the region 108R through the conductive layer 112a and the region 108Q. However, since oxygen is supplied from the insulating layer 110b to at least the region 108R, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. This suppresses a shift in threshold voltage, enabling a transistor with both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0133] The insulating layer 110a has a region in contact with the top surface and side surfaces of the conductive layer 112a and a region in contact with the top surface of the insulating layer 109. By providing the insulating layer 110a between the insulating layer 109 and the conductive layer 112a and the insulating layer 110b, impurities contained in the insulating layer 109 and the conductive layer 112a can be prevented from diffusing into a channel formation region through the insulating layer 110b.

[0134] The insulating layer 109 preferably has a region containing more impurities than the insulating layer 110a. For example, the insulating layer 109 preferably has a region containing more hydrogen than the insulating layer 110a. The film density of the insulating layer 110a is more preferably higher than that of the insulating layer 109. For the insulating layer 109 and the insulating layer 110a, the description of the insulating layer 110d and the insulating layer 110c can be referred to.

[0135] The insulating layer 109 is preferably provided in at least a region where the conductive layer 112a is provided. As shown in FIG. 6A , the insulating layer 109 can have an edge aligned or approximately aligned with an edge of the conductive layer 112a. For example, an insulating film to be the insulating layer 109 and a conductive film to be the conductive layer 112a are formed and processed using the same mask layer, thereby forming the insulating layer 109 and the conductive layer 112a. Processing the insulating film and the conductive film in the same process can reduce manufacturing costs. The insulating layer 110 has a region in contact with the side surface of the insulating layer 109, the top surface and side surface of the conductive layer 112a, and the top surface of the substrate 102.

[0136] Here, if the amount of impurities released from the insulating layer 109 is too large, there is a risk that the amount of impurities diffusing into the channel formation region will be large. By providing the insulating layer 109 in a part of the substrate 102 and not providing the insulating layer 109 in the other part, the area of ​​the region where the insulating layer 109 is provided can be adjusted. This makes it possible to adjust the amount of impurities released from the insulating layer 109. By reducing the area of ​​the region where the insulating layer 109 is provided, the amount of impurities released from the insulating layer 109 is reduced, and the amount of impurities diffusing into the channel formation region can be reduced.

[0137] 6B , the end of the insulating layer 109 may not be aligned with the end of the conductive layer 112a. The insulating layer 109 may have a region that protrudes beyond the end of the conductive layer 112a. The end of the conductive layer 112a is in contact with the top surface of the insulating layer 109. This structure reduces the step between the formation surfaces of the conductive layer 112a and a layer (e.g., the insulating layer 110) formed on the insulating layer 109, thereby improving the coverage of the layer. This can prevent defects such as discontinuities or voids in the layer.

[0138] The structure of the insulating layer 109 shown here can be applied to other structure examples. Also, a structure in which the insulating layer 109 is not provided may be used.

[0139] 1B and the like, the insulating layer 110 is shown to have a four-layer stacked structure, but one embodiment of the present invention is not limited to this. The insulating layer 110 preferably includes at least the insulating layer 110b and the insulating layer 110d. A structure without one or both of the insulating layer 110a and the insulating layer 110c is also possible. Alternatively, the insulating layer 110 can have a stacked structure of five or more layers.

[0140] 7A and 7B, the insulating layer 110 can have a five-layer stacked structure. 7A and 7B show a configuration in which the insulating layer 110 has an insulating layer 110e, an insulating layer 110a on the insulating layer 110e, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110d on the insulating layer 110c.

[0141] The insulating layer 110e is provided between the insulating layer 110a and the conductive layer 112a. The insulating layer 110e is provided so as to cover the conductive layer 112a. The insulating layer 110e has a region in contact with the top surface and side surfaces of the conductive layer 112a and the side surface of the layer 108. The insulating layer 110e also has a region in contact with the top surface of the insulating layer 109.

[0142] The insulating layer 110e is preferably made of a material that releases impurities (e.g., water and hydrogen) that reduce the electrical resistance of the layer 108. This allows the region of the layer 108 in contact with the insulating layer 110e to contain impurities and become a low-resistance region. This allows the layer 108 to have a low-resistance region between the region in contact with the conductive layer 112a (one of the source and drain regions) and the channel formation region. Providing a low-resistance region between the source or drain region and the channel formation region can suppress hot carrier degradation. Note that the low-resistance region may function as the source or drain region.

[0143] When the region of the layer 108 in contact with the insulating layer 110e functions as a source region or a drain region, the distance from the source region of the layer 108 to the gate electrode and the distance from the drain region to the gate electrode can be made more uniform, thereby making the electric field of the gate electrode applied to the channel formation region more uniform.

[0144] The insulating layer 110e can be formed using the same materials as those for the insulating layer 110d and the insulating layer 109. For example, a silicon nitride film or a silicon nitride oxide film can be suitably used for the insulating layer 110e. Note that the insulating layer 110e, the insulating layer 110d, and the insulating layer 109 can be formed using the same material. Alternatively, different materials can be used for one or more of the insulating layer 110e, the insulating layer 110d, and the insulating layer 109. For the insulating layer 110e, the description of the insulating layer 110d and the insulating layer 109 can be referred to.

[0145] By providing the insulating layer 110a between the insulating layer 110e and the insulating layer 110b, impurities contained in the insulating layer 110e can be prevented from diffusing into the channel formation region through the insulating layer 110a and the insulating layer 110b.

[0146] The insulating layer 110e preferably has a region containing more impurities than the insulating layer 110a. For example, the insulating layer 110e preferably has a region containing more hydrogen than the insulating layer 110a. The film density of the insulating layer 110a is more preferably higher than that of the insulating layer 110e. For the insulating layer 110e and the insulating layer 110a, the description of the insulating layer 110d and the insulating layer 110c can be referred to.

[0147] The configuration of the insulating layer 110 shown here can also be applied to other configuration examples.

[0148] [Layer 108] Metal oxides that can be used for the layer 108 will be specifically described.

[0149] Examples of metal oxides include indium oxide (also referred to as indium oxide, IO), gallium oxide (also referred to as gallium oxide), and zinc oxide (also referred to as zinc oxide). The metal oxide preferably contains at least indium. The metal oxide preferably contains one or both of indium and zinc. The metal oxide preferably contains one or more elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have a high bond energy with oxygen and an ionic radius similar to that of indium or zinc. Furthermore, tin is more preferred because it is tetravalent and can increase carrier mobility. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification may also include metalloid elements.

[0150] The layer 108 may be made of, for example, indium oxide, indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In—Sn oxide, also referred to as ITO), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium tungsten oxide (In—W oxide, also referred to as IWO), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide), or the like. Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as AZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO). Alternatively, examples of usable materials include indium tin oxide containing silicon (ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0151] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, the presence of a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0152] The metal oxide may contain one or more nonmetallic elements. The nonmetallic elements in the metal oxide may increase the carrier concentration or narrow the band gap, thereby increasing the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0153] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0154] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. When a plurality of elements are contained as the element M, the sum of the ratios of the number of atoms of the element M to the sum of the numbers of atoms of all contained metal elements can be referred to as the content of the element M.

[0155] By increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0156] By increasing the content of element M in the metal oxide, it is possible to obtain a metal oxide with a large band gap. Ｏ ) is suppressed, the formation of oxygen vacancies (V Ｏ ) can be suppressed, and a shift in the threshold voltage of the transistor can be suppressed. As a result, the cutoff current can be reduced, resulting in a normally-off transistor. Furthermore, the transistor can have a small off-state current. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, resulting in improved reliability.

[0157] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the layer 108. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of a transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0158] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M Examples of suitable compositions include In:M:Zn = 5:1:9, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and compositions in the vicinity thereof. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-state current or field-effect mobility of the transistor.

[0159] The atomic ratio of In in the In-M-Zn oxide can be less than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, In:M:Zn=1:3:6, and compositions close to these. By increasing the ratio of the number of M atoms in the metal oxide, oxygen deficiency (V Ｏ ) can be suppressed.

[0160] When the element M contains a plurality of elements, the atomic ratio of the element M can be the sum of the atomic ratios of these elements.

[0161] By using a material with a high indium content for the layer 108, the on-state current or the field-effect mobility of the transistor can be increased. Furthermore, by containing the element M, oxygen vacancies (V Ｏ) can be suppressed. The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metal elements) is preferably 0.1% to 25%, more preferably 0.1% to 20%, even more preferably 0.1% to 10%, even more preferably 0.1% to 8%, even more preferably 0.1% to 6%, and even more preferably 0.1% to 4%. This allows for a transistor with excellent electrical characteristics. For example, it is preferable to use a metal oxide having a ratio of In:M:Zn=40:1:10 or a metal oxide having a similar ratio. The element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides having a ratio of In:Sn:Zn=40:1:10 or a metal oxide having a similar ratio can be suitably used. Alternatively, metal oxides having a ratio of In:Al:Zn=40:1:10 or a metal oxide having a similar ratio can be suitably used.

[0162] Here, if a polycrystalline metal oxide is used for the layer 108, the crystal grain boundaries may become recombination centers, trapping carriers and reducing the on-state current of the transistor. Furthermore, if a polycrystalline metal oxide is used for the layer 108, the surface of the layer 108 may become uneven. This may increase the step on the surface on which a layer (e.g., the insulating layer 106) formed on the layer 108 is formed, which may cause defects such as discontinuities or voids in the layer. When a metal oxide having a composition that easily forms a polycrystalline structure is used for the layer 108, it is preferable to include an element that inhibits crystallization. This prevents the layer 108 from becoming polycrystalline, resulting in a transistor with a large on-state current. Furthermore, the coverage of a layer (e.g., the insulating layer 106) formed on the layer 108 can be improved, preventing defects such as discontinuities or voids in the layer.

[0163] For example, compared with indium tin oxide (ITO), indium tin oxide containing silicon (ITSO) is less likely to form a polycrystalline structure and is therefore suitable for use in the layer 108. When ITSO is used, the silicon content (the ratio of the number of silicon atoms to the sum of the numbers of atoms of all metal elements contained) is preferably 1% to 20%, more preferably 3% to 20%, even more preferably 3% to 15%, and even more preferably 5% to 15%. As the atomic ratio of metal elements, for example, In:Sn:Si=45:5:4, In:Sn:Si=95:5:8, and metal oxides in the vicinity thereof can be suitably used. When indium tin oxide containing silicon (ITSO) is used for the layer 108, it is preferable that the ITSO have crystallinity. Note that the layer 108 may have an amorphous region or may be amorphous.

[0164] A metal oxide that does not contain element M can be applied to the layer 108. When the metal oxide is an In-Zn oxide, the atomic ratio of the metal elements can be, for example, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 1:2, In:Zn = 3:1, In:Zn = 3:2, In:Zn = 2:3, In:Zn = 4:1, In:Zn = 4:3, In:Zn = 5:1, In:Zn = 5:2, In:Zn = 5:3, In:Zn = 5:4, In:Zn = 5:6, In:Zn = 5:7, In:Zn = 5:8, In:Zn = 5:9, In:Zn = 7:1, In:Zn = 10:1, In:Zn = 10:3, In:Zn = 10:7, and compositions in the vicinity thereof. Furthermore, it is more preferable that the atomic ratio of In is equal to or greater than the atomic ratio of Zn. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be increased.

[0165] The composition of the layer 108 can be analyzed using, for example, Energy Dispersive X-ray Spectrometry (EDX), X-ray Photoelectron Spectroscopy (XPS, or Electron Spectrometry for Chemical Analysis (ESCA)), Inductively Coupled Plasma-Mass Spectrometry (ICP-MS), or Inductively Coupled Plasma-Atomic Emission Spectroscopy (ICP-AES). Spectrometry) can be used. Alternatively, a combination of these techniques can be used for analysis. It is preferable to separate the peaks of the spectrum obtained by the analysis and identify and quantify the elements. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or element M may be below the detection limit.

[0166] The metal oxide film can be preferably formed by sputtering or atomic layer deposition (ALD). When the metal oxide film is formed by sputtering, the composition of the formed metal oxide film may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide film may decrease to about 50% of the zinc content in the sputtering target.

[0167] The layer 108 is preferably formed using a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide, the density of defect states in the layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0168] The layer 108 is preferably formed using a CAAC-OS or an nc-OS.

[0169] The CAAC-OS has a plurality of layered crystals. The c-axes of the crystals are oriented in the normal direction to the surface where the layer 108 is formed. The layer 108 preferably has layered crystals parallel to or approximately parallel to the surface where the layer 108 is formed. For example, the layer 108 preferably has layered crystals parallel to or approximately parallel to the top surface of the conductive layer 112a in a region in contact with the top surface of the conductive layer 112a. In particular, the layer 108 preferably has layered crystals parallel to or approximately parallel to the side surface 77 of the insulating layer 110, which is the surface where the layer 108 is formed, in a region in contact with the side surface 77. With this structure, the layered crystals of the layer 108 are formed parallel to or approximately parallel to the channel length direction of the transistor 100, thereby enabling the transistor to have a large on-state current.

[0170] By using a metal oxide with high crystallinity for the channel formation region, the density of defect states in the channel formation region can be reduced, while by using a metal oxide with low crystallinity, a transistor capable of passing a large current can be realized.

[0171] The higher the substrate temperature during deposition of a metal oxide film, the higher the crystallinity of the resulting metal oxide film. The substrate temperature during deposition can be adjusted, for example, by the temperature of the stage on which the substrate is placed during deposition. Furthermore, the higher the ratio of the flow rate of oxygen gas to the total deposition gas used for deposition (hereinafter also referred to as oxygen flow rate ratio) or the oxygen partial pressure in the processing chamber, the higher the crystallinity of the resulting metal oxide film.

[0172] The crystallinity of the layer 108 can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED), or by a combination of these techniques.

[0173] When a metal oxide is used for the layer 108, V ＯIt is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain a metal oxide with a sufficiently reduced amount of H, impurities such as water and hydrogen in the metal oxide must be removed (sometimes referred to as dehydration or dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V Ｏ It is important to repair the Ｏ By using a metal oxide in which impurities such as H are sufficiently reduced in a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0174] When a metal oxide is used for the layer 108, the carrier concentration in the channel forming region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ It is more preferable that the carrier concentration in the channel formation region is less than 1×10. −９ cm −３ It can be said that:

[0175] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0176] The layer 108 may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0177] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the channel formation region of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0178] The layer 108 can have a stacked structure having two or more metal oxide layers. The two or more metal oxide layers in the layer 108 can have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. When the two or more metal oxide layers in the layer 108 have the same or substantially the same composition, the boundary (interface) between these metal oxide layers may not be clearly visible.

[0179] The channel length and channel width of the transistor 100 will be described with reference to FIGS. 5A and 5B. FIG. 5A is a cross-sectional view of the semiconductor device 10, and FIG. 5B is a top view of the semiconductor device 10. Here, a region of the layer 108 that is in contact with the side surface of the insulating layer 110b (region 108R) will be described as a channel formation region of the transistor 100.

[0180] In FIG. 5A , the channel length L100 of the transistor 100 is indicated by a dashed double-headed arrow. The channel length L100 corresponds to the length of the region where the layer 108 and the side surface of the insulating layer 110b meet in a cross-sectional view. That is, the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle θ110b between the side surface of the insulating layer 110b facing the layer 108 and the surface on which the insulating layer 110b is to be formed (here, the top surface of the insulating layer 110a). Therefore, the channel length L100 can be set to a value smaller than the minimum exposure dimension of the exposure tool, enabling the realization of a fine-sized transistor. Specifically, it is possible to realize a transistor with an extremely short channel length that could not be realized using conventional exposure tools for mass production of flat panel displays (e.g., minimum dimensions of approximately 2 μm or 1.5 μm). Furthermore, it is possible to realize a transistor with a channel length of less than 10 nm without using the extremely expensive exposure tools used in cutting-edge LSI technology.

[0181] The channel length L100 may be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L100 may be 100 nm or more and 1 μm or less.

[0182] By shortening the channel length L100, the on-state current of the transistor 100 can be increased. By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

[0183] The channel length L100 can be controlled by adjusting the thickness T110b and angle θ110b of the insulating layer 110b.

[0184] The thickness T110b of the insulating layer 110b can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and can be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.

[0185] The side surface of the insulating layer 110 facing the layer 108 is preferably tapered. The angle θ110b is preferably less than 90 degrees. By reducing the angle θ110b, the coverage of a layer (e.g., the layer 108) formed on the insulating layer 110 can be improved. Furthermore, when the angle θ110b is 90 degrees or less, the smaller the angle θ110b, the longer the channel length L100 can be, and the larger the angle θ110b, the shorter the channel length L100 can be.

[0186] The angle θ110b can be, for example, 30 degrees or more, 35 degrees or more, 40 degrees or more, 45 degrees or more, 50 degrees or more, 55 degrees or more, 60 degrees or more, 65 degrees or more, or 70 degrees or more, and can be less than 90 degrees, 85 degrees or less, or 80 degrees or less. The angle θ110b can also be 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less.

[0187] 1B and the like, the angle θ110b is shown as being less than 90 degrees, but this is not a limitation of one embodiment of the present invention. The angle θ110b may also be set to 90 degrees or approximately 90 degrees. This can shorten the channel length L100 and reduce the area occupied by the semiconductor device.

[0188] 1B and other figures show a configuration in which the shape of the side surface 77 is straight in cross section, but this is not a limitation of one aspect of the present invention. In cross section, the shape of the side surface 77 may be curved. Alternatively, the shape of the side surface 77 may include both straight and curved regions.

[0189] In FIG. 1A and other figures, the top surface shape of the insulating layer 110 is shown as a rectangle, but the top surface shape is not particularly limited.

[0190] 5B, the channel width W100 of the transistor 100 is indicated by a two-dot chain line with a double arrow. The channel width W100 is the width of the region where the layer 108 and the conductive layer 104 overlap in a direction perpendicular to the channel length direction.

[0191] When the layer 108 and the conductive layer 104 are formed using lithography, the channel width W100 is equal to or greater than the minimum exposure dimension of an exposure device. The channel width W100 can be, for example, 20 nm or more, 50 nm or more, 100 nm or more, 200 nm or more, 500 nm or more, or 1 μm or more, and can be less than 500 μm, 200 μm or less, 100 μm or less, 50 μm or less, 20 μm or less, 10 μm or less, or 5 μm or less.

[0192] Note that although the example described here is a structure in which the region of the layer 108 in contact with the insulating layer 110b functions as a channel formation region of the transistor 100, one embodiment of the present invention is not limited to this. The region of the layer 108 in contact with the insulating layer 110a may also function as a channel formation region of the transistor 100. Similarly, the region of the layer 108 in contact with the insulating layer 110c may also function as a channel formation region.

[0193] [Conductive Layer 112a, Conductive Layer 104] The conductive layer 112a and the conductive layer 104 can each have a single-layer structure or a stacked structure of two or more layers. Materials that can be used for these conductive layers include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys containing one or more of the above metals. For these conductive layers, conductive materials with low electrical resistivity, including one or more of copper, silver, gold, and aluminum, can be preferably used. Copper and aluminum are particularly preferred because of their excellent mass productivity.

[0194] An oxide conductor can be used for each of the conductive layer 112a and the conductive layer 104. For the oxide conductor, refer to the above description.

[0195] When oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes electrically conductive, and the conductivity of the metal oxide increases. The metal oxide that has become electrically conductive can be called an oxide conductor.

[0196] The conductive layer 112a and the conductive layer 104 can each have a stacked-layer structure of a conductive film containing the above-described oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0197] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can be applied to each of the conductive layer 112a and the conductive layer 104. By using a Cu-X alloy film, it can be processed by wet etching, thereby reducing manufacturing costs.

[0198] Note that the conductive layer 112a and the conductive layer 104 can be formed using the same material or different materials.

[0199] The conductive layer 112a has a region in contact with the layer 108. When a metal oxide is used for the layer 108, if a metal that is easily oxidized (e.g., aluminum) is used for the conductive layer, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 112a and the layer 108, which may hinder electrical conduction between them. Therefore, for these conductive layers, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor.

[0200] The conductive layer 112a is preferably made of, for example, titanium, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, or oxide containing lanthanum and nickel. These are preferable because they are conductive materials that are difficult to oxidize or materials that maintain low electrical resistance even when oxidized.

[0201] The conductive layer 112a can be formed using any of the above-mentioned oxide conductors. Specifically, oxide conductors such as indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, ITSO, and zinc oxide doped with gallium can be used. In particular, oxide conductors containing indium have high conductivity and are therefore suitable for use as the conductive layer 112a.

[0202] The conductive layer 112a may also be made of a nitride conductor, such as tantalum nitride and titanium nitride.

[0203] The conductive layer 112a and the conductive layer 104 can each have a single-layer structure or a stacked structure of two or more layers.

[0204] When the conductive layer 112a has a stacked structure, the first conductive layer in contact with the layer 108 is preferably made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor. For example, ITO or ITSO can be suitably used for the first conductive layer. On the other hand, there is no particular limitation on the material used for the second conductive layer that is not in contact with any of the layers 108. For example, the second conductive layer is preferably made of a material that has lower electrical resistivity than the first conductive layer. This can reduce the electrical resistance of the conductive layer 112a. For example, copper or tungsten can be suitably used for the second conductive layer.

[0205] [Insulating Layer 106] The insulating layer 106 preferably has one or more inorganic insulating layers. The insulating layer 106 can be made of the same material as that used for the insulating layer 110.

[0206] The insulating layer 106 has a region in contact with the layer 108, the conductive layer 112a, the conductive layer 104, and the insulating layer 110. When a metal oxide is used for the layer 108, any of the above oxides and oxynitrides is preferably used for at least a film that is in contact with the layer 108 among the films that constitute the insulating layer 106. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be preferably used for the insulating layer 106.

[0207] Note that in a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0208] 1B and the like, the insulating layer 106 has a single-layer structure, but one embodiment of the present invention is not limited to this. The insulating layer 106 can have a stacked structure of two or more layers. 8A and 8B show a structure in which the insulating layer 106 has a two-layer structure of an insulating layer 106a and an insulating layer 106b over the insulating layer 106a.

[0209] When the insulating layer 106 has a stacked structure, the insulating layers on the layer 108 side and the layer 108 side (the insulating layer 106a here) are preferably made of oxide or oxynitride. For example, the insulating layer 106a can be preferably made of one or more of silicon oxide, silicon oxynitride, and aluminum oxide. Alternatively, the insulating layer 106a can be made of nitride or nitride oxide. For example, aluminum nitride can be preferably used for the insulating layer 106a.

[0210] It is preferable that one or more layers constituting the insulating layer 106 function as a barrier film. By providing a barrier film, it is possible to suppress the diffusion of metal components contained in the conductive layer 104 and impurities (e.g., water and hydrogen) contained in layers formed on the transistor 100 into the layer 108 through the insulating layer 106. Furthermore, it is possible to suppress the diffusion of oxygen contained in the insulating layer 110b to the region 108P side through the insulating layer 106. This suppresses an increase in the electrical resistance of the region 108P. In addition, the amount of oxygen supplied from the insulating layer 110b to the channel formation region increases, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, a transistor having good electrical characteristics and high reliability can be obtained. Furthermore, the conductive layer 104 can be prevented from being oxidized by oxygen contained in the insulating layer 110b, which can prevent the electrical resistance of the conductive layer 104 from increasing. As a result, a transistor having good electrical characteristics and high reliability can be obtained. The above-mentioned materials can be used as the barrier film. For example, one or more of silicon nitride, aluminum oxide, and aluminum nitride can be suitably used for one or more layers constituting the insulating layer 106.

[0211] When the insulating layer 106 has a stacked-layer structure, for example, silicon oxynitride can be used for the insulating layer 106a and silicon nitride can be used for the insulating layer 106b. Alternatively, silicon oxynitride can be used for the insulating layer 106a and aluminum oxide can be used for the insulating layer 106b. Alternatively, silicon oxynitride can be used for the insulating layer 106a and aluminum nitride can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a and silicon oxynitride can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a and silicon nitride can be used for the insulating layer 106b. Alternatively, aluminum nitride can be used for the insulating layer 106a and silicon oxynitride can be used for the insulating layer 106b.

[0212] Although an example in which the insulating layer 106 has a stacked structure of two layers is shown here, one embodiment of the present invention is not limited to this. The insulating layer 106 can also have a stacked structure of three or more layers.

[0213] The configuration of the insulating layer 106 shown here can also be applied to other configuration examples.

[0214] [Substrate 102] There are no significant limitations on the material of the substrate 102, but it must have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a resin substrate can be used as the substrate 102. Alternatively, a substrate on which a semiconductor element is provided can be used as the substrate 102. A substrate on which an insulating film is formed on the surface can be used as the substrate 102. The shape of the substrate 102 is not particularly limited, and can be, for example, circular or rectangular.

[0215] A flexible substrate can be used as the substrate 102, and the transistor 100 can be formed directly on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate 102 and the transistor 100. By providing the peeling layer, after a semiconductor device is partially or entirely completed thereon, the semiconductor device can be separated from the substrate 102 and transferred to another substrate. In this case, the transistor 100 can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0216] The following describes a configuration example of a semiconductor device that is partially different from the configuration example described above. Note that, in the following, descriptions of parts that overlap with the configuration example described above may be omitted. Furthermore, in the drawings shown below, parts that have the same functions as the configuration example described above may be hatched with the same pattern and may not be assigned reference numerals.

[0217] 9A shows a top view (also referred to as a plan view) of a semiconductor device 10A. FIG. 9B shows a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 9A , and FIG. 9C shows a cross-sectional view of a cut surface taken along dashed dotted line B1-B2 in FIG.

[0218] The semiconductor device 10A includes a transistor 100A, an insulating layer 110, and an insulating layer 109. The semiconductor device 10A differs from the semiconductor device 10 shown in FIG. 1A etc. mainly in that the insulating layer 110 has an opening.

[0219] Fig. 10A shows a perspective view of the semiconductor device 10A, and Fig. 10B shows a perspective view of Fig. 10A from which the conductive layer 104 and the insulating layer 106 are omitted.

[0220] The insulating layer 110 has an opening 141 that reaches the conductive layer 112a. In other words, the side surface 77 of the insulating layer 110 and the top surface of the conductive layer 112a are exposed in the opening 141.

[0221] The layer 108 is provided so as to cover a part of the opening 141. The layer 108 is also provided so as to cross the opening 141. The layer 108 has an area in contact with the upper surface and side surface 77 of the insulating layer 110 and the upper surface of the conductive layer 112a.

[0222] An insulating layer 106 is provided on the layer 108. A conductive layer 104 is provided on the insulating layer 106. The layer 108, the insulating layer 106, and the conductive layer 104 each have a region located within the opening 141.

[0223] The layer 108 has a region 74 and a region 74a in contact with the side surface 77. The region 74 and the region 74a each function as a channel formation region of the transistor 100A. The conductive layer 104 has a region facing the side surface 77 with the region 74 and the insulating layer 106 interposed therebetween, and also has a region facing the side surface 77 with the region 74a and the insulating layer 106 interposed therebetween.

[0224] The channel length and channel width of the transistor 100A will be described with reference to FIGS. 11A and 11B.

[0225] 11B, the channel length L100 of the transistor 100A is indicated by a dashed double-headed arrow. The channel length L100 can be understood from the above description, and therefore will not be described in detail again.

[0226] 11A , in the transistor 100A, a width W1 of the region where the layer 108 and the conductive layer 104 overlap in the region 74 and a width W2 of the region where the layer 108 and the conductive layer 104 overlap in the region 74a are indicated by double-arrowed, two-dot chain lines. The channel width W100 of the transistor 100A is the sum of the width W1 and the width W2.

[0227] 11A and other figures show a configuration in which the top surface shape of the opening 141 is a rectangle with rounded corners, but one embodiment of the present invention is not limited thereto. The top surface shape of the opening 141 is not limited thereto and may be, for example, a circle, an ellipse, a triangle, a square (including a rectangle, a diamond, and a square), a polygon such as a pentagon, or a shape with rounded corners of these polygons. Note that the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees). Note that forming the top surface shape of the opening 141 as a circle can improve processing accuracy when forming the opening 141, and thus allows the formation of a fine-sized opening 141. Note that in this specification and other figures, a circle is not limited to a perfect circle.

[0228] The opening 141 is provided only in one of the source region and the drain region and in a region nearby the source region and the insulating layer 110 is provided in the remaining region. Therefore, the area of ​​the region where the insulating layer 110 is provided can be increased, and unevenness caused by the region where the insulating layer 110 is provided and the region where the insulating layer 110 is not provided can be reduced. This improves the coverage of the layers provided on the transistor 100A and the insulating layer 110, and suppresses defects such as discontinuities or voids in the layers.

[0229] The configuration of the opening 141 shown here can also be applied to other configuration examples.

[0230] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0231] Embodiment 2 In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 12A to 38B. FIG.

[0232] <Configuration Example 1> [Configuration Example 1-1] A semiconductor device according to one embodiment of the present invention will be described. FIG. 12A shows a top view (also referred to as a plan view) of a semiconductor device 20. FIG. 12B shows an equivalent circuit diagram of the semiconductor device 20. FIG. 12C shows a cross-sectional view of the cut surface taken along dashed dotted line A3-A4 in FIG. 12A, and FIG. 13 shows a cross-sectional view of the cut surface taken along dashed dotted line B3-B4 in FIG. 1C can be referred to for a cross-sectional view of the cut surface taken along dashed dotted line B1-B2 of the semiconductor device 20.

[0233] The semiconductor device 20 includes a transistor 100, a transistor 200, an insulating layer 110, and an insulating layer 109. The insulating layer 109 is provided over a substrate 102, and the transistors 100 and 200 are provided over the insulating layer 109.

[0234] The above description can be referred to for the transistor 100. The transistor 200 can have a similar structure to that of the transistor 100. The transistor 200 includes a conductive layer 204, an insulating layer 106, a layer 108, and a conductive layer 212a. In the transistor 200, the conductive layer 204 functions as a gate electrode, the insulating layer 106 functions as a gate insulating layer, and the conductive layer 212a functions as one of a source electrode and a drain electrode.

[0235] The transistors 100 and 200 share a layer 108. The layer 108 has a region 108P in contact with the top layer of the insulating layer 110 (here, the insulating layer 110d). The transistors 100 and 200 share the region 108P. The region 108P functions as the other of the source and drain electrodes of the transistor 100 and the transistor 200. The layer 108 has a channel formation region of the transistor 100, a channel formation region of the transistor 200, and a region 108P that functions as the other of the source and drain electrodes of the transistors 100 and 200. The region of the layer 108 in contact with the conductive layer 112a functions as one of the source and drain regions of the transistor 100, and the region in contact with the conductive layer 212a functions as one of the source and drain regions of the transistor 200.

[0236] By sharing the layer 108 between the transistors 100 and 200, the area occupied by the circuit can be reduced, leading to a compact semiconductor device.

[0237] The other of the source and the drain of the transistor 100 is connected to the other of the source and the drain of the transistor 200. Note that although the transistors 100 and 200 are both n-channel transistors in FIG. 12B , one embodiment of the present invention is not limited to this. One or both of the transistors 100 and 200 can be p-channel transistors. Alternatively, a structure without one of the transistors 100 and 200 is also possible.

[0238] Fig. 14A shows a perspective view of the semiconductor device 20. Fig. 14B shows a perspective view in which the conductive layer 104, the conductive layer 204, and the insulating layer 106 are omitted from Fig. 14A.

[0239] The conductive layers 112a and 212a are provided over the insulating layer 109, and the insulating layer 110 is provided over the conductive layers 112a and 212a. The conductive layers 112a and 212a each have a region in contact with the insulating layer 109. The insulating layer 110 has a region in contact with the conductive layer 112a and 212a.

[0240] The conductive layer 212a can be formed using the materials listed for the conductive layer 112a. The conductive layer 212a can be formed in the same process as the conductive layer 112a. For example, a conductive film that will become the conductive layer 112a and the conductive layer 212a is formed and then processed to form the conductive layer 112a and the conductive layer 212a. Forming the conductive layer 112a and the conductive layer 212a in the same process can reduce manufacturing costs. Alternatively, the conductive layer 112a and the conductive layer 212a can be formed in different processes. By forming the conductive layer 112a and the conductive layer 212a in different processes, different materials can be used for the conductive layer 112a and the conductive layer 212a, thereby broadening the range of material selection.

[0241] 12C , the insulating layer 110 has an end 31 and an end 31a that contacts the upper surface of the conductive layer 212a. The region where the side of the insulating layer 110 contacts the upper surface of the conductive layer 212a corresponds to the end 31a. The conductive layer 112a has a region where the insulating layer 110 is provided and a region where the insulating layer 110 is not provided. The conductive layer 212a has a region where the insulating layer 110 is provided and a region where the insulating layer 110 is not provided. The insulating layer 110 also has a side 77 on the conductive layer 112a and a side 77a on the conductive layer 212a. The lower end of the side 77a corresponds to the end 31a. The above description can be referred to for the end 31 and the side 77.

[0242] The insulating layer 110 preferably has a stacked structure. For the insulating layer 110, the above description can be referred to.

[0243] A layer 108 is provided over the conductive layer 112a, the conductive layer 212a, and the insulating layer 110. The layer 108 has regions in contact with the top surface of the conductive layer 112a, the top surface of the conductive layer 212a, and the top surface and side surface (here, the side surface 77 and the side surface 77a) of the insulating layer 110. The layer 108 is connected to the conductive layer 112a and the conductive layer 212a. The layer 108 has a shape that follows the shapes of the top surface of the conductive layer 112a, the top surface of the conductive layer 212a, and the top surface, side surface 77, and side surface 77a of the insulating layer 110. The layer 108 is provided across a region on the conductive layer 112a where the insulating layer 110 is not provided, a region where the insulating layer 110 is provided, and a region on the conductive layer 212a where the insulating layer 110 is not provided.

[0244] The layer 108 has a first region in contact with the conductive layer 112a, a second region in contact with the side surface 77, a third region in contact with the top surface of the insulating layer 110, a fourth region in contact with the side surface 77a, and a fifth region in contact with the conductive layer 212a. The first region is in contact with the second region, the second region is in contact with the third region, the third region is in contact with the fourth region, and the fourth region is in contact with the fifth region. It can be said that the first to fifth regions are continuous in this order.

[0245] Fig. 15 shows a cross-sectional view taken along the dashed dotted line C1-C2 in Fig. 12C. Fig. 15 is a cross-sectional view taken along a plane including the insulating layer 110. Fig. 16A shows an enlarged view of Fig. 12C.

[0246] 1C , 13 , and 15 , layer 108 has end 33 in contact with the upper surface of conductive layer 112 a, end 37 in contact with side surface 77, end 35 in contact with the upper surface of insulating layer 110, end 37 a in contact with side surface 77 a, and end 33 a in contact with the upper surface of conductive layer 112 a. End 37 a is the end on the surface of layer 108 that is in contact with side surface 77 a. End 33 a is the end on the surface of layer 108 that is in contact with the upper surface of conductive layer 212 a. The above descriptions can be referenced for end 33, end 37, and end 35.

[0247] 15 , the insulating layer 110 has, on a side surface 77, a region 70 where the layer 108 is provided and a region 72 where the layer 108 is not provided. In the region 70, the layer 108 is in contact with the insulating layer 110. The insulating layer 106 has a region facing the side surface 77 with the layer 108 interposed therebetween. On the other hand, in the region 72, the insulating layer 106 is in contact with the insulating layer 110. Furthermore, the insulating layer 110 has, on a side surface 77a, a region 70a where the layer 108 is provided and a region 72a where the layer 108 is not provided. In the region 70a, the layer 108 is in contact with the insulating layer 110. The insulating layer 106 has a region facing the side surface 77a with the layer 108 interposed therebetween. On the other hand, in the region 72a, the insulating layer 106 is in contact with the insulating layer 110.

[0248] The conductive layer 104, which functions as a gate electrode of the transistor 100, is provided over the insulating layer 106 and has a region in contact with the top surface of the insulating layer 106. The conductive layer 104 has a region overlapping with the layer 108 with the insulating layer 106 interposed therebetween. The conductive layer 104 also has a region facing the side surface 77 with the insulating layer 106 and the layer 108 interposed therebetween. The conductive layer 104 is provided to cover at least the region of the layer 108 that is in contact with the side surface 77. This allows the region to function as a channel formation region of the transistor 100.

[0249] The conductive layer 204, which functions as a gate electrode of the transistor 200, is provided over the insulating layer 106 and has a region in contact with the top surface of the insulating layer 106. The conductive layer 204 has a region overlapping with the layer 108 with the insulating layer 106 interposed therebetween. The conductive layer 204 also has a region facing the side surface 77a with the insulating layer 106 and the layer 108 interposed therebetween. The conductive layer 204 is provided to cover at least the region in contact with the side surface 77a of the layer 108. This allows the region to function as a channel formation region of the transistor 200.

[0250] The conductive layer 204 can be formed using the materials listed for the conductive layer 104. The conductive layer 204 can be formed in the same process as the conductive layer 104. For example, conductive films to be the conductive layers 104 and 204 are formed and then processed to form the conductive layers 104 and 204. By forming the conductive layers 104 and 204 in the same process, manufacturing costs can be reduced. Alternatively, the conductive layers 104 and 204 can be formed in different processes. By forming the conductive layers 104 and 204 in different processes, different materials can be used for the conductive layers 104 and 204, thereby widening the range of material selection.

[0251] A step can be formed between a region on the conductive layer 112a where the insulating layer 110 is provided and a region on the conductive layer 112a where the insulating layer 110 is not provided, and the layer 108, the insulating layer 106, and the conductive layer 104 are provided along the step. Similarly, a step can be formed between a region on the conductive layer 212a where the insulating layer 110 is provided and a region on the conductive layer 212a where the insulating layer 110 is not provided, and the layer 108, the insulating layer 106, and the conductive layer 204 are provided along the step.

[0252] The transistor 100 and the transistor 200 can each be called a VFET. This allows the area occupied by a semiconductor device including the transistor 100 and the transistor 200 to be significantly reduced.

[0253] The channel length and channel width of the transistor 200 will be described with reference to FIGS. 16A and 16B. FIG. 16A is a cross-sectional view of the semiconductor device 20, and FIG. 16B is a top view of the semiconductor device 10. Note that the channel length L100 and channel width W100 of the transistor 100 can be determined by referring to the above description.

[0254] 16A, the channel length L200 of the transistor 200 is indicated by a dashed double-headed arrow. Here, the region of the layer 108 in contact with the side surface of the insulating layer 110b is described as the channel formation region of the transistor 200. The channel length L200 corresponds to the length of the region where the layer 108 and the side surface of the insulating layer 110b are in contact in a cross-sectional view. Therefore, the channel length L200 is determined by the thickness T110b and the angle θ110b. For the channel length L200, the description of the channel length L100 can be referred to.

[0255] 16B , the channel width W200 of the transistor 200 is indicated by a double-headed arrow of a two-dot chain line. The channel width W200 is the width of a region where the layer 108 and the conductive layer 204 overlap in a direction perpendicular to the channel length direction. For the channel width W200, refer to the description of the channel width W100. Note that although FIG. 16B and other figures show a configuration in which the channel width W100 and the channel width W200 are the same, one embodiment of the present invention is not limited to this. The channel width W100 and the channel width W200 can be different from each other.

[0256] The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 provided over the conductive layer 112a. Similarly, the channel length of the transistor 200 can be controlled by the thickness of the insulating layer 110 provided over the conductive layer 212a. Therefore, a transistor with a short channel length can be manufactured with high precision.

[0257] The conductive layer 112a, the region 108P, the conductive layer 212a, the conductive layer 104, and the conductive layer 204 can each function as a wiring. The transistor 100 and the transistor 200 can be provided in a region where these wirings overlap. That is, in a circuit including the transistor 100, the transistor 200, and the wiring, the area occupied by the transistor 100, the transistor 200, and the wiring can be reduced. Therefore, a semiconductor device with a small area can be provided.

[0258] Although FIG. 12A and the like illustrate a structure in which the layer 108 is in contact with a plurality of side surfaces (here, the side surface 77 and the side surface 77a) of the insulating layer 110, one embodiment of the present invention is not limited to this.

[0259] 17A to 18B, the layer 108 can be provided on one side of the insulating layer 110. FIG. 17A is a top view of the semiconductor device 20, and FIG. 17B is a cross-sectional view taken along the dashed dotted line A3-A4 shown in FIG. 17A. FIG. 18A is a perspective view of the semiconductor device 20. FIG. 18B is a perspective view of FIG. 18A from which the conductive layer 104, the conductive layer 204, and the insulating layer 106 are omitted.

[0260] The insulating layer 110 has a side surface 77 on the conductive layer 112a and a side surface 77 on the conductive layer 212a. The layer 108 has a region in contact with the side surface 77, the top surface of the insulating layer 110, the top surface of the conductive layer 112a, and the top surface of the conductive layer 212a.

[0261] There are no particular limitations on the side surface of the insulating layer 110 on which the layer 108 is provided, which increases the degree of freedom in the layout of the layer 108 and reduces the area occupied by the semiconductor device.

[0262] Although the side surface 77 and the side surface 77a are shown separately in FIG. 12C and other figures, the side surfaces of the insulating layer 110 may be continuously connected, making it difficult to distinguish between the side surface 77 and the side surface 77a.

[0263] The insulating layer 109 is provided between the transistor 100, the transistor 200, and the insulating layer 110 and the substrate 102. The insulating layer 109 has regions in contact with the conductive layer 112a, the conductive layer 212a, the insulating layer 110, and the insulating layer 106. The above description can be referred to for the insulating layer 109.

[0264] The configuration of the layer 108 and the region 108P shown here can also be applied to other configuration examples.

[0265] [Configuration Example 1-2] Fig. 19A shows a top view of a semiconductor device 20A according to one embodiment of the present invention. Fig. 19B shows an equivalent circuit diagram of the semiconductor device 20A. Fig. 19C shows a cross-sectional view of the cut surface taken along dashed dotted line A3-A4 in Fig. 19A, and Fig. 20 shows a cross-sectional view of the cut surface taken along dashed dotted line B3-B4. For a cross-sectional view of the cut surface taken along dashed dotted line B1-B2, see Fig. 1C.

[0266] The semiconductor device 20A includes a transistor 100, a transistor 200, an insulating layer 110, an insulating layer 210, and an insulating layer 109.

[0267] The above description can be referred to for the transistor 100. The transistor 200 includes a conductive layer 204, an insulating layer 106, a layer 208, and a conductive layer 112a. In the transistor 200, the conductive layer 204 functions as a gate electrode, the insulating layer 106 functions as a gate insulating layer, and the conductive layer 112a functions as one of a source electrode and a drain electrode.

[0268] The conductive layer 112a is shared by the transistor 100 and the transistor 200. The conductive layer 112a functions as one of a source electrode and a drain electrode of the transistor 100 and also functions as one of a source electrode and a drain electrode of the transistor 200.

[0269] By sharing the conductive layer 112a between the transistor 100 and the transistor 200, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be provided.

[0270] One of the source and the drain of the transistor 100 is connected to one of the source and the drain of the transistor 200. Note that although the transistors 100 and 200 are both n-channel transistors in FIG. 19B, one embodiment of the present invention is not limited thereto. One or both of the transistors 100 and 200 can be p-channel transistors.

[0271] A perspective view of the semiconductor device 20A is shown in Fig. 21A. A perspective view in which the conductive layer 104, the conductive layer 204, and the insulating layer 106 are omitted from Fig. 21A is shown in Fig. 21B.

[0272] A conductive layer 112a is provided over the insulating layer 109, and an insulating layer 110 and an insulating layer 210 are provided over the conductive layer 112a. The insulating layer 110 has a region in contact with the conductive layer 112a. The insulating layer 210 has a region in contact with the conductive layer 112a.

[0273] The insulating layer 210 can be formed using the materials listed for the insulating layer 110. The insulating layer 210 can be formed in the same process as the insulating layer 110. For the insulating layer 210, the description of the insulating layer 110 can be referred to.

[0274] The insulating layer 210 preferably has a laminated structure. Figure 19C and other figures show an example in which the insulating layer 210 has an insulating layer 210a, an insulating layer 210b on the insulating layer 210a, an insulating layer 210c on the insulating layer 210b, and an insulating layer 210d on the insulating layer 210c. For the insulating layers 210a, 210b, 210c, and 210d, the descriptions of the insulating layers 110a, 110b, 110c, and 110d can be referenced, and detailed descriptions thereof will be omitted.

[0275] The layer 208 has a region 208P in contact with the top layer of the insulating layer 210 (here, the insulating layer 210d). The insulating layer 210d preferably contains impurities that reduce the electrical resistance of the layer 208 and uses a material that releases the impurities. The region 208P is conductive due to the impurities released from the insulating layer 210d. The region 208P can be referred to as an oxide conductor (OC). As a result, the region 208P functions as the other of the source electrode and drain electrode of the transistor 200. For the region 208P, the description of the region 108P can be referred to.

[0276] 19C , insulating layer 110 has an end portion 31, and insulating layer 210 has an end portion 41 that contacts the upper surface of conductive layer 112a. Conductive layer 112a has a region where insulating layer 110 is provided, a region where insulating layer 210 is provided, and a region where neither insulating layer 110 nor insulating layer 210 is provided. Insulating layer 110 has a side surface 77 on conductive layer 112a, and insulating layer 210 has a side surface 87 on conductive layer 112a. The lower end of side surface 77 becomes end portion 31, and the lower end of side surface 87 becomes end portion 41.

[0277] The layer 108 is provided over the conductive layer 112a and the insulating layer 110. For the layer 108, refer to the above description.

[0278] A layer 208 is provided over the conductive layer 112a and the insulating layer 210. The layer 208 has regions in contact with the top surface of the conductive layer 112a and the top surface and side surface (here, the side surface 87) of the insulating layer 210. The layer 208 is connected to the conductive layer 112a. The layer 208 has a shape that follows the shapes of the top surface of the conductive layer 112a and the top surface and side surface 87 of the insulating layer 210. The layer 208 is provided across a region over the conductive layer 112a where the insulating layer 210 is not provided and a region over the conductive layer 112a where the insulating layer 210 is provided.

[0279] The layer 108 has a first region in contact with the conductive layer 112a, a second region in contact with the side surface 77, and a third region in contact with the top surface of the insulating layer 110. The first region is in contact with the second region, and the second region is in contact with the third region. It can also be said that the first region, the second region, and the third region are continuous in this order.

[0280] The layer 208 has a fourth region in contact with the conductive layer 112a, a fifth region in contact with the side surface 87, and a sixth region in contact with the top surface of the insulating layer 210. The fourth region is in contact with the fifth region, and the fifth region is in contact with the sixth region. It can also be said that the fourth region, the fifth region, and the sixth region are continuous in this order.

[0281] 22 is a cross-sectional view taken along the dashed dotted line C1-C2 in FIG.

[0282] 20 and 22 , layer 208 has end 43 in contact with the upper surface of conductive layer 212a, end 47 in contact with side surface 87, and end 45 in contact with the upper surface of insulating layer 210. End 43 is an end on the surface of layer 208 that is in contact with the upper surface of conductive layer 112a. End 47 is an end on the surface of layer 208 that is in contact with side surface 87. End 45 is an end on the surface of layer 208 that is in contact with the upper surface of insulating layer 210.

[0283] 22 , the insulating layer 210 has, on the side surface 87, a region 80 where the layer 208 is provided and a region 82 where the layer 208 is not provided. In the region 80, the layer 208 contacts the insulating layer 210. The insulating layer 106 has a region facing the side surface 87 with the layer 208 interposed therebetween. On the other hand, in the region 82, the insulating layer 106 contacts the insulating layer 210.

[0284] In semiconductor device 20A, layer 208 is provided in contact with conductive layer 112a and side surface 87. Insulating layer 210, side surface 87, end 41, end 43, end 45, end 47, region 80, and region 82 in semiconductor device 20A correspond to insulating layer 110, side surface 77a, end 31a, end 33a, end 35, end 37a, region 70a, and region 72a in semiconductor device 20 (see FIGS. 12C, 13, and 15).

[0285] The layer 208 can be formed in the same process as the layer 108. For example, semiconductor films to become the layers 108 and 208 are formed and then processed to form the layers 108 and 208. By forming the layers 108 and 208 in the same process, manufacturing costs can be reduced. Alternatively, the layers 108 and 208 can be formed in different processes. By forming the layers 108 and 208 in different processes, different materials can be used for the layers 108 and 208, thereby widening the range of material options.

[0286] The configuration of the layer 208, the region 208P, and the insulating layer 210 shown here can also be applied to other configuration examples.

[0287] Configuration Example 1-3 FIG. 23A shows a top view of a semiconductor device 20B according to one embodiment of the present invention. FIG. 23B shows an equivalent circuit diagram of the semiconductor device 20B. FIG. 23C shows a cross-sectional view of the cut surface taken along dashed dotted line A3-A4 in FIG. 23A. FIG. 1C can be referred to for a cross-sectional view of the cut surface taken along dashed dotted line B1-B2 in FIG. 23A. FIG. 24 shows a cross-sectional view of the cut surface taken along dashed dotted line B3-B4.

[0288] The semiconductor device 20B includes a transistor 100, a transistor 200, an insulating layer 110, an insulating layer 210, and an insulating layer 109.

[0289] The above description can be referred to for the transistor 100. The transistor 200 includes a conductive layer 204, an insulating layer 106, a layer 208, and a conductive layer 212a. In the transistor 200, the conductive layer 204 functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. The conductive layer 212a functions as one of a source electrode and a drain electrode.

[0290] An insulating layer 110 is provided over the conductive layer 112a and the conductive layer 212a. A layer 108 is provided over the conductive layer 112a and the insulating layer 110. The layer 108 has a region 108P in contact with the insulating layer 110d. The region 108P functions as the other of the source and drain electrodes of the transistor 100. A layer 208 is provided over the conductive layer 212a and the insulating layer 110. The layer 208 has a region 208P in contact with the insulating layer 110d. The region 208P functions as the other of the source and drain electrodes of the transistor 200.

[0291] The insulating layer 106 has an opening 149 that reaches the region 108P. The conductive layer 204 is provided so as to cover the opening 149. The conductive layer 204 contacts the region 108P in the opening 149 and is connected to the region 108P.

[0292] The other of the source and the drain of the transistor 100 is connected to the gate of the transistor 200. Note that although the transistors 100 and 200 are both n-channel transistors in FIG. 23B, one embodiment of the present invention is not limited thereto. One or both of the transistors 100 and 200 can be p-channel transistors.

[0293] Although the structure in which the other of the source and the drain of the transistor 100 is connected to the gate of the transistor 200 is shown, one embodiment of the present invention is not limited to this. One of the source and the drain of the transistor 100 can be connected to the gate of the transistor 200. For example, an opening that reaches the conductive layer 112a is provided in the insulating layer 106, and the conductive layer 204 is provided to cover the opening. As a result, the conductive layer 204 can be in contact with the conductive layer 112a in the opening and can be connected to the conductive layer 112a.

[0294] The configuration of the opening 149 and the conductive layer 204 shown here can also be applied to other configuration examples.

[0295] [Configuration Example 1-4] FIG. 25A shows a top view of a semiconductor device 20C according to one embodiment of the present invention. FIG. 25B shows an equivalent circuit diagram of the semiconductor device 20C. FIG. 25C shows a cross-sectional view of the cut surface taken along dashed dotted line A3-A4 in FIG. 25A. FIG. 1C can be referred to for a cross-sectional view of the cut surface taken along dashed dotted line B1-B2 in FIG. 25A.

[0296] The semiconductor device 20C includes a transistor 100, a capacitor 150, an insulating layer 110, an insulating layer 210, and an insulating layer 109.

[0297] The above description of the transistor 100 can be referred to. The capacitor 150 includes a region 108P, an insulating layer 106 on the region 108P, and a conductive layer 104C on the insulating layer 106. The region 108P, the insulating layer 106, and the conductive layer 104C overlap each other. The region 108P and the conductive layer 104C function as a pair of electrodes of the capacitor 150, and the insulating layer 106 sandwiched between the pair of electrodes functions as a dielectric of the capacitor 150.

[0298] The conductive layer 104C can be formed in the same process as the conductive layer 104. The region 108P functions as the other of the source electrode and drain electrode of the transistor 100 and also functions as one of a pair of electrodes of the capacitor 150. By sharing the region 108P between the transistor 100 and the capacitor 150, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be provided.

[0299] The other of the source and the drain of the transistor 100 is connected to one of a pair of electrodes of the capacitor 150. Note that although the transistor 100 is an n-channel transistor in FIG. 25B, one embodiment of the present invention is not limited to this. The transistor 100 can also be a p-channel transistor.

[0300] An example of a configuration different from that of semiconductor device 20C is shown in FIG. 26A. FIG. 26A is a top view of semiconductor device 20D. FIG. 26B shows an equivalent circuit diagram of semiconductor device 20D. FIG. 26C shows a cross-sectional view of the cut surface taken along dashed dotted line A3-A4 in FIG. 26A. For a cross-sectional view of the cut surface taken along dashed dotted line B1-B2 in FIG. 26A, refer to FIG. 1C.

[0301] The semiconductor device 20D includes a transistor 100, a capacitor 150A, an insulating layer 110, an insulating layer 210, and an insulating layer 109.

[0302] The above description of the transistor 100 can be referred to. The capacitor 150A includes a conductive layer 112a, an insulating layer 106 over the conductive layer 112a, and a conductive layer 104C over the insulating layer 106. The conductive layer 112a, the insulating layer 106, and the conductive layer 104C overlap with each other. The conductive layer 112a and the conductive layer 104C function as a pair of electrodes of the capacitor 150A, and the insulating layer 106 sandwiched between the pair of electrodes functions as a dielectric of the capacitor 150A.

[0303] The conductive layer 112a functions as one of a source electrode and a drain electrode of the transistor 100 and also functions as one of a pair of electrodes of the capacitor 150A. By sharing the conductive layer 112a between the transistor 100 and the capacitor 150A, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be provided.

[0304] One of the source and the drain of the transistor 100 is connected to one of a pair of electrodes of the capacitor 150A. Note that although the transistor 100 is an n-channel transistor in FIG. 26B, one embodiment of the present invention is not limited to this. The transistor 100 can also be a p-channel transistor.

[0305] 25A to 26C show the configuration in which the source or drain of the transistor 100 is connected to a capacitor, the connection between the transistor and the capacitor is not limited to this. Furthermore, the capacitor connected to the transistor 100 is not limited to the configuration of the capacitor 150 or the capacitor 150A.

[0306] The configuration of the capacitance element shown here can also be applied to other configuration examples.

[0307] 27A illustrates an equivalent circuit diagram of a semiconductor device 30 according to one embodiment of the present invention. The semiconductor device 30 includes transistors 100_1 to 100_p (p is an integer of 2 or greater). The transistors 100_1 to 100_p are connected in series and share a gate. The semiconductor device 30 can be regarded as a single transistor.

[0308] 27A illustrates the transistors 100_1 to 100_p as n-channel transistors, one embodiment of the present invention is not limited to this. The transistors 100_1 to 100_p can also be p-channel transistors.

[0309] A specific description will be given taking as an example the case where the number of transistors connected in series (p) is 4. FIG. 27B shows an equivalent circuit diagram of a semiconductor device 30 which is one embodiment of the present invention. FIG. 28A shows a top view of the semiconductor device 30. FIG. 28B shows a cross-sectional view of the cut surface taken along dashed dotted line A3-A4 in FIG. 28A. FIG. 29A shows a perspective view of the semiconductor device 30. FIG. 29B shows a perspective view in which the conductive layer 104 and the insulating layer 106 are omitted from FIG. 29A.

[0310] The semiconductor device 30 includes transistors 100_1 to 100_4. The structure of the transistor 100 or the transistor 200 described above can be applied to each of the transistors 100_1 to 100_4.

[0311] 28A and other figures show a configuration in which the transistors 100_1 to 100_4 are arranged in one row and four columns, the arrangement of the transistors is not particularly limited. For example, the transistors 100_1 to 100_4 may be arranged in two rows and two columns.

[0312] The transistor 100_1 includes a conductive layer 104, an insulating layer 106, a layer 108_1, and a conductive layer 112a. The layer 108_1 includes a region 108P_1 in contact with the insulating layer 110d. The conductive layer 112a functions as one of a source electrode and a drain electrode of the transistor 100_1, and the region 108P_1 functions as the other electrode. For the region 108P_1, refer to the description of the region 108P and the region 208P.

[0313] The transistor 100_2 includes a conductive layer 104, an insulating layer 106, a layer 108_1, and a conductive layer 112b. The layer 108_1 is shared by the transistors 100_1 and 100_2. The region 108P_1 is shared by the transistors 100_1 and 100_2. The conductive layer 112b functions as one of a source electrode and a drain electrode of the transistor 100_2, and the region 108P_1 functions as the other. That is, the other of the source electrode and the drain electrode of the transistor 100_1 is connected to the other of the source electrode and the drain electrode of the transistor 100_2.

[0314] The transistor 100_3 includes a conductive layer 104, an insulating layer 106, a layer 108_2, and a conductive layer 112b. The layer 108_2 includes a region 108P_2 in contact with the insulating layer 210d. The conductive layer 112b functions as one of a source electrode and a drain electrode of the transistor 100_3, and the region 108P_2 functions as the other. The conductive layer 112b is shared by the transistors 100_2 and 100_3. That is, one of a source electrode and a drain electrode of the transistor 100_2 is connected to one of a source electrode and a drain electrode of the transistor 100_3. For the region 108P_2, refer to the descriptions of the regions 108P and 208P.

[0315] The transistor 100_4 includes a conductive layer 104, an insulating layer 106, a layer 108_2, and a conductive layer 112c. The layer 108_2 is shared by the transistors 100_3 and 100_4. The region 108P_2 is shared by the transistors 100_3 and 100_4. The conductive layer 112c functions as one of a source electrode and a drain electrode of the transistor 100_4, and the region 108P_2 functions as the other. That is, the other of the source electrode and the drain electrode of the transistor 100_3 is connected to the other of the source electrode and the drain electrode of the transistor 100_4.

[0316] The conductive layers 112a, 112b, and 112c are provided over the insulating layer 109. The conductive layers 112a, 112b, and 112c can be formed in the same process. For the conductive layers 112b and 112c, the description of the conductive layer 112a can be referred to.

[0317] The insulating layer 110 is provided over the conductive layers 112a and 112b, and the insulating layer 210 is provided over the conductive layers 112b and 112c. The above description can be referred to for the insulating layer 110 and the insulating layer 210.

[0318] The insulating layer 110 has an end portion in contact with the top surface of the conductive layer 112a and an end portion in contact with the top surface of the conductive layer 112b. The insulating layer 210 has an end portion in contact with the top surface of the conductive layer 112b and an end portion in contact with the top surface of the conductive layer 112c.

[0319] A layer 108_1 is provided over the conductive layer 112a, the conductive layer 112b, and the insulating layer 110. The layer 108_1 has regions in contact with the top surface of the conductive layer 112a, the top surface of the conductive layer 112b, and the top surface and side surfaces of the insulating layer 110.

[0320] The layer 108_2 is provided over the conductive layer 112b, the conductive layer 112c, and the insulating layer 210. The layer 108_2 has regions in contact with the top surface of the conductive layer 112b, the top surface of the conductive layer 112c, and the top surface and side surfaces of the insulating layer 210.

[0321] The layers 108_1 and 108_2 can be formed in the same process. The description of the layers 108 and 208 can be referred to for the layers 108_1 and 108_2.

[0322] An insulating layer 106 is provided over the layer 108_1 and the layer 108_2. The insulating layer 106 functions as a gate insulating layer for the transistors 100_1 to 100_4. The insulating layer 106 has regions in contact with the top surface and side surfaces of the layer 108_1, the top surface and side surfaces of the layer 108_2, the top surface of the conductive layer 112a, the top surface of the conductive layer 112b, the top surface of the conductive layer 112c, the top surface and side surfaces of the insulating layer 110, and the top surface and side surfaces of the insulating layer 210.

[0323] A conductive layer 104 is provided over the insulating layer 106. The conductive layer 104 functions as a gate electrode of the transistors 100_1 to 100_4. The conductive layer 104 has a region facing a side surface of the insulating layer 110 with the insulating layer 106 and the layer 108_1 interposed therebetween. The conductive layer 104 also has a region facing a side surface of the insulating layer 210 with the insulating layer 106 and the layer 108_2 interposed therebetween.

[0324] When the semiconductor device 30 is regarded as a single transistor, the channel length of the transistor is the sum of the channel lengths of the transistors 100_1 to 100_4. For example, if the channel length of each of the transistors 100_1 to 100_4 is L100, the semiconductor device 30 can be regarded as a transistor having a channel length of "L100×4" (see FIG. 16A). The semiconductor device 30, which is configured with p transistors, can be regarded as a transistor having a channel length of "L100×p". Note that the semiconductor device 30 can be regarded as a transistor having a channel width of W100 (see FIG. 16B). By connecting multiple transistors in series, the channel length is increased, thereby improving saturation. Furthermore, the channel lengths can be varied by adjusting the number (p) of transistors connected in series. The number (p) of transistors connected in series can be determined so as to achieve a desired saturation.

[0325] In this specification and the like, a small change in current in the saturation region in the Id-Vd characteristics of a transistor may be expressed as "high saturation."

[0326] Although FIG. 28A and the like illustrate a structure in which the layer 108 is separated into layers 108_1 and 108_2 in the transistors 100_1 to 100_4, one embodiment of the present invention is not limited to this.

[0327] 30A and 30B , the transistors 100_1 to 100_4 can share the layer 108_1. The layer 108_1 has a region in contact with the top surfaces of the conductive layers 112a, 112b, and 112c, the top and side surfaces of the insulating layer 110, and the top and side surfaces of the insulating layer 210. Sharing the layer 108_1 among the transistors 100_1 to 100_4 eliminates the need for a space between the metal oxide layers of the transistors 100_1 and 100_2 and the metal oxide layers of the transistors 100_3 and 100_4 (see the layers 108_1 and 108_2 in FIGS. 28A and 28B ). Therefore, a semiconductor device with a small occupation area can be obtained.

[0328] Note that the configuration of the semiconductor device 30 can be applied to other configuration examples. For example, in the semiconductor devices 20 to 20D described above, the semiconductor device 30 can be applied to one or both of the transistor 100 and the transistor 200.

[0329] <Configuration Example 2> FIG. 31A shows a top view of a semiconductor device 40 according to one embodiment of the present invention. FIG. 31B shows a cross-sectional view of the section taken along dashed dotted line A3-A4 in FIG. 31A , FIG. 32A shows a cross-sectional view of the section taken along dashed dotted line B1-B2, and FIG. 32B shows a cross-sectional view of the section taken along dashed dotted line B3-B4. FIG. 19B can be referred to for an equivalent circuit diagram of the semiconductor device 40.

[0330] 33A and 33B are perspective views of the semiconductor device 40. Fig. 33B is a perspective view in which the conductive layer 104, the conductive layer 204, and the insulating layer 106 shown in Fig. 33A are omitted.

[0331] The semiconductor device 40 includes a transistor 100, a transistor 200, an insulating layer 110, and an insulating layer 109. The semiconductor device 40 differs mainly from the semiconductor device 20A shown in FIG. 19A etc. in that the insulating layer 110 has a groove (slit).

[0332] The insulating layer 110 has a slit 137 that reaches the conductive layer 112a and the insulating layer 109. As shown in FIG. 31B , the insulating layer 110 is divided by the slit 137, and the insulating layer 110 has a pair of side surfaces (side surface 77 and side surface 77a) that face each other across the slit 137. The side surface 77 includes a region located on the conductive layer 112a and a region located on the insulating layer 109. Similarly, the side surface 77a includes a region located on the conductive layer 112a and a region located on the insulating layer 109. The insulating layer 110 has an end portion 31 and an end portion 31a that contact the upper surface of the conductive layer 112a. On the conductive layer 112a, the lower end of the side surface 77 is the end portion 31, and the lower end of the side surface 77a is the end portion 31a.

[0333] Layer 108 and layer 208 are provided so as to cover a portion of slit 137. Layer 108 has an area in contact with the upper surface of conductive layer 112a and the upper surface and side surface 77 of insulating layer 110. As shown in FIG. 32A , layer 108 has an end 33 in contact with the upper surface of conductive layer 112a and an end 35 in contact with the upper surface of insulating layer 110. Layer 208 has an area in contact with the upper surface of conductive layer 112a and the upper surface and side surface 77a of insulating layer 110. As shown in FIG. 32B , layer 208 has an end 33b in contact with the upper surface of conductive layer 112a and an end 35a in contact with the upper surface of insulating layer 110.

[0334] The insulating layer 106 is provided over the layer 108 and the layer 208, and the conductive layer 104 and the conductive layer 204 are provided over the insulating layer 106. The conductive layer 104 has a region facing the side surface 77 with the insulating layer 106 and the layer 108 interposed therebetween. The conductive layer 204 has a region facing the side surface 77a with the insulating layer 106 and the layer 208 interposed therebetween.

[0335] 31A and the like illustrate a structure in which two transistors (here, the transistor 100 and the transistor 200) are provided in the insulating layer 110; however, one embodiment of the present invention is not limited to this. Three or more transistors can be provided in the insulating layer 110. For example, a plurality of transistors each having a layer 108 in contact with the side surface 77 can be provided. Similarly, a plurality of transistors each having a layer 208 in contact with the side surface 77a can be provided. Alternatively, a transistor can be provided which has a layer 108 or a layer 208 in contact with a side surface of the insulating layer 110 that is different from both the side surface 77 and the side surface 77a.

[0336] By increasing the area where the insulating layer 110 is provided, the amount of oxygen supplied from the insulating layer 110 (for example, the insulating layer 110b) to the layer 108 and the layer 208 can be increased. As a result, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0337] 31A and other drawings show the slit 137 extending in one direction, but this is not a limitation of one aspect of the present invention. The shape of the top surface of the slit 137 is not particularly limited.

[0338] Although FIG. 31A and other figures illustrate a structure in which the insulating layer 110 is divided by the slit 137, one embodiment of the present invention is not limited to this. An example structure different from that of FIG. 31A is shown in FIG. 34A . FIG. 34A is a top view of a semiconductor device 40. For a cross-sectional view of the cut surface taken along dashed dotted line A3-A4 in FIG. 34A , FIG. 31B can be referred to, for a cross-sectional view of the cut surface taken along dashed dotted line B1-B2, FIG. 27B can be referred to, and for a cross-sectional view of the cut surface taken along dashed dotted line B3-B4, FIG. 32B can be referred to. For an equivalent circuit diagram of the semiconductor device 40, FIG. 19B can be referred to. FIG. 34B is a perspective view of the semiconductor device 40 in which the conductive layer 104, the conductive layer 204, and the insulating layer 106 are omitted. As shown in FIGS. 34A and 34B , a structure in which the insulating layer 110 is not divided by the slit 137 is possible. The layer 108 and the layer 208 can be provided on the side surfaces (here, the side surfaces 77 and 77 a ) of the insulating layer 110 formed by the slits 137 .

[0339] The configuration of the insulating layer 110 and the slits 137 shown here can also be applied to other configuration examples.

[0340] <Configuration Example 3> FIG. 35A shows a top view of a semiconductor device 40A according to one embodiment of the present invention. FIG. 35B shows a cross-sectional view of the section taken along dashed dotted line A3-A4 in FIG. 35A , FIG. 36A shows a cross-sectional view of the section taken along dashed dotted line B1-B2, and FIG. 36B shows a cross-sectional view of the section taken along dashed dotted line B3-B4. FIG. 12B can be referred to for an equivalent circuit diagram of the semiconductor device 40A. FIG. 37A shows a perspective view of the semiconductor device 40A. FIG. 37B shows a perspective view in which the conductive layer 104, the conductive layer 204, and the insulating layer 106 are omitted from FIG. 37A .

[0341] The semiconductor device 40A includes a transistor 100A, a transistor 200A, an insulating layer 110, and an insulating layer 109. The semiconductor device 40A differs mainly from the semiconductor device 20 shown in FIG. 12C and other drawings in that the insulating layer 110 has an opening.

[0342] The above description can be referred to for the transistor 100A. The transistor 200A can have a similar structure to that of the transistor 100A. The transistor 200A includes a conductive layer 204, an insulating layer 106, a layer 108, and a conductive layer 212a. The transistors 100A and 200A share the layer 108. The transistors 100A and 200A also share a region 108P.

[0343] The insulating layer 110 has an opening 141 that reaches the conductive layer 112a and an opening 241 that reaches the conductive layer 212a. The above description can be referred to for the opening 141. In other words, the side surface 77a and the top surface of the conductive layer 212a are exposed in the opening 241.

[0344] The layer 108 is provided so as to cover a part of the opening 141 and a part of the opening 241. The layer 108 is also provided so as to cross the opening 141 and the opening 241. The layer 108 has regions in contact with the upper surface of the conductive layer 112a, the upper surface of the conductive layer 112a, and the upper surface, side surface 77, and side surface 77a of the insulating layer 110.

[0345] An insulating layer 106 is provided on the layer 108. A conductive layer 104 and a conductive layer 204 are provided on the insulating layer 106. The layer 108, the insulating layer 106, and the conductive layer 104 each have a region located within the opening 141 and a region located within the opening 241.

[0346] The layer 108 has a region 74 and a region 74a in contact with the side surface 77. The region 74 and the region 74a each function as a channel formation region of the transistor 100A. The conductive layer 104 has a region facing the side surface 77 with the region 74 and the insulating layer 106 interposed therebetween, and also has a region facing the side surface 77 with the region 74a and the insulating layer 106 interposed therebetween.

[0347] The layer 108 has a region 84 and a region 84a in contact with the side surface 77a. The region 84 and the region 84a each function as a channel formation region of the transistor 200A. The conductive layer 204 has a region facing the side surface 77a with the region 84 and the insulating layer 106 interposed therebetween, and a region facing the side surface 77a with the region 84a and the insulating layer 106 interposed therebetween.

[0348] The channel lengths and channel widths of the transistor 100A and the transistor 200A will be described with reference to FIGS. 38A and 38B.

[0349] 38B, the channel length L100 of the transistor 100A and the channel length L200 of the transistor 200A are indicated by dashed double-headed arrows. The channel length L100 can be explained by referring to the above description, and therefore a detailed explanation will be omitted. The channel length L200 can be explained by referring to the description of the channel length L100.

[0350] 38A , in the transistor 100A, a width W1 of the region where the layer 108 and the conductive layer 104 overlap in the region 74 and a width W2 of the region where the layer 108 and the conductive layer 104 overlap in the region 74a are indicated by double-dot-dashed arrows in a direction perpendicular to the channel length direction. The channel width W100 of the transistor 100A is the sum of the width W1 and the width W2.

[0351] 38A , in the transistor 200A, the width W3 of the region where the layer 208 and the conductive layer 204 overlap in the region 84 and the width W4 of the region where the layer 208 and the conductive layer 204 overlap in the direction perpendicular to the channel length direction are indicated by double-arrowed dashed lines. The channel width W200 of the transistor 200A is the sum of the width W3 and the width W4. Note that although the widths W1 to W4 are the same in FIG. 38A and other drawings, one embodiment of the present invention is not limited to this. One or more of the widths W1 to W4 may be different.

[0352] 38A and other figures illustrate a configuration in which the top surface shapes of the openings 141 and 241 are rectangular with rounded corners, but one embodiment of the present invention is not limited thereto. The top surface shapes of the openings 141 and 241 are not limited thereto and may be, for example, a circle, an ellipse, a triangle, a square (including a rectangle, a diamond, and a square), a polygon such as a pentagon, or a shape with rounded corners of these polygons. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees). By forming the top surface shapes of the openings 141 and 241 as circular, the processing accuracy when forming the openings 141 and 241 can be improved, and the openings 141 and 241 can be formed with a fine size. In this specification and other documents, a circle is not limited to a perfect circle. 38A and the like show a structure in which the top surface shape of the opening 141 is the same as the top surface shape of the opening 241, but this is not a limitation of one embodiment of the present invention. The top surface shape of the opening 141 may be different from the top surface shape of the opening 241.

[0353] The opening 141 is provided only in the layer 108 and a region near it, and the opening 241 is provided only in the layer 208 and a region near it, and the insulating layer 110 is provided in the remaining region. Therefore, the area of ​​the region where the insulating layer 110 is provided can be increased, and unevenness caused by the region where the insulating layer 110 is provided and the region where the insulating layer 110 is not provided can be reduced. This can improve the coverage of the layers provided over the transistor 100A, the transistor 200A, and the insulating layer 110, and can suppress defects such as discontinuities or voids in the layers.

[0354] The configurations of the openings 141 and 241 shown here can also be applied to other configuration examples.

[0355] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0356] 39A to 42C , a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Note that with regard to materials and formation methods of elements, descriptions of parts similar to those described in Embodiment 2 may be omitted.

[0357] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and atomic layer deposition (ALD). CVD methods include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD).

[0358] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet film formation methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0359] When processing a thin film that constitutes a semiconductor device, a lithography method or the like can be used. Alternatively, the thin film can be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film can be directly formed by a film formation method using a shielding mask such as a metal mask.

[0360] There are two typical lithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0361] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other examples include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0362] The thin film can be etched by one or more of dry etching, wet etching, and sandblasting.

[0363] 12A to 16B will be described with reference to Fig. 39A to Fig. 41. Fig. 39A to Fig. 41 show cross-sectional views taken along dashed line A3-A4 in Fig. 12A.

[0364] First, the insulating layer 109 is formed over the substrate 102. The insulating layer 109 can be formed by a sputtering method or a PECVD method.

[0365] Next, a conductive film to be the conductive layer 112a and the conductive layer 212a is formed over the insulating layer 109 and processed to form the conductive layer 112a and the conductive layer 212a (FIG. 39A). The conductive film can be preferably formed by a sputtering method.

[0366] Subsequently, an insulating film 110af that will become the insulating layer 110a and an insulating film 110bf that will become the insulating layer 110b are formed on the conductive layer 112a and the conductive layer 212a (FIG. 39B).

[0367] The insulating films 110af and 110bf can be preferably formed by sputtering or PECVD. After forming the insulating film 110af, it is preferable to form the insulating film 110bf without exposing the surface of the insulating film 110af to the atmosphere. This can prevent impurities from the atmosphere from adhering to the surface of the insulating film 110af. Examples of such impurities include water and organic substances. For example, after forming the insulating film 110af, it is preferable to form the insulating film 110bf consecutively using the same apparatus.

[0368] The substrate temperature during deposition of the insulating films 110af and 110bf is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, further preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature during deposition of the insulating films 110af and 110bf within the above-described range, the amount of impurities (e.g., water and hydrogen) released from the insulating films 110af and 110bf can be reduced, and diffusion of the impurities into the layer 108 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0369] Note that, since the insulating films 110af and 110bf are formed before the layer 108, there is no need to worry about oxygen being desorbed from the layer 108 due to heat applied during the formation of the insulating films 110af and 110bf.

[0370] After the insulating films 110af and 110bf are formed, heat treatment is preferably performed. By performing the heat treatment, impurities (for example, water and hydrogen) can be removed from the insulating films 110af and the insulating films 110bf and from their surfaces.

[0371] After the insulating film 110bf is formed, it is preferable to supply oxygen to the insulating film 110bf. By supplying oxygen to the insulating film 110bf (later the insulating layer 110b), oxygen can be later supplied from the insulating layer 110b to the layer 108, thereby reducing oxygen vacancies and V Ｏ H can be reduced. Therefore, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0372] As a method for supplying oxygen, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. For the plasma treatment, an apparatus that converts oxygen gas into plasma by high frequency power can be suitably used. Examples of apparatus that convert gas into plasma by high frequency power include a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus. The plasma treatment is preferably carried out in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N ２ O), nitrogen dioxide (NO ２ It is preferable to perform the plasma treatment in an atmosphere containing one or more of carbon monoxide, carbon dioxide, and / or arsenic. The amount of oxygen supplied can be adjusted by, for example, the power and treatment time in the plasma treatment. Fig. 39C schematically shows with arrows how oxygen is supplied to the insulating film 110bf.

[0373] After the insulating film 110bf is formed, nitrogen is preferably supplied to the insulating film 110bf. The nitrogen supply method can be referred to the description of the oxygen supply method described above. As a nitrogen supply method, plasma treatment in an atmosphere containing nitrogen can be suitably used. For example, nitrogen, dinitrogen monoxide (N ２ O), and nitrogen dioxide (NO ２ The amount of nitrogen supplied can be adjusted by, for example, the power and processing time in the plasma processing.

[0374] In the insulating layer (here, the insulating film 110bf or the later insulating layer 110b), nitrogen reacts with oxygen to form nitrogen oxide (NO Ｘ , X is a real number greater than 0). ２ O, NO and NO ２ In the insulating layer, the nitrogen oxide forms a level, which is located within the band gap of the metal oxide. ２ The transition level where the charge of the indium oxide changes between the 0 state and the -1 state is located within the band gap of the indium oxide. ２When the ions diffuse to the interface between the insulating layer and the channel formation region or in the vicinity of the interface, the level traps electrons. As a result, negative charges (also referred to as negative fixed charges) are formed at the interface between the insulating layer and the channel formation region or in the vicinity of the interface, which allows the threshold voltage of the transistor to be increased in the positive direction. This allows the transistor to be a normally-off transistor, resulting in a semiconductor device with low power consumption.

[0375] Increasing the amount of nitrogen oxide can increase the threshold voltage to the positive side. However, if the amount of nitrogen oxide is too large, the threshold voltage may fluctuate greatly when a positive potential (positive bias) is applied to the gate of the transistor, which may result in reduced reliability. Therefore, it is preferable to use a nitrogen oxide amount within a range that does not affect reliability.

[0376] The amount of nitrogen oxides can be evaluated, for example, by measuring the amount of desorption in thermal desorption spectrometry (TDS) or the amount of electron spin in electron spin resonance (ESR). In TDS, NO (mass-to-charge ratio (m / z) = 30), N ２ O (m / z=44), and NO ２ The amount of NO (m / z = 46) desorbed can be evaluated. ２ In some cases, it may be difficult to quantify the amount of NO and N released. ２ By evaluating the amount of O released, ２ In ESR, the amount of NO can be evaluated. ２ Since the N atom has 7 electrons and the O atom has 8 electrons, the ESR signal derived from NO ２ The molecule has an open-shell structure. Therefore, the neutral NO ２ Since the molecule has a lone electron, it can be measured by ESR. １４ Since N has a nuclear spin of 1, １４The peak of the ESR signal related to N is split into three. At this time, the split width of the ESR signal is the hyperfine coupling constant.

[0377] The order of the treatment for supplying oxygen and the treatment for supplying nitrogen is not particularly limited. Oxygen can be supplied after nitrogen is supplied. Nitrogen can also be supplied after oxygen is supplied. Alternatively, oxygen and nitrogen can be supplied in the same treatment. For example, oxygen and nitrogen can be supplied by performing a plasma treatment in an atmosphere containing nitrogen and oxygen. For example, dinitrogen monoxide (N ２ By carrying out a plasma treatment using nitrogen oxides, nitrogen oxides can be efficiently produced, which is preferable.

[0378] After the insulating film 110bf is formed, it is preferable to perform the plasma treatment without exposing the surface of the insulating film 110bf to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can improve productivity. Specifically, after the insulating film 110bf is formed in the PECVD apparatus, it is preferable to perform the plasma treatment in the PECVD apparatus without exposing the surface of the insulating film 110bf to the atmosphere. ２ O plasma treatment can be performed.

[0379] Next, it is preferable to form the film 130 on the insulating film 110bf (FIG. 39D). The film 130 can be formed by a sputtering method. By forming the film 130 in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf.

[0380] The conductivity of the film 130 does not matter. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 130. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used as the film 130.

[0381] The film 130 is preferably made of an oxide material containing one or more of the same elements as those of the layer 108. In particular, it is preferably made of a metal oxide that can be used for the layer 108.

[0382] During the deposition of the film 130, the amount of oxygen supplied to the insulating film 110bf can be increased by increasing the oxygen flow rate of the deposition gas introduced into the processing chamber of the deposition apparatus or the oxygen partial pressure in the processing chamber. The oxygen flow rate or oxygen partial pressure is, for example, preferably 50% to 100%, more preferably 60% to 100%, even more preferably 70% to 100%, still more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate to 100% and the oxygen partial pressure as close to 100% as possible.

[0383] By forming the film 130 by sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf during the formation of the film 130, and oxygen desorption from the insulating film 110bf can be prevented. As a result, a large amount of oxygen can be trapped in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the layer 108 by a subsequent heat treatment. As a result, oxygen vacancies and V in the layer 108 can be reduced. Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0384] Heat treatment is preferably performed after the film 130 is formed. By performing heat treatment after the film 130 is formed, oxygen can be effectively supplied from the film 130 to the insulating film 110bf.

[0385] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, and further preferably 350° C. or higher and 400° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) can be used. Note that the content of hydrogen, water, and the like in the atmosphere is preferably as low as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere containing as little hydrogen, water, and the like as possible can prevent hydrogen, water, and the like from being taken into the insulating films 110af and 110bf as much as possible. The heat treatment can be performed using an oven, a rapid thermal annealing (RTA) device, etc. By using an RTA device, the heat treatment time can be shortened.

[0386] After the film 130 is formed or after the heat treatment, oxygen can be further supplied to the insulating film 110bf through the film 130. Oxygen can be supplied by, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment. The above description of the plasma treatment can be referred to, and therefore, detailed description thereof will be omitted.

[0387] Next, the film 130 is removed ( FIG. 39E ). There is no particular limitation on the method for removing the film 130, but wet etching is preferably used. By using wet etching, etching of the insulating film 110bf can be suppressed when removing the film 130. This prevents the thickness of the insulating film 110bf from becoming thin, and allows the thickness of the insulating layer 110b to be uniform.

[0388] The process of supplying oxygen to the insulating film 110bf is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions can be supplied to the insulating film 110bf by ion doping, ion implantation, or plasma treatment. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 110bf, and then oxygen can be supplied to the insulating film 110bf through the film. The film is preferably removed after oxygen is supplied. The film that suppresses oxygen desorption can be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten.

[0389] Next, an insulating film 110cf to be the insulating layer 110c and an insulating film 110df to be the insulating layer 110d are formed on the insulating film 110bf (FIG. 40A). For the formation of the insulating film 110cf, the description regarding the formation of the insulating film 110af can be referred to.

[0390] When an oxide or oxynitride is used for the insulating layer 110c, the insulating film 110cf can be formed in an oxygen-containing atmosphere to supply oxygen to the insulating film 110bf. The insulating film 110cf can be preferably formed by sputtering. For example, the insulating film 110cf can be formed by sputtering using an aluminum target in an oxygen-containing atmosphere. When forming the insulating film 110cf, the amount of oxygen supplied to the insulating film 110bf can be increased by increasing the oxygen flow rate of the deposition gas introduced into the treatment chamber of the deposition apparatus or the oxygen partial pressure in the treatment chamber. The oxygen flow rate or oxygen partial pressure is preferably, for example, 50% to 100%, more preferably 60% to 100%, even more preferably 70% to 100%, even more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate ratio to 100% and the oxygen partial pressure to as close to 100% as possible.

[0391] By forming the insulating film 110cf in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf during the formation of the insulating film 110cf, and oxygen desorption from the insulating film 110bf can be prevented. As a result, a large amount of oxygen can be trapped in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the layer 108 by a subsequent heat treatment. As a result, oxygen vacancies and V in the layer 108 can be reduced. Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0392] Heat treatment can also be performed after the insulating film 110cf is formed. By performing heat treatment after the insulating film 110cf is formed, oxygen can be effectively supplied from the insulating film 110cf to the insulating film 110bf.

[0393] The insulating film 110df is preferably formed using a gas containing an impurity. When hydrogen is used as the impurity element, the insulating layer 110d is preferably formed using a gas containing hydrogen. When a silicon nitride film is formed as the insulating film 110df by a PECVD method, silane (SiH ４ ), nitrogen (N ２ ) and ammonia (NH ３ ) can be used. The ammonia flow rate ratio when forming the insulating film 110df is preferably higher than the ammonia flow rate ratio when forming the insulating film 110cf. In this case, by increasing the ammonia flow rate ratio, the hydrogen content in the insulating film 110df (later insulating layer 110d) can be increased, and the amount of hydrogen released by heat applied to the insulating layer 110d can be increased.

[0394] Subsequently, the insulating films 110df, 110cf, 110bf, and 110af are processed to form the insulating layer 110 including the insulating layers 110d, 110c, 110b, and 110a (FIG. 40B). The insulating layer 110 can be preferably formed by, for example, dry etching.

[0395] Next, a metal oxide film 108f to be the layer 108 is formed so as to cover the conductive layer 112a, the conductive layer 212a, and the insulating layer 110 ( FIG. 40C ). The metal oxide film 108f is provided in contact with the upper surfaces of the conductive layers 112a and 212a, and the upper and side surfaces of the insulating layer 110.

[0396] The metal oxide film 108f is preferably formed by sputtering using a metal oxide target. Alternatively, the metal oxide film 108f is preferably formed by ALD. By using the ALD method, a metal oxide film can be formed with high coverage on the side surfaces of the insulating layer 110. Furthermore, the ALD method makes it easy to control the film formation rate, and therefore allows thin films to be formed with high yield. Therefore, the ALD method is particularly suitable when the metal oxide film 108f is thin. Alternatively, the CVD method can be used to form the metal oxide film 108f.

[0397] The metal oxide film 108f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 108f is preferably a high-purity film in which impurities including hydrogen are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 108f.

[0398] Oxygen gas is preferably used when the metal oxide film 108f is formed. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 110. For example, when an oxide or an oxynitride is used for the insulating layer 110b, oxygen can be suitably supplied to the insulating layer 110b.

[0399] By supplying oxygen to the insulating layer 110b, oxygen is supplied to the layer 108 in a later process, and oxygen vacancies and V Ｏ H can be reduced.

[0400] When forming the metal oxide film 108f, a mixture of oxygen gas and an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) can be used. Note that the higher the oxygen flow rate ratio or oxygen partial pressure of the deposition gas when forming the metal oxide film, the higher the crystallinity of the metal oxide film, and thus a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow rate ratio or oxygen partial pressure, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film, and thus a transistor with a large on-state current can be realized.

[0401] Here, if the oxygen flow rate ratio or oxygen partial pressure is high, the metal oxide film may become polycrystalline. In the case of a polycrystalline metal oxide film, the grain boundaries may become recombination centers, trapping carriers and reducing the on-state current of the transistor. Therefore, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure so that the metal oxide film 108f does not become polycrystalline. Because the ease with which a metal oxide film becomes polycrystalline varies depending on the composition of the metal oxide film, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure depending on the composition of the metal oxide film 108f. However, one embodiment of the present invention is not limited thereto, and a polycrystalline metal oxide can be used. When the grain boundaries of a polycrystalline metal oxide film do not affect the transistor characteristics, a transistor using a polycrystalline metal oxide can have higher reliability than a transistor using a metal oxide with low crystallinity.

[0402] The higher the substrate temperature during deposition of the metal oxide film, the higher the crystallinity and density of the metal oxide film, which allows for a highly reliable transistor. On the other hand, the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film, which allows for a high on-state current of the transistor.

[0403] The substrate temperature during deposition of the metal oxide film 108f is preferably from room temperature (e.g., 25° C.) to 250° C., more preferably from room temperature to 200° C., and even more preferably from room temperature to 140° C. For example, setting the substrate temperature from room temperature to 140° C. is preferable because it increases productivity. Furthermore, by depositing the metal oxide film at room temperature or without heating the substrate, the crystallinity can be reduced.

[0404] Note that if the substrate temperature is too high, the metal oxide film may have a polycrystalline structure. It is preferable to set the substrate temperature depending on the composition of the material used for the metal oxide film 108f.

[0405] When the ALD method is used, it is preferable to use a film formation method such as a thermal ALD method or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it exhibits extremely high coverage. The PEALD method is preferable because it not only exhibits high coverage but also allows low-temperature film formation.

[0406] The metal oxide film can be formed by, for example, the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0407] For example, when forming an In—Ga—Zn oxide film, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0408] Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amido]-indium.

[0409] Gallium-containing precursors include, for example, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0410] Precursors containing aluminum include, for example, aluminum chloride and trimethylaluminum.

[0411] Tin-containing precursors include, for example, tin(IV) chloride and tetrakis(dimethylamido)tin.

[0412] Precursors containing zinc include, for example, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0413] Oxidizing agents include, for example, ozone, oxygen, and water.

[0414] The composition of the resulting film can be controlled by adjusting one or more of the types of source gases, the flow rate ratio of the source gases, the time for which the source gases are flowed, and the order in which the source gases are flowed. By adjusting these, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these, it is possible to form a metal oxide film 108f whose composition changes continuously.

[0415] Before forming the metal oxide film 108f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen into the insulating layer 110. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, dinitrogen monoxide (N ２By performing plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO), oxygen can be supplied to the insulating layer 110. By performing plasma treatment containing nitrous oxide gas, oxygen can be supplied while organic substances on the surface of the insulating layer 110 are suitably removed. After such treatment, it is preferable to form the metal oxide film 108f continuously without exposing the surface of the insulating layer 110 to the air.

[0416] When the layer 108 has a stacked structure, it is preferable to deposit a metal oxide film first and then deposit a subsequent metal oxide film without exposing the surface of the first metal oxide film to the air.

[0417] When the layer 108 has a stacked structure, all layers constituting the layer 108 can be deposited by the same method (e.g., sputtering or ALD). Alternatively, different deposition methods can be used for different layers. For example, the first metal oxide layer can be deposited by sputtering, and the second metal oxide layer can be deposited by ALD.

[0418] Subsequently, the metal oxide film 108f is processed into an island shape to form the layer 108 (FIG. 40D).

[0419] The layer 108 can be preferably formed by wet etching. At this time, parts of the conductive layer 112a, the conductive layer 212a, the insulating layer 110, and the insulating layer 109 that do not overlap with the layer 108 may be etched and thinned. For example, the insulating layer 110d of the insulating layer 110 may be removed by etching, exposing the surface of the insulating layer 110c. Note that, in etching the metal oxide film 108f, using a material with a high selectivity for the insulating layer 110d can prevent the insulating layer 110d from becoming thin.

[0420] Heat treatment is preferably performed after the metal oxide film 108f is formed or after the metal oxide film 108f is processed into the layer 108. The heat treatment can remove hydrogen and water contained in the metal oxide film 108f or the layer 108 or adsorbed on the surface. Furthermore, the heat treatment may improve the film quality of the metal oxide film 108f or the layer 108 (for example, reduce defects or improve crystallinity).

[0421] By the heat treatment, oxygen can also be supplied from the insulating layer 110b to the metal oxide film 108f or the layer 108. In this case, it is preferable to perform the heat treatment before processing into the layer 108. The above description can be referred to for the heat treatment, and therefore detailed description thereof will be omitted.

[0422] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, a process in which heat is applied in a later step (e.g., a film formation step) may also serve as this heat treatment.

[0423] Subsequently, the insulating layer 106 is formed to cover the layer 108 and the insulating layer 110 (FIG. 41). The insulating layer 106 can be formed by, for example, PECVD, sputtering, or ALD.

[0424] When a metal oxide is used for the layer 108, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion. When the insulating layer 106 functions as a barrier film, oxygen is suppressed from being released from the layer 108, and oxygen vacancies (V Ｏ In addition, oxygen contained in the layer 108 is prevented from diffusing into the conductive layer 104 and the conductive layer 204 through the insulating layer 106, and thus the conductive layer 104 and the conductive layer 204 can be prevented from being oxidized. As a result, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0425] By increasing the temperature during deposition of the insulating layer 106 that functions as a gate insulating layer, the insulating layer can have fewer defects. However, if the temperature during deposition of the insulating layer 106 is high, oxygen is released from the layer 108, causing oxygen vacancies and V in the layer 108. ＯH may increase. The substrate temperature during deposition of the insulating layer 106 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during deposition of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced and oxygen desorption from the layer 108 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0426] It is preferable to perform plasma treatment on the surface of the layer 108 before forming the insulating layer 106. The plasma treatment can reduce impurities such as water adsorbed to the surface of the layer 108. Therefore, impurities at the interface between the layer 108 and the insulating layer 106 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable when the surface of the layer 108 is exposed to the air between the formation of the layer 108 and the formation of the insulating layer 106. The plasma treatment can be performed in an atmosphere containing, for example, oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. It is also preferable to perform the plasma treatment and the formation of the insulating layer 106 successively without exposure to the air.

[0427] Subsequently, the conductive layer 104 is formed on the insulating layer 106 (FIG. 12C). The conductive film that becomes the conductive layer 104 can be preferably formed by, for example, a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method.

[0428] Through the above steps, the semiconductor device 20 of one embodiment of the present invention can be manufactured.

[0429] <Manufacturing Method Example 2> An example of a manufacturing method of the semiconductor device 40A shown in Figures 35A to 38B will be described. Figures 42A to 42C show cross-sectional views taken along dashed line A3-A4 shown in Figure 35A.

[0430] First, the process up to the formation of the insulating film 110df is performed in the same manner as in Manufacturing Method Example 1. For the process up to the formation of the insulating film 110df, the description of FIGS.

[0431] Next, portions of the insulating films 110df, 110cf, 110bf, and 110af are removed to form an opening 141 reaching the conductive layer 112a and an opening 241 reaching the conductive layer 212a ( FIG. 42A ). This forms the insulating layer 110 including the insulating layers 110d, 110c, 110b, and 110a. The insulating layer 110 can be formed by, for example, dry etching.

[0432] Subsequently, a metal oxide film 108f that will become the layer 108 is formed so as to cover the openings 141 and 241 (FIG. 42B). The above description can be referred to for the formation of the metal oxide film 108f.

[0433] Subsequently, the metal oxide film 108f is processed into an island shape to form the layer 108 (FIG. 42C). For the formation of the layer 108 and subsequent steps, the description in <Manufacturing Method Example 1> can be referred to.

[0434] Through the above steps, the semiconductor device 40A of one embodiment of the present invention can be manufactured.

[0435] Embodiment 4 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0436] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used as a display unit for electronic devices having relatively large screens, such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0437] The display device of the present embodiment can be a high-definition display device, and can therefore be used, for example, as a display unit for a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit for a wearable device that can be worn on the head, such as a head-mounted display (HMD) for VR, or a glasses-type AR device.

[0438] The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device include a module in which a connector such as a flexible printed circuit (hereinafter referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0439] The display device of this embodiment may have a function as a touch panel. For example, various detection elements (also referred to as sensor elements) that can detect the proximity or contact of a detection target such as a finger can be applied to the display device.

[0440] Examples of sensor types include a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type.

[0441] The capacitance type includes, for example, a surface capacitance type and a projected capacitance type. The projected capacitance type includes, for example, a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferred because it enables simultaneous multi-point detection.

[0442] Examples of touch panels include out-cell, on-cell, and in-cell types. Note that an in-cell touch panel is a type in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element and an opposing substrate.

[0443] <Display Device 50A> FIG. 43 shows a perspective view of the display device 50A.

[0444] The display device 50A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 43, the substrate 152 is indicated by a dashed line.

[0445] The display device 50A has a display portion 162, a connection portion 140, a circuit portion 164, a conductive layer 165, etc. Fig. 43 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Fig. 43 can also be said to be a display module having the display device 50A, an IC, and an FPC.

[0446] The connection portion 140 is provided on the outside of the display portion 162. The connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140. FIG. 43 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion 162. The connection portion 140 connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.

[0447] The circuit portion 164 includes, for example, a scan line driver circuit (also referred to as a gate driver). Alternatively, the circuit portion 164 may include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0448] The conductive layer 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164. The signals and power are input to the conductive layer 165 from the outside through the FPC 172 or are input to the conductive layer 165 from the IC 173.

[0449] 43 shows an example in which an IC 173 is provided on a substrate 151 by a COG method. The IC 173 may be, for example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit. The display device 50A and the display module may be configured without an IC. The IC may also be mounted on an FPC by a COF method or the like.

[0450] The semiconductor device of one embodiment of the present invention can be applied to, for example, one or both of the display portion 162 and the circuit portion 164 of the display device 50A. An oxide semiconductor (OS) can be suitably used for a channel formation region of a transistor included in the display device. By using an OS transistor, the display device can have low power consumption. Furthermore, the semiconductor device of one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all of the transistors included in the display device can be OS transistors. By using OS transistors for all of the transistors included in the display device in this manner, an effect of reducing manufacturing costs can be obtained.

[0451] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-resolution display device. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, resulting in a display device with a narrow frame. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0452] The display section 162 is an area in the display device 50A that displays an image, and has a plurality of periodically arranged pixels 201. Fig. 43 shows an enlarged view of one pixel 201.

[0453] The pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied, such as a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0454] 43 includes a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light. Note that the number of sub-pixels included in one pixel is not particularly limited.

[0455] Each of the sub-pixels 11R, 11G, and 11B includes a display element and a circuit that controls the driving of the display element.

[0456] Various elements can be used as the display element, including, for example, a liquid crystal element and a light-emitting element. Other examples include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements that employ a microcapsule method, an electrophoresis method, an electrowetting method, or an electronic liquid powder (registered trademark) method, etc. Furthermore, a QLED (Quantum-dot LED) that uses a light source and color conversion technology using quantum dot materials may also be used.

[0457] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0458] Examples of modes that can be used in display devices using liquid crystal elements include vertical alignment (VA) mode, Fringe Field Switching (FFS) mode, In-Plane-Switching (IPS) mode, Twisted Nematic (TN) mode, Axially Symmetric Aligned Micro-cell (ASM) mode, Optically Compensated Birefringence (OCB) mode, Ferroelectric Liquid Crystal (FLC) mode, Anti-Ferroelectric Liquid Crystal (AFLC) mode, and Electrically Compensated Birefringence (ECB) mode. Examples of the VA mode include a Multi-Domain Vertical Alignment (MVA) mode, a Patterned Vertical Alignment (PVA) mode, and an Advanced Super View (ASV) mode.

[0459] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, polymer liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, and the like, depending on the conditions. Furthermore, either positive-type or negative-type liquid crystals may be used as the liquid crystal material, and the type can be selected depending on the mode or design to be applied.

[0460] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), semiconductor lasers, etc. Examples of the LED that can be used include mini LEDs and micro LEDs.

[0461] Examples of light-emitting substances that the light-emitting element has include fluorescent substances (fluorescent materials), phosphorescent substances (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF materials), and inorganic compounds (quantum dot materials, etc.).

[0462] The light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light-emitting element with a microcavity structure.

[0463] One of a pair of electrodes included in the light-emitting element functions as an anode, and the other electrode functions as a cathode.

[0464] Note that the display device of one embodiment of the present invention may be any of a top-emission type that emits light in a direction opposite to a substrate on which a light-emitting element is formed, a bottom-emission type that emits light toward a substrate on which a light-emitting element is formed, and a dual-emission type that emits light to both sides.

[0465] Figure 44A shows an example of a cross section of the display device 50A when a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end portion are cut away.

[0466] 44A includes transistors 205D, 205R, 205G, and 205B, light-emitting elements 130R, 130G, and 130B between a substrate 151 and a substrate 152. The light-emitting element 130R is a display element included in the sub-pixel 11R that emits red light, the light-emitting element 130G is a display element included in the sub-pixel 11G that emits green light, and the light-emitting element 130B is a display element included in the sub-pixel 11B that emits blue light.

[0467] The display device 50A employs an SBS structure, which allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in the selection of materials and configurations and facilitating improvements in brightness and reliability.

[0468] The display device 50A is a top emission type, which allows transistors and the like to be arranged overlapping the light emitting region of the light emitting element, thereby enabling a higher pixel aperture ratio than a bottom emission type.

[0469] The transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B are all formed over a substrate 151. These transistors can be manufactured in the same process. Note that the transistors 205D, the transistor 205R, the transistor 205G, and the transistor 205B may have different structures.

[0470] In this embodiment, an example in which OS transistors are used as the transistors 205D, 205R, 205G, and 205B will be described. The transistors according to one embodiment of the present invention can be used as the transistors 205D, 205R, 205G, and 205B. That is, the display device 50A includes the transistor according to one embodiment of the present invention in both the display portion 162 and the circuit portion 164. By using the transistor according to one embodiment of the present invention in the display portion 162, the pixel size can be reduced, leading to higher resolution. Furthermore, by using the transistor according to one embodiment of the present invention in the circuit portion 164, the area occupied by the circuit portion 164 can be reduced, leading to a narrower frame. The description of the previous embodiment can be referred to for the transistor according to one embodiment of the present invention.

[0471] 44A illustrates an example in which the structure of the transistor 100 illustrated in FIG. 1A and the like is applied to the transistor 205D, and the structure of the semiconductor device 30 illustrated in FIG. 28B and the like is applied to the transistors 205R, 205G, and 205B. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film.

[0472] The transistor 205D includes a conductive layer 104 that functions as a gate, an insulating layer 106 that functions as a gate insulating layer, a conductive layer 112a that functions as one of a source and a drain, and a layer 108 that includes a metal oxide. The layer 108 has a region in contact with a side surface of the insulating layer 110. The layer 108 includes a channel formation region and a region 108P that functions as the other of the source and the drain.

[0473] The transistor 205R, the transistor 205G, and the transistor 205B each include a transistor 100_2 and a transistor 100_3, respectively, in which the number (p) of transistors connected in series is 2 (see FIGS. 27A to 28B ). The transistor 205R, the transistor 205G, and the transistor 205B each include a conductive layer 104 that functions as a gate, an insulating layer 106 that functions as a gate insulating layer, a conductive layer 112b that functions as one of a source and a drain, and layers 108_1 and 108_2 that include metal oxide. The layer 108_1 has a region in contact with a side surface of the insulating layer 110, and the layer 108_2 has a region in contact with a side surface of the insulating layer 210. The layer 108_2 includes a region 108P_2 that functions as the other of a source and a drain.

[0474] The transistors 205R, 205G, and 205B function as drive transistors that control the current flowing through the light-emitting elements 130R, 130G, and 130B, for example. By applying the configuration of the semiconductor device 30 to the drive transistors, the channel length can be increased, and saturation can be improved. Therefore, even if the source-drain voltage of these transistors is changed, the change in source-drain current is small, and therefore the light emission brightness of the light-emitting elements 130R, 130G, and 130B can be stabilized.

[0475] Note that the transistor included in the display device of this embodiment is not limited to the transistor of one embodiment of the present invention. For example, the display device may include a combination of the transistor of one embodiment of the present invention and a transistor having another structure.

[0476] The display device of this embodiment may include, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor. The transistor included in the display device of this embodiment may be either a top-gate transistor or a bottom-gate transistor. Alternatively, gates may be provided above and below a layer in which a channel is formed.

[0477] The display device of this embodiment may have a Si transistor.

[0478] To increase the emission luminance of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between its source and drain than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting element and increase the emission luminance of the light-emitting element.

[0479] When a transistor operates in a saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely controlled by changing the gate-source voltage, thereby controlling the amount of current flowing to a light-emitting element. This allows a pixel circuit to have a larger number of gray levels.

[0480] In terms of the saturation of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed to a light-emitting element, even when the current-voltage characteristics of the light-emitting element vary. In other words, when an OS transistor operates in a saturation region, the change in the source-drain current is small even when the source-drain voltage is changed, and therefore the light-emitting luminance of the light-emitting element can be stabilized.

[0481] The transistors included in the circuit portion 164 and the transistors included in the display portion 162 may have the same structure or different structures. The transistors included in the circuit portion 164 may all have the same structure or may have two or more types. Similarly, the transistors included in the display portion 162 may all have the same structure or may have two or more types.

[0482] All the transistors included in the display portion 162 may be OS transistors, all the transistors included in the display portion 162 may be Si transistors, or some of the transistors included in the display portion 162 may be OS transistors and the rest may be Si transistors.

[0483] For example, by using both an LTPS transistor and an OS transistor in the display portion 162, a display device with low power consumption and high driving capability can be realized. A structure in which an LTPS transistor and an OS transistor are combined is sometimes referred to as LTPO. Note that a more preferable example is a structure in which an OS transistor is used as a transistor that functions as a switch for controlling conduction / non-conduction between wirings, and an LTPS transistor is used as a transistor for controlling current.

[0484] For example, one of the transistors included in the display portion 162 functions as a transistor for controlling a current flowing to a light-emitting element and can also be called a driving transistor. One of the source and drain of the driving transistor is connected to a pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor as the driving transistor. This can increase the current flowing to the light-emitting element in the pixel circuit.

[0485] On the other hand, another transistor included in the display portion 162 functions as a switch for controlling pixel selection / non-selection and can also be called a selection transistor. The gate of the selection transistor is connected to a gate line, and one of the source and drain is connected to a source line (signal line). An OS transistor is preferably used as the selection transistor. This allows the gradation of a pixel to be maintained even when the frame frequency is significantly low (for example, 1 fps or less), and therefore power consumption can be reduced by stopping the driver when displaying a still image.

[0486] An insulating layer 218 is provided to cover the transistors 205D, 205R, 205G, and 205B, and an insulating layer 235 is provided over the insulating layer 218.

[0487] The insulating layer 218 preferably functions as a protective layer for the transistor. The insulating layer 218 is preferably made of a material through which impurities such as water and hydrogen are less likely to diffuse. This allows the insulating layer 218 to function as a barrier film. With such a structure, diffusion of impurities from the outside into the transistor can be effectively suppressed, and the reliability of the display device can be improved.

[0488] The insulating layer 218 preferably includes one or more inorganic insulating layers. The insulating layer 218 can be made of the same material as that used for the insulating layer 110.

[0489] The insulating layer 235 preferably functions as a planarization layer, and is preferably an organic insulating film. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, and precursors of these resins. The insulating layer 235 may also have a laminated structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 235 preferably functions as an etching protection layer. This prevents recesses from being formed in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc. Alternatively, recesses may be formed in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc. Note that the pixel electrodes 111R, 111G, and 111B may be collectively referred to as pixel electrodes 111.

[0490] On the insulating layer 235, the light emitting elements 130R, 130G, and 130B are provided.

[0491] The light-emitting element 130R has a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. The light-emitting element 130R shown in Fig. 44A emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0492] The light-emitting element 130G has a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. The light-emitting element 130G shown in Fig. 44A emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0493] The light-emitting element 130B has a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. The light-emitting element 130B shown in Fig. 44A emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0494] 44A, the EL layers 113R, 113G, and 113B are all shown with the same thickness, but this is not limited to this. The EL layers 113R, 113G, and 113B may have different thicknesses. For example, it is preferable to set the thickness of the EL layers 113R, 113G, and 113B so that the optical path length is such that the light emitted by each layer is intensified. This allows for a microcavity structure to be realized, and the color purity of the light emitted from each light-emitting element to be improved.

[0495] The pixel electrode 111R is connected to the region 108P_2 of the transistor 205R in openings provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235. Similarly, the pixel electrode 111G is connected to the region 108P_2 of the transistor 205G, and the pixel electrode 111B is connected to the region 108P_2 of the transistor 205B.

[0496] Ends of each of the pixel electrodes 111R, 111G, and 111B are covered with an insulating layer 237. The insulating layer 237 functions as a partition wall. The insulating layer 237 can be formed in a single layer structure or a stacked layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the materials that can be used for the insulating layer 218 and the insulating layer 235 can be used for the insulating layer 237. The insulating layer 237 can electrically insulate the pixel electrode and the common electrode. Furthermore, the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.

[0497] The insulating layer 237 is provided at least in the display unit 162. The insulating layer 237 may be provided not only in the display unit 162 but also in the connection unit 140 and the circuit unit 164. Furthermore, the insulating layer 237 may be provided up to the edge of the display device 50A.

[0498] The common electrode 115 is a continuous film provided in common to the light-emitting elements 130R, 130G, and 130B. The common electrode 115 shared by the plurality of light-emitting elements is connected to a conductive layer 123 provided in the connection portion 140. For the conductive layer 123, it is preferable to use a conductive layer formed from the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.

[0499] In a display device according to one embodiment of the present invention, a conductive film that transmits visible light is preferably used for the pixel electrode and the common electrode, which are electrodes from which light is extracted, and a conductive film that reflects visible light is preferably used for the electrode from which light is not extracted.

[0500] A conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.

[0501] Materials for forming the pair of electrodes of the light-emitting element can include metals, alloys, electrically conductive compounds, and mixtures thereof, as appropriate. Specific examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing these metals in combination. Other examples of such materials include indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Other examples of such materials include aluminum-containing alloys (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), and silver-containing alloys, such as an alloy of silver and magnesium and an alloy of silver, palladium, and copper (Ag-Pd-Cu, also referred to as APC). Other examples of the material include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not exemplified above, rare earth metals such as europium and ytterbium, alloys containing appropriate combinations of these, and graphene.

[0502] The light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, one of the pair of electrodes of the light-emitting element is preferably an electrode that is transparent and reflective to visible light (semi-transmissive / semi-reflective electrode), and the other is preferably an electrode that is reflective to visible light (reflective electrode). By having the light-emitting element have a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.

[0503] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode having a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the electrical resistivity of these electrodes is 1×10 −２ Preferably, it is Ωcm or less.

[0504] The EL layers 113R, 113G, and 113B are each provided in an island shape. In FIG. 44A , the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap. When forming island-shaped EL layers using a fine metal mask, the ends of adjacent EL layers may overlap as shown in FIG. 44A , but this is not limited to this. That is, adjacent EL layers may not overlap but may be spaced apart. Furthermore, the display device may have both regions where adjacent EL layers overlap and regions where adjacent EL layers do not overlap but are spaced apart.

[0505] Each of the EL layers 113R, 113G, and 113B includes at least a light-emitting layer. The light-emitting layer includes one or more light-emitting materials. As the light-emitting material, a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a material that emits near-infrared light can also be used as the light-emitting material.

[0506] The light-emitting material may include a fluorescent material, a phosphorescent material, a TADF material, and a quantum dot material.

[0507] The light-emitting layer may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole-transport properties (hole-transport material) and a substance with high electron-transport properties (electron-transport material) can be used. Furthermore, as the one or more organic compounds, a bipolar substance (a substance with high electron-transport properties and hole-transport properties) or a TADF material can be used.

[0508] The light-emitting layer preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material that are a combination that easily forms an exciplex. This configuration allows efficient emission using Exciplex-Triple Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, energy transfer becomes smooth and light emission can be achieved efficiently. This configuration allows for high efficiency, low-voltage operation, and a long lifetime of the light-emitting element.

[0509] In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole-injecting properties (hole-injecting layer), a layer containing a hole-transporting material (hole-transporting layer), a layer containing a substance with high electron-blocking properties (electron-blocking layer), a layer containing a substance with high electron-injecting properties (electron-injecting layer), a layer containing an electron-transporting material (electron-transporting layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer).In addition, the EL layer may include one or both of a bipolar substance and a TADF material.

[0510] The light-emitting element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-emitting element can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

[0511] The light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer. The tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer injects electrons into one of the two light-emitting units and holes into the other. The tandem structure allows the light-emitting element to emit light with high brightness. Furthermore, the tandem structure can reduce the current required to achieve the same brightness compared to a single structure, thereby improving reliability. The tandem structure can also be called a stack structure.

[0512] In Figure 44A, when light-emitting elements with a tandem structure are used, it is preferable that EL layer 113R has a structure having multiple light-emitting units that emit red light, EL layer 113G has a structure having multiple light-emitting units that emit green light, and EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0513] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded via an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 152. For example, a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting elements. In FIG. 44A , the space between the substrates 152 and 151 is filled with the adhesive layer 142, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 142 may be provided so as not to overlap with the light-emitting elements. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 142.

[0514] The protective layer 131 is preferably provided in at least the display portion 162 and is provided so as to cover the entire display portion 162. The protective layer 131 is preferably provided so as to cover not only the display portion 162 but also the connection portion 140 and the circuit portion 164. The protective layer 131 is also preferably provided up to the edge of the display device 50A. Meanwhile, in the connection portion 197, a region where the protective layer 131 is not provided is generated in order to connect the FPC 172 and the conductive layer 166.

[0515] By providing the protective layer 131 on the light emitting elements 130R, 130G, and 130B, the reliability of the light emitting elements can be improved.

[0516] The protective layer 131 can have a single-layer structure or a stacked structure of two or more layers. The conductivity of the protective layer 131 does not matter. The protective layer 131 can be formed using at least one of an insulating film, a semiconductor film, and a conductive film.

[0517] The protective layer 131 has an inorganic film, which can prevent the common electrode 115 from being oxidized, suppress impurities (moisture, oxygen, etc.) from entering the light-emitting element, and so on, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.

[0518] The protective layer 131 preferably includes one or more inorganic insulating layers. The protective layer 131 can be made of a material that can be used for the insulating layer 110. In particular, the protective layer 131 is preferably made of a nitride or a nitride oxide, and more preferably made of a nitride.

[0519] The protective layer 131 may be an inorganic film containing ITO, In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, IGZO, or the like. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 115. The inorganic film may further contain nitrogen.

[0520] When light emitted from the light-emitting element is extracted through the protective layer 131, it is preferable that the protective layer 131 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

[0521] For example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used as the protective layer 131. By using such a stacked structure, impurities (water, oxygen, etc.) can be prevented from entering the EL layer side.

[0522] Furthermore, the protective layer 131 may have an organic film. For example, the protective layer 131 may have both an organic film and an inorganic film. Examples of organic films that can be used for the protective layer 131 include the organic insulating films that can be used for the insulating layer 235.

[0523] A connection portion 197 is provided in a region of the substrate 151 where the substrate 152 does not overlap. In the connection portion 197, the conductive layer 165 is connected to the FPC 172 via the conductive layer 166 and the connection layer 242. Here, an example is shown in which the conductive layer 165 is formed in the same process as the regions 108P and 108P_2. An example is shown in which the conductive layer 166 is a conductive layer obtained by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B. The connection portion between the conductive layer 165 and the conductive layer 166 can have the same structure as the connection portion between the pixel electrode 111 and the region 108P_2. Specifically, FIG. 44A shows an example in which an opening is provided above the conductive layer 165, and the conductive layer 166 is in contact with the upper surface of the conductive layer 165 through the opening. The conductive layer 166 is exposed on the upper surface of the connection portion 197. This allows the connection portion 197 and the FPC 172 to be connected via the connection layer 242 .

[0524] The display device 50A is a top-emission type. Light emitted by the light-emitting elements is emitted toward the substrate 152. The substrate 152 is preferably made of a material that is highly transparent to visible light. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

[0525] It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 facing the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, in the circuit section 164, and the like.

[0526] A colored layer such as a color filter may be provided on the surface of the substrate 152 on the substrate 151 side or on the protective layer 131. When a color filter is provided over the light-emitting element, the color purity of light emitted from the pixel can be increased.

[0527] The colored layer is a colored layer that selectively transmits light in a specific wavelength range and absorbs light in other wavelength ranges. For example, a red (R) color filter that transmits light in the red wavelength range, a green (G) color filter that transmits light in the green wavelength range, and a blue (B) color filter that transmits light in the blue wavelength range can be used. Each colored layer can be made of one or more of a metal material, a resin material, a pigment, and a dye. The colored layers are formed at desired positions by a printing method, an inkjet method, an etching method using lithography, or the like.

[0528] Various optical members can be arranged on the outside of the substrate 152 (the surface opposite to the substrate 151). Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. In addition, a surface protection layer such as an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, or an impact absorbing layer may be arranged on the outside of the substrate 152. For example, a glass layer or a silica layer (SiO ｘ The surface protection layer can be preferably formed of a material such as DLC (diamond-like carbon), aluminum oxide (AlO ｘ), polyester-based materials, or polycarbonate-based materials may also be used. Note that it is preferable to use a material with high transmittance to visible light for the surface protection layer. It is also preferable to use a material with high hardness for the surface protection layer.

[0529] The substrate 151 and the substrate 152 can each be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting element is extracted. When a flexible material is used for the substrate 151 and the substrate 152, the flexibility of the display device can be increased, and a flexible display can be realized. Furthermore, a polarizing plate may be used for at least one of the substrates 151 and 152.

[0530] Substrate 151 and substrate 152 can be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of substrate 151 and substrate 152 can be made of glass having a thickness sufficient to provide flexibility.

[0531] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has low birefringence (it can also be said that the amount of birefringence is small). Examples of films with high optical isotropy include triacetyl cellulose (TAC, also called cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0532] The adhesive layer 142 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability, such as epoxy resin, is preferable. Alternatively, a two-component resin may be used. Alternatively, an adhesive sheet or the like may be used.

[0533] The connection layer 242 may be an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0534] <Display Device 50B> Figure 44B shows an example of a cross section of the display unit 162 of the display device 50B. The display device 50B differs from the display device 50A mainly in that a light-emitting element having a common EL layer 113 and a colored layer (such as a color filter) are used for each subpixel of each color. The configuration shown in Figure 44B can be combined with the region including the FPC 172, the circuit portion 164, the stacked structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection portion 140, and the end portion configuration shown in Figure 44A. Note that in the following description of the display device, descriptions of parts similar to those of the display device described above may be omitted.

[0535] A display device 50B shown in FIG. 44B includes light-emitting elements 130R, 130G, and 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.

[0536] The light emitting element 130R has a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. The light emitted from the light emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.

[0537] The light emitting element 130G has a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. Light emitted from the light emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.

[0538] The light emitting element 130B has a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. Light emitted from the light emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.

[0539] The light-emitting elements 130R, 130G, and 130B each share the EL layer 113 and the common electrode 115. The configuration in which the subpixels of each color are provided with a common EL layer 113 can reduce the number of manufacturing steps compared to the configuration in which the subpixels of each color are provided with different EL layers.

[0540] For example, the light emitting elements 130R, 130G, and 130B shown in Fig. 44B emit white light. The white light emitted from the light emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of a desired color.

[0541] A light-emitting element that emits white light preferably includes two or more light-emitting layers. When two light-emitting layers are used to obtain white light emission, light-emitting layers can be selected such that the emission colors of the two light-emitting layers have a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer have a complementary color relationship, a configuration in which the light-emitting element as a whole emits white light can be obtained. Furthermore, when three or more light-emitting layers are used to obtain white light emission, the emission colors of the three or more light-emitting layers can be combined to form a configuration in which the light-emitting element as a whole emits white light.

[0542] The EL layer 113 preferably includes, for example, a light-emitting layer having a light-emitting substance that emits blue light and a light-emitting layer having a light-emitting substance that emits visible light with a wavelength longer than blue. The EL layer 113 preferably includes, for example, a light-emitting layer that emits yellow light and a light-emitting layer that emits blue light. Alternatively, the EL layer 113 preferably includes, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.

[0543] A tandem structure is preferably used for the light-emitting element emitting white light. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and a light-emitting unit that emits blue light, in this order, or a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and red light, and a light-emitting unit that emits blue light, in this order, or the like can be applied. For example, the number of stacked light-emitting units and the order of colors can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, and B, and the number of stacked light-emitting layers in light-emitting unit X and the order of colors can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R. Furthermore, another layer can be provided between the two light-emitting layers.

[0544] By applying a microcavity structure, a light emitting element configured to emit white light may emit light of a specific wavelength such as red, green, or blue that is intensified.

[0545] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in FIG. 44B emit blue light. In this case, the EL layer 113 includes one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. Furthermore, in the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, a color conversion layer can be provided between the light-emitting element 130R or the light-emitting element 130G and the substrate 152 to convert the blue light emitted by the light-emitting element 130R or the light-emitting element 130G into light with a longer wavelength, thereby extracting red or green light. Furthermore, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a coloring layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. A portion of the light emitted by the light-emitting element may be transmitted directly without being converted by the color conversion layer. By extracting the light transmitted through the color conversion layer via the colored layer, light other than the desired color can be absorbed by the colored layer, thereby increasing the color purity of the light emitted by the sub-pixel.

[0546] <Display Device 50C> A display device 50C shown in FIG. 45 differs from the display device 50B mainly in that it is a bottom-emission type display device.

[0547] Light emitted from the light-emitting element is emitted toward the substrate 151. A material that is highly transparent to visible light is preferably used for the substrate 151. On the other hand, the light-transmitting property of a material used for the substrate 152 does not matter.

[0548] It is preferable to form a light-shielding layer 117 between the substrate 151 and the transistor. Fig. 45 shows an example in which the light-shielding layer 117 is provided over the substrate 151, the insulating layer 153 is provided over the light-shielding layer 117, and the transistors 205D, 205R (not shown), 205G, and 205B are provided over the insulating layer 153. Furthermore, the coloring layers 132R, 132G, and 132B are provided over the insulating layer 218, and the insulating layer 235 is provided over the coloring layers 132R, 132G, and 132B.

[0549] The light emitting element 130R overlapping the colored layer 132R includes a pixel electrode 111R, an EL layer 113, and a common electrode 115.

[0550] The light emitting element 130G overlapping the colored layer 132G includes a pixel electrode 111G, an EL layer 113, and a common electrode 115.

[0551] The light emitting element 130B overlapping the colored layer 132B has a pixel electrode 111B, an EL layer 113 and a common electrode 115.

[0552] The pixel electrodes 111R, 111G, and 111B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom-emission display device, a metal or the like with low electrical resistivity can be used for the common electrode 115, which can suppress voltage drops caused by the electrical resistance of the common electrode 115 and achieve high display quality.

[0553] The transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced; therefore, in a bottom-emission display device, the aperture ratio of a pixel can be increased or the pixel size can be reduced.

[0554] <Display Device 50D> A display device 50D shown in FIG. 46A differs from the display device 50A mainly in that it has a light receiving element 130S.

[0555] The display device 50D has a light-emitting element and a light-receiving element in each pixel. In the display device 50D, it is preferable to use an organic EL element as the light-emitting element and an organic photodiode as the light-receiving element. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device using an organic EL element.

[0556] In the display device 50D, in which pixels have a light-emitting element and a light-receiving element, the pixels have a light-receiving function, so that it is possible to detect contact or proximity of an object while displaying an image. Therefore, the display unit 162 has one or both of an imaging function and a sensing function in addition to an image display function. For example, in addition to displaying an image using all of the sub-pixels of the display device 50D, it is also possible for some sub-pixels to emit light as a light source, other sub-pixels to perform light detection, and the remaining sub-pixels to display an image.

[0557] Therefore, there is no need to provide a light receiving unit and a light source separately from the display device 50D, and the number of components in the electronic device can be reduced. For example, there is no need to provide a separate biometric authentication device or a capacitive touch panel for scrolling, etc. Therefore, by using the display device 50D, it is possible to provide an electronic device with reduced manufacturing costs.

[0558] When a light receiving element is used as an image sensor, the display device 50D can capture an image using the light receiving element. For example, the image sensor can capture an image for personal authentication using a fingerprint, palm print, iris, pulse shape (including vein shape and artery shape), face, or the like.

[0559] The light receiving element can be used as a touch sensor (also called a direct touch sensor) or a non-contact sensor (also called a hover sensor, hover touch sensor, or touchless sensor). A touch sensor can detect an object (such as a finger, hand, or pen) when the object comes into direct contact with the display device. A non-contact sensor can detect an object without the object touching the display device.

[0560] The light receiving element 130S has a pixel electrode 111S on an insulating layer 235, a functional layer 113S on the pixel electrode 111S, and a common electrode 115 on the functional layer 113S. Light Lin is incident on the functional layer 113S from outside the display device 50D.

[0561] The pixel electrode 111S is connected to a region 108P_2 of the transistor 205S in an opening provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235.

[0562] The end of the pixel electrode 111S is covered with an insulating layer 237.

[0563] The common electrode 115 is a continuous film provided in common to the light receiving element 130S, the light emitting element 130R (not shown), the light emitting element 130G, and the light emitting element 130B. The common electrode 115 shared by the light emitting element and the light receiving element is connected to a conductive layer 123 provided in the connection portion 140.

[0564] The functional layer 113S has at least an active layer (also referred to as a photoelectric conversion layer). The active layer includes a semiconductor. Examples of the semiconductor include inorganic semiconductors such as silicon and organic semiconductors including organic compounds. In this embodiment, an example in which an organic semiconductor is used as the semiconductor included in the active layer is shown. Using an organic semiconductor is preferable because the light-emitting layer and the active layer can be formed by the same method (for example, vacuum deposition), allowing the use of a common manufacturing device.

[0565] The functional layer 113S may further include a layer containing a substance with high hole transporting properties, a substance with high electron transporting properties, a bipolar substance, or the like, as a layer other than the active layer. Furthermore, without being limited to the above, the functional layer 113S may further include a layer containing a substance with high hole injection properties, a hole blocking material, a substance with high electron injection properties, an electron blocking material, or the like. For example, the materials that can be used for the light-emitting element described above can be used for the functional layer 113S.

[0566] The light-receiving element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-receiving element can be formed by a method such as vapor deposition (including vacuum vapor deposition), transfer, printing, inkjet printing, or coating.

[0567] A display device 50D shown in FIGS. 46B and 46C has, between a substrate 151 and a substrate 152, a layer 353 having a light receiving element, a circuit layer 355, and a layer 357 having a light emitting element.

[0568] The layer 353 includes, for example, the light receiving element 130S. The layer 357 includes, for example, the light emitting elements 130R, 130G, and 130B.

[0569] The circuit layer 355 includes a circuit for driving the light receiving element and a circuit for driving the light emitting element. The circuit layer 355 includes, for example, transistors 205R, 205G, and 205B. In addition, the circuit layer 355 may include one or more of a switch, a capacitor, a resistor, a wiring, a terminal, and the like.

[0570] 46B shows an example in which the light receiving element 130S is used as a touch sensor. As shown in FIG. 46B, light emitted by the light emitting element in layer 357 is reflected by a finger 352 that touches the display device 50D, and the light receiving element in layer 353 detects the reflected light. This makes it possible to detect that the finger 352 has touched the display device 50D.

[0571] 46C shows an example in which the light receiving element 130S is used as a non-contact sensor. As shown in FIG. 46C, light emitted by a light emitting element in a layer 357 is reflected by a finger 352 that is close to (i.e., not in contact with) the display device 50D, and the light receiving element in a layer 353 detects the reflected light.

[0572] 47A is an example of a display device employing an MML (metal maskless) structure. That is, the display device 50E has light-emitting elements fabricated without using a fine metal mask.

[0573] The island-shaped light-emitting layers in the light-emitting elements of a display device employing the MML structure are formed by depositing a light-emitting layer on one surface and then processing it using lithography. This allows for the realization of high-definition display devices or display devices with a high aperture ratio, which have been difficult to achieve until now. Furthermore, since the light-emitting layers can be created separately for each color, a display device with extremely vivid images, high contrast, and high display quality can be realized. For example, if a display device is composed of three types of light-emitting elements, namely, light-emitting elements that emit blue light, light-emitting elements that emit green light, and light-emitting elements that emit red light, the three types of island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer and processing by lithography three times.

[0574] Because MML structure devices can be manufactured without using a metal mask, they can exceed the upper limit of resolution imposed by the alignment accuracy of the metal mask. Furthermore, when devices are manufactured without using a metal mask, the equipment required for manufacturing the metal mask and the metal mask cleaning process are unnecessary. Furthermore, since the same or similar equipment as that used for manufacturing transistors can be used for lithography processing, there is no need to introduce special equipment for manufacturing MML structure devices. As such, the MML structure allows for low manufacturing costs, making it suitable for mass production of devices.

[0575] In a display device to which the MML structure is applied, there is no need to artificially increase the resolution by applying a special pixel arrangement such as a pentile arrangement, and therefore it is possible to realize a display device with high resolution (for example, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more) using a so-called stripe arrangement in which R, G, and B sub-pixels are each arranged in one direction.

[0576] By providing a sacrificial layer over the light-emitting layer, damage to the light-emitting layer during the manufacturing process of the display device can be reduced, and the reliability of the light-emitting element can be improved.

[0577] By employing a film formation step using an area mask and a processing step using a resist mask, a light-emitting element can be manufactured through a relatively simple process.

[0578] The layered structure from the substrate 151 to the insulating layer 235 and the layered structure from the protective layer 131 to the substrate 152 are the same as those of the display device 50A, and therefore will not be described here.

[0579] In FIG. 47A, light emitting elements 130 R, 130 G, and 130 B are provided on an insulating layer 235 .

[0580] The light-emitting element 130R includes a conductive layer 124R on the insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114. The light-emitting element 130R shown in FIG. 47A emits red light (R). The layer 133R includes a light-emitting layer that emits red light. In the light-emitting element 130R, the layer 133R and the common layer 114 can be collectively referred to as an EL layer. One or both of the conductive layer 124R and the conductive layer 126R can be referred to as a pixel electrode.

[0581] The light-emitting element 130G includes a conductive layer 124G on the insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114. The light-emitting element 130G shown in FIG. 47A emits green light (G). The layer 133G includes a light-emitting layer that emits green light. In the light-emitting element 130G, the layer 133G and the common layer 114 can be collectively referred to as an EL layer. Furthermore, one or both of the conductive layer 124G and the conductive layer 126G can be referred to as a pixel electrode.

[0582] The light-emitting element 130B has a conductive layer 124B on the insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114. The light-emitting element 130B shown in FIG. 47A emits blue light (B). The layer 133B has a light-emitting layer that emits blue light. In the light-emitting element 130B, the layer 133B and the common layer 114 can be collectively referred to as an EL layer. Furthermore, one or both of the conductive layer 124B and the conductive layer 126B can be referred to as a pixel electrode.

[0583] In this specification and the like, among the EL layers included in the light-emitting elements, layers provided in an island shape for each light-emitting element are referred to as layer 133B, layer 133G, or layer 133R, and a layer shared by a plurality of light-emitting elements is referred to as a common layer 114. Note that in this specification and the like, the layers 133R, 133G, and 133B may be referred to as island-shaped EL layers or EL layers formed in an island shape, without including the common layer 114. Furthermore, a light-emitting element manufactured without using a metal mask may not have a common layer, and all layers constituting the EL layer may be formed in an island shape.

[0584] The layers 133R, 133G, and 133B are spaced apart from one another. By providing an island-shaped EL layer for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This makes it possible to prevent unintended light emission due to crosstalk, and realize a display device with extremely high contrast.

[0585] 47A, the layers 133R, 133G, and 133B are all shown to have the same thickness, but this is not limiting. The layers 133R, 133G, and 133B may have different thicknesses.

[0586] The conductive layer 124R is connected to the region 108P_2 of the transistor 205R in an opening provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235. Similarly, the conductive layer 124G is connected to the region 108P_2 of the transistor 205G, and the conductive layer 124B is connected to the region 108P_2 of the transistor 205B.

[0587] The conductive layers 124R, 124G, and 124B are formed so as to cover the openings provided in the insulating layer 235. A layer 128 is buried in the recesses of the conductive layers 124R, 124G, and 124B, respectively.

[0588] The layer 128 has a function of planarizing the recesses of the conductive layers 124R, 124G, and 124B. Conductive layers 126R, 126G, and 126B connected to the conductive layers 124R, 124G, and 124B are provided on the conductive layers 124R, 124G, and 124B and the layer 128. Therefore, the regions overlapping with the recesses of the conductive layers 124R, 124G, and 124B can also be used as light-emitting regions, thereby increasing the aperture ratio of the pixel. It is preferable to use a conductive layer that functions as a reflective electrode for the conductive layers 124R and 126R.

[0589] The layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 128. In particular, the layer 128 is preferably formed using an insulating material, and more preferably using an organic insulating material. For example, the organic insulating material that can be used for the insulating layer 237 described above can be used for the layer 128.

[0590] 47A shows an example in which the top surface of layer 128 has a flat portion, but there are no particular limitations on the shape of layer 128. The top surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.

[0591] The height of the upper surface of layer 128 and the height of the upper surface of conductive layer 124R may be the same or approximately the same, or may be different from each other. For example, the height of the upper surface of layer 128 may be lower or higher than the height of the upper surface of conductive layer 124R.

[0592] The end of the conductive layer 126R may be flush with the end of the conductive layer 124R, or may cover the side surface of the end of the conductive layer 124R. The end of each of the conductive layers 124R and 126R preferably has a tapered shape. Specifically, the end of each of the conductive layers 124R and 126R preferably has a tapered shape with a taper angle greater than 0 degrees and less than 90 degrees. When the end of the pixel electrode has a tapered shape, the layer 133R provided along the side surface of the pixel electrode has an inclined portion. By tapering the side surface of the pixel electrode, the coverage of the EL layer provided along the side surface of the pixel electrode can be improved.

[0593] The conductive layers 124G, 126G and the conductive layers 124B, 126B are similar to the conductive layers 124R, 126R, and therefore detailed description thereof will be omitted.

[0594] The upper surface and side surfaces of the conductive layer 126R are covered with the layer 133R. Similarly, the upper surface and side surfaces of the conductive layer 126G are covered with the layer 133G, and the upper surface and side surfaces of the conductive layer 126B are covered with the layer 133B. Therefore, the entire region where the conductive layers 126R, 126G, and 126B are provided can be used as the light-emitting region of the light-emitting elements 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixel.

[0595] Part of the top surface and side surfaces of each of the layers 133R, 133G, and 133B are covered with insulating layers 125 and 127. A common layer 114 is provided on the layers 133R, 133G, 133B, and insulating layers 125 and 127, and a common electrode 115 is provided on the common layer 114. The common layer 114 and the common electrode 115 are each a continuous film provided in common to a plurality of light-emitting elements.

[0596] In FIG. 47A , the insulating layer 237 shown in FIG. 44A and other figures is not provided between the conductive layer 126R and the layer 133R. Similarly, the insulating layer 237 is not provided between the conductive layer 126G and the layer 133G, and between the conductive layer 126B and the layer 133B. That is, the display device 50E does not have an insulating layer (also referred to as a partition wall, bank, spacer, etc.) that contacts the pixel electrode and covers the upper edge of the pixel electrode. Therefore, the distance between adjacent light-emitting elements can be made extremely narrow. This allows a high-definition or high-resolution display device to be obtained. Furthermore, a mask for forming the insulating layer is not required, thereby reducing the manufacturing cost of the display device.

[0597] Each of the layers 133R, 133G, and 133B has a light-emitting layer. Each of the layers 133R, 133G, and 133B preferably has a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer). Alternatively, each of the layers 133R, 133G, and 133B preferably has a light-emitting layer and a carrier block layer (hole block layer or electron block layer). Alternatively, each of the layers 133R, 133G, and 133B preferably has a light-emitting layer, a carrier block layer, and a carrier transport layer on the carrier block layer. It is more preferable that the carrier transport layer is provided on the light-emitting layer. It is more preferable that the carrier block layer is provided on the light-emitting layer. When the layers 133R, 133G, and 133B are exposed to the air during the manufacturing process of the display device, providing one or both of a carrier transport layer and a carrier block layer on the light-emitting layer prevents the light-emitting layer from being exposed to the outermost surface, thereby preventing the light-emitting layer from being exposed to the air. This reduces damage to the light-emitting layer and improves the reliability of the light-emitting element.

[0598] The common layer 114 includes, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may include a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. The common layer 114 is shared by the light-emitting elements 130R, 130G, and 130B.

[0599] The side surfaces of the layers 133R, 133G, and 133B are covered with the insulating layer 125. The insulating layer 127 covers the side surfaces of the layers 133R, 133G, and 133B with the insulating layer 125 interposed therebetween.

[0600] The side surfaces (and even part of the upper surfaces) of the layers 133R, 133G, and 133B are covered with at least one of the insulating layer 125 and the insulating layer 127, which prevents the common layer 114 (or the common electrode 115) from coming into contact with the pixel electrodes and the side surfaces of the layers 133R, 133G, and 133B, thereby preventing short circuits in the light-emitting elements, thereby improving the reliability of the light-emitting elements.

[0601] The insulating layer 125 preferably has a region in contact with each side surface of the layer 133R, the layer 133G, and the layer 133B. By configuring the insulating layer 125 to be in contact with the layer 133R, the layer 133G, and the layer 133B, peeling of the layer 133R, the layer 133G, and the layer 133B can be prevented, and the reliability of the light-emitting element can be improved.

[0602] The insulating layer 127 is provided on the insulating layer 125 so as to fill the recesses in the insulating layer 125. The insulating layer 127 preferably covers at least a part of the side surface of the insulating layer 125.

[0603] By providing the insulating layers 125 and 127, the gaps between adjacent island-shaped layers can be filled, which reduces large unevenness in height on the surface on which layers (e.g., a carrier injection layer, a common electrode, etc.) are formed on the island-shaped layers, thereby making the surface flatter, thereby improving the coverage of the carrier injection layer, the common electrode, etc.

[0604] The common layer 114 and the common electrode 115 are provided over the layer 133R, the layer 133G, the layer 133B, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are provided, a step is generated between a region where the pixel electrode and the island-shaped EL layer are provided and a region where the pixel electrode and the island-shaped EL layer are not provided (a region between light-emitting elements). In the display device of one embodiment of the present invention, the insulating layer 125 and the insulating layer 127 can flatten the step, thereby improving the coverage of the common layer 114 and the common electrode 115. Therefore, poor connection due to disconnection can b...

Claims

a transistor and a first insulating layer; the transistor includes a conductive layer and a metal oxide layer; the first insulating layer is located on the conductive layer; the first insulating layer has an end portion in contact with the upper surface of the conductive layer; the first insulating layer has a second insulating layer and a third insulating layer on the second insulating layer; the metal oxide layer has an end portion in contact with an upper surface of the conductive layer, an end portion in contact with a side surface of the second insulating layer, an end portion in contact with a side surface of the third insulating layer, and an end portion in contact with an upper surface of the third insulating layer; The third insulating layer has a region having a higher hydrogen content than the second insulating layer. 　 In claim 1, the transistor has a gate electrode and a gate insulating layer; the gate insulating layer has a region in contact with an upper surface and a side surface of the metal oxide layer; the gate electrode has a region facing a side surface of the first insulating layer with the gate insulating layer and the metal oxide layer interposed therebetween. 　 a transistor and a first insulating layer; the transistor includes a conductive layer, a metal oxide layer, a gate insulating layer, and a gate electrode; the first insulating layer is located on the conductive layer; the first insulating layer has an end portion in contact with the upper surface of the conductive layer; the first insulating layer has a second insulating layer and a third insulating layer on the second insulating layer; the metal oxide layer has a region in contact with an upper surface of the conductive layer, a side surface of the second insulating layer, and an upper surface and a side surface of the third insulating layer; the gate insulating layer has a region in contact with an upper surface and a side surface of the metal oxide layer and a side surface of the first insulating layer; the gate electrode has a region facing a side surface of the first insulating layer with the gate insulating layer and the metal oxide layer interposed therebetween, The third insulating layer has a region having a higher hydrogen content than the second insulating layer. 　 In claim 2 or claim 3, the first insulating layer has an opening that reaches the conductive layer; the metal oxide layer, the gate insulating layer, and the gate electrode each have a region located within the opening. 　 In any one of claims 1 to 3, the second insulating layer comprises silicon and oxygen; The semiconductor device, wherein the third insulating layer includes silicon and nitrogen. 　 In any one of claims 1 to 3, the first insulating layer has a fourth insulating layer between the second insulating layer and the third insulating layer; the fourth insulating layer comprises silicon and nitrogen; The third insulating layer has a region having a higher hydrogen content than the fourth insulating layer. 　 In claim 6, a fifth insulating layer; the fifth insulating layer has a region in contact with a lower surface of the conductive layer, the first insulating layer has a sixth insulating layer; the sixth insulating layer is located between the second insulating layer and the conductive layer; the fifth insulating layer comprises silicon and nitrogen; the sixth insulating layer comprises silicon and nitrogen; The fifth insulating layer has a region having a higher hydrogen content than the sixth insulating layer. In any one of claims 1 to 3, the first insulating layer has a fourth insulating layer between the second insulating layer and the third insulating layer; the fourth insulating layer comprises aluminum and oxygen; The third insulating layer has a region having a higher hydrogen content than the fourth insulating layer. 　 In claim 8, a fifth insulating layer; the fifth insulating layer has a region in contact with a lower surface of the conductive layer, the first insulating layer has a sixth insulating layer between the second insulating layer and the conductive layer; the fifth insulating layer comprises silicon and nitrogen; the sixth insulating layer comprises silicon and nitrogen; The fifth insulating layer has a region having a higher hydrogen content than the sixth insulating layer. 　 In any one of claims 1 to 3, The semiconductor device, wherein the metal oxide layer comprises indium. 　 In any one of claims 1 to 3, The semiconductor device, wherein the conductive layer contains indium and oxygen.

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