Semiconductor device

Abstract

Provided is a semiconductor device that can be easily manufactured. This semiconductor device has a substrate, a transistor and element isolation layer formed on the substrate, first to fifth conductive layers, a first insulating layer, and first to fifth plugs. The transistor has a first low resistance region, a second low resistance region, and a portion of the first conductive layer. Each of a third conductive layer and a fourth conductive layer is a columnar body extending in a direction perpendicular to the substrate. The first low resistance region and the second conductive layer are connected via the first plug. The second low resistance region and the third conductive layer are connected via the second plug and the second plug. The fourth plug, the fifth plug, and the fourth conductive layer are connected to each other at positions overlapping the element isolation layer. The first insulating layer has a region in contact with a side surface and a top surface of the third conductive layer and the fourth conductive layer, and the fifth conductive layer extends in a direction approximately parallel to the first conductive layer in a planar view and has a region in contact with a side surface and a top surface of the first insulating layer.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] As shown in Non-Patent Document 1, research and development of memories using ferroelectrics is being actively carried out. In addition, for the next generation of ferroelectric memories, ferroelectric HfO ２ Research on Hf-based materials (Non-Patent Document 2), ０．５ Zr ０．５ O ２ Research on ferroelectricity of thin films (Non-Patent Document 3), HfO ２ Research on ferroelectricity of thin films (Non-Patent Document 4), and ferroelectric Hf ０．５ Zr ０．５ O ２ Research related to hafnium oxide is also being actively conducted, including the demonstration of integration of FeRAM (Ferroelectric Random Access Memory) using hafnium oxide with CMOS (Non-Patent Document 5).

[0004] A ferroelectric capacitor is an example of a memory or circuit element that uses a ferroelectric material. A ferroelectric capacitor is a type of capacitance element in which a ferroelectric insulating material is sandwiched between a pair of electrodes, and is capable of retaining data by utilizing the hysteresis characteristics of the remanent polarization of the ferroelectric insulating material. This allows data to be retained even without the application of voltage, and therefore the realization of a non-volatile memory (FeRAM) using a ferroelectric capacitor is expected.

[0005] In particular, Patent Documents 1 and 2 disclose a circuit configuration that retains data in a ferroelectric capacitor even when the power supply voltage to a flip-flop circuit is cut off. This circuit configuration makes it possible to back up the data retained in the flip-flop circuit to the ferroelectric capacitor, and to stop the flip-flop circuit.

[0006] Republished Patent Publication No. 03-044953 Japanese Patent Application Laid-Open No. 2013-124290

[0007] T. S. Boescke, et al. , “Ferroelectricity in hafnium oxide thin films”, APL99, 2011 Zhen Fan, et al. , “Ferroelectric HfO2-based materials for next-generation ferroelectric memories”, JOURNAL OF ADVANCED DIELECTRICS, Vol. 6, No. 2, 2016Jun Okuno, et al. , "SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf 0.5 Zr 0.5 O 2 ", VLSI 2020. Akira Toriumi, "Ferroelectricity of HfO 2 thin film", The Japan Society of Applied Physics, Vol. 88, No. 9, 2019. T. Francois, et al. , “Demonstration of BEOL-compatible ferroelectric Hf▲0.5▼Zr▲0.5▼O▲2▼ scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications”, IEDM 2019

[0008] As miniaturization and integration progress, memory cells in FeRAMs are also becoming smaller. Specifically, ferroelectric capacitors are also becoming smaller. In this case, the area where dielectric polarization occurs in the insulating layer, which may have ferroelectricity and is sandwiched between a pair of electrodes of the ferroelectric capacitor, becomes smaller, which can reduce the amount of dielectric polarization. When the amount of dielectric polarization becomes smaller, the threshold voltage distribution of data in the FeRAM also becomes narrower, which can lead to the risk of erroneous data being read during a read operation from the FeRAM. Conversely, to accurately read data from the FeRAM, it is necessary to ensure that the area of ​​the insulating layer, which may have ferroelectricity and is sandwiched between the pair of electrodes of the ferroelectric capacitor, is at least a certain size.

[0009] Furthermore, unlike DRAM (Dynamic Random Access Memory), FeRAM requires plate lines for writing to and reading from the ferroelectric capacitor. The plate lines are wiring lines connected to the electrodes of the ferroelectric capacitor, and preferably extend in the same direction as the word lines. However, depending on the shape of the ferroelectric capacitor, extending the plate lines in the same direction as the word lines may result in longer plate lines. This may increase the wiring resistance and increase the power consumption of the FeRAM.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device with a reduced occupation area.An object of one embodiment of the present invention is to provide a semiconductor device from which data can be accurately read.An object of one embodiment of the present invention is to provide a semiconductor device that can be easily manufactured.An object of one embodiment of the present invention is to provide an electronic device including the above-described memory element.An object of one embodiment of the present invention is to provide a novel memory element or a novel electronic device.

[0011] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems. Therefore, one embodiment of the present invention does not necessarily solve all of the above problem and other problems.

[0012] In view of the above-described problems, one aspect of the present invention provides a semiconductor device having a ferroelectric capacitor including a lower conductive layer having a columnar shape extending in a direction perpendicular or substantially perpendicular to a substrate, an insulating layer that may have ferroelectric properties and is formed on the side and top surfaces of the conductive layer, and an upper conductive layer having a region facing the lower conductive layer via the insulating layer. Furthermore, a plurality of lower conductive layers are provided so as to overlap with word lines extending in a direction parallel or substantially parallel to the substrate. Furthermore, by forming the upper conductive layers as plate lines along the direction in which the word lines extend, a plurality of ferroelectric capacitors can be arranged in the direction in which the word lines extend.

[0013] Furthermore, when the distance between adjacent ferroelectric capacitors is long, it is preferable to provide one or more ferroelectric capacitors as dummy patterns between the adjacent ferroelectric capacitors.

[0014] A typical example of a configuration according to one embodiment of the present invention will be described below.

[0015] (1) One aspect of the present invention is a semiconductor device having a substrate, an element isolation layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first insulating layer, a first plug, a second plug, a third plug, a fourth plug, and a fifth plug.

[0016] The substrate has a first low-resistance region that functions as one of the source and drain of the transistor, a second low-resistance region that functions as the other of the source and drain of the transistor, and a semiconductor region in which the channel of the transistor is formed. The transistor also has a portion of the first conductive layer that functions as a gate. The first insulating layer includes a material that can exhibit ferroelectricity. In a cross-sectional view, the height of the third conductive layer is greater than the width of the third conductive layer, and the height of the fourth conductive layer is greater than the width of the fourth conductive layer.

[0017] The first plug has a region in contact with the first low-resistance region, and the second conductive layer has a region in contact with the first plug. The second plug has a region in contact with the second low-resistance region, and the third plug has a region in contact with the second plug. The third conductive layer is located in a region in contact with an upper surface of the third plug and overlapping with the first conductive layer in a planar view. The fourth plug has a region in contact with the element isolation layer, and the fifth plug has a region in contact with the fourth plug. The fourth conductive layer is located in a region in contact with an upper surface of the fifth plug and overlapping with the element isolation layer in a planar view. The first insulating layer has regions in contact with side surfaces and upper surfaces of the third and fourth conductive layers, and the fifth conductive layer has regions overlapping with the first conductive layer and in contact with the side surfaces and upper surface of the first insulating layer in a planar view.

[0018] The first conductive layer and the fifth conductive layer are positioned to extend in a first direction, and the second conductive layer is positioned to extend in a second direction, which are generally perpendicular to each other.

[0019] (2) Alternatively, in one aspect of the present invention, in the above-described (1), the material that can have ferroelectricity can have an oxide containing one or both of hafnium and zirconium.

[0020] (3) In another embodiment of the present invention, in the above-described (1) or (2), a second insulating layer may be provided. The transistor may have a groove.

[0021] The trench is preferably located between the first low-resistance region and the second low-resistance region in plan view, the second insulating layer is preferably located in a region in contact with the side and bottom surfaces of the trench, and the semiconductor region is preferably located in a region facing the first conductive layer with the second insulating layer interposed therebetween.

[0022] (4) Another embodiment of the present invention is an electronic device including the semiconductor device according to any one of (1) to (3) above and a housing.

[0023] The configuration (1) above allows the first conductive layer functioning as the word line and the fifth conductive layer functioning as the plate line to overlap each other in a plan view. That is, the word line and the plate line can extend in the same direction. Furthermore, since the plate line can be shortened, the wiring resistance can be reduced, and the power consumption of the semiconductor device can be reduced.

[0024] Furthermore, by providing the third and fourth conductive layers as the columnar lower electrodes along the direction of extension of the word lines, ferroelectric capacitors can be arranged side by side in the direction of extension of the word lines. Furthermore, since the lower electrodes are columnar, the area of ​​the insulating layer, which may have ferroelectricity and is sandwiched between the pair of electrodes of the ferroelectric capacitor, can be increased. This allows the threshold voltage distribution of data in the FeRAM to be increased, enabling accurate reading of logic "0" and "1."

[0025] In the above configuration (1), the ferroelectric capacitor including the fourth conductive layer is formed as a dummy pattern.

[0026] Furthermore, in the above-mentioned configuration (2), even a thin film of a few nanometers can have ferroelectricity, which allows the process of fabricating a ferroelectric capacitor to be shortened.

[0027] According to one embodiment of the present invention, a semiconductor device with a reduced occupation area can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device from which data can be accurately read can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be easily manufactured can be provided. Alternatively, according to one embodiment of the present invention, an electronic device including the above-described memory element can be provided. Alternatively, according to one embodiment of the present invention, a novel memory element or a novel electronic device can be provided.

[0028] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Note that the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, etc., and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above.

[0029] FIG. 1 is a schematic perspective view showing an example of the configuration of a semiconductor device. FIGS. 2A and 2B are schematic plan views showing an example of the configuration of a semiconductor device. FIG. 3 is a schematic plan view showing an example of the configuration of a semiconductor device. FIG. 4 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. FIG. 5 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. FIG. 6 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. FIG. 7 is a block diagram showing an example of the configuration of a semiconductor device. FIG. 8 is a diagram illustrating an example of the circuit configuration of a memory cell array and memory cells. FIG. 9A is a graph showing an example of hysteresis characteristics, and FIG. 9B is a timing chart showing an example of a method for driving memory cells. FIG. 10 is a conceptual diagram illustrating the hierarchy of a memory device. FIG. 11A is a block diagram showing an example of the configuration of a semiconductor device, and FIG. 11B is a schematic perspective view showing an example of the configuration of a semiconductor device. FIGS. 12A to 12E are diagrams showing an example of a memory device. FIGS. 13A to 13D are diagrams showing an example of an electronic component. FIGS. 14A and 14B are diagrams showing an example of an electronic device, and FIGS. 14C to 14E are diagrams showing an example of a mainframe computer. Fig. 15A is a diagram showing an example of space equipment. Fig. 15B is a diagram showing an example of a storage system applicable to a data center. Figs. 16A1 to 16A7 and 16B1 to 16B6 are circuit diagrams for explaining electrical connections.

[0030] (Additional Notes Related to the Present Specification) In the present specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. Furthermore, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit. Another example of a semiconductor device is an electronic component in which a chip is housed in a package. Furthermore, for example, a memory device, a display device, a light-emitting device, a computing device, a lighting device, and an electronic device may themselves be a semiconductor device, or may include a semiconductor device.

[0031] In this specification, "connection" includes, for example, "electrical connection."

[0032] When the term "electrical connection" is used to define the connection relationship between circuit elements as an object, it includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, for example, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0033] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0034] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 16A1 and 16A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which current can flow. Note that "A and B are indirectly connected" also includes cases where one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which current can flow. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases where the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 16A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0035] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 16A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 16A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0036] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 16A6 and 16A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 16A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the relationship will be the same as in Figures 16A6 and 16A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0037] Although an example of "indirect connection" has been given above, as an example, the provision of "indirect connection" is included in the provision of "electrical connection," so when "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0038] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit element between them, as shown in FIGS. 16B1, 16B2, and 16B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, as shown in FIGS. 16B4 and 16B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," even when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 16B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0039] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0040] Note that even when independent components are shown connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has both the function of a wiring and the function of an electrode. Therefore, in this specification, the term "connection" also includes such a case where one conductive film has the functions of multiple components.

[0041] Furthermore, in this specification, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, a "resistance element" includes a wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, or a coil. Furthermore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be replaced with a resistance value of 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0042] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, or the gate capacitance of a transistor. The terms "capacitive element" and "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with the term "capacitive element" or "gate capacitance." A "capacitive element" (including a "capacitive element" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in a "capacitive element" can be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." The terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It may also be, for example, 1 pF or more and 10 μF or less.

[0043] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" are sometimes interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or the drain" and "the other of the source or the drain" are sometimes interchangeable. In addition, "one of the source or the drain" may be interchangeable with "first terminal" or "first electrode," and "the other of the source or the drain" may be interchangeable with "second terminal" or "second electrode." Note that, depending on the structure of the transistor, a backgate may be included in addition to the three terminals described above. In this specification, one of the gate or the backgate of the transistor may be referred to as a first gate, and the other of the gate or the backgate of the transistor may be referred to as a second gate. Furthermore, the terms "gate" and "back gate" may be interchangeable for the same transistor. When a transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, etc. in this specification.

[0044] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Alternatively, when operating in the saturation region, the multi-gate structure can provide voltage-current characteristics with a flat slope, such that the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0045] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor element, this includes two or more resistor elements connected in series. For example, when a circuit diagram shows one capacitor element, this includes two or more capacitor elements connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors connected in series, with the gates of the transistors connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors connected in series or in parallel, with the gates of the transistors connected to each other.

[0046] In this specification, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, or an impurity region depending on the circuit configuration and device structure. A terminal, a wiring, or the like can also be referred to as a node.

[0047] Furthermore, in this specification, the term "selector" may refer to, for example, a circuit having multiple input terminals and one output terminal, selecting one of the multiple input terminals, and establishing a conductive state between the selected input terminal and the one output terminal. In other words, the term "selector" may refer to a circuit that selects one of the input signals input to each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, the term "selector" may refer to, for example, a circuit having multiple output terminals and one input terminal, selecting one of the multiple output terminals, and establishing a conductive state between the selected output terminal and the one input terminal. In other words, the term "selector" may refer to a circuit that selects one of the multiple output terminals and outputs the input signal input to the input terminal to the selected output terminal. In other words, the term "selector" may refer to a multiplexer or a demultiplexer. In particular, when inputting or outputting an analog potential or an analog current, the selector may refer to an analog multiplexer or an analog demultiplexer.

[0048] Furthermore, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0049] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0050] In addition, in this specification, the term "high potential" can be appropriately replaced with "high level potential." In addition, in this specification, the term "low potential" can be appropriately replaced with "low level potential."

[0051] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0052] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0053] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, etc., and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0054] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0055] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0056] Furthermore, in this specification, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer". Furthermore, depending on the situation, the terms "film" and "layer" can be replaced with other terms without using them. For example, the terms "conductive layer" or "conductive film" can be changed to the term "conductor". Or, for example, the terms "insulating layer" or "insulating film" can be changed to the term "insulator".

[0057] Furthermore, the terms "electrode," "wiring," and "terminal" used herein do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0058] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, a term such as "signal line" may be changed to the term "power line." Furthermore, a term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, the term "signal" may be changed to the term "potential."

[0059] In addition, timing charts may be used in this specification to explain an operation method of a semiconductor device. The timing charts used in this specification illustrate ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potentials or currents) described in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including a node) in the timing charts described in this specification may be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as long and the other as short, the lengths of the two periods may be equal, or one period may be short and the other period may be long. For example, to clearly illustrate the timing charts, two or more overlapping signals may be intentionally shifted.

[0060] In this specification, the term "impurities in a semiconductor" refers to, for example, a substance other than the main component constituting the semiconductor layer. For example, an element having a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following problems: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity.

[0061] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or more terminals through which a current flows, in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific type as long as it has the function of controlling a current.

[0062] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0063] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0064] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0065] In this specification, the configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. When multiple configuration examples are shown in one embodiment, the configuration examples can be combined with each other as appropriate.

[0066] In addition, the content (part or all of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (part or all of the content) described in that embodiment and another content (part or all of the content) described in one or more other embodiments.

[0067] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0068] Furthermore, a figure (part or all) described in one embodiment can be combined with another part of that figure, another figure (part or all) described in that embodiment, and at least one figure (part or all) described in one or more other embodiments to form even more figures.

[0069] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0070] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Furthermore, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings or the like, the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0071] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences, etc. may be included.

[0072] Embodiment 1 In this embodiment, a memory device which is a semiconductor device of one embodiment of the present invention will be described.

[0073] <Configuration Example of Memory Device> Figures 1 to 6 show a configuration example of the memory device. Figure 1 is a schematic perspective view of the memory device SCD, and Figures 2A and 2B are schematic plan views of the memory device SCD. Figure 3 is a schematic plan view enlarging a portion of Figure 2A. Figure 4 is a schematic cross-sectional view corresponding to the portion of dashed dotted line A1-A2 shown in Figures 2A and 2B. Figure 5 is a schematic cross-sectional view corresponding to the portion of dashed dotted line A3-A4 shown in Figures 2A and 2B. Figure 6 is a schematic cross-sectional view corresponding to the portion of dashed dotted line A5-A6 shown in Figures 2A and 2B.

[0074] 2A, 2B, 4 and 5, a dashed line A7-A8 is shown to clarify the positional relationship.

[0075] 1, the direction in which the conductive layer ME1 (wiring WL) and the conductive layer ME6 (wiring PL) described later extend is defined as the X direction. Therefore, the directions of the dashed dotted lines A5-A6 and A7-A8 can also be referred to as the X direction. The direction in which the conductive layer ME3 (wiring BL) described later extends is defined as the Y direction. The direction perpendicular or substantially perpendicular to the X and Y directions is defined as the Z direction. The X and Y directions can also be perpendicular or substantially perpendicular to each other. The definitions of the X, Y, and Z directions may be similar or different in FIGS. 2A, 2B, 3, and 6. In describing the schematic plan views in FIGS. 2A to 3, the right side may be referred to as the +X direction, the left side as the −X direction, the upper side as the +Y direction, and the lower side as the −Y direction. 4 and the like, the right side may be referred to as the +X direction, the left side as the −X direction, the upper side as the +Z direction, and the lower side as the −Z direction. Also, in the description of the cross-sectional view in FIG. 6, the right side may be referred to as the +X direction, the left side as the −X direction, the upper side as the +Z direction, and the lower side as the −Z direction.

[0076] In order to clearly show the configuration of the memory device SCD, the perspective view shown in FIG. 1 shows only some of the conductive layers, insulating layers, and semiconductor layers shown in FIGS. 2 to 6.

[0077] 1 to 6, the memory device SCD has a substrate BS, a transistor Tr formed on the substrate BS, and a capacitance element CFE and a capacitance element DCF located above the transistor Tr. Specifically, as shown in FIG. 4, the memory device SCD has a memory cell MC, and the memory cell MC has a transistor Tr and a capacitance element CFE.

[0078] The memory cell MC is a storage circuit having one transistor and one capacitance element, and has a DRAM (Dynamic Random Access Memory) configuration. Furthermore, by using a material that can have ferroelectricity as the dielectric of the capacitance element, the capacitance element can be made into a ferroelectric capacitor, and the memory cell MC can have a FeRAM (Ferroelectric Random Access Memory) configuration.

[0079] The memory device SCD also has conductive layers ME1, ME2, ME3, ME4, ME5, ME6, insulating layers GI1, UI1, UI2, UI3, IS1, IS2, IS3, IS4, BI1, BI2, and FDI. Note that some of the components listed above may also be included in the transistor Tr, the capacitance element CFE, or the capacitance element DCF.

[0080] As an example, a semiconductor substrate (single crystal made of silicon, germanium, or the like) can be used as the substrate BS. Note that in this specification, the description will be given assuming that a single crystal substrate made of silicon is used as the substrate BS.

[0081] The transistor Tr will be described with reference to FIGS. 1 to 4. The transistor Tr is a transistor formed on a substrate BS, and a transistor region TA is formed by forming an element isolation layer ST in the substrate BS. Two trenches MZ are formed in one transistor region TA, and the two trenches MZ divide the low-resistance region included in the transistor region TA of the substrate BS into three. In FIG. 4, these are respectively shown as low-resistance region LRa, low-resistance region LRb, and low-resistance region LRc. Furthermore, semiconductor regions SAb and SAc are formed in the substrate BS corresponding to the side and bottom surfaces of the two trenches MZ. Note that the semiconductor regions SAb and SAc may also be referred to as channel formation regions.

[0082] That is, the transistor Tr has a semiconductor region SAb (or semiconductor region SAc) that is U-shaped in cross section, and low-resistance regions LRa and LRb (or low-resistance regions LRc) that face each other via the trench MZ in plan or cross section. As described above, two transistors Tr can be formed in the transistor region TA.

[0083] An insulating layer GI1 is located on the side and bottom surfaces of the trench MZ formed in the substrate BS. Furthermore, a conductive layer ME1 is located in the trench MZ in a region facing the semiconductor region SAb (or semiconductor region SAc) with the insulating layer GI1 interposed therebetween. Note that, as shown in FIGS. 1 to 3, the conductive layer ME1 is provided so as to extend in the X direction. Furthermore, an insulating layer UI1 is located so as to contact both the conductive layer ME1 and the insulating layer GI1 and to fill the remaining trench MZ.

[0084] The insulating layer GI1 functions as a gate insulating film of the transistor Tr and also as an insulating layer for preventing the low resistance region LRa from directly contacting the low resistance region LRb (or the low resistance region LRc).

[0085] The insulating layer GI1 may be made of, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0086] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0087] The conductive layer ME1 has a region that functions as the gate of the transistor Tr.

[0088] The conductive layer ME1 also has a region that functions as a wiring. For example, the conductive layer ME1 has a region that functions as a wiring WL, which will be described in Embodiment 2 below. In addition, in FIGS. 1 to 6, the conductive layer ME1 is also denoted in parentheses with WL[x]. Note that [x] indicates the ordinal number of the wiring. For example, in FIG. 4, the conductive layer ME1 having regions that function as gates of the four transistors Tr shown is denoted in parentheses with wiring WL[1], wiring WL[3], wiring WL[4], and wiring WL[6]. However, in this specification, [x] may not necessarily coincide with the row number or column number in the matrix.

[0089] In particular, in the memory device SCD, the conductive layer ME1 (wiring WL) functions as a word line for transmitting a selection signal when a write operation or a read operation is performed on the memory cell MC, and also functions as a word line for transmitting a non-selection signal when the memory cell MC is not the target for write or read.

[0090] In the conductive layer ME1, it is difficult to clearly separate the region that functions as the gate of the transistor Tr from the region that functions as wiring, and they may share the same region.

[0091] The conductive layer ME1 is preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, and lanthanum, an alloy containing two or more of the above-mentioned metal elements, or an alloy combining two or more of the above-mentioned metal elements. Furthermore, the conductive layer ME1 is preferably made of a conductive compound such as tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. In addition, the conductive layer ME1 may be made of a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element (e.g., phosphorus), or a silicide (e.g., nickel silicide).

[0092] By using a material with high electrical conductivity (a material with low electrical resistance), the power consumption of the memory device SCD can be reduced. In addition, by using a material with high electrical conductivity (a material with low electrical resistance), the amount of generated electric heat can be reduced, thereby reducing the influence of heat on the transistor Tr.

[0093] The conductive layer ME1 may also have a configuration in which multiple conductive layers made of the above-mentioned materials are stacked. For example, it may have a stacked structure in which the material containing the metal element described above and a conductive material containing oxygen are combined. It may also have a stacked structure in which the material containing the metal element described above and a conductive material containing nitrogen are combined. It may also have a stacked structure in which the material containing the metal element described above and a conductive material containing oxygen and a conductive material containing nitrogen are combined.

[0094] The materials listed above are merely examples, and it is preferable to select an appropriate material depending on the type of substrate used for the substrate BS. For example, if the substrate BS is a single-crystal substrate containing silicon, it is preferable to select a material for the conductive layer ME1 that does not contain metal elements that diffuse into the single-crystal substrate and do not degrade the electrical characteristics of the transistors formed on the substrate BS.

[0095] The insulating layer UI1 functions as a planarizing film that fills the grooves MZ and covers the uneven shape of the substrate BS. Similarly to the insulating layer GI1, the insulating layer UI1 also functions as an insulating layer that prevents the low resistance region LRa and the low resistance region LRb (or the low resistance region LRc) from directly contacting each other.

[0096] For example, the insulating layer UI1 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Alternatively, the insulating layer UI1 can be made of, for example, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because of their thermal stability. The material used for the insulating layer UI1 may also be an appropriate combination of the insulating materials described above. For example, the insulating layer UI1 may have a single-layer structure selected from the above materials, or a laminated structure combining the above materials.

[0097] The low-resistance regions LRa and LRb (or low-resistance region LRc) included in the transistor region TA function as source or drain regions in the transistor Tr. For example, one of the two transistors Tr included in the transistor region TA can be a transistor in which the low-resistance region LRa serves as one of the source or drain regions and the low-resistance region LRb serves as the other of the source or drain regions. Furthermore, for example, the other of the two transistors Tr included in the transistor region TA can be a transistor in which the low-resistance region LRa serves as one of the source or drain regions and the low-resistance region LRc serves as the other of the source or drain regions.

[0098] Next, the element isolation layer ST will be described with reference to FIG.

[0099] The element isolation layer ST functions as an insulating layer for electrically isolating adjacent transistor regions TA, for example. The element isolation layer ST may also be called an STI (Shallow Trench Isolation) region, an STI portion, or the like.

[0100] The element isolation layer ST includes, for example, an insulating layer UI2, an insulating layer UI3, and a conductive layer ME1.

[0101] The insulating layer UI2 functions as an insulating layer for electrically isolating adjacent transistor regions TA. The insulating layer UI2 also functions as an insulating layer for filling a part of a groove that is generated when multiple transistor regions TA are formed on the substrate BS. For these reasons, the insulating layer UI2 is located on the substrate BS, which corresponds to the side surface of the groove.

[0102] The insulating layer UI2 can be made of the same material as that used for the insulating layer UI1.

[0103] Furthermore, a conductive layer ME1 is provided in the trench so as to contact a portion of the insulating layer UI2. The conductive layer ME1 provided in the element isolation layer ST in FIG. 4 has, as an example, a region that functions as a wiring. For this reason, in FIG. 4 , the conductive layers ME1 included in the two element isolation layers ST shown are written in parentheses as wiring WL[2] and wiring WL[5], respectively. Furthermore, each of the conductive layer ME1 (wiring WL[2]) and the conductive layer ME1 (wiring WL[5]) has a region that functions as the gate of a transistor Tr in a cross-sectional view different from that in FIG. 2A to FIG. 3 , in particular, it can be seen that the conductive layer ME1 (wiring WL[2]) at a position different from the dashed-dotted line A1-A2 has a region that functions as the gate of another transistor Tr.

[0104] 4, the conductive layer ME1 included in the element isolation layer ST can be formed in the same process as the conductive layer ME1 having a region that functions as the gate of the transistor Tr. Therefore, the conductive layer ME1 included in the element isolation layer ST and the conductive layer ME1 having a region that functions as the gate of the transistor Tr can be made of the same material.

[0105] 4 and other figures, the depth direction length of the conductive layer ME1 provided in the element isolation layer ST and the depth direction length of the conductive layer ME1 provided in the trench MZ in the transistor region TA may be the same or different. For example, the depth direction length of the conductive layer ME1 provided in the element isolation layer ST may be longer or shorter than the depth direction length of the conductive layer ME1 provided in the trench MZ in the transistor region TA. The depth direction length of the conductive layer ME1 provided in the element isolation layer ST is determined by the depth of the element isolation layer ST formed in the substrate BS, the film thickness of the insulating layer UI2, etc.

[0106] The insulating layer UI3 functions as a planarizing film that fills the grooves of the element isolation layer ST and covers the uneven shape of the substrate BS. Similarly to the insulating layer UI2, the insulating layer UI3 also functions as an insulating layer that prevents adjacent transistor regions TA from directly contacting each other.

[0107] Therefore, the insulating layer UI3 can be made of a material that can be used for the insulating layer UI1 or the insulating layer UI2.

[0108] An insulating layer IS1 and an insulating layer BI1 are formed in this order on the upper surfaces of the transistor region TA and the element isolation layer ST of the substrate BS.

[0109] The insulating layer IS1 functions as an interlayer film for arranging wiring, capacitive elements, etc. above the transistor Tr. The insulating layer IS1 may be formed simultaneously with the insulating layer UI3. In other words, the insulating layer IS1 may function as a planarizing film that covers the uneven shape of the substrate BS.

[0110] The insulating layer IS1 can be made of the same material as the insulating layer UI1. In addition to the above, the insulating layer IS1 can also be made of a resin.

[0111] Furthermore, it is preferable to use a material with a low dielectric constant for the insulating layer IS1. By using a material with a low dielectric constant for the insulating layer IS1, the parasitic capacitance occurring between wirings (between conductive layers) can be reduced. For this reason, it is preferable to use one or more of the following materials with a low dielectric constant for the insulating layer IS1: silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies.

[0112] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0113] The insulating layer BI1 functions as an insulating film that separates the transistor Tr from a conductive layer, an insulating layer, etc. located above the insulating layer BI1. Specifically, the insulating layer BI1 functions as a barrier insulating film that suppresses the diffusion of impurities from above the insulating layer BI1 to the transistor Tr. Examples of impurities include materials that deteriorate the electrical characteristics of the transistor Tr. The insulating layer BI1 may also function as a barrier insulating film that suppresses the diffusion of oxygen to prevent the wiring from being oxidized and the resistance value of the wiring from increasing.

[0114] As a barrier insulating film having a function of suppressing oxygen permeation, for example, an insulator containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer. Specific examples of insulators having a function of suppressing oxygen permeation include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Furthermore, examples of insulators having a function of suppressing oxygen permeation include oxides containing aluminum and hafnium (hafnium aluminate). Furthermore, examples of insulators having a function of suppressing oxygen permeation include nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0115] The insulating layer IS1 and the insulating layer BI1 have a plurality of openings that reach the low-resistance regions LRa to LRc included in the transistor region TA of the substrate BS, and conductive layers ME2 that function as contact plugs (sometimes simply referred to as plugs) are embedded in these openings.

[0116] In particular, in this specification, the conductive layer ME2 in contact with the low-resistance region LRa may be referred to as a first plug, and the conductive layer ME2 in contact with the low-resistance region LRb or the low-resistance region LRc may be referred to as a second plug. Furthermore, as will be described in detail later, a conductive layer ME3 is formed on the upper surface of the conductive layer ME2, which is the first plug, and a conductive layer ME4 is formed on the upper surface of the conductive layer ME2, which is the second plug.

[0117] The conductive layer ME2, which functions as a plug, can be made of one or more conductive materials selected from metal materials, alloy materials, metal nitride materials, and metal oxide materials, either as a single layer or as a laminate. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and tungsten is preferred. Furthermore, it is preferable to use a low-resistance conductive material such as aluminum or copper as the material. The use of a low-resistance conductive material can reduce wiring resistance.

[0118] Furthermore, the conductive layer ME2 can be made of a material that can be used for the conductive layer ME1.

[0119] A conductive layer ME3 is formed on each of the upper surface of the insulating layer BI1 and the upper surface of the conductive layer ME2, which is the first plug. Note that, as shown in FIGS. 1 to 3, the conductive layer ME3 is provided so as to extend in the Y direction.

[0120] The conductive layer ME3 has a region that functions as a wiring. For example, the conductive layer ME3 has a region that functions as a wiring BL, which will be described in the second embodiment below. Also, in FIGS. 1 to 6, the conductive layer ME3 is also denoted with a symbol BL[x] in parentheses. Note that, like the conductive layer ME1, [x] indicates the ordinal number of the wiring. For example, in FIG. 4, the conductive layer ME3 is denoted with a wiring BL[2] and a wiring BL[3] in parentheses. However, in this specification, like the conductive layer ME1, [x] may not necessarily coincide with the row number or column number in the matrix.

[0121] In particular, in the memory device SCD, the conductive layer ME3 (wiring BL) functions as a bit line for transmitting a data signal to the memory cell MC.

[0122] The conductive layer ME3 is preferably made of a low-resistance material, similar to the wiring WL. As an example, the conductive layer ME3 may be made of a material that can be used for the conductive layer ME1 or ME2.

[0123] An insulating layer IS2 is formed on the upper surface of each of the insulating layer BI1 and the conductive layer ME3.

[0124] The insulating layer IS2 functions as an interlayer film, similar to the insulating layer IS1, and therefore, for example, the insulating layer IS2 can be made of a material that can be used for the insulating layer IS1.

[0125] The insulating layer IS2 has a plurality of openings that reach the insulating layer BI1 and the conductive layer ME2 that serves as the second plug. A conductive layer ME4 that functions as a plug is buried in these openings.

[0126] In particular, in this specification, the conductive layer ME4 in contact with the conductive layer ME2 functioning as the second plug may be referred to as a third plug.

[0127] As will be described in detail later, the conductive layer ME4 has a region that contacts the conductive layer ME5 to be formed later. Furthermore, the conductive layer ME5 is preferably located in a region that overlaps the conductive layer ME1. As described above, the conductive layer ME4 functions as a routing wiring for providing electrical continuity between the conductive layers ME2 and ME5. To provide electrical continuity between the conductive layers ME2 and ME5, it is preferable to provide a wiring layer between the conductive layers ME2 and ME5. That is, by forming an opening in the insulating layer IS2 for burying the routing wiring and then filling the opening with the conductive layer ME4, which functions as the routing wiring, the conductive layer ME5 can be formed in a region that overlaps the conductive layer ME1.

[0128] The conductive layer ME4 is preferably made of a low-resistance material, similar to the conductive layer ME2 having the function as a plug. As an example, the conductive layer ME4 can be made of a material that can be applied to the conductive layers ME1 to ME3.

[0129] An insulating layer BI2 and an insulating layer IS3 are formed in this order on the upper surfaces of the insulating layer IS2 and the conductive layer ME4, respectively.

[0130] Similar to the insulating layer BI1, the insulating layer BI2 functions as a barrier insulating film to suppress deterioration of the electrical characteristics of the transistor Tr, oxidation of the conductive layer, etc. For this reason, the insulating layer BI2 can be made of a material that can be applied to the insulating layer BI1.

[0131] The insulating layer IS3 functions as an interlayer film, similar to the insulating layers IS1 and IS2, and therefore, for example, the insulating layer IS3 can be made of a material that can be used for the insulating layers IS1 and IS2.

[0132] The insulating layer BI2 and the insulating layer IS3 have a plurality of openings that reach the conductive layer ME4, which is the third plug. The bottom of each opening may also include a partial region of the insulating layer IS2.

[0133] Furthermore, a conductive layer ME5 having a columnar shape is formed so as to include the opening and extend along the +Z direction. The bottom surface of the column may be an ellipse, a shape including a curve (for example, an ellipse, a cloud shape, a triangle with rounded corners, a polygon such as a square or a pentagon, etc.), a shape with corners (for example, a triangle, a polygon such as a square or a pentagon, etc.), or a shape that is a combination of these.

[0134] In this specification, a columnar body refers to a structure having a high aspect ratio in a cross-sectional view. For example, the aspect ratio of the conductive layer ME5 in the cross-sectional view of FIG. 4 refers to the ratio of the length H (which can be referred to as the height of the conductive layer ME5) in a direction perpendicular or approximately perpendicular to the surface on which the conductive layer ME5 is formed (e.g., one or both of the upper surface of the conductive layer ME4 and the upper surface of the insulating layer IS2) to the length L (which can be referred to as the width L of the conductive layer ME5) of the conductive layer ME5 in the direction of the dashed dotted line A1-A2. The aspect ratio of the conductive layer ME5 is preferably as large as possible without causing the conductive layer ME5 to collapse during the fabrication process of the capacitive element CFE or the capacitive element DCF. In other words, the height H of the conductive layer ME5 is preferably greater than the width L of the conductive layer ME5 without causing the conductive layer ME5 to collapse. In the above, the cross-sectional view of Figure 4 has been described as an example, but even in cross-sectional views other than Figure 4, it is preferable that the height H of the conductive layer ME5 be greater than the width L of the conductive layer ME5, as long as the conductive layer ME5 does not fall over.

[0135] In this specification, the term "columnar body" may be interchangeably referred to as "pillar." The columnar body or pillar may have a tapered shape. In this specification, the columnar body or pillar having a tapered shape may be referred to as a truncated cone.

[0136] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface. Alternatively, it refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the film surface underlying the structure. The angle between the inclined side surface and the substrate surface or the film surface is referred to as the taper angle. In this specification, a tapered shape having a taper angle greater than 0 degrees and less than 90 degrees is referred to as a forward taper shape, and a tapered shape having a taper angle greater than 90 degrees and less than 180 degrees is referred to as a reverse taper shape.

[0137] The conductive layer ME5 has a function as, for example, one of a pair of electrodes of the capacitance element CFE.

[0138] The conductive layer ME5 is preferably made of a low-resistance material, similar to, for example, the plugs, wiring, etc. As an example, the conductive layer ME5 can be made of a material that can be applied to the conductive layers ME1 to ME4.

[0139] Furthermore, the conductive layer ME5 can be formed, for example, by forming a sacrificial layer of the desired thickness on the upper surface of the insulating layer IS3, providing multiple openings in the sacrificial layer, the insulating layer IS3, and the insulating layer BI2 that reach the conductive layer ME4, burying the conductive layer ME5 in the multiple openings, and then removing the sacrificial layer.

[0140] An insulating layer FDI is formed on the upper surfaces of the insulating layer IS3 and the conductive layer ME5. In particular, the insulating layer FDI has a region that also contacts the side and upper surface of the conductive layer ME5, which is a columnar body. In addition, a conductive layer ME6 is formed on the upper surface of the insulating layer FDI. In particular, the conductive layer ME6 is formed so as to include a region that faces the conductive layer ME5 via the insulating layer FDI.

[0141] The insulating layer FDI has, for example, a region that functions as a dielectric of the capacitive element CFE.

[0142] For example, the insulating layer FDI can be made of a material that functions as a dielectric. For example, it is preferable to use a high-dielectric-constant (high-k) material as the dielectric. Specifically, for example, for the insulating layer FDI, a high-dielectric-constant material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide can be used. Alternatively, as another example, it is preferable to use an oxide containing one or both of aluminum and hafnium, more preferably an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and even more preferably hafnium oxide having an amorphous structure. Furthermore, as another example, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), or (Ba,Sr)TiO ３ By using a high dielectric constant material for the dielectric of the capacitance element CFE, the capacitance value can be increased, and the voltage written in the capacitance element CFE can be held for a long period of time.

[0143] Furthermore, a material capable of exhibiting ferroelectricity can be used for the insulating layer FDI. Furthermore, by using a material capable of exhibiting ferroelectricity for the insulating layer FDI, the capacitive element CFE can be made into a ferroelectric capacitor.

[0144] Materials that can have ferroelectricity include hafnium oxide, zirconium oxide, and hafnium zirconium oxide (HfZrO Ｘ (where X is a real number greater than 0), and the element J is added to hafnium oxide. １ (Element J here １ refers to one or more elements selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), and strontium (Sr), and zirconium oxide is doped with element J. ２ (Element J here ２Examples of materials that can have ferroelectricity include materials to which one or more elements selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), and strontium (Sr) are added. Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used. Furthermore, as a material that can have ferroelectricity, for example, a mixture or compound of a plurality of materials selected from the materials listed above may be used. Incidentally, hafnium oxide, zirconium oxide, zirconium hafnium oxide, and hafnium oxide containing element J may be used. １ The crystal structure (characteristics) of a material to which an ion beam is added may change depending not only on the film formation conditions but also on various processes. Therefore, in this specification, a material that exhibits ferroelectricity is not only called a ferroelectric but also called a material that can have ferroelectricity.

[0145] Among these, materials having hafnium oxide or materials having hafnium oxide and zirconium oxide are preferred as materials capable of exhibiting ferroelectricity, since they can exhibit ferroelectricity even in thin films of a few nanometers. This allows the process of fabricating a ferroelectric capacitor to be shortened. In this specification, a layer of a material capable of exhibiting ferroelectricity may be referred to as a ferroelectric layer or a metal oxide film.

[0146] When the insulating layer FDI is formed by atomic layer deposition (ALD) using a material containing hafnium oxide and zirconium oxide, for example, tetrakis(ethylmethylamido)hafnium (TEMAHf) or hafnium tetrachloride can be used as a precursor containing hafnium. Also, tetrakis(ethylmethylamido)zirconium (TEMAZr) or zirconium tetrachloride can be used as a precursor containing zirconium. Furthermore, H２ O and O ３ However, the oxidizing agent is not limited to these. For example, O ２ , O ３ , N ２ O, NO ２ , H ２ O and H ２ O ２ It can include one or more selected from the following.

[0147] Furthermore, the insulating layer FDI can have a single layer structure or a laminated structure. In particular, when the insulating layer FDI has a laminated structure, each insulating layer included in the insulating layer FDI can be made of, for example, one or both of the above-mentioned high-k material and the above-mentioned material that can have ferroelectricity.

[0148] The thickness of the insulating layer FDI is preferably 1 nm or more and 30 nm or less, more preferably 2 nm or more and 20 nm or less, and even more preferably 3 nm or more and 15 nm or less.

[0149] Furthermore, unlike paraelectrics, ferroelectric materials maintain their internal dielectric polarization even when no voltage is applied (sometimes called remanent polarization). Because the dielectric polarization is maintained, by using a ferroelectric capacitor for the capacitance element CFE, degradation of data stored in the memory cells MC is suppressed. This allows for a reduction in refresh operations for the memory cells MC, thereby reducing the power consumption of the memory device SCD.

[0150] The conductive layer ME6 has, for example, a region that functions as the other of the pair of electrodes of the capacitance element CFE.

[0151] 4, a capacitive element CFE can be formed in which a portion of the conductive layer ME5 serves as one of a pair of electrodes, a portion of the insulating layer FDI serves as a dielectric, and a portion of the conductive layer ME6 serves as the other of the pair of electrodes. Furthermore, by forming the conductive layer ME5 into a columnar body, the area of ​​the insulating layer FDI sandwiched between the pair of electrodes can be increased. This allows the threshold voltage distribution of data in the FeRAM to be increased, enabling the logic of "0" and "1" to be accurately read.

[0152] 1 to 3, the conductive layer ME6 is provided so as to extend in the X direction. Furthermore, in order to extend the conductive layer ME6 in the X direction, in addition to the capacitive element CFE, the memory device SCD is provided with a capacitive element DCF (not shown in FIG. 4), which will be described later, arranged side by side along the X direction, as shown in FIG. 3. Furthermore, in the plan view of FIGS. 2A to 3, the conductive layer ME6 has a shape in which adjacent circles overlap each other and multiple circles are arranged along the X direction. For this reason, the conductive layer ME6 is sometimes referred to as a rosary-shaped wiring.

[0153] The conductive layer ME6 also has a region that functions as a wiring. For example, the conductive layer ME6 has a region that functions as a wiring PL, which will be described in the second embodiment below. In addition, in FIGS. 1 to 6, the conductive layer ME6 is also denoted with a symbol PL[x] in parentheses. Note that, like the conductive layers ME1 and ME3, [x] indicates the ordinal number of the wiring. For example, in FIG. 4, the conductive layer ME6 is denoted with a wiring PL[1], a wiring PL[2], a wiring PL[3], a wiring PL[4], a wiring PL[5], and a wiring BL[6] in parentheses. However, in this specification, like the conductive layers ME1 and ME3, [x] may not necessarily coincide with the row number or column number in the matrix.

[0154] In particular, when the capacitive element CFE of the memory device SCD is a ferroelectric capacitor, the conductive layer ME6 (wiring PL) functions as a plate line for transmitting a predetermined signal when writing data to or reading data from the memory cell MC.

[0155] When the memory device SCD is a DRAM instead of an FeRAM, the conductive layer ME6 (wiring PL) preferably has a function as a wiring for applying a fixed potential.

[0156] Since the conductive layer ME6 functions as each of the wirings PL[1] to PL[6], it is necessary to electrically isolate adjacent wirings from each other. Specifically, after forming a film that will become the conductive layer ME6 on the insulating layer FDI, regions of the film that will become the conductive layer ME6 that will be between the wirings are removed by etching or the like so as to form each of the wirings PL[1] to PL[6].

[0157] The conductive layer ME6 is preferably made of a low-resistance material, similar to the conductive layers ME1 and ME3 that function as wirings. As an example, the conductive layer ME6 can be made of a material that can be applied to the conductive layers ME1 to ME5.

[0158] An insulating layer IS4 is formed on the upper surfaces of the insulating layer FDI and the conductive layer ME6.

[0159] The insulating layer IS4 functions as an interlayer film, similar to the insulating layers IS1 to IS3. Therefore, for the insulating layer IS4, for example, a material that can be applied to the insulating layers IS1 to IS3 can be used.

[0160] After the insulating layer IS4 is formed, the upper surface of the insulating layer IS4 may be planarized using chemical mechanical polishing (CMP). This allows further wiring, circuit elements, and the like to be formed above the insulating layer IS4. In this case, the memory device SCD can be treated as part of a monolithic stack configuration. For example, by providing a processing circuit, an arithmetic circuit, and the like above the memory device SCD, a new semiconductor layer can be realized in which data resulting from processing performed by the processing circuit, arithmetic circuit, and the like is temporarily stored in the memory device SCD.

[0161] Next, the capacitive element DCF of a dummy pattern provided to extend the conductive layer ME6 in the X direction will be described with reference to FIGS. 4, 5, 6, etc.

[0162] The insulating layer IS1 and the insulating layer BI1 have a plurality of openings that reach the element isolation layer ST of the substrate BS. In particular, in FIG. 5, the openings are formed in regions that overlap with the wiring ME1 (wiring WL[1], wiring WL[3], wiring WL[4], and wiring WL[6]). Furthermore, the openings are filled with conductive layers ME2 that function as plugs.

[0163] Depending on the situation, the opening may be formed in a region that does not overlap with the wiring ME1 (wiring WL[1], wiring WL[3], wiring WL[4], and wiring WL[6]).

[0164] In particular, in this specification, the conductive layer ME2 in contact with the element isolation layer ST may be referred to as a fourth plug.

[0165] The insulating layer IS2 has a plurality of openings that reach the conductive layer ME2, which is the fourth plug. A conductive layer ME4 that functions as a plug is buried in these openings. The openings may include a region that reaches the insulating layer BI1.

[0166] In particular, in this specification, the conductive layer ME4 in contact with the conductive layer ME2 functioning as the fourth plug may be referred to as a fifth plug.

[0167] The insulating layer BI2 and the insulating layer IS3 have a plurality of openings that reach the conductive layer ME4, which is the fourth plug. The bottom of each opening may also include a partial region of the insulating layer IS2.

[0168] Furthermore, a columnar conductive layer ME5 is formed along a direction that includes the opening and is substantially parallel to the +Z direction. In particular, this conductive layer ME5 is preferably formed in a region that overlaps with the wiring ME1 (wiring WL[1], wiring WL[3], wiring WL[4], and wiring WL[6]) in FIG. 5 . In other words, the opening provided in the insulating layer BI2 and the insulating layer IS3 is preferably formed in a region that overlaps with the wiring ME1 (wiring WL[1], wiring WL[3], wiring WL[4], and wiring WL[6]). The conductive layer ME5 filled in the opening functions as one of a pair of electrodes of the capacitance element DCF.

[0169] In the capacitive element DCF, like the capacitive element CFE, a portion of the conductive layer ME5 functions as one of a pair of electrodes, a portion of the insulating layer FDI functions as a dielectric, and a portion of the conductive layer ME6 functions as the other of the pair of electrodes. As described above, the conductive layer ME2, which is the fourth plug, is located on the upper surface of the element isolation layer ST, and the conductive layer ME4, which is the fifth plug, is not in contact with any conductive layers other than the conductive layers ME2 and ME5. Therefore, the conductive layer ME2, which is the fourth plug, and the conductive layers ME4 and ME5, which are the fifth plugs, are each in a floating state. In other words, because one of the pair of electrodes of the capacitive element DCF is in a floating state, the capacitive element DCF does not retain data, unlike the capacitive element CFE.

[0170] By forming the conductive layer ME5 as one of the pair of electrodes of the capacitance element DCF in a region overlapping the wiring ME1 (wiring WL[1], wiring WL[3], wiring WL[4], and wiring WL[6]), as shown in FIGS. 2A to 3 and 6 , the conductive layer ME5 as one of the pair of electrodes of the capacitance element DCF and the conductive layer ME5 as one of the pair of electrodes of the capacitance element CFE can be arranged to extend along the X direction. Furthermore, by forming the conductive layer ME6 so as to face these conductive layers ME5 via the insulating layer FDI, the capacitance element CFE and the dummy pattern capacitance element DCF can be arranged to extend along the X direction. This also allows the conductive layer ME6, which functions as the wiring PL, to extend along the X direction. This also allows the capacitance element CFE and the wiring PL to be formed simultaneously, thereby facilitating the fabrication of the memory device SCD. Furthermore, since there is no need to route the wiring PL over a long distance, the power consumption of the memory device SCD can be reduced.

[0171] Furthermore, when the memory device SCD is an FeRAM, it is preferable that the wirings functioning as word lines and the wirings PL functioning as plate lines extend in the same direction, parallel to each other, or approximately parallel to each other, as shown in Figures 1 to 6. In an FeRAM, a memory cell MC to which a selection signal is given from the wiring WL becomes a target for writing or reading, and a predetermined potential is given from the wiring PL to the target memory cell MC, so it is preferable that the wirings WL and the wiring PL extend in the same direction, parallel to each other, or approximately parallel to each other.

[0172] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0173] Embodiment 2 In this embodiment, structural examples of a memory device which is a semiconductor device of one embodiment of the present invention and a peripheral circuit included in the memory device will be described with reference to FIGS. 7 to 9B. FIG.

[0174] 7 shows an example of the configuration of a memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0175] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying the data signal read from the memory cell. Note that the above wiring is connected to the memory cell of the memory cell array 1470. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, a plate line driver circuit, etc., and can select the row to access.

[0176] The memory device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from the outside as power supply voltages. Control signals (CE, WEN, RES), an address signal ADDR, and a data signal WDATA are also input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0177] The control logic circuit 1460 processes control signals (CE, WEN, RES) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WEN is a write enable signal, and the control signal RES is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as needed.

[0178] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0179] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, wirings connected to the circuits, circuit elements, and the like may be changed, deleted, or added as necessary. The memory device of one embodiment of the present invention has high operating speed and can retain data for a long period of time.

[0180] FIG. 8 shows an example of the configuration of the memory cell array 1470 and memory cells MC.

[0181] The memory cell array 1470 shown in Fig. 8 has memory cells 1480 arranged in a matrix of m / 2 rows and n columns (m is an even number greater than or equal to 1, and n is an integer greater than or equal to 1). The memory cell 1480 shown in Fig. 8 is a storage circuit applicable to the memory cell MC described above, and is an example of a circuit configuration of a memory cell using a ferroelectric capacitor. Fig. 8 also shows a row circuit 1420 and a column circuit 1430.

[0182] 8, a memory cell 1480 includes a transistor M9 and a capacitance element Cfe. Here, in the memory cell 1480, the transistor M9 can correspond to the transistor Tr described in the first embodiment, and the capacitance element Cfe can correspond to the capacitance element CFE described in the first embodiment.

[0183] 8, m memory cells 1480 are connected to one wiring BL. Of the memory cells 1480 connected to the same wiring BL, the transistors Tr included in two memory cells arranged in the same row can be, for example, the two transistors included in the transistor area TA shown in FIG.

[0184] In the following description, attention is focused on one of the memory cells 1480 shown in FIG.

[0185] One of the source and drain of the transistor M9 is connected to a wiring BL (e.g., one of the wirings BL[1] to BL[n]). The other of the source and drain of the transistor M9 is connected to one of a pair of electrodes of a capacitor Cfe. The gate of the transistor M9 is connected to a wiring WL (e.g., one of the wirings WL[1] to WL[m]). The other of the pair of electrodes of the capacitor Cfe is connected to a wiring PL (e.g., one of the wirings PL[1] to PL[m]).

[0186] The wiring WL functions as a word line, and can control switching between an on state and an off state of the transistor M9 by applying a potential to the wiring WL as a selection signal or a non-selection signal. For example, the transistor M9 can be turned on by setting a selection signal applied to the wiring WL to a high potential (H), and the transistor M9 can be turned off by setting a non-selection signal applied to the wiring WL to a low potential (L). The wiring WL is connected to a word line driver circuit included in the row circuit 1420, and the word line driver circuit can apply a selection signal or a non-selection signal to the wiring WL.

[0187] The wiring BL functions as a bit line, and when the transistor M9 is on, a potential corresponding to a data signal applied to the wiring BL is applied to one of a pair of electrodes of the capacitor Cfe. The wiring BL is connected to a bit line driver circuit included in the column circuit 1430. The bit line driver circuit has a function of generating a data signal to be written to the memory cell MC. The bit line driver circuit also has a function of reading data output from the memory cell MC. Specifically, the bit line driver circuit is provided with a sense amplifier, and the data output from the memory cell MC can be read using the sense amplifier.

[0188] The wiring PL functions as a plate line. A predetermined potential is applied to the wiring PL to the other of the pair of electrodes of the capacitance element Cfe. The wiring PL is connected to a plate line driver circuit included in the row circuit 1420. The plate line driver circuit is, for example, a circuit that can apply the potential to the wiring PL during a write operation or a read operation.

[0189] The capacitance element Cfe has a dielectric layer between two electrodes made of a material that can have ferroelectricity. By using a ferroelectric layer that can be thinned as the dielectric layer of the capacitance element and combining it with a miniaturized transistor, a highly integrated memory device can be achieved. Hereinafter, the dielectric layer of the capacitance element Cfe will be referred to as the ferroelectric layer.

[0190] The ferroelectric layer of the capacitance element Cfe has a hysteresis characteristic. Fig. 9A is a graph showing an example of the hysteresis characteristic. In Fig. 9A, the horizontal axis represents the voltage applied to the ferroelectric layer. The voltage can be, for example, the difference between the potential of one of the pair of electrodes of the capacitance element Cfe and the potential of the other of the pair of electrodes of the capacitance element Cfe.

[0191] Further, in FIG. 9A, the vertical axis represents the polarization of the ferroelectric layer. When the value is positive, it indicates that the positive charge is biased to one side of the pair of electrodes of the capacitive element Cfe, and the negative charge is biased to the other electrode side of the pair of electrodes of the capacitive element Cfe. On the other hand, when the polarization has a negative value, it indicates that the positive charge is biased to the other side of the pair of electrodes of the capacitive element Cfe, and the negative charge is biased to one side of the pair of electrodes of the capacitive element Cfe.

[0192] Note that the voltage shown on the horizontal axis of the graph in FIG. 9A may be the difference between the potential of the other electrode of the pair of electrodes of the capacitive element Cfe and the potential of one electrode of the pair of electrodes of the capacitive element Cfe. Also, the polarization shown on the vertical axis of the graph in FIG. 9A may be set to a positive value when the positive charge is biased to the other electrode side of the pair of electrodes of the capacitive element Cfe and the negative charge is biased to one electrode side of the pair of electrodes of the capacitive element Cfe, and may be set to a negative value when the positive charge is biased to one electrode side of the pair of electrodes of the capacitive element Cfe and the negative charge is biased to the other electrode side of the pair of electrodes of the capacitive element Cfe.

[0193] As shown in FIG. 9A, the hysteresis characteristics of the ferroelectric layer can be represented by curve 61 and curve 62. Let the voltages at the intersections of curve 61 and curve 62 be VSP and -VSP. It can be said that VSP and -VSP have different polarities.

[0194] After applying a voltage of -VSP or lower to the ferroelectric layer and then increasing the voltage applied to the ferroelectric layer, the polarization of the ferroelectric layer increases according to curve 61. On the other hand, after applying a voltage of VSP or higher to the ferroelectric layer and then decreasing the voltage applied to the ferroelectric layer, the polarization of the ferroelectric layer decreases according to curve 62. Therefore, VSP and -VSP can each be referred to as a saturation polarization voltage. For example, VSP may be called the first saturation polarization voltage, and -VSP may be called the second saturation polarization voltage. Also, in FIG. 9A, the case where the absolute value of the first saturation polarization voltage is equal to the absolute value of the second saturation polarization voltage is shown, but the absolute values of the two may be different.

[0195] Here, Vc denotes the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to curve 61 and the polarization of the ferroelectric layer is zero. Furthermore, −Vc denotes the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to curve 62 and the polarization of the ferroelectric layer is zero. −Vc and Vc can be referred to as coercive voltages, respectively. The values ​​of Vc and Vc can be said to be values ​​between −VSP and VSP. For example, Vc may be referred to as the first coercive voltage, and −Vc may be referred to as the second coercive voltage. Furthermore, although FIG. 9A shows that the absolute values ​​of the first coercive voltage and the second coercive voltage are equal, the absolute values ​​of the two may be different.

[0196] Furthermore, when no voltage is applied to the ferroelectric layer, the maximum value of polarization is called "remanent polarization Pr" and the minimum value is called "remanent polarization -Pr". Furthermore, the difference between the remanent polarization Pr and the remanent polarization -Pr is called "remanent polarization 2Pr".

[0197] As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe can be expressed by the difference between the potential of one of the pair of electrodes of the capacitance element Cfe and the potential of the other of the pair of electrodes of the capacitance element Cfe. Also, as described above, the other of the pair of electrodes of the capacitance element Cfe is connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, the voltage applied to the ferroelectric layer of the capacitance element Cfe can be controlled.

[0198] 8 will be described. In the following description, the voltage applied to the ferroelectric layer of the capacitor Cfe is the difference (potential difference) between the potential of one of the pair of electrodes of the capacitor Cfe and the potential of the other of the pair of electrodes (wiring PL) of the capacitor Cfe. The transistor M9 is an n-channel transistor.

[0199] 9B is a timing chart showing an example of a method for driving the memory cell 1480. FIG. 9B shows an example of writing and reading binary digital data to the memory cell 1480. Specifically, FIG. 9B shows an example in which data “1” is written to the memory cell 1480 from time T01 to time T02, read and rewrite are performed from time T03 to time T05, read and write data “0” to the memory cell 1480 from time T11 to time T13, read and rewrite are performed from time T14 to time T16, and read and write data “1” to the memory cell 1480 from time T17 to time T19.

[0200] A reference potential Vref is supplied to the sense amplifier electrically connected to the wiring BL. In the read operation shown in Figure 9B, when the potential of the wiring BL is higher than Vref, data "1" is read by the bit line driver circuit. On the other hand, when the potential of the wiring BL is lower than Vref, data "0" is read by the bit line driver circuit.

[0201] Between time T01 and time T02, the word line driver circuit applies a high potential to the wiring WL as a selection signal. This turns on transistor M9. Also, the potential of wiring BL is set to Vw. Because transistor M9 is on, the potential of one of the pair of electrodes of capacitance element Cfe becomes Vw. Furthermore, GND is applied to wiring PL by the plate line driver circuit. As a result, the voltage applied to the ferroelectric layer of capacitance element Cfe becomes "Vw-GND." This allows data "1" to be written to memory cell 1480. Therefore, the period from time T01 to time T02 can be said to be a period during which a write operation is performed.

[0202] Here, Vw is preferably equal to or greater than VSP, for example. Although GND is a ground potential in this specification, it is not necessarily the ground potential as long as the memory cell 1480 can be driven to satisfy the spirit of one embodiment of the present invention. For example, if the absolute values ​​of the first and second saturation polarization voltages are different and the absolute values ​​of the first and second coercive voltages are different, GND can be a potential other than ground.

[0203] Between time T02 and time T03, the bit line driver circuit applies GND to the wiring BL, and the plate line driver circuit applies GND to the wiring PL. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes 0 V. Between time T01 and time T02, the voltage "Vw-GND" applied to the ferroelectric layer of the capacitance element Cfe can be made equal to or higher than VSP, and therefore, between time T02 and time T03, the polarization amount of the ferroelectric layer of the capacitance element Cfe changes according to curve 62 shown in FIG. 9A. As a result, between time T02 and time T03, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe.

[0204] After applying GND to both the wiring BL and the wiring PL, the word line driver circuit applies a low potential to the wiring WL as a non-selection signal, thereby turning off the transistor M9. This completes the write operation, and data "1" is stored in the memory cell 1480. The potentials of the wiring BL and the wiring PL can be set to any potential as long as no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe, i.e., the voltage applied to the ferroelectric layer of the capacitance element Cfe is equal to or greater than the second coercive voltage -Vc.

[0205] Between time T03 and time T04, the word line driver circuit applies a high potential to the line WL as a selection signal. This turns on the transistor M9. Furthermore, the plate line driver circuit applies Vw to the line PL. By setting the potential of the line PL to Vw, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw." As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe is "Vw-GND" between time T01 and time T02. Therefore, polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. During polarization reversal, a current flows through the line BL, and the potential of the line BL becomes higher than Vref. This allows the bit line driver circuit to read the data "1" stored in the memory cell 1480. Therefore, the period from time T03 to time T04 can be considered a period during which a read operation is performed. Note that although Vref is higher than GND and lower than Vw, it may also be higher than Vw, for example.

[0206] Since the above read is a destructive read, the data "1" held in memory cell 1480 is lost. Therefore, from time T04 to time T05, Vw is applied to the wiring BL by the bit line driver circuit, and GND is applied to the wiring PL by the plate line driver circuit. This rewrites the data "1" to memory cell 1480. Therefore, the period from time T04 to time T05 can be said to be the period during which the rewrite operation is performed.

[0207] From time T05 to time T11, the bit line driver circuit applies GND to the wiring BL, and the plate line driver circuit applies GND to the wiring PL. Then, the word line driver circuit applies a low potential as a non-selection signal to the wiring WL. This completes the rewrite operation, and data "1" is held in the memory cell 1480.

[0208] Between time T11 and time T12, the word line driver circuit applies a high potential to the wiring WL as a selection signal. Also, the plate line driver circuit applies a potential Vw to the wiring PL. Since data "1" is stored in the memory cell 1480, the potential of the wiring BL becomes higher than Vref, and the data "1" stored in the memory cell 1480 is read. Therefore, the period from time T11 to time T12 can be said to be a period during which a read operation is performed.

[0209] Between time T12 and time T13, the bit line driver circuit applies GND to the wiring BL. Since the transistor M9 is in the on state, the potential of one of the pair of electrodes of the capacitance element Cfe becomes GND. In addition, the plate line driver circuit applies a potential Vw to the wiring PL. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw." This allows data "0" to be written to the memory cell 1480. Therefore, the period from time T12 to time T13 can be said to be a period during which a write operation is performed.

[0210] From time T13 to time T14, GND is applied to the line BL by the bit line driver circuit, and GND is applied to the line PL by the plate line driver circuit. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes 0 V. Since the voltage "GND-Vw" applied to the ferroelectric layer of the capacitance element Cfe from time T12 to time T13 can be set to -VSP or less, the polarization amount of the ferroelectric layer of the capacitance element Cfe changes according to the curve 61 shown in FIG. 9A from time T13 to time T14. As a result, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe from time T13 to time T14.

[0211] After applying GND to the wiring BL and the wiring PL, the word line driver circuit applies a low potential to the wiring WL as a non-selection signal, thereby turning off the transistor M9. This completes the write operation, and data "0" is stored in the memory cell 1480. The potentials of the wiring BL and the wiring PL can be set to any potential as long as no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe, i.e., the voltage applied to the ferroelectric layer of the capacitance element Cfe is equal to or lower than the first coercive voltage Vc.

[0212] Between time T14 and time T15, the word line driver circuit applies a high potential to the line WL as a selection signal. This turns on the transistor M9. The plate line driver circuit also applies a potential Vw to the line PL. By setting the potential of the line PL to Vw, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw." As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe is "GND-Vw" between time T12 and time T13. Therefore, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. Therefore, the amount of current flowing through the line BL is smaller than when polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. As a result, the increase in the potential of the line BL is smaller than when polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. Specifically, the potential of the line BL is equal to or lower than Vref. Therefore, the bit line driver circuit can read the data "0" stored in the memory cell 1480. Therefore, the period from time T14 to time T15 can be said to be a period during which a read operation is performed.

[0213] From time T15 to time T16, the bit line driver circuit applies GND to the wiring BL, and the plate line driver circuit applies a potential Vw to the wiring PL, thereby rewriting data "0" to the memory cell 1480. Therefore, the period from time T15 to time T16 can be said to be a period during which a rewrite operation is performed.

[0214] Between time T16 and time T17, the bit line driver circuit applies GND to the wiring BL, and the plate line driver circuit applies GND to the wiring PL. After that, the word line driver circuit applies a low potential as a non-selection signal to the wiring WL. This completes the rewrite operation, and data "0" is held in the memory cell 1480.

[0215] Between time T17 and time T18, the word line driver circuit applies a high potential to the wiring WL as a selection signal. Furthermore, the plate line driver circuit applies a potential Vw to the wiring PL. Since data "0" is stored in the memory cell 1480, the potential of the wiring BL becomes lower than Vref, and the data "0" stored in the memory cell 1480 is read out. Therefore, the period from time T17 to time T18 can be considered a period during which a read operation is performed.

[0216] Between time T18 and time T19, the bit line driver circuit applies a potential Vw to the wiring BL. Because the transistor M9 is on, the potential of one electrode of the capacitance element Cfe becomes Vw. In addition, the plate line driver circuit applies a potential GND to the wiring PL. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "Vw-GND." This allows data "1" to be written to the memory cell 1480. Therefore, the period from time T18 to time T19 can be said to be the period during which the write operation is performed.

[0217] After time T19, the bit line driver circuit applies GND to the line BL, and the plate line driver circuit applies GND to the line PL. Then, the word line driver circuit applies a low potential to the line WL as a non-selection signal. This completes the write operation, and data "1" is stored in the memory cell 1480.

[0218] A semiconductor device using a ferroelectric layer for the capacitance element Cfe functions as a nonvolatile memory element that can retain written information even when the power supply is stopped.

[0219] Furthermore, DRAM requires periodic refresh operations, which increases power consumption. A semiconductor device using a ferroelectric layer for the capacitance element Cfe does not require refresh operations, so power consumption can be reduced.

[0220] In this specification and the like, a memory element or a memory circuit including a ferroelectric layer may be referred to as a "ferroelectric memory" or an "FE memory." Therefore, a semiconductor device according to one embodiment of the present invention is both a ferroelectric memory and an FE memory. The FE memory has a capacitance of 1×10 １０ or more, preferably 1×10 １２ or more, more preferably 1×10 １５ The FE memory can be expected to achieve an operating frequency of 10 MHz or more, preferably 1 GHz or more.

[0221] Furthermore, in FE memory, there is a correlation between the remanent polarization 2Pr and data retention capacity, and as the remanent polarization 2Pr decreases, the data retention capacity decreases. In this specification, the period until the remanent polarization 2Pr decreases by 5% (the data retention capacity decreases by 5%) is referred to as the "memory retention period." FE memory can be expected to achieve a memory retention period of one day or more, preferably ten days or more, more preferably one year or more, and even more preferably ten years or more in a temperature environment of 150°C or 200°C.

[0222] The FE memory can also be applied to cache memories and registers of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc. By combining the FE memory with the cache memory and registers of a CPU, a normally-off CPU (NoffCPU (registered trademark)) can be realized. By combining the FE memory with the cache memory and registers of a GPU, a normally-off GPU (NoffGPU (registered trademark)) can be realized.

[0223] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0224] Embodiment 3 In this embodiment, an example of an applicability range of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0225] In semiconductor devices such as computers, various memory devices are used depending on the application. Figure 10 shows a conceptual diagram illustrating the hierarchy of memory devices used in semiconductor devices. In Figure 10, the conceptual diagram illustrating the hierarchy of memory devices is shown as a triangle, with memory devices located higher in the triangle being required to have a faster operating speed, and memory devices located lower in the triangle being required to have a larger memory capacity and a higher recording density.

[0226] In FIG. 10 , from the top layer of the triangle, memories integrated as registers into arithmetic processing units such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and an NPU (Neural Processing Unit), cache memories (sometimes simply referred to as caches, and typically L1, L2, and L3 caches), main memories such as DRAMs (Dynamic Random Access Memory), and storage memories such as 3D NANDs and hard disks (also called HDDs: Hard Disk Drives) are shown.

[0227] The memory embedded as a register in a processing unit such as a CPU, GPU, or NPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a high operating speed is required rather than a large storage capacity. Registers also have the function of storing setting information for the processing unit.

[0228] A cache memory has a function of duplicating and storing part of data stored in a DRAM. By duplicating frequently used data and storing it in the cache memory, the speed of accessing the data can be increased. A cache memory is required to have a smaller storage capacity than a DRAM, but a faster operating speed than a DRAM. Data rewritten in the cache memory is duplicated and supplied to the DRAM. Note that although only the L3 cache is illustrated in FIG. 10 , the cache memory is not limited to this. For example, a memory device using an oxide semiconductor of one embodiment of the present invention can be suitably used for a last level cache (LLC) or a final level cache (FLC), which are located at the lowest level of a cache.

[0229] The DRAM has the function of holding programs, data, etc. read from the 3D NAND.

[0230] 3D NAND has the function of storing data that requires long-term storage, various programs used in computing devices (e.g., artificial neural network models), etc. Therefore, 3D NAND requires large storage capacity and high recording density rather than fast operating speed.

[0231] Hard disks have large capacity and are non-volatile. Instead of hard disks, solid state drives (SSDs) can be used.

[0232] A memory device having a capacitor element including a ferroelectric according to one embodiment of the present invention is capable of retaining data for a long period of time. Therefore, it is suitable for use in the region of Target 1 shown in FIG. 10 . As indicated by the diagonal hatching in FIG. 10 , Target 1 also includes a portion of the cache (L1, L2, L3) and a portion of the 3D NAND. In other words, Target 1 includes the boundary region between the DRAM and the 3D NAND, and the boundary region between the DRAM and the cache (L1, L2, L3). Furthermore, a memory device having a capacitor element including a ferroelectric according to one embodiment of the present invention has a high operating speed, enabling it to achieve excellent write and read operations. Therefore, it is suitable for use in the region of Target 2 shown in FIG. 10 .

[0233] For example, it is preferable to replace the DRAM shown in FIG. 10 with a memory device having a capacitor including a ferroelectric according to one embodiment of the present invention. Here, since a refresh operation is essential for a DRAM, the power consumption is higher than that of other memory devices. Therefore, by replacing the DRAM with a memory device having a capacitor including a ferroelectric, power consumption can be reduced. This configuration can reduce power consumption to half or less, preferably one-tenth or less, more preferably one-hundredth or less, and even more preferably one-thousandth or less, of that of a configuration using a DRAM.

[0234] Another means for reducing power consumption is a configuration in which a storage device such as a DRAM or an FeRAM (including the semiconductor device of one embodiment of the present invention) is stacked on an arithmetic processing device such as a CPU, a GPU, or an NPU. A configuration in which an arithmetic processing device and a storage device are stacked is called a monolithic stack. By configuring the arithmetic processing device and the storage device as a monolithic stack, for example, the power consumption required for data access between the arithmetic processing device and the storage device can be significantly reduced. Therefore, by deploying information processing devices including supercomputers (also called high performance computers (HPCs)), computers, servers, and the like to which such a configuration is applied throughout the world, global warming can be suppressed.

[0235] As described above, the memory device including an oxide semiconductor according to one embodiment of the present invention can be applied to a wide range of memories, from memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs to memories located in the boundary region between DRAMs and 3D NANDs.

[0236] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0237] 11A and 11B , an example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0238] As shown in FIG. 11A , the chip 1200 includes a CPU 1211 , a GPU 1212 , one or more analog arithmetic units 1213 , one or more memory controllers 1214 , one or more interfaces 1215 , and one or more network circuits 1216 .

[0239] 11B, the chip 1200 is provided with bumps (not shown), which are connected to a first surface of a package substrate 1201. In addition, a plurality of bumps 1202 are provided on the back surface of the package substrate 1201 opposite the first surface, which is connected to a motherboard 1203.

[0240] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 and the flash memory 1222 may be replaced with the storage device SCD described in the first embodiment.

[0241] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The memory may be the storage device SCD described above. The GPU 1212 is suitable for parallel calculation of a large amount of data, and may be used for image processing or multiply-and-accumulate operations.

[0242] Furthermore, since the CPU 1211 and GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0243] The analog calculation unit 1213 has one or both of an AD (analog-digital) conversion circuit and a DA (digital-analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0244] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0245] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a Universal Serial Bus (USB) or a High-Definition Multimedia Interface (HDMI (registered trademark)) can be used.

[0246] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0247] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0248] A package substrate 1201 on which a chip 1200 having a GPU 1212 is provided, and a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204.

[0249] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a smaller size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, the product-sum operation circuit included in the GPU 1212 enables calculations such as deep neural networks (DNNs), which are AI models. Representative examples of AI models include convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0250] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0251] Embodiment 5 In this embodiment, an application example of a semiconductor device using a memory device according to one embodiment of the present invention will be described. The memory device SCD described in the above embodiment can be applied to various removable memory devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives) as a cache memory or a main memory. Several configuration examples of removable memory devices are schematically shown in FIGS. 12A to 12E. The semiconductor device according to one embodiment of the present invention is processed into a packaged memory chip and used in various storage devices and removable memories.

[0252] 12A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. A semiconductor device of one embodiment of the present invention can be incorporated into the memory chip 1105 or the like.

[0253] FIG. 12B is a schematic diagram of the appearance of an SD card, and FIG. 12C is a schematic diagram of the internal structure of the SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing a memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Furthermore, a wireless chip with a wireless communication function may be provided on the substrate 1113. This enables reading and writing of data from and to the memory chip 1114 through wireless communication between a host device and the SD card 1110. A semiconductor device of one embodiment of the present invention can be incorporated into the memory chip 1114 or the like.

[0254] FIG. 12D is a schematic diagram of the appearance of an SSD, and FIG. 12E is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory for the controller chip 1156, and may be, for example, a DOSRAM chip. By providing a memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. A semiconductor device of one embodiment of the present invention can be incorporated into the memory chip 1154 or the like.

[0255] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0256] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiments will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0257] [Electronic Component] Fig. 13A shows a perspective view of electronic component 700. Electronic component 700 shown in Fig. 13A has a substrate 701, a semiconductor device 710 on substrate 701, and a mold 711. In particular, semiconductor device 710 is sealed by mold 711. Note that Fig. 13A omits some parts of electronic component 700 in order to show the interior of electronic component 700.

[0258] The substrate 701 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.

[0259] Electronic component 700 is provided with, for example, a lead frame 712. A portion of lead frame 712 located on substrate 701 is covered with mold 711, and another portion of lead frame 712 is exposed to the outside of mold 711. In particular, lead frame 712 exposed to the outside of mold 711 functions as, for example, a terminal for mounting electronic component 700 on a printed circuit board.

[0260] Within mold 711, electrode pads 713 are provided on lead frame 712, and electrode pads 713 are connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on a printed circuit board, for example, by contacting lead frame 712 with wiring on the printed circuit board. In this way, a mounted board is completed by combining multiple electronic components and connecting them on the printed circuit board.

[0261] Next, the semiconductor device 710 will be described. For example, as shown in FIG. 13B , the semiconductor device 710 has a drive circuit layer 715 and a memory layer 716. The memory layer 716 can be configured by stacking a plurality of memory cell arrays. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. Configurations other than the monolithic stacked configuration include a configuration in which a plurality of memory layers 716 are stacked using through-electrode technology (e.g., TSV (Through Silicon Via)) and Cu-Cu direct bonding technology. By configuring the drive circuit layer 715 and the memory layer 716 in a stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration makes it possible to increase the operation speed of the interface between the processor and the memory.

[0262] Furthermore, the semiconductor device 710 has a configuration in which multiple memory cell arrays are stacked, which can improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange.

[0263] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0264] Next, Fig. 13C shows a modified example of electronic component 700. Electronic component 700A shown in Fig. 13C differs from electronic component 700 in that it does not use lead frame 712, but has electrodes 733 provided on the bottom of substrate 701. Electrodes 733 function as connection terminals for mounting electronic component 700A on a printed circuit board.

[0265] 13C shows an example in which electrodes 733 are formed using solder balls. By providing solder balls in a matrix on the bottom of substrate 701, BGA (Ball Grid Array) mounting can be achieved. For this purpose, through-hole vias (penetrating vias) are provided in substrate 701, and conductive layers 732 that function as wiring are provided in these vias. Electrode pads 713 are provided above conductive layer 732 on substrate 701 so as to be in contact with them, and electrodes 733 are provided below conductive layer 732 below substrate 701 so as to be in contact with them.

[0266] Furthermore, the electrodes 733 may be formed of conductive pins instead of solder balls. By providing conductive pins in a matrix on the bottom of the substrate 701, PGA (Pin Grid Array) mounting can be achieved.

[0267] Furthermore, electronic component 700A can be mounted on other substrates using various mounting methods other than BGA and PGA, such as staggered pin grid array (SPGA), land grid array (LGA), quad flat package (QFP), quad flat J-leaded package (QFJ), and quad flat non-leaded package (QFN).

[0268] 13D , an electronic component 700C includes an interposer 731 provided over a package substrate 734 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided over the interposer 731.

[0269] 13D illustrates an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). For example, the semiconductor device 735 can be used as an arithmetic circuit in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0270] The package substrate 734 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate, similar to the substrate 701. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0271] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 734. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 734 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0272] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0273] Furthermore, in SiP and MCM using silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on the interposer.

[0274] Furthermore, if the temperature of the electronic component 700C increases due to heat generated by electric current or the like, the characteristics of the circuit elements (e.g., transistors) included in the electronic component 700C may be degraded. Therefore, it is preferable to provide a heat sink (heat sink) on the electronic component 700C so that the heat sink overlaps the electronic component 700C. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 700C shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the semiconductor device 735.

[0275] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 14A . The electronic device 6500 shown in FIG. 14A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. The semiconductor device of one embodiment of the present invention can be included in the electronic device 6500 as a main memory. The semiconductor device of one embodiment of the present invention can also be included in, for example, the display portion 6502, the control device 6509, or the like.

[0276] 14B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, and a control device 6616. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. The semiconductor device of one embodiment of the present invention can be included in the electronic device 6600 as a main memory. The semiconductor device of one embodiment of the present invention can also be included in the display portion 6615, the control device 6616, and the like.

[0277] The semiconductor device of one embodiment of the present invention is preferably provided in the electronic devices 6500 and 6600 because power consumption can be reduced.

[0278] 14C shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 14C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0279] The computer 5620 can have the configuration shown in the perspective view in Fig. 14D, for example. In Fig. 14D, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0280] A PC card 5621 shown in Figure 14E is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 5621 includes a board 5622. The board 5622 also includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Figure 14E illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for these semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 may be referred to.

[0281] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0282] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0283] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0284] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 700 can be used as the semiconductor device 5627.

[0285] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wirings of the board 5622. For example, the semiconductor device 5628 can be a memory device which is a semiconductor device of one embodiment of the present invention. For example, the electronic component 700 described above can be used for the semiconductor device 5628.

[0286] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0287] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as equipment for processing and storing information.

[0288] Fig. 15A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 15A, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0289] Although not shown in FIG. 15A, the secondary battery 6805 may be provided with a battery management system (also referred to as BMS) or a battery control circuit.

[0290] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0291] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0292] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0293] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably formed using a semiconductor device which is one embodiment of the present invention.

[0294] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0295] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0296] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to install storage and servers for storing a huge amount of data, to ensure a stable power supply for maintaining the data, or to ensure cooling equipment required for maintaining the data.

[0297] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0298] Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0299] Fig. 15B shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 15B has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0300] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0301] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0302] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0303] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0304] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0305] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configuration, structure, method, etc. shown in this embodiment can be appropriately combined and used with another configuration, structure, method, etc. shown in this embodiment. Furthermore, for example, the configuration, structure, method, etc. shown in this embodiment can be appropriately combined and used with the configuration, structure, method, etc. shown in other embodiments. [Explanation of Symbols] BL: wiring, BS: substrate, CFE: capacitive element, Cfe: capacitive element, DCF: capacitive element, FDI: insulating layer, GI: insulating layer, LRa: low resistance region, LRb: low resistance region, LRc: low resistance region, MC: memory cell, MZ: trench, PL: wiring, SAb: semiconductor region, SAc: semiconductor region, SCD: memory device, ST: element isolation layer, T11: time, T12: time, T13: time, T14: time, T15: time, T16: time, T17: time, T18: time, T 19: Time, TA: Transistor area, Tr: Transistor, TrP: Transistor, TrQ: Transistor, WL: Wiring, 61: Curve, 62: Curve, 700: Electronic component, 700A: Electronic component, 700C: Electronic component, 701: Substrate, 710: Semiconductor device, 711: Mold, 712: Lead frame, 713: Electrode pad, 714: Wire, 715: Drive circuit layer, 716: Memory layer, 731: Interposer, 732: Conductive layer, 733: Electrode, 73 4: package substrate, 735: semiconductor device, 1100: USB memory, 1101: housing, 1102: cap, 1103: USB connector, 1104: substrate, 1105: memory chip, 1106: controller chip, 1110: SD card, 1111: housing, 1112: connector, 1113: substrate, 1114: memory chip, 1115: controller chip, 1150: SSD, 1151: housing, 1152: connector, 1153: substrate, 115 4: memory chip, 1155: memory chip, 1156: controller chip, 1200: chip, 1201: package substrate, 1202: bump, 1203: motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: analog calculation unit, 1214: memory controller, 1215: interface, 1216: network circuit, 1221: DRAM, 1222: flash memory, 1400: storage device,1411: peripheral circuit, 1420: row circuit, 1430: column circuit, 1440: output circuit, 1460: control logic circuit, 1470: memory cell array, 1480: memory cell, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button Tan, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 6613: pointing device, 6614: external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: storage system, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device,

Claims

a substrate, an element isolation layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first insulating layer, a first plug, a second plug, a third plug, a fourth plug, and a fifth plug; the substrate has a first low-resistance region that functions as one of a source or a drain of a transistor, a second low-resistance region that functions as the other of the source or the drain of the transistor, and a semiconductor region in which a channel of the transistor is formed; the transistor has a portion of the first conductive layer that functions as a gate; the first insulating layer comprises a material that may have ferroelectric properties; In a cross-sectional view, a height of the third conductive layer is greater than a width of the third conductive layer; In a cross-sectional view, a height of the fourth conductive layer is greater than a width of the fourth conductive layer; the first plug has a region in contact with the first low-resistance region, the second conductive layer has a region in contact with the first plug; the second plug has a region in contact with the second low-resistance region, the third plug has a region in contact with the second plug, the third conductive layer is located in a region that contacts an upper surface of the third plug and overlaps with the first conductive layer in a plan view; the fourth plug has a region in contact with the element isolation layer, the fifth plug has a region in contact with the fourth plug, the fourth conductive layer is in contact with an upper surface of the fifth plug and is located in a region overlapping the element isolation layer in a plan view; the first insulating layer has regions in contact with side surfaces and top surfaces of the third conductive layer and the fourth conductive layer, the fifth conductive layer has a region that overlaps the first conductive layer and is in contact with a side surface and an upper surface of the first insulating layer in a plan view; the first conductive layer and the fifth conductive layer are each positioned to extend in a first direction; the second conductive layer is positioned to extend in a second direction; The first direction and the second direction are approximately perpendicular to each other. Semiconductor device. 　 In claim 1, The material that can have ferroelectric properties has an oxide containing one or both of hafnium and zirconium. Semiconductor device.

3. The method according to claim 1 or 2, further comprising: the substrate has a groove; the groove is located between the first low resistance region and the second low resistance region in a plan view, the second insulating layer is located in a region in contact with a side surface and a bottom surface of the groove, the semiconductor region is located in a region facing the first conductive layer with the second insulating layer interposed therebetween; Semiconductor device.

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