Semiconductor device and method for producing semiconductor device

Abstract

The present invention provides a highly reliable semiconductor device. This semiconductor device has: a base insulating film; and a semiconductor layer, an electroconductive layer, a first interlayer insulating film, and a second interlayer insulating film, on the base insulating film. The first interlayer insulating film is in contact with at least part of the side surface of the electroconductive layer. The second interlayer insulating film is positioned on the first interlayer insulating film and on the electroconductive layer. The first and second interlayer insulating films have a groove. The groove has a region reaching the electroconductive layer. The groove is provided as a recess in the first interlayer insulating film within a region that does not overlap the electroconductive layer. The semiconductor layer has a region in contact with the electroconductive layer within the groove, and a region extending along part of the side wall of the groove. The upper surfaces of the first and second interlayer insulating films can be made flat. The electroconductive layer functions as one of a source electrode or a drain electrode of a transistor. The other of the source electrode or the drain electrode of the transistor is provided on the second interlayer insulating film, and a gate insulating layer and a gate electrode are provided within the groove.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories (storage devices), etc. A CPU is an aggregate of semiconductor elements that have integrated circuits (including transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Integrated circuits (ICs) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, metal oxides have also attracted attention as other semiconductor materials.

[0007] Furthermore, it is known that transistors using metal oxides have extremely low leakage current in an off state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the low leakage current characteristic of transistors using metal oxides. Furthermore, for example, Patent Document 2 discloses a memory device that can retain stored content for a long period of time by utilizing the low leakage current characteristic of transistors using metal oxides.

[0008] In recent years, with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using a metal oxide film and a second transistor using a metal oxide film to provide multiple overlapping memory cells. Patent Document 4 also discloses a technique for increasing the density of integrated circuits by vertically arranging the channels of transistors using a metal oxide film.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0010] M. Oota et al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0011] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized and highly integrated.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device that can be manufactured at low cost.An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high on-state current.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with low parasitic capacitance.

[0012] An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device that can be miniaturized and highly integrated.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high yield.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device at low cost.An object of one embodiment of the present invention is to provide a method for manufacturing a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high operating speed.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device including a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device including a transistor with high on-state current.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device including a transistor with low parasitic capacitance.

[0013] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0014] One embodiment of the present invention is a semiconductor device including a semiconductor layer, a conductive layer, a first insulating layer, and a second insulating layer, wherein the first insulating layer is in contact with at least a part of a first side surface of the conductive layer and at least a part of a second side surface opposite to the first side surface, the second insulating layer is located on the first insulating layer and the conductive layer, the first insulating layer has a first groove, and the second insulating layer has a second groove overlapping with the first groove, the first groove has a region reaching the conductive layer and a region provided as a recess, and the semiconductor layer has a region in contact with the conductive layer and a region along a part of a side surface of the second insulating layer in the second groove.

[0015] Alternatively, in the above aspect, the thickness of the first insulating layer in a region where the first groove portion is not provided and where the first insulating layer does not overlap with the conductive layer may be 0.5 times or more the thickness of the conductive layer.

[0016] Alternatively, in the above aspect, the semiconductor device may have a fourth insulating layer, the fourth insulating layer being located on the second insulating layer, the fourth insulating layer having a first groove portion and a third groove portion overlapping with the second groove portion, and the thickness of the fourth insulating layer may be less than the thickness of the first insulating layer in a region where the first groove portion is not provided and where the fourth insulating layer does not overlap with the conductive layer.

[0017] Alternatively, in the above aspect, the first insulating layer may have a region in contact with the upper surface of the conductive layer.

[0018] Alternatively, in the above aspect, the thickness of the first insulating layer in the region overlapping with the conductive layer may be less than the thickness of the conductive layer.

[0019] Alternatively, one embodiment of the present invention includes a transistor, a first insulating layer, and a second insulating layer. The transistor includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and the third insulating layer. The first insulating layer is in contact with at least a part of a first side surface of the first conductive layer and at least a part of a second side surface opposite to the first side surface. The second insulating layer is located over the first insulating layer and the first conductive layer. The second conductive layer is located over the second insulating layer. The first insulating layer has a first groove. the insulating layer has a second groove overlapping the first groove, the first groove having a region reaching the first conductive layer and a region provided as a recess, the semiconductor layer has a region in contact with the first conductive layer, a region in contact with the second conductive layer, and a region along a part of a side surface of the second insulating layer in the second groove, the third insulating layer is provided on the semiconductor layer so as to have a region located within the second groove, and the third conductive layer has a region facing the semiconductor layer within the second groove with the third insulating layer sandwiched therebetween.

[0020] Alternatively, in the above aspect, the thickness of the first insulating layer in the region where the first groove portion is not provided and where the first insulating layer does not overlap with the first conductive layer may be 0.5 times or more the thickness of the first conductive layer.

[0021] Alternatively, in the above aspect, the semiconductor device may have a fourth insulating layer, the fourth insulating layer being located on the second insulating layer, the second conductive layer being located on the fourth insulating layer, the fourth insulating layer having a first groove portion and a third groove portion overlapping with the second groove portion, and the thickness of the fourth insulating layer may be less than the thickness of the first insulating layer in a region where the first groove portion is not provided and where the fourth insulating layer does not overlap with the first conductive layer.

[0022] Alternatively, in the above aspect, the first insulating layer may have a region in contact with the upper surface of the first conductive layer.

[0023] Alternatively, in the above aspect, the thickness of the first insulating layer in the region overlapping with the first conductive layer may be less than the thickness of the first conductive layer.

[0024] Alternatively, in the above aspect, the semiconductor device may have a capacitance, the capacitance having a first conductive layer, a fourth conductive layer, and a fifth insulating layer, the fifth insulating layer being located on the fourth conductive layer, the first conductive layer being located on the fifth insulating layer, and the first insulating layer having a region in contact with the fifth insulating layer.

[0025] Alternatively, in the above embodiment, the semiconductor layer may contain indium.

[0026] Alternatively, one embodiment of the present invention includes forming a first conductive layer, forming a first insulating layer so as to cover side surfaces and a top surface of the first conductive layer, performing planarization treatment on the first insulating layer, forming a second insulating layer over the first insulating layer and the first conductive layer, forming a second conductive layer over the second insulating layer, forming a first groove in the first insulating layer so as to have a region reaching the first conductive layer and a region provided as a recess, forming a second groove in the second insulating layer, and forming a first insulating layer over the first groove and the second insulating layer. A method for manufacturing a semiconductor device includes forming a semiconductor film to cover a groove portion, and processing the semiconductor film to form a semiconductor layer having a region in contact with a first conductive layer and a region in contact with a second conductive layer; exposing part of a side surface of the second insulating layer in the second groove portion, forming a third insulating layer on the semiconductor layer to have a region located within the second groove portion, and forming the third conductive layer to have a region facing the semiconductor layer with the third insulating layer sandwiched therebetween within the second groove portion.

[0027] Alternatively, in the above aspect, a fourth insulating layer may be formed on the second insulating layer, a second conductive layer may be formed on the fourth insulating layer, and a third groove portion may be formed in the fourth insulating layer after the formation of the second conductive layer and before the formation of the first groove portion and the second groove portion, and the thickness of the fourth insulating layer may be less than the thickness of the first insulating layer in a region where the first groove portion is not provided and where the fourth insulating layer does not overlap with the first conductive layer.

[0028] Alternatively, in the above embodiment, the semiconductor film may be processed under first conditions, and then processed under second conditions that are more isotropic than the first conditions.

[0029] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device that can be manufactured at low cost can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with small parasitic capacitance can be provided.

[0030] According to one embodiment of the present invention, a method for manufacturing a semiconductor device that enables miniaturization and high integration can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high yield can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device at low cost can be provided. According to one embodiment of the present invention, a method for manufacturing a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device including a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device including a transistor with high on-state current can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device including a transistor with low parasitic capacitance can be provided.

[0031] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0032] FIGS. 1A and 1B are plan views showing an example of a semiconductor device. FIGS. 2A and 2B are plan views showing an example of a semiconductor device. FIGS. 3A and 3B are cross-sectional views showing an example of a semiconductor device. FIGS. 4A and 4B are cross-sectional views showing an example of a semiconductor device. FIGS. 5A and 5B are perspective views showing an example of a semiconductor device. FIG. 6 is a cross-sectional view showing an example of a semiconductor device. FIGS. 7A and 7B are cross-sectional views showing an example of a semiconductor device. FIGS. 8A and 8B are cross-sectional views showing an example of a semiconductor device. FIG. 9A is a cross-sectional view showing an example of a semiconductor device. FIG. 9B is a band diagram. FIG. 10 is a cross-sectional view showing an example of a semiconductor device. FIG. 11A is a plan view showing an example of a semiconductor device. FIGS. 11B to 11E are cross-sectional views showing an example of a semiconductor device. FIG. 12A is a plan view showing an example of a semiconductor device. FIGS. 12B to 12E are cross-sectional views showing an example of a semiconductor device. FIGS. 13A and 13B are cross-sectional views showing an example of a semiconductor device. FIG. 14 is a cross-sectional view showing an example of a semiconductor device. FIG. 15A is a plan view showing an example of a semiconductor device. 15B to 15E are cross-sectional views showing an example of a semiconductor device. FIG. 16A is a plan view showing an example of a semiconductor device. FIGS. 16B to 16D are cross-sectional views showing an example of a semiconductor device. FIG. 17A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 17B to 17E are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 18A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 18B to 18E are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 19A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 19B to 19E are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 20A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 20B to 20E are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 21A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 21B to 21E are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 22A is a plan view showing an example of a manufacturing method of a semiconductor device. 22B to 22E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device, and Fig. 23A is a plan view illustrating an example of a method for manufacturing a semiconductor device.23B to 23E are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 24A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 24B to 24E are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 25A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 25B to 25E are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 26A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 26B to 26E are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 27A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 27B to 27E are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 28A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 28B to 28E are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 29A is a plan view illustrating an example of a memory device. FIGS. 29B and 29C are cross-sectional views illustrating an example of a memory device. FIGS. 30A and 30B are cross-sectional views illustrating an example of a memory device. FIG. 31A is a plan view illustrating an example of a memory device.

[0073] Fig. 31B is a circuit diagram showing an example of a memory cell. Figs. 32 is a cross-sectional view showing an example of a memory device. Figs. 33A and 33B are cross-sectional views showing an example of a memory device. Fig. 34 is a cross-sectional view showing an example of a memory device. Fig. 35 is a cross-sectional view showing an example of a memory device. Fig. 36 is a block diagram showing an example of a semiconductor device. Figs. 37A to 37G are circuit diagrams showing an example of a memory cell. Figs. 38A and 38B are perspective views showing an example of a semiconductor device. Fig. 39 is a block diagram showing an example of a CPU. Figs. 40A and 40B are perspective views showing an example of a semiconductor device. Figs. 41A and 41B are perspective views showing an example of a semiconductor device. Fig. 42 is a conceptual diagram explaining the hierarchy of a memory device. Fig. 43 is a diagram showing an example of an electronic component. Figs. 44A to 44C are diagrams showing an example of a mainframe computer. Fig. 44D is a diagram showing an example of space equipment. Fig. 44E is a diagram showing an example of a storage system applicable to a data center. Figs. 45A to 45F are diagrams showing an example of electronic equipment. Figs. 46A to 46G are diagrams showing an example of electronic equipment. 47A to 47F are diagrams showing an example of an electronic device.48A and 48B are SEM images according to an example. FIGS. 49A and 49B are SEM images according to an example. FIGS. 50A and 50B are SEM images according to an example. FIGS. 51A to 51D are SEM images according to an example. FIG. 52A is a plan view showing the structure of a sample according to an example. FIGS. 52B and 52C are cross-sectional views showing the structure of a sample according to an example. FIGS. 53A to 53F are SEM images according to an example.

[0033] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0034] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0035] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0036] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes, stacking order, or arrangement order. Furthermore, even if a term is not accompanied by an ordinal number in this specification, ordinal numbers may be accompanied in the claims to avoid confusion between components. Furthermore, even if a term is accompanied by an ordinal number in this specification, ordinal numbers may be accompanied by a different ordinal number in the claims. Furthermore, even if a term is accompanied by an ordinal number in this specification, ordinal numbers may be omitted in the claims.

[0037] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing a switching operation to control conduction or non-conduction. The term "transistor" used in this specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0038] In this specification and the like, a transistor having a metal oxide in a channel formation region may be referred to as an OS (oxide semiconductor) transistor, and a transistor having silicon in a channel formation region may be referred to as a Si transistor.

[0039] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0040] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably.

[0041] Note that impurities in a semiconductor refer to, for example, elements other than the main components that constitute the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The inclusion of impurities can, for example, increase the defect level density of the semiconductor or reduce the crystallinity. When the semiconductor is a metal oxide, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the metal oxide. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen deficiency (V) in the metal oxide. Ｏ In some cases, a nucleus (also referred to as a nucleus) may be formed.

[0042] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0043] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less than 1 atomic%). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

[0044] In this specification, the term "content" refers to the proportion of a component contained in a film. For example, if a metal oxide layer contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide layer is A, then the number of atoms of each of metal elements X, Y, and Z is A. Ｘ , AＹ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) The content of the metal element X in the metal oxide layer can be expressed as the content not taking into account oxygen, impurities, etc.

[0045] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0046] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0047] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0048] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0049] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0050] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0051] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0052] In this specification, "normally on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, and "normally off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0053] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0054] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0055] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0056] In this specification and the like, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0057] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." Furthermore, the X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other, i.e., vertical directions.

[0058] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings.

[0059] One embodiment of the present invention relates to a semiconductor device including a transistor in which a source electrode and a drain electrode are located at different heights and a current flowing through a semiconductor layer has a vertical component, and a manufacturing method thereof. Such a transistor is called a vertical transistor. In a vertical transistor, two or more of a source electrode, a semiconductor, and a drain electrode can be provided so as to overlap each other. For example, one of the source electrode and the drain electrode of the transistor can be provided above the other of the source electrode and the drain electrode of the transistor. As a result, the occupied area can be significantly reduced compared to a planar transistor in which the source electrode and the drain electrode are located at the same height or approximately the same height and in which a current flowing through a semiconductor layer has a lateral component. Therefore, miniaturization or high integration of the semiconductor device can be achieved.

[0060] A semiconductor device according to one embodiment of the present invention includes a transistor over a substrate, a first interlayer insulating film, and a second interlayer insulating film. The first interlayer insulating film is in contact with at least part of one side surface of a source electrode and a drain electrode of the transistor. For example, the first interlayer insulating film can be provided so as to be in contact with one side surface and a top surface of the source electrode and the drain electrode of the transistor.

[0061] The second interlayer insulating film is located on the first interlayer insulating film and on one of the source electrode and drain electrode of the transistor. The first interlayer insulating film has a first groove. The second interlayer insulating film has a second groove overlapping the first groove. The first and second grooves extend in a predetermined direction parallel to the substrate surface. The first groove may have a region that reaches one of the source electrode and drain electrode of the transistor. The first groove is provided as a recess in a region that does not overlap with one of the source electrode and drain electrode of the transistor. Here, the thickness of the first interlayer insulating film in a region where the first groove is not provided and does not overlap with one of the source electrode and drain electrode of the transistor is preferably 0.5 times or more and less than 2 times the thickness of the electrode, and more preferably at least the thickness of the electrode and less than 1.5 times the thickness of the electrode.

[0062] In this specification and the like, a groove can be rephrased as a slit or a trench. Also, a groove portion can be rephrased as a slit portion or a trench portion. Note that a groove portion may also be rephrased as a slit or a trench.

[0063] In a region not overlapping with the first trench, the upper surface of the first interlayer insulating film may be flat, and the upper surface of the second interlayer insulating film may be flat.

[0064] In this specification, when the upper surface of a film or layer is said to be flat, it also includes cases where the upper surface of the film or layer has a fine convex surface, a convex curved surface, a concave surface, a concave curved surface, an uneven shape, etc. Specifically, when the average surface roughness Ra of the film or layer is 3 nm or less, the upper surface of the film or layer is said to be flat. The average surface roughness Ra is a three-dimensional extension of the arithmetic mean roughness defined in JIS B 0601:2001 (ISO 4287:1997) so that it can be applied to curved surfaces. The average surface roughness Ra can be evaluated using an atomic force microscope (AFM).

[0065] The other of the source electrode and the drain electrode of the transistor is provided on the second interlayer insulating film. Specifically, two island-shaped conductive layers are provided so as to face each other across the first and second trenches in a plan view. The two conductive layers are connected to each other and have a region that functions as the other of the source electrode and the drain electrode of the transistor.

[0066] The semiconductor layer of the transistor is provided to cover part of the first groove and part of the second groove. The semiconductor layer has a region in contact with one of the source electrode and the drain electrode of the transistor, a region in contact with the other of the source electrode and the drain electrode of the transistor, a region along the side surface of the first insulating layer in the first groove, and a region along the side surface of the second insulating layer in the second groove. The semiconductor layer can be, for example, a metal oxide, specifically, a metal oxide that functions as a semiconductor (also referred to as an oxide semiconductor). Examples of the metal oxide include indium oxide (also referred to as In oxide, IO), indium gallium oxide, indium zinc oxide, and indium gallium zinc oxide. Examples of the metal oxide include yttrium oxide, erbium oxide, gadolinium oxide, and ytterbium oxide.

[0067] The transistor's gate insulating layer is provided on the semiconductor layer so as to have a region located within the second trench. The transistor's gate electrode is provided in the second trench so as to have a region facing the semiconductor layer with the gate insulating layer sandwiched therebetween. The transistor's gate electrode extends in a direction parallel to the extension direction of the second trench.

[0068] As described above, in a semiconductor device according to one embodiment of the present invention, the first interlayer insulating film is provided so as to be in contact with at least part of a side surface of one of a source electrode and a drain electrode of a transistor. The thickness of the first interlayer insulating film in a region that does not overlap with one of the source electrode and the drain electrode of the transistor is set to, for example, 0.5 to less than 2 times the thickness of the electrode. Furthermore, the first interlayer insulating film is preferably made of a material that has a high etching selectivity with respect to the second interlayer insulating film.

[0069] As a result, for example, when forming the first trench, it is possible to prevent a portion of the insulating layer below the first interlayer insulating film from being exposed. This prevents the insulating layer from being unintentionally processed and partially removed. Therefore, a highly reliable semiconductor device can be provided. Furthermore, since the manufacturing yield of the semiconductor device can be increased, it is possible to provide a semiconductor device that can be manufactured at low cost.

[0070] For example, when forming a semiconductor layer, after forming a semiconductor film so as to cover the first and second grooves, the semiconductor film is processed to remove a portion of the semiconductor film. The semiconductor film can be processed using an etching process. In particular, dry etching is preferably used because it allows miniaturization or high integration of semiconductor devices. Here, when forming a semiconductor layer by processing a portion of the semiconductor film, a portion of a region along the side surface of the first insulating layer in the first groove and a portion of a region along the side surface of the second insulating layer in the second groove are removed. The removal of the regions is preferably performed under isotropic conditions (also referred to as conditions under which isotropic etching occurs).

[0071] When a semiconductor film is processed using a dry etching process under isotropic conditions, ions contained in the etching gas may not be sufficiently accelerated. This may result in a long processing time for the semiconductor film. Therefore, for example, if a portion of an insulating layer under a first interlayer insulating film is exposed due to the formation of a first groove, the insulating layer is exposed to the etching gas for a long time. This makes the insulating layer more susceptible to unintentional processing. Therefore, by providing the first interlayer insulating film as described above, even when a long processing time is required for the semiconductor film, it is possible to prevent, for example, the insulating layer under the first interlayer insulating film from being unintentionally processed and partially removed. As described above, one embodiment of the present invention can provide a miniaturized or highly integrated semiconductor device with high reliability. Furthermore, a miniaturized or highly integrated semiconductor device that can be manufactured at low cost can be provided. Furthermore, for example, a material with a low etching selectivity with respect to the semiconductor film can be used for the insulating layer under the first interlayer insulating film. This allows for a wider range of materials to be selected for the insulating layer under the first interlayer insulating film.

[0072] <Configuration Example 1 of Semiconductor Device> FIG. 1A is a plan view illustrating an example of a semiconductor device of one embodiment of the present invention. The semiconductor device illustrated in FIG. 1A includes a transistor 200. FIG. 1B is a plan view in which some elements are omitted from FIG. 1A . FIG. 2A is a plan view in which some elements are further omitted from FIG. 1B . FIG. 2B is a plan view in which some elements are further omitted from FIG. 2A .

[0073] Fig. 3A is a cross-sectional view taken along dashed lines A1-A2 in Fig. 1A to Fig. 2B. Fig. 3B is a cross-sectional view taken along dashed lines A3-A4 in Fig. 1A to Fig. 2B. Fig. 4A is a cross-sectional view taken along dashed lines B1-B2 in Fig. 1A to Fig. 2B. Fig. 4B is a cross-sectional view taken along dashed lines B3-B4 in Fig. 1A to Fig. 2B.

[0074] 5A and 5B are perspective views illustrating an example of a semiconductor device according to one embodiment of the present invention. Fig. 5B illustrates a part of the configuration illustrated in Fig. 5A. Fig. 5B includes an example of a cross-sectional configuration taken along dashed line A1-A2 illustrated in Figs. 1A to 2B.

[0075] Fig. 6 is a cross-sectional view taken along dashed line C1-C2 in Fig. 3A and Fig. 3B. Fig. 6 is also called a plan view, and more specifically, can be said to be a plan view showing an example of the cross-sectional configuration taken along dashed line C1-C2.

[0076] 1A to 6, the X direction, Y direction, and Z direction are indicated by arrows. Note that although the same X, Y, and Z symbols are used in each of FIGS. 1A to 6, the directions do not necessarily have to match between these figures. In the subsequent figures, the X direction, Y direction, and Z direction do not necessarily have to match between the figures.

[0077] 1A to 6 includes an insulating layer 210 on a substrate (not shown), a transistor 200 on the insulating layer 210, an insulating layer 280a, an insulating layer 280b on the insulating layer 280a, an insulating layer 280c on the insulating layer 280b, an insulating layer 283 on the transistor 200 and on the insulating layer 280c, an insulating layer 285 on the insulating layer 283, a conductive layer 244a, a conductive layer 244b, and a conductive layer 245 on the conductive layer 244a, the conductive layer 244b, and the insulating layer 285. Here, FIG. 1B is a plan view in which the conductive layer 245 is omitted from FIG. 1A.

[0078] The insulating layer 210 functions as a base insulating film or an interlayer insulating film. The insulating layers 280a, 280b, 280c, 283, and 285 function as interlayer insulating films. In the examples shown in Figure 1A and Figures 3A to 5B, the conductive layer 245 is provided to extend in the X direction.

[0079] The transistor 200 includes a conductive layer 220, conductive layers 240a and 240b on an insulating layer 280c, a semiconductor layer 230 on the conductive layer 220, the conductive layer 240a, and the conductive layer 240b, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. Furthermore, insulating layers 280a, 280b, and 280c are provided in this order on the conductive layer 220. Here, FIG. 2A is a plan view in which the conductive layer 260, the conductive layer 244a, and the conductive layer 244b are omitted from FIG. 1B. That is, FIG. 2A is a plan view in which the conductive layer 245, the conductive layer 260, the conductive layer 244a, and the conductive layer 244b are omitted from FIG. 1A. Furthermore, FIG. 2B is a plan view in which the semiconductor layer 230 is omitted from FIG. 2A. That is, FIG. 2B is a plan view in which the conductive layer 245, the conductive layer 260, the conductive layer 244a, the conductive layer 244b, and the semiconductor layer 230 are omitted from FIG. 1A.

[0080] 1A to 2B do not show the insulating layer 210, the insulating layer 280a, the insulating layer 280c, the insulating layer 250, the insulating layer 283, and the insulating layer 285. Some components may also be omitted in the subsequent plan views.

[0081] For example, a metal oxide can be used for the semiconductor layer 230. In this case, the transistor 200 is an OS transistor.

[0082] The conductive layer 260 has a region that functions as a gate electrode of the transistor 200. The insulating layer 250 has a region that functions as a gate insulating layer of the transistor 200. The conductive layer 220 has a region that functions as one of a source electrode and a drain electrode of the transistor 200. The conductive layer 240a and the conductive layer 240b function as the other of the source electrode and the drain electrode of the transistor 200 and are connected to each other through the conductive layer 245.

[0083] The conductive layer 220 and the conductive layer 245 are provided to extend in the X direction. The conductive layer 260 is provided to extend in the Y direction. The conductive layer 240a and the conductive layer 240b are provided in an island shape.

[0084] 3A to 5B , the insulating layer 280a has a region in contact with the conductive layer 220. Specifically, the insulating layer 280a has a region in contact with a side surface of the conductive layer 220. FIG. 4B shows an example in which the insulating layer 280a has a region in contact with a side surface 221 of the conductive layer 220 and a region in contact with a side surface 222 opposite to the side surface 221. Also, FIGS. 3A to 5B show an example in which the insulating layer 280a is provided so as to be in contact with the side surface and the top surface of the conductive layer 220.

[0085] The insulating layer 280a, the insulating layer 280b, and the insulating layer 280c have grooves 290. The grooves 290 extend in a direction parallel to the extension direction of the conductive layer 260. That is, the grooves 290 extend in the Y direction, similar to the conductive layer 260. As described above, the conductive layer 245 extends in the X direction. As a result, the conductive layer 245 intersects with the grooves 290 and the conductive layer 260 in a planar view, for example, perpendicularly or substantially perpendicularly to them.

[0086] In the region not overlapping with the groove 290, the top surface of the insulating layer 280a, the top surface of the insulating layer 280b, and the top surface of the insulating layer 280c can be flat. For example, after the insulating layer 280a is formed, planarization treatment is performed on the insulating layer 280a. As the planarization treatment, chemical mechanical polishing (CMP) treatment is preferable. Note that as the planarization treatment, treatment using etching (also referred to as etch-back treatment) may be performed. After the planarization treatment is performed on the insulating layer 280a, the insulating layer 280b and the insulating layer 280c are formed over the insulating layer 280a, so that the top surfaces of the insulating layer 280b and the insulating layer 280c can be flat. Here, by performing the planarization treatment on the insulating layer 280a, for example, the thickness of the insulating layer 280a in the region overlapping with the conductive layer 220 can be made thinner than the thickness of the insulating layer 280a in the region not overlapping with the conductive layer 220.

[0087] The groove 290 has a region that reaches the conductive layer 220. The groove 290 is provided as a recess in a region of the insulating layer 280a that does not overlap with the conductive layer 220. FIG. 3A shows an example in which the conductive layer 220 has a recess. The recess can be included in the groove 290. The recess does not have to be included in the groove 290. FIGS. 3A to 4A show an example in which the depth of the groove 290 in the region that does not overlap with the conductive layer 220 is deeper than the depth of the groove 290 in the region that overlaps with the conductive layer 220.

[0088] When the bottom surface of the recess in the conductive layer 220 is included in the groove 290, the bottom of the groove 290 includes the bottom surface of the recess in the conductive layer 220. Furthermore, the sidewall of the groove 290 includes the side surface of the recess in the conductive layer 220, the side surface of the insulating layer 280a, the side surface of the insulating layer 280b, and the side surface of the insulating layer 280c.

[0089] In the above case, the bottom of groove 290 includes the upper surface of conductive layer 220 and the upper surface of insulating layer 280a. In other words, the bottom of groove 290 includes the bottom surface of the recess in conductive layer 220 and the bottom surface of the recess in insulating layer 280a. Furthermore, the sidewall of groove 290 includes the side surface of the recess in conductive layer 220, the side surface of insulating layer 280a, the side surface of insulating layer 280b, and the side surface of insulating layer 280c. Groove 290 includes the groove in conductive layer 220, the groove in insulating layer 280a, the groove in insulating layer 280b, and the groove in insulating layer 280c.

[0090] In this specification and the like, the groove 290 provided in the insulating layer 280a may be referred to as a first groove. The groove 290 provided in the insulating layer 280b may be referred to as a second groove. The groove 290 provided in the insulating layer 280c may be referred to as a third groove. The first groove, the second groove, and the third groove may be provided so as to overlap one another. The recess of the conductive layer 220 may be provided so as to overlap the first groove, the second groove, and the third groove. Note that the ordinal numbers may be interchanged as appropriate.

[0091] As described above, in the examples shown in FIGS. 1A to 6 , the conductive layer 220 is provided to extend in the X direction. The conductive layer 220 may also be provided to extend in the Y direction. The conductive layer 220 may also be provided to have a rectangular, approximately rectangular, square, or approximately square shape in a plan view. The groove portion 290 and the conductive layer 260 may also be provided to extend in the X direction. Furthermore, the conductive layer 245 may also be provided to extend in the Y direction.

[0092] 4B , the thickness of the conductive layer 220 is defined as thickness T220. Specifically, the thickness of the conductive layer 220 in the region that does not overlap with the groove portion 290 is defined as thickness T220. Furthermore, the thickness of the insulating layer 280a is defined as thickness Ta. Specifically, thickness Ta can be the thickness of the insulating layer 280a in the region where the groove portion 290 is not provided and where the insulating layer 280a does not overlap with the conductive layer 220. Furthermore, the thickness of the insulating layer 280a in the region that overlaps with the conductive layer 220 is defined as thickness Tao. Thickness Ta can be, for example, the sum of thickness T220 and thickness Tao.

[0093] 4B, the thickness of insulating layer 280b is defined as Tb. The thickness of insulating layer 280c is defined as Tc. For example, thickness Tb can be greater than thickness Tao and can also be greater than thickness Tc.

[0094] The groove portion 290 can be formed by processing the insulating layer 280c, the insulating layer 280b, and the insulating layer 280a using an etching process. In particular, a dry etching process is preferable because it is suitable for fine processing. Furthermore, for example, a recess can be formed in the conductive layer 220 by the dry etching process. The recess can be included in the groove portion 290 as described above.

[0095] Here, it is preferable to process the insulating layer 280b under conditions different from those for processing the insulating layer 280a. Specifically, it is preferable to process the insulating layer 280b under conditions that provide a high selectivity with respect to the insulating layer 280a. This makes it possible to prevent a portion of the insulating layer 280a from being unintentionally removed during processing of the insulating layer 280b.

[0096] It is preferable that the thickness Tao is as thin as possible compared to the thickness T220. This makes it possible to expose at least a portion of the top surface of the conductive layer 220 by forming the groove 290, while preventing a portion of the insulating layer 210 from being exposed and being removed. Therefore, a highly reliable semiconductor device can be provided. Furthermore, since the manufacturing yield of the semiconductor device can be increased, a semiconductor device that can be manufactured at low cost can be provided. For example, by forming the insulating layer 280a so as to cover the side and top surfaces of the conductive layer 220 and then performing a planarization process on the insulating layer 280a, the thickness Tao can be made thinner than the thickness T220.

[0097] The time required to etch the insulating layer 280a by a thickness Tao is defined as the reference etching time. The thickness Tao is, for example, less than the thickness T220. That is, the thickness Ta is, for example, less than twice the thickness T220. This prevents a portion of the insulating layer 210 from being exposed even when overetching is performed for the same time as the reference etching time. That is, even if the overetching time is 100% of the reference etching time, it prevents a portion of the insulating layer 210 from being exposed. Here, overetching prevents the insulating layer 280a from remaining in the region of the insulating layer 280b of the conductive layer 220 that overlaps with the groove portion 290. This increases the manufacturing yield of semiconductor devices, thereby providing semiconductor devices that can be manufactured at low cost.

[0098] Furthermore, the thickness Tao is preferably set to, for example, less than 0.5 times the thickness T220. That is, the thickness Ta is preferably set to, for example, less than 1.5 times the thickness T220. In this case, even when overetching is performed for a time twice the reference etching time, it is possible to prevent a portion of the insulating layer 210 from being exposed. That is, even when the overetching time is set to 200% of the reference etching time, it is possible to prevent a portion of the insulating layer 210 from being exposed. Furthermore, the thickness Tao is more preferably set to, for example, less than 0.4 times the thickness T220. That is, the thickness Ta is more preferably set to, for example, less than 1.4 times the thickness T220. In this case, even when overetching is performed for a time 2.5 times the reference etching time, it is possible to prevent a portion of the insulating layer 210 from being exposed. That is, even when the overetching time is set to 250% of the reference etching time, it is possible to prevent a portion of the insulating layer 210 from being exposed. Furthermore, the thickness Tao is more preferably set to, for example, less than 0.2 times the thickness T220. That is, it is more preferable that the thickness Ta is, for example, less than 1.2 times the thickness T220. In this case, even if over-etching is performed for a time period five times the standard etching time, it is possible to prevent a portion of the insulating layer 210 from being exposed. That is, even if the over-etching time is set to 500% of the above-mentioned standard etching time, it is possible to prevent a portion of the insulating layer 210 from being exposed.

[0099] The thickness T220 can be, for example, 5 nm to 500 nm, preferably 10 nm to 100 nm, more preferably 20 nm to 80 nm, and even more preferably 30 nm to 60 nm. The thickness Tao can be, for example, greater than 0 nm and less than 500 nm, preferably greater than 0 nm and 100 nm, more preferably greater than 0 nm and 60 nm, more preferably greater than 0 nm and 40 nm, and even more preferably greater than 0 nm and 20 nm.

[0100] The insulating layer 280a and the insulating layer 280c can be formed as barrier insulating layers against oxygen. The insulating layer 280b can be formed as a material with a lower dielectric constant than the insulating layer 280a and the insulating layer 280c. By using an oxygen barrier insulating layer as the insulating layer 280a, it is possible to prevent the conductive layer 220 from oxidizing and increasing its electrical resistance. By using an oxygen barrier insulating layer as the insulating layer 280c, it is possible to prevent the conductive layer 240a and the conductive layer 240b from oxidizing and increasing their electrical resistance. By using a material with a lower dielectric constant than the insulating layer 280a and the insulating layer 280c as the insulating layer 280b, it is possible to prevent the formation of parasitic capacitance, for example, between the conductive layer 220 and the conductive layer 240a and between the conductive layer 220 and the conductive layer 240b. This makes it possible to provide a semiconductor device capable of high-speed operation. Note that details of the material for the oxygen barrier insulating layer and the material with a low dielectric constant will be described later.

[0101] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are defined as a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, and NO ２ The term "oxygen" when used in reference to a corresponding substance refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0102] Here, if the thickness Tb is greater than the thickness Tc, it is preferable because it can effectively prevent parasitic capacitance from being formed, for example, between the conductive layer 220 and the conductive layer 240a, and between the conductive layer 220 and the conductive layer 240b. When the thickness Tb is greater than the thickness Tc, i.e., when the thickness Tc is thinner than the thickness Tb, the thickness Tc can be less than the thickness Ta. Furthermore, the thickness Tc can be approximately the same as the thickness Tao. Note that, for example, the thickness Tb affects the channel length of the transistor 200. Therefore, for example, the thickness Tb is appropriately set according to the design value of the channel length of the transistor 200. Note that the thickness Tc may also be set according to the design value of the channel length of the transistor 200.

[0103] For example, it is preferable to use a silicon nitride film or an aluminum oxide film as the insulating layer 280a and the insulating layer 280c, and a silicon oxide film or a silicon oxynitride film as the insulating layer 280b. Note that at least one of the insulating layer 280a, the insulating layer 280b, and the insulating layer 280c may have a stacked structure of two or more layers. The insulating layer 280c does not necessarily have to be provided. Furthermore, a barrier insulating layer against oxygen does not necessarily have to be used as one or both of the insulating layer 280a and the insulating layer 280c.

[0104] Here, the insulating layer 280b preferably has a region containing excess oxygen. This allows oxygen to be supplied from the insulating layer 280b to the semiconductor layer 230. Therefore, oxygen vacancies and V Ｏ H can be reduced.

[0105] The concentrations of impurities such as hydrogen or water in the insulating layers 280a, 280b, and 280c are preferably reduced. This can prevent impurities from entering the channel formation region of the transistor 200. For example, when the insulating layers 280a, 280b, and 280c are formed by sputtering, molecules containing hydrogen do not need to be used in the film formation gas. Therefore, by forming the insulating layers 280a, 280b, and 280c by sputtering, the hydrogen concentrations in the insulating layers 280a, 280b, and 280c can be reduced.

[0106] At least some of the components of the transistor 200 are disposed in the groove 290. Specifically, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are disposed such that at least some of them are located in the groove 290. The conductive layer 240a and the conductive layer 240b are provided to face each other across the groove 290 in a plan view. Note that the groove 290 may be provided not only between the insulating layer 280a, the insulating layer 280b, and the insulating layer 280c, but also between the conductive layer 240a and the conductive layer 240b.

[0107] 1A to 3A show an example in which the inner side surface (groove 290 side) of the conductive layer 240a coincides or substantially coincides with the sidewall of the groove 290. Also shown is an example in which the inner side surface (groove 290 side) of the conductive layer 240b coincides or substantially coincides with the sidewall of the groove 290. With such a structure, the conductive layer 240a, the conductive layer 240b, and the groove 290 can be formed at the same time.

[0108] The semiconductor layer 230 is provided so as to cover a portion of the groove 290. The semiconductor layer 230 has a region in contact with the upper surface of the conductive layer 240a outside the groove 290, a region in contact with the side surface of the conductive layer 240a, a region in contact with the upper surface of the conductive layer 240b, and a region in contact with the side surface of the conductive layer 240b. The semiconductor layer 230 also has a region in contact with the conductive layer 220 inside the groove 290. Specifically, the semiconductor layer 230 can have a region in contact with the bottom surface of the recess of the conductive layer 220 inside the groove 290 and a region in contact with the side surface of the recess.

[0109] Furthermore, the semiconductor layer 230 has a region along the sidewall of the groove 290. Within the groove 290, the semiconductor layer 230 can have a region in contact with the side surface of the insulating layer 280a, a region in contact with the side surface of the insulating layer 280b, and a region in contact with the side surface of the insulating layer 280c.

[0110] 1A to 5B show an example in which the end of the semiconductor layer 230 is located outside the end of the conductive layer 240a and the end of the conductive layer 240b in a region that does not overlap with the groove portion 290. In the example shown in Figures 1A to 5B, it can be said that the semiconductor layer 230 covers the entire conductive layer 240a and the entire conductive layer 240b.

[0111] The insulating layer 250 is provided on the semiconductor layer 230 so as to have a region located within the groove 290. The insulating layer 250 can be provided so as to cover the semiconductor layer 230. The insulating layer 250 has a recess at a position overlapping the groove 290.

[0112] The conductive layer 260 is provided so as to be located within the recessed portion of the insulating layer 250. The conductive layer 260 is provided so as to fill at least a portion of the recessed portion of the insulating layer 250. The conductive layer 260 has a region within the groove 290 that faces the semiconductor layer 230 with the insulating layer 250 sandwiched therebetween.

[0113] As described above, the semiconductor layer 230 is provided in the groove 290. In addition, the transistor 200 has a configuration in which one of the source electrode and the drain electrode (here, the conductive layer 220) is located on the lower side and the other of the source electrode and the drain electrode (here, the conductive layer 240 a and the conductive layer 240 b) is located on the upper side, so that current flows in the vertical direction. In other words, a channel is formed along the sidewall of the groove 290.

[0114] In the semiconductor layer 230, a region facing the conductive layer 260 with the insulating layer 250 sandwiched therebetween in the groove 290 and a region in the vicinity thereof function as a channel formation region of the transistor 200. A region in the vicinity of the conductive layer 220 of the semiconductor layer 230 functions as one of a source region and a drain region. At least one of a region in the vicinity of the conductive layer 240a and a region in the vicinity of the conductive layer 240b of the semiconductor layer 230 functions as the other of the source region and the drain region. In other words, the channel formation region is sandwiched between the source region and the drain region. The source region and the drain region are low-resistance regions with higher carrier concentrations than the channel formation region.

[0115] With the above configuration, a channel formation region and a source region or a drain region can be formed in the groove 290. This allows the transistor 200 to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows for miniaturization or high integration of semiconductor devices.

[0116] The channel length of the transistor 200 is the distance between the source region and the drain region in the semiconductor layer 230. In FIG. 3A , the channel length Lc of the transistor 200 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length Lc is the distance between the lower end of the region where the semiconductor layer 230 and the conductive layer 240b contact each other and the upper end of the region where the semiconductor layer 230 and the conductive layer 220 contact each other. Note that the channel length Lc may also be the distance between the lower end of the region where the semiconductor layer 230 and the conductive layer 240a contact each other and the upper end of the region where the semiconductor layer 230 and the conductive layer 220 contact each other in a cross-sectional view.

[0117] The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. However, the channel length of the transistor 200 can be set by the thicknesses of the insulating layers 280a, 280b, and 280c, etc. Therefore, the channel length of the transistor 200 can be made into a very fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 200, thereby improving its frequency characteristics.

[0118] Note that the channel length of the transistor 200 is determined by the thicknesses of the insulating layers 280a, 280b, and 280c, etc. Therefore, the channel length does not affect the area occupied by the transistor 200, for example, the area of ​​the transistor 200 in a plan view. By setting the channel length of the transistor 200 to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in the formation of the groove 290, etc.

[0119] From the above, the channel length of the transistor included in the semiconductor device of one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more, and 1 μm or less, 500 nm or less, or 300 nm or less.

[0120] Here, by having a recess in the conductive layer 220 at a position overlapping the groove 290, for example, the height of the lower surface of the insulating layer 250 and the height of the lower surface of the conductive layer 260 within the groove 290 can be lowered compared to when the recess is not provided. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Note that the surface used as the reference is not limited to the surface on which the transistor is to be formed. For example, the top surface of a substrate on which the semiconductor device is provided may be used as the reference.

[0121] By lowering the height of the bottom surface of the conductive layer 260, a gate electric field can be easily applied to the semiconductor layer 230. This can improve the electrical characteristics of the transistor 200. Furthermore, whether the conductive layer 220 or the conductive layer 240a and the conductive layer 240b is used as the drain electrode, the electrical characteristics of the transistor 200 can be improved. Here, when the thickness Tao is smaller than the thickness T220 as described above, it is possible to form the recess in the conductive layer 220 while preventing, for example, a portion of the insulating layer 210 from being exposed and being removed. As described above, a high-performance semiconductor device that can be manufactured at low cost can be provided.

[0122] In the semiconductor device of one embodiment of the present invention, when the semiconductor layer 230 is formed, a semiconductor film is formed so as to cover the groove 290, and then the semiconductor film is processed to remove a part of the semiconductor film. The semiconductor film can be processed by etching. In particular, dry etching is preferably used because it enables miniaturization or high integration of the semiconductor device. Here, when the semiconductor film is processed to form the semiconductor layer 230, a part of a region of the semiconductor film along the sidewall of the groove 290 is removed. The removal of the region is preferably performed under isotropic conditions.

[0123] When a semiconductor film is processed using dry etching under isotropic conditions, ions contained in the etching gas may not be sufficiently accelerated. This may result in a long time required to process the semiconductor film. Therefore, if, for example, a part of the insulating layer 210 is exposed due to the formation of the groove 290, the insulating layer 210 is exposed to the etching gas for a long time. Therefore, the insulating layer 210 is likely to be unintentionally processed. Therefore, by providing the insulating layer 280a as described above, even when a long time is required to process the semiconductor film, for example, the insulating layer 210 can be prevented from being unintentionally processed and partially removed. As described above, one embodiment of the present invention can provide a miniaturized or highly integrated semiconductor device with high reliability. Furthermore, a miniaturized or highly integrated semiconductor device that can be manufactured at low cost can be provided. Furthermore, for example, a material with a low etching selectivity with respect to the semiconductor film can be used for the insulating layer 210. This allows a wider range of materials to be selected for the insulating layer 210.

[0124] The insulating layer 283 is located over the conductive layer 260 and the insulating layer 250. The insulating layer 283 can be a barrier insulating layer against impurities such as hydrogen. This can prevent impurities such as hydrogen from entering the transistor 200. Therefore, a highly reliable semiconductor device can be provided. An example of a barrier insulating layer against hydrogen is a silicon nitride film. Note that details of materials for the barrier insulating layer against hydrogen will be described later.

[0125] The insulating layer 285 is located on the insulating layer 283. The insulating layer 285, the insulating layer 283, the insulating layer 250, and the semiconductor layer 230 have an opening 270a that reaches the conductive layer 240a and an opening 270b that reaches the conductive layer 240b. A conductive layer 244a is provided in the opening 270a, and a conductive layer 244b is provided in the opening 270b. For example, the conductive layer 244a is provided to fill the opening 270a, and the conductive layer 244b is provided to fill the opening 270b. The conductive layer 244a may have a region in contact with the conductive layer 240a in the opening 270a. The conductive layer 244b may have a region in contact with the conductive layer 240b in the opening 270b. Hereinafter, the openings 270a and 270b may be collectively referred to as openings 270. The conductive layer 244 a and the conductive layer 244 b may be collectively referred to as the conductive layer 244 .

[0126] The conductive layer 245 is provided over the insulating layer 285, the conductive layer 244a, and the conductive layer 244b. The conductive layer 245 can have a region in contact with the top surface of the conductive layer 244a and a region in contact with the top surface of the conductive layer 244b. As described above, the conductive layer 240a and the conductive layer 240b can be connected via the conductive layer 244a, the conductive layer 245, and the conductive layer 244b.

[0127] The conductive layer 245 overlaps with the conductive layer 260 with the insulating layer 283 and the insulating layer 285 interposed therebetween, which function as an interlayer insulating film. This can reduce parasitic capacitance compared to, for example, a case where the conductive layer 240a and the conductive layer 240b are extended in the Y direction without the conductive layer 245 being provided. For example, the parasitic capacitance between the conductive layer 240a and the conductive layer 260 and the parasitic capacitance between the conductive layer 240b and the conductive layer 260 can be reduced. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device capable of high-speed operation. Note that the height of the top surfaces of the conductive layers 244a and 244b is preferably the same as or approximately the same as the height of the top surface of the insulating layer 285.

[0128] As described above, the conductive layer 245 intersects with the conductive layer 260 in a plan view, for example, perpendicular or substantially perpendicular to the conductive layer 260. This allows the area where the conductive layer 245 and the conductive layer 260 overlap to be smaller than when the conductive layer 245 and the conductive layer 260 are arranged parallel to each other in a plan view. Therefore, the parasitic capacitance generated between the conductive layer 260 and the conductive layer 245 can be reduced. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device capable of high-speed operation. Note that, for example, when the insulating layer 285 is sufficiently thick and the parasitic capacitance per unit area generated between the conductive layer 260 and the conductive layer 245 is negligibly small, the conductive layer 260 and the conductive layer 245 may be arranged parallel to each other in a plan view.

[0129] 3A, 4B, and 5B show an example in which the conductive layer 240a has a two-layer structure including a conductive layer 240a1 and a conductive layer 240a2 on the conductive layer 240a1, and an example in which the conductive layer 240b has a two-layer structure including a conductive layer 240b1 and a conductive layer 240b2 on the conductive layer 240b1.

[0130] 3A, 4B, and 5B show an example in which the opening 270a is provided not only in the insulating layer 285, the insulating layer 283, the insulating layer 250, and the semiconductor layer 230, but also in the conductive layer 240a2. Similarly, FIGS. 3A and 5B show an example in which the opening 270b is provided also in the conductive layer 240b2. Also, an example is shown in which the opening 270a reaches the conductive layer 240a1, and the opening 270b reaches the conductive layer 240b1. In this case, the conductive layer 244a can have a region in contact with the top surface of the conductive layer 240a1 and the side surface of the conductive layer 240a2. Similarly, the conductive layer 244b can have a region in contact with the top surface of the conductive layer 240b1 and the side surface of the conductive layer 240b2.

[0131] By having the conductive layer 244a in contact with the top surface of the conductive layer 240a1, the contact resistance between the conductive layer 240a and the conductive layer 244a can be reduced, even if the contact resistance per unit area between the conductive layer 240a2 and the conductive layer 244a is greater than the contact resistance per unit area between the conductive layer 240a1 and the conductive layer 244a. Furthermore, by having the conductive layer 244a in contact with the side surface of the conductive layer 240a2, the contact area between the conductive layer 240a and the conductive layer 244a can be increased compared to when the conductive layer 244a is in contact only with the top surface of the conductive layer 240a. This reduces the contact resistance between the conductive layer 240a and the conductive layer 244a. Similarly, by having the conductive layer 244b in contact with the top surface of the conductive layer 240b1 and the side surface of the conductive layer 240b2, the contact resistance between the conductive layer 240b and the conductive layer 244b can be reduced.

[0132] Note that the conductive layer 240a2 may not have the opening 270a, and the conductive layer 240b2 may not have the opening 270b. In this case, the opening 270a reaches the upper surface of the conductive layer 240a2, and the opening 270b reaches the upper surface of the conductive layer 240b2. When the conductive layer 240a2 does not have the opening 270a, the opening 270a can be formed more easily than when the conductive layer 240a2 has the opening 270a. Similarly, when the conductive layer 240b2 does not have the opening 270b, the opening 270b can be formed more easily than when the conductive layer 240b2 has the opening 270b.

[0133] 3A , 4B , and 5B , the opening 270a includes an opening in the insulating layer 285, an opening in the insulating layer 283, an opening in the insulating layer 250, an opening in the semiconductor layer 230, and an opening in the conductive layer 240a2. Similarly, in the example shown in FIGS. 3A and 5B , the opening 270b includes an opening in the insulating layer 285, an opening in the insulating layer 283, an opening in the insulating layer 250, an opening in the semiconductor layer 230, and an opening in the conductive layer 240b2. Note that the shape and size of the openings 270a and 270b in a planar view may differ depending on the layer. Furthermore, when the shape of the openings 270a and 270b in a planar view is circular, the openings in each layer may or may not be concentric.

[0134] 3A to 5B show an example in which the conductive layer 220 has a two-layer structure including a conductive layer 220_1 and a conductive layer 220_2 on the conductive layer 220_1. FIGS. 3A and 5B show an example in which the upper surface of the conductive layer 220_2 has a recess that is part of the groove 290. The bottom surface of the recess corresponds to the bottom surface of the recess in the conductive layer 220_2. The side surface of the recess corresponds to the side surface of the recess in the conductive layer 220_2. The conductive layer 220_1 may also have a recess that is part of the groove 290. In this case, the conductive layer 220_2 can be configured to be separated by the groove 290.

[0135] 4B , of the side surfaces 221, the side surface of the conductive layer 220_1 is denoted as a side surface 221_1, and the side surface of the conductive layer 220_2 is denoted as a side surface 221_2. Furthermore, of the side surfaces 222, the side surface opposite to the side surface 221_1 is denoted as a side surface 222_1, and the side surface opposite to the side surface 221_2 is denoted as a side surface 222_2.

[0136] 3A to 5B show an example in which the conductive layer 260 has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. The conductive layer 260_1 can be disposed to surround the bottom and side surfaces of the conductive layer 260_2.

[0137] 3A to 5B, a conductive film to be the conductive layer 260_1 is first formed over the insulating layer 250, and then a conductive film to be the conductive layer 260_2 is formed over the conductive film. Subsequently, the entire surface of the conductive film is processed by anisotropic etching. In this manner, the conductive layer 260_1 and the conductive layer 260_2 shown in FIGS. 3A to 5B can be formed. Note that when the conductive layer 260_1 and the conductive layer 260_2 shown in FIGS. 3A to 5B are formed, it is not necessary to form a resist mask by, for example, photolithography.

[0138] The semiconductor device of one embodiment of the present invention may include an insulating layer over the transistor 200. Specifically, an insulating layer may be provided over the conductive layer 245 and the insulating layer 285.

[0139] The insulating layer is preferably a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen from above the transistor 200 to the semiconductor layer 230.

[0140] 6 is a cross-sectional view taken along dashed-dotted lines C1-C2 in FIGS. 3A and 3B . As shown in FIG. 6 , in the cross section taken along dashed-dotted lines C1-C2, an insulating layer 250 is provided in the groove 290 so as to cover the side of the semiconductor layer 230 that does not contact the insulating layer 280b. A conductive layer 260, specifically, a conductive layer 260_2, is provided in the center of the groove 290. In the cross section taken along dashed-dotted lines C1-C2, a conductive layer 260_1 is provided in the groove 290 so as to cover the side of the insulating layer 250 opposite the insulating layer 280b and the semiconductor layer 230. Furthermore, a conductive layer 260_2 is provided so as to fill the region inward of the conductive layer 260_1 in the groove 290 (the opposite side of the insulating layer 250).

[0141] The conductive layer 260 and the semiconductor layer 230 are provided in the groove 290 so as to face each other with the insulating layer 250 sandwiched therebetween. That is, in the groove 290, the conductive layer 260 covers the semiconductor layer 230 via the insulating layer 250. In the example shown in FIG. 6 , the channel width of the transistor 200 is determined by the length of the semiconductor layer 230 in the Y direction. In FIG. 6 , the length L230 of the semiconductor layer 230 in the Y direction is shown. The channel width of the transistor 200 can be calculated as "2×L230".

[0142] Increasing the length L230 of the semiconductor layer 230 in the Y direction can increase the channel width per unit area of ​​the transistor 200 and increase the on-state current. On the other hand, decreasing the length L230 can reduce the area occupied by the transistor 200 and increase the integration density of the semiconductor device.

[0143] The width of the groove 290 in the X direction is set by the thickness of each of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided in the groove 290. The width of the groove 290 in the X direction is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 300 nm or less, 200 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less.

[0144] <Configuration Example 2 of Semiconductor Device> Below, a configuration example of a semiconductor device that is partially different in configuration from the semiconductor device exemplified in <Configuration Example 1 of Semiconductor Device> will be described. Note that descriptions of overlapping parts will be omitted, and only the differences will be described in detail. Furthermore, even if the position or shape of components differs, if their functions are the same, they may be assigned the same reference numerals and their descriptions may be omitted.

[0145] 7A is a diagram showing an example in which the top surface of the insulating layer 280a shown in FIG. 4B coincides with or substantially coincides with the top surface of the conductive layer 220 in a region that does not overlap with the groove portion 290. In the example shown in FIG. 7A, the thickness Ta coincides with or substantially coincides with the thickness T220. For example, the insulating layer 280a is formed so as to cover the side and top surfaces of the conductive layer 220, and then CMP treatment is performed on the insulating layer 280a until the top surface of the conductive layer 220 is exposed, thereby manufacturing the semiconductor device shown in FIG. 7A. Here, the planarization treatment of the insulating layer 280a may remove part of the conductive layer 220, or part of the conductive layer 220_2 in the example shown in FIG. 7A.

[0146] 7B is a diagram showing an example in which the height of the upper surface of insulating layer 280a shown in FIG. 4B relative to the upper surface of insulating layer 210 is lower than the height of the upper surface of conductive layer 220 relative to the upper surface of insulating layer 210. In the example shown in FIG. 7B, thickness Ta is thinner than thickness T220. Note that in the example shown in FIG. 7B, the thickness of insulating layer 280b in the region overlapping with conductive layer 220 is thickness Tb.

[0147] 7B may be manufactured by forming an insulating layer 280a so as to cover the side surfaces and the top surface of the conductive layer 220, and then performing an etch-back process on the insulating layer 280a until the top surface of the conductive layer 220 is exposed. When manufacturing the semiconductor device shown in FIG. 7B, it is preferable to form an insulating layer 280b and then perform a planarization process on the insulating layer 280b by, for example, a CMP process.

[0148] 7B , the thickness Ta is set to, for example, 0.5 times or more the thickness T220. This can prevent a portion of the insulating layer 210 from being exposed due to the formation of the groove 290. For example, it is possible to prevent a portion of the insulating layer 210 from being exposed while forming a recess that will become a part of the groove 290 in the conductive layer 220.

[0149] In the semiconductor device shown in FIGS. 7A and 7B , after processing the insulating layer 280b to form the groove 290, there is no need to process the insulating layer 280a under different conditions. This reduces the number of manufacturing steps compared to the semiconductor device shown in FIG. 4B . Meanwhile, the semiconductor device shown in FIG. 4B can have a greater thickness Ta than the semiconductor device shown in FIGS. 7A and 7B . This may make it easier to prevent exposure of the top surface of the insulating layer 210 due to the formation of the groove 290. Furthermore, since endpoint detection is not required for the planarization process of the insulating layer 280a, the planarization process may be easier to perform. Furthermore, removal of a portion of the conductive layer 220 by the planarization process of the insulating layer 280a can be prevented. Furthermore, since the top surface of the conductive layer 220 is not exposed even when the planarization process of the insulating layer 280a is performed, removal of a portion of the conductive layer 220 by a cleaning solution can be prevented, for example, even when a cleaning process is performed before the formation of the insulating layer 280b. By preventing a portion of the conductive layer 220 from being removed, variations in electrical characteristics between the transistors 200 can be reduced even when a plurality of transistors 200 are formed in one semiconductor device.

[0150] 3A shows a configuration in which the inner (groove 290 side) side surfaces of the conductive layers 240a and 240b are flush with the groove 290 side side surfaces of the insulating layers 280a, 280b, and 280c (which may also be described as aligned, approximately aligned, coincident, or substantially coincident), but the present invention is not limited to this. For example, the inner (groove 290 side) side surfaces of the conductive layers 240a and 240b may be discontinuous with the groove 290 side side surfaces of the insulating layers 280a, 280b, and 280c. Furthermore, the inclination of the inner (groove 290 side) side surfaces of the conductive layers 240a and 240b may differ from the inclination of the groove 290 side side surfaces of the insulating layers 280a, 280b, and 280c. At this time, part of the side wall of the groove 290 becomes tapered.

[0151] 8A shows an example in which the inner side surfaces (groove 290 side) of the conductive layers 240a and 240b are tapered. FIG. 8B shows an example in which the inner side surfaces (groove 290 side) of the conductive layers 240a and 240b, and the side surfaces of the insulating layers 280a, 280b, and 280c on the groove 290 side are tapered.

[0152] By tapering the sidewalls of the groove 290, the coverage of the semiconductor layer 230, the insulating layer 250, etc. can be improved, and defects such as voids can be reduced. When the sidewalls of the groove 290 are tapered, for example, the taper angle (angle θ240) of the side surface of the conductive layer 240a on the inner side (groove 290 side) and the taper angle (angle θ280) of the side surfaces of the insulating layers 280a, 280b, and 280c on the groove 290 side are preferably 45 degrees or more and less than 90 degrees. Specifically, an angle of 80 degrees or more and less than 90 degrees is preferable, as described above, because this allows for miniaturization or high integration of semiconductor devices. Furthermore, an angle of 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less is preferable, because this improves the coverage of the film formed in the groove 290.

[0153] Furthermore, for example, it is preferable that the angle θ240 is smaller than the angle θ280. This configuration improves the coverage of the semiconductor layer 230 and other layers on the inner (groove 290 side) sides of the conductive layers 240a and 240b, thereby reducing defects such as voids. The inclination of the side surface of the insulating layer 280a at the groove 290, the inclination of the side surface of the insulating layer 280b at the groove 290, and the inclination of the side surface of the insulating layer 280c at the groove 290 may be different from each other. Similarly, when the conductive layers 240a and 240b have a stacked structure, the inclination of the side surface of each layer at the inner (groove 290 side) side may be different. For example, the inclination of the side surface of the conductive layer 240a1 may be different from the inclination of the side surface of the conductive layer 240a2. The inclination of the side surface of the conductive layer 240b1 may be different from the inclination of the side surface of the conductive layer 240b2.

[0154] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer that constitutes the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0155] [Semiconductor Layer] As described above, the semiconductor layer 230 can contain a metal oxide. In this case, the transistor 200 including the semiconductor layer 230 is an OS transistor. In the following description, the semiconductor layer 230 is assumed to contain a metal oxide unless otherwise specified.

[0156] The crystallinity of the semiconductor material used for the semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0157] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for the semiconductor layer 230, the off-state current of the transistor 200 can be reduced. Because the off-state current of an OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0158] For an oxide semiconductor that can be used for a semiconductor layer of a transistor according to one embodiment of the present invention, refer to the description in Embodiment 2. Detailed description thereof will be omitted here.

[0159] It should be noted that a semiconductor material other than metal oxide may be used for the semiconductor layer 230. Examples of such other semiconductor materials include semiconductors made of simple elements and compound semiconductors.

[0160] Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0161] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0162] Here, the semiconductor layer 230 preferably contains indium and oxygen. For example, the semiconductor layer 230 can be made of indium oxide, indium gallium oxide, indium zinc oxide, indium gallium zinc oxide, indium gallium tin zinc oxide, or the like. The semiconductor layer 230 can have a stacked structure. For example, the semiconductor layer 230 can have a stacked structure of indium oxide and indium gallium zinc oxide on indium oxide. The semiconductor layer 230 may also contain, for example, yttrium oxide, erbium oxide, gadolinium oxide, or ytterbium oxide.

[0163] 9A is a diagram showing an example in which the semiconductor layer 230 shown in FIG. 3A has a two-layer structure including a semiconductor layer 230_1 and a semiconductor layer 230_2 over the semiconductor layer 230_1. Also, FIG. 9A shows an example in which an oxide layer 227 is provided under the semiconductor layer 230_1. In the example shown in FIG. 9A, the oxide layer 227 is provided between the conductive layer 220_2 and the semiconductor layer 230_1, between the conductive layer 240a2 and the semiconductor layer 230_1, between the conductive layer 240b2 and the semiconductor layer 230_1, and between the insulating layer 280c and the semiconductor layer 230_1. Note that the oxide layer 227 may or may not be included as a component of the transistor 200.

[0164] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0165] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0166] Note that if many defects exist in the semiconductor layer 230, a level due to the defects (also referred to as a defect level) is formed. When a negative voltage is applied to the gate, Fermi level pinning caused by the defect level suppresses an increase in the energy barrier, making it easier for electrons to overcome the energy barrier. In other words, it is estimated that the threshold voltage shifts negatively or the off-current increases.

[0167] Therefore, it is preferable to provide a layer with high resistivity between the semiconductor layer 230 and the conductive layer 220, between the semiconductor layer 230 and the conductive layer 240a, and between the semiconductor layer 230 and the conductive layer 240b. By providing such a layer, an energy barrier can be maintained and a negative shift in the threshold voltage or a decrease in on-state current can be suppressed. Therefore, the threshold voltage of the transistor 200 is shifted in the positive direction, and the transistor 200 can be made normally off. As described above, the electrical characteristics of the transistor 200 can be improved, and the reliability of the transistor 200 can be improved. An example of such a layer is the oxide layer 227.

[0168] For example, the resistivity of the oxide layer 227 is preferably higher than that of the semiconductor layer 230_1. Specifically, the oxide layer 227 preferably contains at least one of aluminum, gallium, and yttrium, and more preferably contains gallium. For example, the oxide layer 227 preferably has a region with a higher gallium content than the semiconductor layer 230_1. With this structure, the oxide layer 227 can have a higher resistivity than the semiconductor layer 230_1.

[0169] The oxide layer 227 preferably has crystallinity, and preferably has single crystal or single crystal-like crystallinity. Here, the lattice constant of the oxide layer 227 preferably matches or substantially matches (can also be referred to as lattice matching) the lattice constant of the semiconductor layer 230. By forming the semiconductor layer 230 on such an oxide layer 227, the crystallinity of the oxide layer 227 can be reflected in the semiconductor layer 230, and the semiconductor layer 230 can sometimes have good crystallinity.

[0170] For example, yttria-stabilized zirconia (YSZ) can be used as the oxide layer 227. Here, the oxide layer 227 contains yttrium and zirconium. When YSZ is used for the oxide layer 227, it is preferable that the YSZ has high crystallinity, and preferably has single crystal or crystallinity close to single crystal. By using YSZ with high crystallinity for the oxide layer 227, the crystallinity of YSZ may be reflected in the semiconductor layer 230 in some cases. For example, by using indium oxide for the semiconductor layer 230, indium oxide with single crystal or crystallinity close to single crystal can be formed.

[0171] As described above, when an oxide insulating material is used for the oxide layer 227, it is preferable that the oxide layer 227 contains at least one of gallium, aluminum, and zirconium. For example, aluminum oxide, gallium oxide, zirconium oxide, etc. may also be used.

[0172] For example, when an oxide semiconductor material that can be used for the semiconductor layer 230 is used for the oxide layer 227, an In—Ga—Zn oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a composition therearound, or an In—Ga—Zn oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a composition therearound can be used for the oxide layer 227. Alternatively, indium zinc oxide, gallium zinc oxide, zinc oxide, or the like can be used. The crystal structure of the oxide semiconductor used for the oxide layer 227 can be a c-axis aligned crystal (CAAC) structure, which will be described later.

[0173] Note that the oxide layer 227 is not limited to the above. For example, the oxide layer 227 can be made of silicon, silicon carbide, gallium nitride, or the like, which have high crystallinity.

[0174] As described above, by providing the oxide layer 227 between the semiconductor layer 230 and the conductive layer 220, between the semiconductor layer 230 and the conductive layer 240a, and between the semiconductor layer 230 and the conductive layer 240b, the electrical characteristics of the transistor 200 can be improved and the reliability of the transistor 200 can be increased.

[0175] The semiconductor layer 230_1 preferably contains indium (In), and more preferably has a high In content. For example, the In content in the semiconductor layer 230_1 is preferably higher than the In content in the semiconductor layer 230_2. By using a metal oxide with a high In content as the semiconductor layer 230_1, the on-state current can be increased and the frequency characteristics can be improved.

[0176] The etching rate of the semiconductor layer 230_1 is preferably low. For example, the etching rate of the semiconductor layer 230_1 in one etchant is preferably lower than the etching rate of the semiconductor layer 230_2. Furthermore, the film density of the semiconductor layer 230_1 is preferably high. For example, the film density of the semiconductor layer 230_1 is preferably higher than the film density of the semiconductor layer 230_2. This can reduce the number of defects contained in the semiconductor layer 230_1. Therefore, the defect state density in the semiconductor layer 230_1 can be reduced, and a highly reliable transistor can be realized.

[0177] Furthermore, by using an oxide film with a low etching rate for the semiconductor layer 230_1, diffusion of oxygen in the semiconductor layer 230_1 can be suppressed. Therefore, excessive oxygen can be prevented from being mixed into the semiconductor layer 230_1, and oxygen in the semiconductor layer 230_1 can be prevented from diffusing outward. Therefore, a highly reliable transistor can be realized.

[0178] Note that the etching rate of the semiconductor layer 230_1 may be high. In addition, the film density of the semiconductor layer 230_1 may be low. This allows etching to be performed at a high etching rate, thereby reducing the time required to etch the semiconductor layer 230_1.

[0179] The film density can be evaluated using, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflection (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a pale (bright) transmission electron (TE) image. Even when the same material is used for the insulating layer, if the film densities are different, the boundary between the two can sometimes be observed as a difference in contrast in a cross-sectional TEM image.

[0180] For example, the semiconductor layer 230_1 preferably contains indium oxide. Furthermore, indium oxide is preferably used for the semiconductor layer 230_1. Alternatively, an In—Zn oxide may be used for the semiconductor layer 230_1. Specifically, a metal oxide having an atomic ratio of In:Zn=1:1 or a composition thereof, an atomic ratio of In:Zn=2:1 or a composition thereof, or an atomic ratio of In:Zn=4:1 or a composition thereof can be used.

[0181] Alternatively, the semiconductor layer 230_1 may include an In—Zn oxide containing a trace amount of element M. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin.

[0182] For example, a metal oxide having an atomic ratio of In:Ga:Zn=4:0.1:1 or a composition thereof, an atomic ratio of In:Ga:Zn=2:0.1:1 or a composition thereof, or an atomic ratio of In:Ga:Zn=1:0.1:1 or a composition thereof can be used. Furthermore, a metal oxide having an atomic ratio of In:Sn:Zn=4:0.1:1 or a composition thereof, an atomic ratio of In:Sn:Zn=2:0.1:1 or a composition thereof, or an atomic ratio of In:Sn:Zn=1:0.1:1 or a composition thereof can be used. For example, yttrium oxide, erbium oxide, gadolinium oxide, or ytterbium oxide may be used as the semiconductor layer 230_1.

[0183] The semiconductor layer 230_2 preferably uses a metal oxide having a higher Ga content than the semiconductor layer 230_1. Increasing the Ga content can improve the barrier property of the semiconductor layer 230_2 against hydrogen. Therefore, hydrogen can be prevented from diffusing from above the semiconductor layer 230_2 to the semiconductor layer 230_1. Increasing the Ga content can also reduce impurities such as hydrogen or water contained in the semiconductor layer 230 due to heat or the like applied after the formation of the semiconductor layer 230. Note that the same effect may be achieved by using a metal oxide having a lower In content than the semiconductor layer 230_1 for the semiconductor layer 230_2.

[0184] For example, the semiconductor layer 230_2 preferably uses a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, an atomic ratio of In:Ga:Zn=1:3:2 or a similar composition, or an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition, in which the semiconductor layer 230_2 contains indium and gallium.

[0185] Typically, gallium oxide, indium oxide, and a metal oxide having a composition of In:Ga:Zn=1:1:1 (atomic ratio) or a composition thereof can be used for the oxide layer 227, the semiconductor layer 230_1, and the semiconductor layer 230_2. The thicknesses of the oxide layer 227, the semiconductor layer 230_1, and the semiconductor layer 230_2 are set to 0.5 nm to 1 nm, 5 nm, and 5 nm, respectively.

[0186] Note that when indium oxide, In—Zn oxide, or In—Zn oxide containing a trace amount of element M is used as the semiconductor layer 230_1, the conduction band minimum of the oxide layer 227 may be located closer to the vacuum level than the conduction band minimum of the semiconductor layer 230_1. Furthermore, by increasing the Ga content, the conduction band minimum of the semiconductor layer 230_2 may be located closer to the vacuum level than the conduction band minimum of the semiconductor layer 230_1. In this case, the semiconductor layer 230_1 is sandwiched between the oxide layer 227 and the semiconductor layer 230_2, whose conduction band minimums are located closer to the vacuum level, and can function mainly as a current path (channel).

[0187] By sandwiching the semiconductor layer 230_1 between the oxide layer 227 and the semiconductor layer 230_2, carriers trapped at the interface of the semiconductor layer 230_1 and its vicinity can be reduced. In addition, the channel can be distanced from the surface of the insulating layer 250, thereby reducing the influence of surface scattering. This makes it possible to realize a buried channel transistor in which the channel is distanced from the insulating layer interface, thereby increasing field-effect mobility.

[0188] FIG. 9B shows a band diagram of the semiconductor layer 230 and its vicinity. In FIG. 9B, the vertical axis represents energy, and the horizontal axis represents the film thickness direction at the center of the channel formation region. FIG. 9B also shows the valence band maximum (VBM) and conduction band minimum (CBM) of the oxide layer 227, the semiconductor layer 230_1, the semiconductor layer 230_2, and the insulating layer 250 when no voltage is applied between the gate and the source. Also, FIG. 9B shows the vacuum level Vac with a dashed line.

[0189] Note that the energy of the upper end of the valence band and the energy of the lower end of the conduction band vary depending on the constituent elements and compositions of the oxide layer 227, the semiconductor layer 230_1, the semiconductor layer 230_2, and the insulating layer 250. Therefore, the relationship in level between the upper ends of the valence bands and the relationship in level between the lower ends of the conduction bands will be mainly described using the band diagram in FIG. 9B.

[0190] Depending on the constituent elements and compositions of the oxide layer 227, the semiconductor layer 230_1, and the semiconductor layer 230_2, the transistor 200 may have a structure in which the semiconductor layer 230_1 is sandwiched between the oxide layer 227 and the semiconductor layer 230_2, whose conduction band minimums are closer to the vacuum level than the semiconductor layer 230_1, as shown in FIG. 9B . This structure can realize a buried channel. That is, this structure forms a path through which more current (electrons are illustrated as carriers in FIG. 9B ) flows in the semiconductor layer 230_1. Therefore, an increase in on-state current, improvement in reliability, etc. can be achieved.

[0191] For example, the conduction band bottom of the oxide layer 227 is located closer to the vacuum level than the conduction band bottom of the semiconductor layer 230_1, and the band offset between the oxide layer 227 and the semiconductor layer 230_1 is preferably 0.01 eV to 1.0 eV, more preferably 0.01 eV to 0.7 eV, and even more preferably 0.01 eV to 0.5 eV. Alternatively, the band offset is preferably 0.1 eV to 1.0 eV, more preferably 0.1 eV to 0.7 eV, and even more preferably 0.1 eV to 0.5 eV. Note that in this specification and the like, the band offset between the first layer and the second layer refers to the energy difference between the conduction band bottom of the first layer and the conduction band bottom of the second layer.

[0192] Similarly, the conduction band bottom of the semiconductor layer 230_2 is located closer to the vacuum level than the conduction band bottom of the semiconductor layer 230_1, and the band offset between the semiconductor layer 230_2 and the semiconductor layer 230_1 is preferably 0.01 eV to 1.0 eV, more preferably 0.01 eV to 0.7 eV, and even more preferably 0.01 eV to 0.5 eV, or preferably 0.1 eV to 1.0 eV, more preferably 0.1 eV to 0.7 eV, and even more preferably 0.1 eV to 0.5 eV.

[0193] The band gap of a metal oxide can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy, or X-ray absorption fine structure (XAFS). Furthermore, a combination of these techniques can be used for analysis. The electron affinity or the bottom of the conduction band can be determined from the ionization potential, which is the energy difference between the vacuum level and the top of the valence band, and the band gap. The ionization potential can be evaluated by, for example, ultraviolet photoelectron spectroscopy (UPS).

[0194] In a semiconductor device including the oxide layer 227, the semiconductor layer 230 may have a single-layer structure. In this case, the semiconductor layer 230 may be formed using, for example, the material that can be used for the semiconductor layer 230_1 described above. For example, indium oxide may be used for the semiconductor layer 230. Alternatively, indium gallium zinc oxide may be used for the oxide layer 227, and indium oxide may be used for the semiconductor layer 230. In this case, for example, a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a composition close thereto, or an atomic ratio of In:Ga:Zn=1:3:4 or a composition close thereto may be used for the oxide layer 227. Alternatively, YSZ may be used for the oxide layer 227, and indium oxide may be used for the semiconductor layer 230.

[0195] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 280a, insulating layer 280b, insulating layer 280c, insulating layer 283, insulating layer 285, insulating layer 250, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An organic insulating film may also be used for an insulating layer included in a semiconductor device.

[0196] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. Furthermore, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as an interlayer insulating film can reduce the parasitic capacitance that occurs between wirings. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0197] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0198] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0199] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of a semiconductor device. Examples of materials capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to that. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set as appropriate. For example, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set to 1:1 or close to that. In the above, lanthanum may be replaced with a lanthanoid. Furthermore, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0200] Furthermore, examples of materials that may exhibit ferroelectricity include metal nitrides containing element M1, element M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be appropriately set. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that may exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0201] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ etc.

[0202] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0203] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. Alternatively, the insulating layer 130 described below can have a layered structure made of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0204] Metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0205] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0206] Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the manifestation of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for the insulating layer to exhibit ferroelectricity, the insulating layer 130 must contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystal structure, as this will result in the manifestation of ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0207] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide and make it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0208] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0209] Specifically, examples of materials for the insulating layer that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Other examples include nitrides such as aluminum nitride, aluminum titanium nitride, and silicon nitride. Other examples include nitride oxides such as silicon nitride oxide.

[0210] An insulating layer such as a gate insulating layer that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of materials for an insulating layer that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0211] An insulating layer provided in contact with or near an oxide semiconductor layer is preferably a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the oxide semiconductor layer.

[0212] Examples of materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), and oxides containing hafnium and silicon (hafnium silicate). These metal oxides may further contain zirconium, and examples include oxides containing hafnium and zirconium.

[0213] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced. For example, an amorphous structure may be realized by adding silicon to the metal oxide. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate).

[0214] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0215] The insulating layer may partially include either or both of a crystalline region and a grain boundary.

[0216] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0217] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0218] Examples of materials for the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0219] Since the insulating layer 210 functions as an interlayer insulating film, it is preferable to use the above-mentioned material having a low relative dielectric constant. By using a material having a low relative dielectric constant for the interlayer insulating film, the parasitic capacitance generated between wirings can be reduced.

[0220] A barrier insulating layer against hydrogen is preferably used for the insulating layer 210. When the insulating layer 210 provided below the semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen from below the transistor 200 to the semiconductor layer 230 can be suppressed. For example, a silicon nitride film is preferably used as the insulating layer 210.

[0221] An insulating layer having a function of capturing or fixing hydrogen is preferably used as the insulating layer 210. When the insulating layer 210 has the function of capturing or fixing hydrogen, hydrogen in the semiconductor layer 230 can be diffused into the insulating layer 210 and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0222] The concentration of impurities such as hydrogen or water in the insulating layer 210 is preferably reduced, which can prevent impurities such as hydrogen or water from entering the channel formation region of the semiconductor layer 230.

[0223] 3A to 4B show an example in which the insulating layer 210 has a single-layer structure. Note that the insulating layer 210 can have a stacked structure of two or more layers. For example, the insulating layer 210 can have a two-layer structure of a first insulating layer and a second insulating layer over the first insulating layer. In this case, for example, it is preferable to use a barrier insulating layer against hydrogen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. Specifically, it is preferable to use a silicon nitride film as the first insulating layer and a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film as the second insulating layer.

[0224] It is preferable to use a barrier insulating layer against hydrogen as the insulating layer 250. When the insulating layer 250 provided on the semiconductor layer 230 has a barrier property against hydrogen, it is possible to suppress diffusion of hydrogen contained in the conductive layer 260 into the semiconductor layer 230. For example, a silicon nitride film is suitable as the insulating layer 250 because it has a high barrier property against hydrogen.

[0225] Furthermore, since the insulating layer 250 is in contact with the semiconductor layer 230, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen. This allows hydrogen contained in the semiconductor layer 230 to be more effectively captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0226] In addition, an insulating layer having a region containing excess oxygen is preferably used as the insulating layer 250. This allows oxygen to be supplied from the insulating layer 250 to the semiconductor layer 230, thereby reducing oxygen vacancies in the semiconductor layer 230. A silicon oxide film, a silicon oxynitride film, or the like is suitable as the insulating layer 250 because it has a structure that is stable against heat.

[0227] 3A to 4B show an example in which the insulating layer 250 has a single-layer structure. Note that the insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed of two or more types of films. By forming the insulating layer 250 using two or more types of films, the insulating layer 250 can be given multiple functions. Examples of the functions of the insulating layer 250 include a function of extracting hydrogen from the semiconductor layer 230 and a function of suppressing diffusion of hydrogen into the semiconductor layer 230.

[0228] For example, the insulating layer 250 can have a two-layer structure of a first insulating layer and a second insulating layer over the first insulating layer. In this case, the first insulating layer is in contact with the semiconductor layer 230. For example, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. With such a structure, the hydrogen concentration in the semiconductor layer 230 can be reduced and diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0229] Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. With such a structure, the amount of oxygen vacancies and the hydrogen concentration in the semiconductor layer 230 can be reduced, and diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0230] Furthermore, for example, the insulating layer 250 can have a third insulating layer between the semiconductor layer 230 and the first insulating layer. In other words, the insulating layer 250 can have a three-layer structure including a third insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0231] For example, it is preferable to use an insulating layer having a region containing excess oxygen or an insulating layer containing a material with a low dielectric constant as the third insulating layer, an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and an insulating layer having barrier properties against hydrogen and oxygen as the second insulating layer. The third insulating layer is preferably a silicon oxide film or a silicon oxynitride film. By using an oxide film for the third insulating layer in contact with the semiconductor layer 230, oxygen can be supplied to the semiconductor layer 230. Furthermore, providing the second insulating layer can suppress diffusion of oxygen contained in the third insulating layer into the conductive layer 260, thereby suppressing oxidation of the conductive layer 260. Furthermore, a decrease in the amount of oxygen supplied from the third insulating layer to the semiconductor layer 230 can be suppressed.

[0232] Furthermore, for example, the insulating layer 250 can have a fourth insulating layer between the semiconductor layer 230 and the third insulating layer. In other words, the insulating layer 250 can have a four-layer structure including a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer. The fourth insulating layer is a layer that contacts the semiconductor layer 230 among the two or more layers that the insulating layer 250 has.

[0233] It is preferable to use an insulating layer having a barrier property against oxygen as the fourth insulating layer. Note that the same configuration as that of the layers used in the above-described three-layer structure can be applied to the first to third insulating layers. The fourth insulating layer is a layer in contact with the semiconductor layer 230. When the fourth insulating layer has a barrier property against oxygen, oxygen can be prevented from being released from the semiconductor layer 230.

[0234] For example, an aluminum oxide film may be used as the fourth insulating layer. The aluminum oxide film has a function of capturing or fixing hydrogen or a barrier property against hydrogen, and is therefore suitable as the fourth insulating layer in contact with the semiconductor layer 230. Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side.

[0235] In addition, when an aluminum oxide film is used as the fourth insulating layer and an In—Zn oxide film is used as the semiconductor layer 230_2, diffusion of hydrogen into the semiconductor layer 230_1 can be suppressed in some cases.

[0236] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage kept constant in the subthreshold region.

[0237] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Each layer constituting the insulating layer 250 preferably has a region with the above thickness in at least a portion thereof.

[0238] [Conductive Layer] The conductive layers (conductive layer 220, conductive layer 240a, conductive layer 240b, conductive layer 260, conductive layer 244, conductive layer 245, etc.) included in the semiconductor device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0239] In addition, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain low electrical resistance even when absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten, indium oxide containing titanium, indium tin oxide (In-Sn oxide, also referred to as ITO), indium tin oxide containing titanium, indium tin oxide containing silicon (also referred to as ITSO), indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0240] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0241] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0242] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0243] The conductive layer 220, the conductive layer 240a, and the conductive layer 240b are each conductive layers in contact with the semiconductor layer 230, and therefore are preferably made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220, the conductive layer 240a, and the conductive layer 240b.

[0244] By using a conductive material containing oxygen for the conductive layer 220, the conductive layer 220 can maintain its conductivity even if it absorbs oxygen. Similarly, by using a conductive material containing oxygen for the conductive layer 240a and the conductive layer 240b, the conductive layer 240a and the conductive layer 240b can maintain their conductivity even if they absorb oxygen. Furthermore, even when an insulating layer containing oxygen such as hafnium oxide is used as the insulating layer 210, this is preferable because the conductive layer 220 can maintain its conductivity. For example, ITO, ITSO, In—Zn oxide, or the like is preferably used for each of the conductive layer 220, the conductive layer 240a, and the conductive layer 240b.

[0245] When the conductive layer 220, the conductive layer 240a, and the conductive layer 240b each have a stacked structure, by using a conductive material containing oxygen for the layer in the stacked structure that has the largest contact area with the semiconductor layer 230, the contact resistance between the conductive layer 220 and the semiconductor layer 230, between the conductive layer 240a and the semiconductor layer 230, and between the conductive layer 240b and the semiconductor layer 230 can be reduced.

[0246] The conductive layer 220 shown in FIGS. 3A, 4A, and 4B has a two-layer structure including a conductive layer 220_1 and a conductive layer 220_2 on the conductive layer 220_1. In this case, the conductive layer 220_2 is preferably made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a conductive metal oxide, or a conductive material that has a function of suppressing oxygen diffusion. The conductive layer 220_2 is preferably made of, for example, a conductive material containing oxygen. The conductive layer 220_1 is preferably made of a material that is more conductive than the conductive layer 220_2. Specifically, the conductive layer 220_2 is preferably made of an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide), and the conductive layer 220_1 is preferably made of tungsten. The conductive layer 220_1 may also be made of ruthenium, titanium nitride, tantalum nitride, or the like. By using an oxide conductor for the conductive layer 220_2 that is mainly in contact with the semiconductor layer 230, it is possible to reduce contact resistance with the semiconductor layer 230. Furthermore, by using a material having higher conductivity than an oxide conductor for a layer that constitutes the conductive layer 220, the conductivity of the conductive layer 220 can be increased.

[0247] Note that a conductive material containing oxygen can be used for the conductive layer 220_1, and a material having higher conductivity than the conductive layer 220_1 can be used for the conductive layer 220_2. In this case, a highly conductive material is used for the layer of the conductive layer 220 that is closest to the channel formation region of the semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200 can be increased.

[0248] 3A shows an example in which the conductive layer 220_1 and the conductive layer 220_2 each have a single-layer structure. Note that one or both of the conductive layer 220_1 and the conductive layer 220_2 may have a stacked structure of two or more layers. FIG. 10 shows an example in which the conductive layer 220_1 shown in FIG. 3A has a two-layer structure of a conductive layer 220_11 and a conductive layer 220_12 over the conductive layer 220_11.

[0249] 10 has a three-layer structure including a conductive layer 220_11, a conductive layer 220_12 on the conductive layer 220_11, and a conductive layer 220_2 on the conductive layer 220_12. For example, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion for the conductive layer 220_11, a material with high conductivity for the conductive layer 220_12, and a conductive material containing oxygen (more preferably, an oxide conductor) for the conductive layer 220_2. Specifically, it is preferable to use titanium nitride for the conductive layer 220_11, tungsten for the conductive layer 220_12, and an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 220_2. In this case, the titanium nitride film is in contact with the insulating layer 210, and the oxide conductive film is in contact with the semiconductor layer 230. Furthermore, an oxide conductor is used for the layer closest to the channel formation region of the semiconductor layer 230. Compared to tungsten, an oxide conductor has lower contact resistance with the semiconductor layer 230; therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200 can be increased. With such a structure, the conductive layer 220 can maintain conductivity even when in contact with the semiconductor layer 230. Furthermore, when an oxide insulating layer is used for the insulating layer 210, excessive oxidation of the conductive layer 220 can be suppressed by the insulating layer 210. Furthermore, by using a metal material (here, tungsten) having higher conductivity than an oxide conductor and titanium nitride as the conductive layer 220_12, the conductivity of the conductive layer 220 can be increased.

[0250] 3A and 4B show an example in which the conductive layer 240a has a two-layer structure including a conductive layer 240a1 and a conductive layer 240a2 on the conductive layer 240a1. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240a2 and a material having higher conductivity than the conductive layer 240a2 for the conductive layer 240a1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 240a2 and tungsten for the conductive layer 240a1. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 240a1. Using an oxide conductor for the conductive layer 240a2, which is mainly in contact with the semiconductor layer 230, can reduce contact resistance with the semiconductor layer 230. Furthermore, using a material having higher conductivity than an oxide conductor for the layers constituting the conductive layer 240a can increase the conductivity of the conductive layer 240a.

[0251] Note that a conductive material containing oxygen can be used for the conductive layer 240a1, and a material having higher conductivity than the conductive layer 240a1 can be used for the conductive layer 240a2. In this case, an oxide conductor is used for the layer of the conductive layer 240a that is closest to the channel formation region of the semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200 can be increased.

[0252] 3A shows an example in which the conductive layer 240b has a two-layer structure including a conductive layer 240b1 and a conductive layer 240b2 on the conductive layer 240b1. The conductive layer 240b1 can be made of the same material as that used for the conductive layer 240a1. The conductive layer 240b2 can be made of the same material as that used for the conductive layer 240a2.

[0253] The conductive layer 260 has a region that functions as a gate electrode. The conductive layer 260 is preferably made of a highly conductive material such as tungsten or ruthenium. Furthermore, the conductive layer 260 is preferably made of a conductive material that is resistant to oxidation, or a conductive material that has a function of suppressing oxygen diffusion. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.

[0254] Furthermore, the conductive layer 260 preferably uses a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more selected from ITO, indium oxide containing tungsten, indium zinc oxide containing tungsten, indium oxide containing titanium, indium tin oxide containing titanium, In—Zn oxide, and ITSO may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0255] 3A to 4A has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. In this case, for example, a titanium nitride film is preferably used as the conductive layer 260_1 and a tungsten film is preferably used as the conductive layer 260_2. Alternatively, a tantalum nitride film is preferably used as the conductive layer 260_1 and a copper film is preferably used as the conductive layer 260_2. Such a structure can increase the conductivity of the conductive layer 260.

[0256] The conductive layer 260 may also have a stacked structure of three or more layers, such as a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0257] The conductive layer 244 and the conductive layer 245 can be formed using a material that can be used for the conductive layer 240a and the conductive layer 240b. For example, a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, can be used for the conductive layer 244 and the conductive layer 245. Alternatively, a low-resistance conductive material, such as aluminum or copper, can be used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0258] 3A shows an example in which the conductive layer 244 and the conductive layer 245 have a single-layer structure. Note that the conductive layer 244 and the conductive layer 245 can have a stacked structure of two or more layers.

[0259] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, or a memory element.

[0260] In this specification and the like, a semiconductor substrate made of silicon is referred to as a silicon substrate.

[0261] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0262] <Configuration Example 3 of Semiconductor Device> Below, a configuration example of a semiconductor device that is partially different in configuration from the semiconductor device exemplified in <Configuration Example 1 of Semiconductor Device> will be described. Note that descriptions of overlapping parts will be omitted, and only the differences will be described in detail. Furthermore, even if the position or shape of components differs, if their functions are the same, they may be assigned the same reference numerals and their descriptions may be omitted.

[0263] 11A, 11B, 11C, 11D, and 11E correspond to FIGS. 1A, 3A, 3B, 4A, and 4B, respectively, and show an example in which the conductive layer 260 has a region that does not overlap with the groove portion 290. The conductive layer 260 shown in FIGS. 11A to 11E can have, for example, a region that overlaps with the conductive layer 240a and a region that overlaps with the conductive layer 240b.

[0264] 11A to 11E can be formed by, for example, photolithography. That is, the conductive layer 260 can be formed by forming a mask on a conductive film that will become the conductive layer 260 and removing part of the conductive film by etching or the like. This makes it easier to form the conductive layer 260 in a desired shape than, for example, when the conductive layer 260 is formed by processing the entire surface of the conductive film that will become the conductive layer 260 by anisotropic etching without forming a mask. On the other hand, when the conductive layer 260 is formed by processing the entire surface of the conductive film that will become the conductive layer 260 by anisotropic etching, the number of manufacturing steps for a semiconductor device can be reduced compared to when the conductive layer 260 is formed by using photolithography.

[0265] 12A, 12B, 12C, 12D, and 12E correspond to FIGS. 1A, 3A, 3B, 4A, and 4B, respectively, and illustrate an example in which the end portions of the semiconductor layer 230 are located on the conductive layer 220, the conductive layer 240a, and the conductive layer 240b. In the semiconductor device illustrated in FIGS. 12A to 12E, the area occupied by the transistor 200 can be made smaller than that in the semiconductor device illustrated in FIGS. 1A and 3A to 4B. Therefore, the semiconductor device can be miniaturized or highly integrated. Meanwhile, in the semiconductor device illustrated in FIGS. 1A and 3A to 4B, the contact areas between the semiconductor layer 230 and the conductive layer 220, the contact areas between the semiconductor layer 230 and the conductive layer 240a, and the contact areas between the semiconductor layer 230 and the conductive layer 240b can be made larger than those in the semiconductor device illustrated in FIGS. 12A to 12E. This makes it possible to reduce the contact resistance between the semiconductor layer 230 and the conductive layer 220, the contact resistance between the semiconductor layer 230 and the conductive layer 240a, and the contact resistance between the semiconductor layer 230 and the conductive layer 240b compared to the semiconductor device shown in Figures 12A to 12E.

[0266] Fig. 13A is a diagram showing an example in which an insulating layer 225 is provided in the groove 290 shown in Fig. 3A. Fig. 13B is a cross-sectional view taken along dashed line C1-C2 in Fig. 13A. Fig. 13B is also called a plan view, and specifically can be said to be a plan view showing an example of the cross-sectional configuration taken along dashed line C1-C2.

[0267] The semiconductor device shown in FIGS. 13A and 13B differs from the semiconductor device shown in FIGS. 3A and 6, for example, in that it has an insulating layer 225 in the groove 290.

[0268] In the transistor 200 shown in Figures 13A and 13B, the stacked structure from the conductive layer 220 to the conductive layer 240a and the conductive layer 240b and the stacked structure from the semiconductor layer 230 to the conductive layer 260 are similar to those of the transistor 200 described above, and therefore detailed description thereof will be omitted.

[0269] The insulating layer 225 is provided along at least a portion of the sidewall of the groove 290. Figures 13A and 13B show an example in which the insulating layer 225 is provided so as to cover the side surface of the groove 290. Specifically, an example is shown in which the insulating layer 225 has, within the groove 290, a region in contact with the side surface of the insulating layer 280a, a region in contact with the side surface of the insulating layer 280b, and a region in contact with the side surface of the insulating layer 280c. Also shown is an example in which the insulating layer 225 has a region in contact with the side surface of the conductive layer 240a on the inner side (groove 290 side) of the conductive layer 240b, a region in contact with the side surface of the conductive layer 240b on the inner side (groove 290 side), and a region in contact with the conductive layer 220. The insulating layer 225 can also be referred to as a sidewall, a sidewall insulating layer, a sidewall protective layer, or the like.

[0270] The insulating layer 225 can be made of an insulating material that can be used for the insulating layer 250 .

[0271] As described above, it is preferable that oxygen vacancies and impurities be reduced as much as possible in the channel formation region of the oxide semiconductor layer. In particular, it is preferable that hydrogen be reduced as much as possible in the channel formation region of the oxide semiconductor layer.

[0272] Therefore, it is preferable to use a barrier insulating layer against hydrogen as the insulating layer 225 provided outside the semiconductor layer 230. This can suppress diffusion of hydrogen into the semiconductor layer 230 and improve the reliability of the transistor 200. For example, it is preferable to use a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film as the insulating layer 225, and it is more preferable to use a silicon nitride film.

[0273] Note that a silicon nitride film also has a barrier property against oxygen. Therefore, by using a silicon nitride film for the insulating layer 225, oxygen can be prevented from being extracted from the semiconductor layer 230, which can prevent oxygen vacancies from being formed in the semiconductor layer 230. Furthermore, by using a silicon nitride film for the insulating layer 225, excessive oxygen can be prevented from being supplied to the semiconductor layer 230. Therefore, the channel formation region of the semiconductor layer 230 can be prevented from becoming oxygen-excessive, thereby improving the reliability of the transistor 200. Furthermore, the insulating layer 225 may be in contact with the side surface of the conductive layer 240a in the groove 290. In this case, by using a silicon nitride film for the insulating layer 225, it is possible to prevent the side surface of the conductive layer 240a in the groove 290 from being oxidized and an oxide film from being formed on the side surface. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0274] The silicon nitride film of the insulating layer 225 is preferably formed using the PEALD method, which can improve the coverage of the insulating layer 225 on the sidewalls of the trench 290 and form an insulating layer 225 with a uniform thickness.

[0275] 13A and 13B show an example in which the insulating layer 225 has a single-layer structure. Note that the insulating layer 225 can have a stacked structure of two or more layers.

[0276] As shown in FIG. 14 , the conductive layer 220_2 preferably has a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. In other words, the bottom surface of the first recess is located lower (closer to the insulating layer 210) than the bottom surface of the second recess. When forming the groove 290, the second recess is provided in the conductive layer 220_2, and then, when processing the insulating layer 225, the first recess is provided in the conductive layer 220_2. Therefore, in FIG. 14 , the side surface of the second recess is aligned with the side surfaces of the insulating layer 280a, 280b, and 280c in the groove 290, and the side surface of the first recess is aligned with the surface of the insulating layer 225 facing the semiconductor layer 230. Hereinafter, the first recess and the second recess may be collectively referred to as recesses.

[0277] 14 , the insulating layer 225 contacts the bottom and side surfaces of the recess (specifically, the second recess) of the conductive layer 220, the side surfaces of the conductive layer 240a, and the side surfaces of the conductive layer 240b, and also contacts the side surfaces of the insulating layer 280a, the side surfaces of the insulating layer 280b, and the side surfaces of the insulating layer 280c within the groove 290. The semiconductor layer 230 contacts the bottom and side surfaces of the recess (specifically, the first recess) of the conductive layer 220 and the side surfaces of the insulating layer 225 within the groove 290. The insulating layer 250 is located inside the semiconductor layer 230 within the groove 290, and the conductive layer 260 is located inside the insulating layer 250 within the groove 290.

[0278] The conductive layer 220_2 has the first recess and the second recess, so that the side surface of the conductive layer 220_2 is in contact with the semiconductor layer 230. This increases the contact area between the conductive layer 220_2 and the semiconductor layer 230, thereby reducing the contact resistance between the conductive layer 220_2 and the semiconductor layer 230. Therefore, the on-state current of the transistor 200 can be increased.

[0279] Fig. 15A is a plan view illustrating an example of a semiconductor device according to one embodiment of the present invention. Fig. 15B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 15A . Fig. 15C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 15A . Fig. 15D is a cross-sectional view taken along dashed dotted line B1-B2 in Fig. 15A . Fig. 15E is a cross-sectional view taken along dashed dotted line B3-B4 in Fig. 15A .

[0280] 15A to 15E includes an insulating layer 210 over a substrate (not shown), a transistor 200A over the insulating layer 210, an insulating layer 280a over the insulating layer 210, an insulating layer 280b over the insulating layer 280a, an insulating layer 280c over the insulating layer 280b, an insulating layer 284 over the insulating layer 280a and the insulating layer 280c, an insulating layer 285 over the insulating layer 284, and a conductive layer 265 over the transistor 200A, the insulating layer 284, and the insulating layer 285. Note that a description of the same configuration as that of the transistor 200 in the configuration of the transistor 200A may be omitted as appropriate.

[0281] The conductive layer 265 has a region in contact with the top surface of the conductive layer 260. Note that the conductive layer 265 may be considered a component of the transistor 200A. In the example shown in FIGS. 15A to 15E , the conductive layer 265 is provided extending in the X direction. The conductive layer 265 has a region that functions as a gate wiring. The conductive layer 265 can be formed using a material that can be used for the conductive layer 245.

[0282] 15B, the side surfaces of the conductive layer 260, the insulating layer 250, and the semiconductor layer 230 are aligned or substantially aligned outside the groove 290. Also, as shown in FIGS. 15B and 15C, the side surfaces of the conductive layer 260, the insulating layer 250, and the semiconductor layer 230 that contact the insulating layer 284 are aligned or substantially aligned.

[0283] 15B to 15E , the insulating layer 284 is provided on the insulating layer 280 a, the insulating layer 280 c, the conductive layer 240 a, and the conductive layer 240 b. Outside the groove 290, the insulating layer 284 has regions in contact with the top surfaces and side surfaces of the conductive layer 240 a and the conductive layer 240 b, a region in contact with the side surface of the semiconductor layer 230, a region in contact with the side surface of the insulating layer 250, and a region in contact with the side surface of the conductive layer 260. 15B to 15D , in the region overlapping with the groove 290, the insulating layer 284 has a region in contact with a side surface of the semiconductor layer 230, a region in contact with a side surface of the insulating layer 250, a region in contact with a side surface of the conductive layer 260, a region in contact with a side surface of the insulating layer 280a, a region in contact with a side surface of the insulating layer 280b, and a region in contact with a side surface of the insulating layer 280c. The insulating layer 284 also has a region in contact with a side surface of the inner side (groove 290 side) of the conductive layer 240a, and a region in contact with a side surface of the inner side (groove 290 side) of the conductive layer 240b.

[0284] The insulating layer 284 is preferably an insulating layer having a function of capturing or fixing hydrogen. When the insulating layer 284 has a function of capturing or fixing hydrogen, hydrogen in the semiconductor layer 230 can be diffused into the insulating layer 284 and the hydrogen can be captured or fixed. Furthermore, diffusion of hydrogen from above the insulating layer 284 to the semiconductor layer 230 can be suppressed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced. As the insulating layer 284, an aluminum oxide film, a hafnium oxide film, a hafnium silicate film, or the like can be used.

[0285] Furthermore, a barrier insulating layer against hydrogen can be used as the insulating layer 284. This can suppress diffusion of hydrogen from above the insulating layer 284 into the semiconductor layer 230. A silicon nitride film and a silicon nitride oxide film each have the characteristics of releasing little impurities (for example, water and hydrogen) from themselves and being less permeable to oxygen and hydrogen, and therefore can be suitably used for the insulating layer 284.

[0286] When a silicon nitride film is used as the insulating layer 284, the silicon nitride film is preferably formed by a sputtering method. The sputtering method does not require the use of hydrogen-containing molecules in the film formation gas, and therefore can reduce the hydrogen concentration in the insulating layer 284. Furthermore, by forming the insulating layer 284 by a sputtering method, a silicon nitride film with high density can be formed.

[0287] Alternatively, the insulating layer 284 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 284 may be a stacked film of an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0288] An opening 271 that reaches the insulating layer 250 is provided in the insulating layer 284 at a position that overlaps the groove 290. The conductive layer 260 is disposed so that at least a portion of the conductive layer 260 is located within the opening 271. The conductive layer 260 contacts the insulating layer 250 within the opening 271.

[0289] The insulating layer 284 also has an opening in the groove 290 in a region that does not overlap with the insulating layer 250. An insulating layer 285 is provided to fill the opening.

[0290] The conductive layer 260 is provided so as to fill the groove 290 and the opening 271. The conductive layer 260 has a portion that faces the semiconductor layer 230 in the groove 290 with the insulating layer 250 interposed therebetween, and a portion that is located within the opening 271.

[0291] The portion of the conductive layer 265 that does not overlap with the groove portion 290 is mainly located on the insulating layer 285. Therefore, the conductive layer 265 mainly overlaps with the conductive layer 240a and the conductive layer 240b via the insulating layer 284 and the insulating layer 285. This allows the distance between the conductive layer 265 and the conductive layer 240a and the distance between the conductive layer 265 and the conductive layer 240b to be increased. This reduces the parasitic capacitance generated between the conductive layer 265 and the conductive layer 240a and between the conductive layer 265 and the conductive layer 240b. Note that the conductive layer 240a and the conductive layer 265, and the conductive layer 240b and the conductive layer 265 may have overlapping portions without the insulating layer 285 interposed therebetween.

[0292] That is, the transistor 200A has a structure in which parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0293] 15B shows an example in which the width of opening 271 is greater than the width of groove 290. Note that, in a plan view, it is preferable that the overlapping area between opening 271 and groove 290 is small. The smaller the overlapping area between opening 271 and groove 290, the greater the distance between conductive layer 240a and conductive layer 260, and the smaller the parasitic capacitance occurring between conductive layer 240a and conductive layer 260. Similarly, the greater the distance between conductive layer 240b and conductive layer 260, and the smaller the parasitic capacitance occurring between conductive layer 240b and conductive layer 260.

[0294] Although the present embodiment has been described with reference to an example in which the opening 271 is rectangular in plan view, the present invention is not limited thereto. In plan view, the opening 271 may be, for example, a substantially circular shape such as an oval or an ellipse, a polygonal shape such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or any of these polygons with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees).

[0295] The width of the opening 271 may vary in the depth direction. In particular, the width of the opening 271 used here is the maximum width of the opening 271 provided in the insulating layer 284 in a cross-sectional view.

[0296] It is preferable that the height of the top surface of the conductive layer 260 is the same as or approximately the same as the height of the top surface of the insulating layer 285 or the insulating layer 284. The conductive layer 265 is provided over the insulating layer 285, the insulating layer 284, and the conductive layer 260, and is in contact with the top surface of the conductive layer 260. It can also be said that the conductive layer 260 and the conductive layer 265 are connected to each other.

[0297] Fig. 16A is a plan view of a semiconductor device having two transistors. Fig. 16B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 16A. Fig. 16C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 16A. Fig. 16D is a cross-sectional view taken along dashed dotted line C1-C2 in Figs. 16B and 16C. Fig. 16D is also called a plan view, and specifically can be said to be a plan view showing an example of a cross-sectional configuration taken along dashed dotted line C1-C2.

[0298] The semiconductor device shown in Figures 16A to 16D has an insulating layer 210 on a substrate (not shown), transistors 200Ba and 200Bb on the insulating layer 210, an insulating layer 280a on the insulating layer 210, an insulating layer 280b on the insulating layer 280a, an insulating layer 280c on the insulating layer 280b, an insulating layer 284 on the insulating layer 280a and on the insulating layer 280c, an insulating layer 285 on the insulating layer 284, and conductive layers 265 on the transistor 200Ba, the transistor 200Bb, the insulating layer 284, and the insulating layer 285.

[0299] 16A to 16C differs from the semiconductor device illustrated in Figures 15A to 15E in that two transistors, a transistor 200Ba and a transistor 200Bb, are included in the region where the conductive layer 265 overlaps with the groove 290. The transistor 200Ba includes a conductive layer 220a on the insulating layer 210, a conductive layer 240a on the insulating layer 280c, a semiconductor layer 230a on the conductive layer 220a and the conductive layer 240a, an insulating layer 250a on the semiconductor layer 230a, and a conductive layer 260a on the insulating layer 250a. Similarly, transistor 200Bb has a conductive layer 220b on insulating layer 210, a conductive layer 240b on insulating layer 280c, a semiconductor layer 230b on conductive layer 220b and conductive layer 240b, an insulating layer 250b on semiconductor layer 230b, and a conductive layer 260b on insulating layer 250b.

[0300] The transistors 200Ba and 200Bb have a linearly symmetrical configuration with respect to the dashed-dotted line D1-D2 shown in Figures 16A and 16D. Therefore, the configuration of the transistor 200Bb can be understood by referring to the description of the configuration of the transistor 200Ba, by replacing the transistor 200Ba, conductive layer 220a, conductive layer 240a, semiconductor layer 230a, insulating layer 250a, and conductive layer 260a with the transistor 200Bb, conductive layer 220b, conductive layer 240b, semiconductor layer 230b, insulating layer 250b, and conductive layer 260b, respectively, and making appropriate necessary modifications. Hereinafter, the transistor 200Ba will be mainly described.

[0301] In the transistor 200Ba, the conductive layer 260a functions as a gate electrode, and the insulating layer 250a has a region functioning as a gate insulating layer. The conductive layer 220a has a region functioning as one of a source electrode and a drain electrode. The conductive layer 240a has a region functioning as the other of the source electrode and the drain electrode. The conductive layer 265 has a region functioning as a gate wiring.

[0302] 16B and 16D , the insulating layer 284 is provided in the groove 290 so as to contact the side surface of the semiconductor layer 230a. By using an insulating layer having the function of capturing or fixing hydrogen as the insulating layer 284, it is possible to suppress the diffusion of hydrogen from above the insulating layer 284 to the semiconductor layer 230a, and further to capture or fix the hydrogen contained in the semiconductor layer 230a. Therefore, the hydrogen concentration in the semiconductor layer 230a can be reduced.

[0303] By providing two transistors in a region where the groove 290 and the conductive layer 265 overlap, the area occupied by the semiconductor device can be reduced, and miniaturization or high integration of the semiconductor device can be achieved.

[0304] <Example of Manufacturing Method of Semiconductor Device> An example of a manufacturing method of a semiconductor device of one embodiment of the present invention will be described below with reference to FIGS. 17A to 28E . In the drawings illustrating an example of the manufacturing method of a semiconductor device, (A) in each drawing is a plan view. (B) in each drawing is a cross-sectional view taken along dashed-dotted line A1-A2 in (A) of each drawing. (C) in each drawing is a cross-sectional view taken along dashed-dotted line A3-A4 in (A) of each drawing. (D) in each drawing is a cross-sectional view taken along dashed-dotted line B1-B2 in (A) of each drawing. (E) in each drawing is a cross-sectional view taken along dashed-dotted line B3-B4 in (A) of each drawing.

[0305] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0306] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to form insulating films, while DC sputtering is mainly used to form metal conductive films. Pulsed DC sputtering is mainly used to form films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0307] CVD methods can be further classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0308] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0309] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a plasma ALD (PEALD: Plasma Enhanced ALD) method in which a plasma-excited reactant is used, or the like can be used.

[0310] Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but employs one or both of the following conditions: a high substrate temperature during film formation and / or an impurity removal treatment. Therefore, the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without these conditions.

[0311] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0312] The CVD and ALD methods differ from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which have a faster film formation rate.

[0313] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0314] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0315] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0316] Furthermore, when processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0317] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, and then remove part of the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then expose and develop it to process the thin film into the desired shape.

[0318] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0319] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0320] An example of a method for manufacturing the semiconductor device shown in FIG. 1A and FIGS. 3A to 4B will be described below.

[0321] First, as shown in FIGS. 17A to 17E , an insulating layer 210 is formed on a substrate (not shown), and a conductive layer 220 is formed on the insulating layer 210. For example, a first conductive film that will become the conductive layer 220_1 is formed, and a second conductive film that will become the conductive layer 220_2 is formed on the first conductive film. The first conductive film and the second conductive film are then processed to form the conductive layer 220, which includes the conductive layer 220_1 and the conductive layer 220_2. The first conductive film and the second conductive film, i.e., the conductive film that will become the conductive layer 220, can be processed using an etching process. Dry etching is particularly preferable because it is suitable for microfabrication. In the example shown in FIGS. 17A to 17E , the conductive layer 220 is formed to extend in the X direction.

[0322] Next, as shown in FIGS. 17A to 17E , an insulating layer 280a is formed on the conductive layer 220 and the insulating layer 210. Specifically, the insulating layer 280a is formed so as to cover the side and top surfaces of the conductive layer 220. The insulating layer 280a can be formed using, for example, a sputtering method or an ALD method. When the insulating layer 280a is formed by a sputtering method, the insulating layer 280a can be formed at a higher deposition rate than when the insulating layer 280a is formed by, for example, an ALD method. This makes it easier to form a thick insulating layer 280a. On the other hand, when the insulating layer 280a is formed by an ALD method, the conductive layer 220 can be covered with better coverage than when the insulating layer 280a is formed by, for example, a sputtering method. Note that when forming a silicon nitride film as the insulating layer 280a, for example, by using a sputtering method, the insulating layer 280a can be formed without using hydrogen-containing molecules in the deposition gas. This allows the insulating layer 280a to be a layer that does not contain hydrogen. Therefore, in subsequent steps, it is possible to prevent impurities such as hydrogen or water from being mixed into the semiconductor film.

[0323] The insulating layer 280a may be formed by combining multiple film formation methods. For example, the insulating layer 280a can be formed by forming a first insulating layer by ALD and then forming a second insulating layer on the first insulating layer by sputtering. The second insulating layer is formed to be thicker than the first insulating layer. As a result, the insulating layer 280a can be formed thick while covering the conductive layer 220 with good coverage. Here, the first insulating layer and the second insulating layer can be made of the same material. For example, both the first insulating layer and the second insulating layer can be silicon nitride films.

[0324] 18A to 18E, the insulating layer 280a is subjected to planarization treatment. For example, the insulating layer 280a is subjected to planarization treatment until the thickness of the insulating layer 280a in the region overlapping with the conductive layer 220 becomes sufficiently thinner than the thickness of the insulating layer 280a in the region not overlapping with the conductive layer 220. Alternatively, the insulating layer 280a may be subjected to planarization treatment until the top surface of the conductive layer 220 is exposed. As described above, CMP treatment is preferable as the planarization treatment. Note that etch-back treatment may also be performed as the planarization treatment.

[0325] Next, as shown in FIGS. 18A to 18E , an insulating layer 280b is formed on the insulating layer 280a. Furthermore, an insulating layer 280c is formed on the insulating layer 280b. The insulating layers 280b and 280c can be formed, like the insulating layer 280a, by sputtering or ALD, for example. When forming, for example, a silicon oxide film as the insulating layer 280b, the insulating layer 280b can be formed by sputtering without using hydrogen-containing molecules in the deposition gas. This allows the insulating layer 280b to be a layer that does not contain hydrogen. When forming, for example, a silicon nitride film as the insulating layer 280c, the insulating layer 280c can be formed by sputtering without using hydrogen-containing molecules in the deposition gas. This allows the insulating layer 280c to be a layer that does not contain hydrogen, like the insulating layer 280b. As described above, the incorporation of impurities such as hydrogen or water into the semiconductor film can be suppressed in subsequent processes.

[0326] Here, it is preferable to form the insulating layers 280b and 280c so that the thickness of the insulating layer 280b is greater than the thickness of the insulating layer 280c, since this can suppress the formation of parasitic capacitance between the conductive layer 220 and the conductive film 240f to be formed later. As described above, when the thickness of the insulating layer 280b is greater than the thickness of the insulating layer 280c, i.e., when the thickness of the insulating layer 280c is thinner than the thickness of the insulating layer 280b, the thickness of the insulating layer 280c can be less than the thickness of the insulating layer 280a in the region where the groove 290 is not formed and where the insulating layer 280c does not overlap with the conductive layer 220. Furthermore, the thickness of the insulating layer 280c can be approximately the same as the thickness of the insulating layer 280a in the region where the insulating layer 280c overlaps with the conductive layer 220.

[0327] 18A to 18E, a conductive film 240f is formed on the insulating layer 280c. As the conductive film 240f, for example, a conductive film 240f1 is formed on the insulating layer 280c, and a conductive film 240f2 is formed on the conductive film 240f1.

[0328] 19A to 19E, the conductive film 240f is processed to form a conductive layer 240. Specifically, the conductive layer 240_2 is formed from the conductive film 240f2. The conductive layer 240_1 is formed from the conductive film 240f1. The conductive layer 240 is a layer that will later become the conductive layer 240a and the conductive layer 240b. Specifically, the conductive layer 240_1 is a layer that will later become the conductive layer 240a1 and the conductive layer 240b1. The conductive layer 240_2 is a layer that will later become the conductive layer 240a2 and the conductive layer 240b2. The conductive film 240f can be processed using an etching treatment. In particular, dry etching is preferable because it is suitable for fine processing.

[0329] 20A to 20E, the conductive layer 240 is processed to form a conductive layer 240a and a conductive layer 240b. Specifically, a conductive layer 240a2 and a conductive layer 240b2 are formed from the conductive layer 240_2. A conductive layer 240a1 and a conductive layer 240b1 are formed from the conductive layer 240_1. The conductive layer 240a and the conductive layer 240b are formed in an island shape.

[0330] The conductive layers 240a and 240b can be formed by photolithography. Specifically, a resist mask is formed in a region other than a region that will later become the groove 290, and part of the conductive layer 240 is removed by, for example, etching, thereby forming the conductive layers 240a and 240b. Here, dry etching is preferably used as the etching process because it facilitates fine processing.

[0331] Next, as shown in FIGS. 20A to 20E , the insulating layer 280c and the insulating layer 280b are processed to form a groove 290 in the insulating layer 280c and the insulating layer 280b. The groove 290 can be formed to extend in the Y direction. The groove 290 can be formed using the same resist mask as that used to form the conductive layer 240a and the conductive layer 240b. By removing a portion of the insulating layer 280c and a portion of the insulating layer 280b using, for example, an etching process, the groove 290 can be formed in the insulating layer 280c and the insulating layer 280b, respectively. Here, using a dry etching process as the etching process is preferable because it facilitates fine processing.

[0332] The conductive layer 240, the insulating layer 280c, and the insulating layer 280b can be processed using different etching conditions. For example, the etching gas used in the etching process of the conductive layer 240, the etching gas used in the etching process of the insulating layer 280c, and the etching gas used in the etching process of the insulating layer 280b can be different from one another. These etching gases can be made of materials that can be used as etching gases for dry etching of semiconductor films, which will be described later. The etching gas may also contain a gas containing fluorine. Examples of the gas containing fluorine include fluorocarbon gas, hydrofluorocarbon gas, and SF ６ Fluorocarbon gases include C ｘ F ｙ A gas represented by (y≦2x+2) can be used. An example of a fluorocarbon gas that satisfies y=2x+2 is CF. ４ , C ２ F ６ , C ３ F ８, C ４ F １０ , C ５ F １２ Examples of fluorocarbon gases that satisfy the condition y<2x+2 include saturated fluorocarbon compounds such as C ２ F ４ , C ２ F ２ , C ３ F ７ , C ３ F ４ , C ４ F ８ , C ４ F ６ , C ４ F ４ , C ４ F ２ , C ５ F １０ , C ５ F ８ , C ５ F ６ , C ５ F ４ Examples of hydrofluorocarbon gases include unsaturated fluorocarbon compounds such as CHF ３ Gas, CH ２ F ２ In addition, the gas containing fluorine may include noble gases, oxygen (O ２ ) gas, carbon dioxide, nitrogen (N ２ At least one of a fluorine-containing gas, a fluorine-containing gas, a hydrogen gas, etc. may be added.

[0333] Here, it is preferable to process the insulating layer 280b under conditions that provide a high etching selectivity with respect to the insulating layer 280a. This allows the insulating layer 280a to function as an etching stop film. In this case, it is possible to prevent the thickness of the insulating layer 280a from becoming thin in the region that does not overlap with the conductive layer 220. Therefore, when later forming the groove portion 290 in the insulating layer 280a, it is possible to prevent, for example, a portion of the insulating layer 210 from being exposed.

[0334] 21A to 21E, the insulating layer 280a is processed to form grooves 290 in the insulating layer 280a. The grooves 290 can be formed in the insulating layer 280a by removing a portion of the insulating layer 280a using, for example, an etching process. As described above, using dry etching as the etching process is preferable because it facilitates fine processing.

[0335] The insulating layer 280a can be processed using etching conditions different from those for the insulating layer 280b. For example, if the insulating layer 280a has the same material as the insulating layer 280c, the insulating layer 280a can be processed using the same etching conditions as those for the insulating layer 280c. After the insulating layer 280a is processed to form the groove 290, the resist mask is removed.

[0336] The groove 290 is formed to have a region that reaches the conductive layer 220. Furthermore, as shown in FIG. 21C , the groove 290 is formed as a recess in the insulating layer 280a in a region that does not overlap with the conductive layer 220. Note that the groove 290 can also be formed as a recess in the conductive layer 220. FIG. 21B shows an example in which a recess is formed in the conductive layer 220_2. FIGS. 21B to 21D show examples in which the depth of the groove 290 in the region that does not overlap with the conductive layer 220 is deeper than the depth of the groove 290 in the region that overlaps with the conductive layer 220.

[0337] In the planarization process of the insulating layer 280a shown in FIGS. 18A to 18E , by making the thickness of the insulating layer 280a in the region overlapping with the conductive layer 220 sufficiently thinner than the thickness of the insulating layer 280a in the region not overlapping with the conductive layer 220, it is possible to prevent a portion of the insulating layer 210 from being exposed in the process shown in FIGS. 21A to 21E . In other words, it is possible to prevent the groove 290 from reaching the insulating layer 210 in the region not overlapping with the conductive layer 220. For example, the time required to etch the insulating layer 280a until the groove 290 reaches the conductive layer 220 is defined as the reference etching time. Then, even if the over-etching time is longer than the reference etching time in the process of forming the groove 290 in the insulating layer 280a, it is possible to prevent the groove 290 from reaching the insulating layer 210. As described above, by performing over-etching, it is possible to prevent the insulating layer 280a from remaining in, for example, the region of the insulating layer 280b of the conductive layer 220 that overlaps with the groove portion 290. This makes it possible to increase the manufacturing yield of the semiconductor device, and therefore to provide a semiconductor device that can be manufactured at low cost.

[0338] Subsequently, heat treatment is preferably performed at a temperature of, for example, 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, and more preferably 320° C. or higher and 450° C. or lower.

[0339] The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the above-described heat treatment, impurities such as hydrogen or water contained in the insulating layers 280a, 280b, 280c, and the like can be reduced before the formation of the semiconductor layer 230.

[0340] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being introduced into the insulating layer 280 a, the insulating layer 280 b, the insulating layer 280 c, and the like as much as possible.

[0341] 22A to 22E , a semiconductor film 230f, which will later become the semiconductor layer 230, is formed to cover the groove 290. The semiconductor film 230f is formed to have a region that follows the sidewall of the groove 290. Within the groove 290, the semiconductor film 230f is formed to have a region that follows the recess of the conductive layer 220_2, a region that follows the side surface of the insulating layer 280a, a region that follows the side surface of the insulating layer 280b, and a region that follows the side surface of the insulating layer 280c. Furthermore, the semiconductor film 230f is formed to have a region that follows the side surface of the conductive layer 240a, a region that follows the side surface of the conductive layer 240b, a region that is located on the conductive layer 240a, and a region that is located on the conductive layer 240b. The semiconductor film 230f is formed in contact with the bottom and side surfaces of the recess of the conductive layer 220, the side and top surfaces of the conductive layer 240a, and the side and top surfaces of the conductive layer 240b.

[0342] The semiconductor film 230f can be formed by, for example, an ALD method. The semiconductor film 230f can also be formed by, for example, a sputtering method. The semiconductor film 230f can have a stacked structure of two or more layers. For example, the semiconductor film 230f can have a structure in which two or more films formed by different methods are stacked.

[0343] 9A , an oxide film to be the oxide layer 227 is formed before the formation of the semiconductor film 230f, and then a semiconductor film to be the semiconductor layer 230_1 and a semiconductor film to be the semiconductor layer 230_2 are formed in this order on the oxide film as the semiconductor film 230f. Hereinafter, the formation of the oxide film to be the oxide layer 227, the semiconductor film to be the semiconductor layer 230_1, and the semiconductor film to be the semiconductor layer 230_2 will be described.

[0344] The oxide layer 227 is a layer provided in the groove portion 290. Therefore, the oxide film that becomes the oxide layer 227 is preferably formed by the ALD method or the CVD method, and more preferably by the ALD method. This allows the oxide film to be formed with good coverage.

[0345] The semiconductor film to be the semiconductor layer 230_1 is preferably formed as a film with as uniform a thickness as possible along the top surface and side surface of the oxide film. By forming the film using the ALD method, a thin film can be formed with good controllability. Therefore, the semiconductor film to be the semiconductor layer 230_1 is preferably formed using the ALD method.

[0346] Furthermore, when the semiconductor film 230f has high crystallinity, diffusion of impurities in the semiconductor film 230f is suppressed, so that the electrical characteristics of the transistor are less likely to fluctuate and reliability can be improved. When the semiconductor film to be the semiconductor layer 230_2 is formed by a sputtering method, it is preferable because the semiconductor layer 230_2 can be easily formed into a layer with high crystallinity compared to when an ALD method is used.

[0347] When the semiconductor film to be the semiconductor layer 230_2 is formed by sputtering, oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased. When the oxide film is formed by sputtering, an In-M-Zn oxide target or the like can be used.

[0348] When a semiconductor film to be the semiconductor layer 230_2 is formed by a sputtering method, an oxygen-excess oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide semiconductor layer can be improved by performing film formation while heating the substrate.

[0349] Furthermore, when a semiconductor film to be the semiconductor layer 230_2 is formed by a sputtering method, damage to the formation surface may cause an element contained in the conductive layer 220 to be mixed into a region of the semiconductor layer 230 near the conductive layer 220. If the element is tin, the mixing of tin into a region of the semiconductor layer 230 near the conductive layer 220 generates carriers, which allows contact between the conductive layer 220 and the semiconductor layer 230, thereby realizing a transistor with excellent electrical characteristics. Similarly, an element contained in the conductive layer 240a and an element contained in the conductive layer 240b may be mixed into a region of the semiconductor layer 230 near the conductive layer 240a and a region of the semiconductor layer 230 near the conductive layer 240b, respectively. As described above, contact between the conductive layer 240a and the semiconductor layer 230 and contact between the conductive layer 240b and the semiconductor layer 230 are ensured, and a transistor with excellent electrical characteristics may be manufactured.

[0350] Note that the description in Embodiment Mode 2 can be referred to for a manufacturing method of the semiconductor film 230f.

[0351] In one embodiment of the present invention, a gallium oxide film is deposited by a thermal ALD method as the oxide film to be the oxide layer 227. An indium oxide film is deposited by a thermal ALD method as the semiconductor film to be the semiconductor layer 230_1. An In—Ga—Zn oxide film is deposited by a sputtering method as the semiconductor film to be the semiconductor layer 230_2. The oxide film to be the oxide layer 227 can be deposited by an ALD method using a precursor containing gallium and an oxidizer. The semiconductor film to be the semiconductor layer 230_1 can be deposited by an ALD method using a precursor containing indium and an oxidizer containing ozone. The semiconductor film to be the semiconductor layer 230_2 can be deposited by a sputtering method using a sputtering target containing indium and gallium.

[0352] An indium oxide film formed by an ALD method has a low etching rate. Therefore, by using an indium oxide film as a semiconductor film to be the semiconductor layer 230_1, a highly reliable transistor can be manufactured.

[0353] Note that the oxide film to be the oxide layer 227 and the semiconductor film to be the semiconductor layer 230_1 are preferably formed successively without exposure to the atmosphere. By forming the oxide film to be the oxide layer 227 and the semiconductor film to be the semiconductor layer 230_1 successively without exposure to the atmosphere, productivity can be improved. Furthermore, impurities (typically, moisture and the like) introduced into the interface between the oxide film to be the oxide layer 227 and the semiconductor film to be the semiconductor layer 230_1 and the vicinity thereof can be reduced.

[0354] After the semiconductor film that becomes the semiconductor layer 230_1 is formed, a process of supplying oxygen to the semiconductor film may be performed. By this process, oxygen can be supplied to the semiconductor film that becomes the semiconductor layer 230_1 by heat or the like applied after the process. Note that the above description can be referred to for details of the process of supplying oxygen.

[0355] Next, it is preferable to perform heat treatment. The temperature of the heat treatment is preferably 100° C. or higher and 650° C. or lower, more preferably 250° C. or higher and 600° C. or lower, and even more preferably 350° C. or higher and 550° C. or lower. For details of the heat treatment, refer to the above description.

[0356] In addition, it is preferable that the gas used in the heat treatment be highly purified. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being taken into the semiconductor layer 230 as much as possible.

[0357] The heat treatment reduces impurities such as carbon, hydrogen, and water in the semiconductor film 230f. Reducing the impurities in the film in this manner improves the crystallinity of the semiconductor film 230f, resulting in a denser, more compact structure. This increases the crystalline regions in the semiconductor film 230f, reducing in-plane variations in the crystalline regions in the semiconductor film 230f. This reduces in-plane variations in the electrical characteristics of the transistor.

[0358] In addition, it is preferable that oxygen be supplied from the insulating film containing oxygen to the channel formation region of the semiconductor film 230f by the heat treatment. Ｏ H can be reduced.

[0359] In this way, excess oxygen may be supplied to the semiconductor film 230f from an insulating layer in contact with the semiconductor film 230f. The excess oxygen has a function of trapping electrons, which makes it easier for negative charges to be formed. Therefore, the threshold voltage of the transistor is shifted in the positive direction, making it possible to realize a normally-off transistor.

[0360] Note that microwave plasma treatment may be performed after the semiconductor film 230f is formed. For example, microwave plasma treatment can be performed after the semiconductor film that will become the semiconductor layer 230_1 or the semiconductor film that will become the semiconductor layer 230_2 is formed. As a result, the concentration of impurities such as hydrogen or water contained in the semiconductor film 230f can be reduced. Furthermore, a crystalline region of the semiconductor film 230f may grow. Note that details of the microwave plasma treatment will be described in Embodiment 2.

[0361] 23A to 23E, a mask 231 is formed on the semiconductor film 230f. The mask 231 may include photoresist. The mask 231 may be formed, for example, by applying photoresist to the semiconductor film 230f, followed by exposure and development. The mask 231 is formed in a region where the semiconductor layer 230 will be formed later, in a plan view.

[0362] For example, one or both of a spin on carbon (SOC) film and a spin on glass (SOG) film can be used as a hard mask in combination with a photoresist as the mask 231. The mask 231 can have a laminated structure of, for example, an SOC film, an SOG film on the SOC film, and a photoresist on the SOG film.

[0363] 23A to 24E , the semiconductor film 230f is processed to form the semiconductor layer 230. In a method for manufacturing a semiconductor device according to one embodiment of the present invention, the semiconductor layer 230 is formed by removing a region of the semiconductor film 230f that does not overlap with the mask 231. The semiconductor layer 230 is formed to cover part of the groove 290. The semiconductor layer 230 is formed to have a region in contact with the conductive layer 240a and a region in contact with the conductive layer 240b. The semiconductor layer 230 is also formed to have a region in contact with the conductive layer 220 in the groove 290.

[0364] Furthermore, the semiconductor layer 230 is formed to have a region that runs along the sidewall of the groove 290. The semiconductor layer 230 can be formed to have, within the groove 290, a region that contacts the side surface of the insulating layer 280a, a region that contacts the side surface of the insulating layer 280b, and a region that contacts the side surface of the insulating layer 280c. Note that by processing the semiconductor film 230f, part of the sidewall of the groove 290 is exposed. Specifically, part of the sidewall of the insulating layer 280b in the groove 290 and part of the sidewall of the insulating layer 280c in the groove 290 are exposed. Also, part of the side surface of the recess of the insulating layer 280a and part of the bottom of the recess are exposed.

[0365] The semiconductor film 230f can be removed by etching. In particular, dry etching is preferable compared to wet etching, for example, because it allows for miniaturization or high integration of semiconductor devices.

[0366] For example, a gas containing halogen can be used as an etching gas for the dry etching process. For example, an etching gas containing at least one of chlorine and bromine can be used as the halogen-containing gas. For example, Cl ２ Gas, BCl ３ Gas, SiCl ４ Gas, or BBr ３ The gas may be used alone or in combination of two or more gases. The etching gas for the dry etching process may contain the above-mentioned fluorine-containing gas. For example, a gas obtained by adding at least one of the following gases to the above-mentioned fluorine-containing gas may be used.

[0367] Furthermore, a gas containing carbon, such as a hydrocarbon, can be used as the etching gas. For example, methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C ２ H ２ ), and propyne (C ３ H ４ ) can be used.

[0368] For example, a noble gas can be added to the etching gas. Examples of noble gases include helium, neon, argon, krypton, xenon, and radon. In addition, one or both of nitrogen gas and hydrogen gas may be added to the etching gas. Furthermore, when a gas containing halogen is used as the etching gas, oxygen (O ２) gas, carbon dioxide, nitrogen (N ２ At least one of a nitrogen gas, a hydrogen gas, a hydrocarbon gas, etc. may be added as appropriate.

[0369] Furthermore, as the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0370] Here, in order to form the semiconductor layer 230 so as to have a region located within the groove 290 extending in a predetermined direction, for example, the Y direction, it is necessary to remove a part of the region of the semiconductor film 230f along the sidewall of the groove 290. In this case, it is preferable to perform the dry etching process under highly isotropic conditions, compared to, for example, the case of removing only the region along the bottom surface of the groove 290 and the region located outside the groove 290.

[0371] In dry etching, the isotropy can be increased by, for example, reducing the bias power. In addition, the isotropy can be increased by, for example, increasing the pressure of the etching gas. By reducing the bias power, ions generated from the plasma are less likely to be attracted in a direction perpendicular to the substrate, thereby increasing the isotropy. In addition, by increasing the pressure of the etching gas, the mean free path of molecules in the atmosphere becomes shorter. Therefore, collisions between molecules occur more easily, thereby increasing the isotropy.

[0372] Here, if the isotropy is increased in the dry etching process, ions contained in the etching gas may not be sufficiently accelerated. As a result, etching may take a long time. Specifically, if the semiconductor film 230f is processed using the dry etching process under isotropic conditions, processing the semiconductor film 230f may take a long time.

[0373] Therefore, if, for example, a part of the insulating layer 210 is exposed due to the process of forming the groove 290 shown in FIGS. 20A to 21E , the insulating layer 210 is exposed to an etching gas for a long time. Therefore, the insulating layer 210 is likely to be unintentionally processed. Therefore, by forming the insulating layer 280a through the process shown in FIGS. 17A to 18E , even if it takes a long time to process the semiconductor film 230f, for example, the insulating layer 210 can be prevented from being unintentionally processed and partially removed. As described above, according to one embodiment of the present invention, a miniaturized or highly integrated and highly reliable semiconductor device can be manufactured. Furthermore, a miniaturized or highly integrated semiconductor device that can be manufactured at low cost can be manufactured. Furthermore, for example, the insulating layer 210 can be formed using a material with a low etching selectivity with respect to the semiconductor film 230f. This allows for a wider range of materials to be selected for the insulating layer 210, for example.

[0374] Furthermore, when the dry etching process is performed on the semiconductor film 230f for a long time, products resulting from the etching gas may be deposited on the surface of the semiconductor film 230f. For example, when a metal oxide film is used as the semiconductor film 230f, products resulting from the bonding of elements contained in the etching gas with oxygen in the semiconductor film 230f may be deposited on the surface of the semiconductor film 230f. For example, BCl ３ When an etching gas containing BCl is used, boron oxide (BOx) may be deposited on the surface of the semiconductor film 230f. ３ It is preferable to use an etching gas containing BOx, since it is easy to remove the region along the sidewall of the semiconductor film 230f in the groove 290. On the other hand, BOx has low volatility and is therefore likely to be deposited as a product on the surface of the semiconductor film 230f.

[0375] If the above-described products are deposited on the surface of the semiconductor film 230f, for example, a transistor with a desired shape may not be fabricated. Also, impurities may diffuse into the semiconductor layer 230. As a result, the fabrication yield of the semiconductor device may decrease. Also, the reliability of the semiconductor device may decrease.

[0376] Therefore, it is preferable to perform a dry etching process on the semiconductor film 230f under first conditions with high anisotropy, and then perform a dry etching process on the semiconductor film 230f under second conditions with higher isotropy than the first conditions. Specifically, first, a region of the semiconductor film 230f along the bottom surface of the groove 290 and a region outside the groove 290 are removed by a dry etching process under the first conditions. Then, a region of the semiconductor film 230f along the sidewall of the groove 290 is removed by a dry etching process under the second conditions.

[0377] As a result, the surface area of ​​the semiconductor film 230f when dry etching is performed on the semiconductor film 230f under the second condition can be made smaller than when dry etching is performed only under the second condition without performing dry etching under the first condition. Therefore, it is possible to prevent products resulting from etching gas from being deposited on the surface of the semiconductor film 230f. This can increase the manufacturing yield of semiconductor devices. Furthermore, it is possible to manufacture highly reliable semiconductor devices.

[0378] The second condition may have a smaller bias power than the first condition. The etching gas used under the first condition may be different from the etching gas used under the second condition. For example, a hydrocarbon-containing gas may be used as the etching gas under the first condition, and a halogen-containing gas may be used as the etching gas under the second condition. For example, a methane-containing gas may be used as the etching gas under the first condition, and a BCl 2 -containing gas may be used as the etching gas under the second condition. ３ A gas containing the following may also be used.

[0379] 23A to 23E show the formation of a mask 231 and the processing of a semiconductor film 230f under a first condition, and Fig. 24A to 24E show the processing of a semiconductor film 230f under a second condition.

[0380] It is preferable to remove the products deposited on the surface of the semiconductor film 230f. A method for removing the products includes plasma treatment. The plasma treatment can be performed in an atmosphere containing, for example, oxygen and / or an inert gas. Examples of the inert gas that can be used include noble gases such as argon, helium, and neon, nitrogen, and mixtures thereof.

[0381] In this specification and the like, a process for removing the by-products is referred to as a by-product removal process. Examples of the by-product removal process include the above-mentioned plasma treatment. The by-product removal process can be performed, for example, after the semiconductor layer 230 is formed.

[0382] When plasma treatment is performed in an atmosphere containing oxygen, for example, the products deposited on the surface of the semiconductor film 230f can be removed by a chemical reaction between the products and oxygen. For example, the products deposited on the surface of the semiconductor film 230f can be removed by decomposing the products. Here, the process of performing plasma treatment in an atmosphere containing oxygen and decomposing the products is also called an ashing process.

[0383] When performing plasma treatment in an atmosphere containing an inert gas, for example, by-products deposited on the surface of the semiconductor film 230 f can be physically removed by colliding the by-products deposited on the surface of the semiconductor film 230 f with an inert gas accelerated by plasma, thereby scattering and removing the by-products.

[0384] Here, it is preferable to perform a cleaning process after the product removal process. This may make it easier to remove the products. Examples of cleaning methods include wet cleaning (which can also be called wet etching) using a cleaning solution or the like. Alternatively, cleaning by heat treatment, for example, may be performed. Furthermore, ultrasonic cleaning may be performed. Note that the cleaning process does not necessarily have to be performed. Furthermore, when the semiconductor film 230f is processed under multiple conditions as described above, a cleaning process may be performed for each condition. For example, when the semiconductor film 230f is processed under first and second conditions, a cleaning process may be performed after the process under the first conditions, and then a process under the second conditions may be performed.

[0385] Wet cleaning may be performed using an aqueous solution prepared by diluting one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid with pure water or carbonated water. Wet cleaning may also be performed using pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0386] In this specification, an aqueous solution of hydrofluoric acid diluted with pure water or carbonated water may be referred to as diluted hydrofluoric acid, and an aqueous solution of ammonia water diluted with pure water may be referred to as diluted ammonia water. The concentration or temperature of the aqueous solution may be adjusted appropriately depending on the impurities to be removed, the configuration of the semiconductor device to be cleaned, and other factors. The ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.

[0387] For ultrasonic cleaning, a frequency of 200 kHz or more is preferably used, and a frequency of 900 kHz or more is more preferably used. By using such a frequency, damage to the semiconductor layer 230 can be reduced, for example.

[0388] When performing a cleaning process, the product does not necessarily have to be removed by the product removal process alone, as long as the product can be removed by the cleaning process. For example, if the product can be removed by performing a cleaning process after the above-mentioned plasma process, not all of the product does not have to be removed by the plasma process. In this case, the product removal process can be rephrased as a process for making the product easier to remove, specifically, a process for making the product easier to remove in the cleaning process. Note that, as long as the product can be removed by the cleaning process, the volume of the product may increase by the product removal process.

[0389] 24A to 24E, the mask 231 is removed. The mask 231 can be removed by, for example, wet etching. Alternatively, the mask 231 may be removed by, for example, dry etching.

[0390] In the above description, an example is shown in which the conductive layer 240 is formed by processing the conductive film 240f, and then the conductive layer 240 is processed to form the conductive layers 240a and 240b, and then the groove 290 is formed, but one embodiment of the present invention is not limited to this. For example, the groove 290 may be formed in the conductive film 240f, the insulating layer 280c, the insulating layer 280b, and the insulating layer 280a, and then the conductive film 240f may be processed to form the island-shaped conductive layers 240a and 240b.

[0391] 25A to 25E, an insulating layer 250 is formed on the semiconductor layer 230. The insulating layer 250 is formed so as to have a region located inside a groove 290 with a high aspect ratio. Therefore, the insulating layer 250 is preferably formed using a film formation method with good coverage, and more preferably formed using a CVD method, an ALD method, or the like.

[0392] It is preferable to perform microwave plasma treatment after the formation of the insulating layer 250. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the semiconductor layer 230 can be reduced. Furthermore, a crystalline region of the semiconductor layer 230 may grow. Note that details of the microwave plasma treatment will be described in Embodiment 2.

[0393] In addition, when the insulating layer 250 has a four-layer structure including a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer, microwave plasma treatment may be performed after the formation of the third insulating layer. Furthermore, microwave plasma treatment may be performed again after the formation of the first insulating layer. In this way, microwave plasma treatment in an oxygen-containing atmosphere may be performed multiple times (at least two times or more).

[0394] After the third insulating layer is formed, a process for supplying oxygen to the third insulating layer may be performed. This makes it possible to supply oxygen to the semiconductor layer 230. Note that the above description can be referred to for details of the process for supplying oxygen.

[0395] In this embodiment, the insulating layer 250 is formed by depositing an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film in this order using an ALD method.

[0396] 25A to 25E , a conductive film 260f, which will later become the conductive layer 260, is formed on the insulating layer 250. As the conductive film 260f, for example, a conductive film 260f1 on the insulating layer 250 and a conductive film 260f2 on the conductive film 260f1 are formed. The conductive film 260f is formed to have a region located within the groove 290. For example, the conductive film 260f1 is formed along the sidewalls and bottom of the groove 290. Furthermore, the conductive film 260f2 is formed to fill the region in the groove 290 that is more inward than the conductive film 260f1 (the opposite side to the insulating layer 250).

[0397] 26A to 26E, the conductive film 260f is processed to form the conductive layer 260. Specifically, the conductive layer 260_2 is formed from the conductive film 260f2. Furthermore, the conductive layer 260_1 is formed from the conductive film 260f1. The conductive layer 260 is formed on the insulating layer 250 so as to have a region located within the groove portion 290.

[0398] For example, the conductive layer 260 can be formed in the groove 290 by processing the entire surface of the conductive film 260f by anisotropic etching without forming a mask. Alternatively, the conductive layer 260 may be formed in the groove 290 by performing a CMP process on the conductive film 260f. When the conductive layer 260 is formed by performing a CMP process on the conductive film 260f, the upper surface of the conductive layer 260 can be made to coincide or approximately coincide with the upper surface of the insulating layer 250. The conductive layer 260 is formed to extend in a direction parallel to the extension direction of the groove 290. The conductive layer 260 is formed to extend, for example, in the Y direction, similar to the groove 290.

[0399] 27A to 27E , an insulating layer 283 is formed on the conductive layer 260 and the insulating layer 250, and an insulating layer 285 is formed on the insulating layer 283. After that, the insulating layers 285, 283, 250, the semiconductor layer 230, and the conductive layer 240a2 are processed to form an opening 270a that reaches the conductive layer 240a1. Furthermore, the insulating layers 285, 283, 250, the semiconductor layer 230, and the conductive layer 240b2 are processed to form an opening 270b that reaches the conductive layer 240b1. The openings 270a and 270b can be formed in parallel.

[0400] When the openings 270a and 270b are formed, the insulating layer 285, the insulating layer 283, the insulating layer 250, the semiconductor layer 230, the conductive layer 240a2, and the conductive layer 240b2 can be processed by etching. In particular, dry etching is preferable because it is suitable for fine processing.

[0401] 28A to 28E , conductive layer 244a is formed to have a region located within opening 270a, and conductive layer 244b is formed to have a region located within opening 270b. For example, conductive layer 244a is formed to fill opening 270a, and conductive layer 244b is formed to fill opening 270b. Conductive layer 244a can be formed to have a region in contact with the top surface of conductive layer 240a1 and a region in contact with the side surface of conductive layer 240a2 within opening 270a. Conductive layer 244b can be formed to have a region in contact with the top surface of conductive layer 240b1 and a region in contact with the side surface of conductive layer 240b2 within opening 270b.

[0402] For example, a conductive film to be the conductive layer 244a and the conductive layer 244b is formed so as to have a region located in the opening 270a and a region located in the opening 270b. Then, planarization treatment is performed on the conductive film to expose the top surface of the insulating layer 285, thereby forming the conductive layer 244a and the conductive layer 244b. CMP treatment is suitable as the planarization treatment. The planarization treatment removes at least a region of the conductive film that overlaps with the top surface of the insulating layer 285. By forming the conductive layer 244a and the conductive layer 244b using CMP treatment, the number of masks can be reduced compared to when the conductive layer 244a and the conductive layer 244b are formed by, for example, etching. In this manner, the transistor 200 is formed.

[0403] 28A to 28E , a conductive layer 245 is formed over the insulating layer 285, the conductive layer 244a, and the conductive layer 244b. For example, the conductive layer 245 can be formed by forming a conductive film that will become the conductive layer 245 and processing the conductive film. The conductive film can be processed by etching. In particular, dry etching is preferable because it is suitable for microfabrication.

[0404] The conductive layer 245 can be formed to have a region in contact with the upper surface of the conductive layer 244a and a region in contact with the upper surface of the conductive layer 244b. The conductive layer 245 can also be formed to be in contact with the upper surface of the insulating layer 285. The conductive layer 245 can be formed to extend in the X direction. As described above, the conductive layer 260 can be formed to extend in the Y direction. As a result, the conductive layer 245 intersects with the conductive layer 260 in a plan view.

[0405] The conductive layer 245 can be formed to overlap with the conductive layer 260 with the insulating layer 285 functioning as an interlayer insulating film and the insulating layer 283 interposed therebetween. This can reduce parasitic capacitance compared to, for example, a case in which the conductive layer 240a and the conductive layer 240b are formed to extend in the Y direction without forming the conductive layer 245. For example, the parasitic capacitance between the conductive layer 240a and the conductive layer 260 and the parasitic capacitance between the conductive layer 240b and the conductive layer 260 can be reduced. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device capable of high-speed operation.

[0406] As described above, the conductive layer 245 intersects with the conductive layer 260 in a plan view, for example, perpendicular or substantially perpendicular to the conductive layer 260. This allows the area where the conductive layer 245 and the conductive layer 260 overlap to be smaller than when the conductive layer 245 and the conductive layer 260 are formed parallel to each other in a plan view. This allows the parasitic capacitance generated between the conductive layer 260 and the conductive layer 245 to be reduced. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device capable of high-speed operation. Note that, for example, when the insulating layer 285 is sufficiently thick and the parasitic capacitance per unit area generated between the conductive layer 260 and the conductive layer 245 is negligibly small, the conductive layer 260 and the conductive layer 245 may be formed parallel to each other in a plan view.

[0407] In this manner, the semiconductor device shown in FIG. 1A and FIGS. 3A to 4B can be manufactured.

[0408] <Structure Example of Memory Device> A structure example of a memory device to which the semiconductor device of one embodiment of the present invention is applied will be described below. Specifically, the structure example of a memory device including a transistor 200 and a capacitor will be described.

[0409] 29A is a plan view illustrating a configuration example of a memory cell 150 included in a memory device of one embodiment of the present invention. As illustrated in FIG. 29A , the memory cell 150 includes a capacitor 100 and a transistor 200.

[0410] Fig. 29B is a cross-sectional view taken along dashed dotted lines A1-A2 in Fig. 29A. Fig. 29C is a cross-sectional view taken along dashed dotted lines B1-B2 in Fig. 29A. Note that Fig. 3B can be referred to for an example of the cross-sectional configuration taken along dashed dotted lines A3-A4 in Fig. 29A. Also, Fig. 4B can be referred to for an example of the cross-sectional configuration taken along dashed dotted lines B3-B4 in Fig. 29A.

[0411] The memory device shown in Figures 29A to 29C includes an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, a memory cell 150 on the conductive layer 110, an insulating layer 180 on the conductive layer 110, an insulating layer 280a on the insulating layer 180, an insulating layer 280b on the insulating layer 280a, an insulating layer 280c on the insulating layer 280b, an insulating layer 283 on the insulating layer 280c, an insulating layer 285 on the insulating layer 283, a conductive layer 244a, a conductive layer 244b, and conductive layers 245 on the conductive layer 244a, the conductive layer 244b, and the insulating layer 285.

[0412] The insulating layer 140 functions as a base insulating film or an interlayer insulating film. The insulating layer 140 can be formed using the same material as the insulating layer 210. The insulating layer 180, the insulating layer 280a, the insulating layer 280b, the insulating layer 280c, the insulating layer 283, and the insulating layer 285 function as interlayer insulating films. The conductive layer 110 has a region that functions as a wiring.

[0413] The memory cell 150 includes a capacitor 100 over the conductive layer 110 and a transistor 200 over the capacitor 100. The above-described <Structural Example 1 of Semiconductor Device> can be referred to for descriptions of the transistor 200, the insulating layer 280a, the insulating layer 280b, the insulating layer 280c, the groove 290, the insulating layer 283, the insulating layer 285, the opening 270a, the opening 270b, the conductive layer 244a, the conductive layer 244b, and the conductive layer 245. Note that the transistor 200, the insulating layer 280a, the insulating layer 280b, the insulating layer 280c, the groove 290, the insulating layer 283, the insulating layer 285, the opening 270a, the opening 270b, the conductive layer 244a, the conductive layer 244b, and the conductive layer 245 may have the structure shown in the above-described <Structural Example 2 of Semiconductor Device> or the structure shown in <Structural Example 3 of Semiconductor Device>. For a method for forming the transistor 200, the insulating layer 280a, the insulating layer 280b, the insulating layer 280c, the groove 290, the insulating layer 283, the insulating layer 285, the opening 270a, the opening 270b, the conductive layer 244a, the conductive layer 244b, and the conductive layer 245, refer to the above-mentioned <Example of manufacturing method of semiconductor device>.

[0414] The transistor 200 is preferably an OS transistor. Because an OS transistor has a low off-state current, its use in a storage device enables stored data to be retained for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so the power consumption of the storage device can be sufficiently reduced. By using the transistor 200 in a storage device, the storage device can be highly integrated and has low power consumption. Furthermore, the high frequency characteristics of an OS transistor enable high-speed reading and writing to and from the storage device.

[0415] The capacitor 100 has a conductive layer 115 on the conductive layer 110 , an insulating layer 130 on the conductive layer 115 , and a conductive layer 220 on the insulating layer 130 .

[0416] In the capacitor 100, the conductive layer 220 has a region that functions as one of a pair of electrodes (sometimes referred to as an upper electrode). The conductive layer 115 has a region that functions as the other of the pair of electrodes (sometimes referred to as a lower electrode). Furthermore, the insulating layer 130 has a region that functions as a dielectric. In other words, the capacitor 100 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0417] As shown in FIGS. 29B and 29C , an opening 190 is provided in the insulating layer 180, reaching the conductive layer 110. The conductive layer 115 is disposed within the opening 190. The conductive layer 115 has a region in contact with the top surface of the conductive layer 110 within the opening 190 and a region in contact with the side surface of the insulating layer 180 within the opening 190. The insulating layer 130 is disposed so as to be located within the opening 190. The conductive layer 220 is disposed so that at least a portion thereof is located within the opening 190. As shown in FIGS. 29B and 29C , the conductive layer 220 is preferably disposed so as to fill the opening 190. The films disposed within the opening 190 are preferably formed using an ALD method. This improves the film coverage. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 220 are preferably formed using an ALD method.

[0418] 29A to 29C , the thickness of the conductive layer 220 in a region that does not overlap with either the opening 190 or the groove 290 is defined as thickness T220. In other words, the thickness of the conductive layer 220 in a region that is located outside the opening 190 and does not overlap with the groove 290 is defined as thickness T220. Specifically, the thickness of the conductive layer 220 in a region that is located on the insulating layer 130 and does not overlap with either the opening 190 or the groove 290 can be defined as thickness T220.

[0419] The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across a dielectric not only on the bottom surface but also on the side surfaces within the opening 190, allowing for a larger capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can stabilize the read operation of the memory device. Furthermore, it is possible to promote miniaturization or high integration of memory devices.

[0420] As shown in Fig. 29A, it is preferable that opening 190 has a circular shape in plan view. By making it circular, the processing accuracy when forming opening 190 can be improved, and opening 190 of a fine size can be formed. Note that in this specification and the like, "circular" is not limited to a perfect circle. Also, in the present embodiment, an example has been shown in which opening 190 has a circular shape in plan view, but the present invention is not limited to this. Shapes that can be applied to opening 190 are the same as the shapes that can be applied to opening 271 described above.

[0421] 29B and 29C show an example in which the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. With such a structure, miniaturization or high integration of the memory device can be achieved.

[0422] A conductive layer 115 is provided along the sidewall of the opening 190 and the upper surface of the conductive layer 110. An insulating layer 130 is provided on the conductive layer 115. A conductive layer 220 is provided on the insulating layer 130 so as to fill the opening 190. A capacitor 100 having such a configuration may be referred to as a trench capacitor. However, the configuration of the capacitor 100 is not limited to this, and for example, a pillar capacitor, a parallel plate capacitor, or the like may also be used.

[0423] The insulating layer 130 is provided on the conductive layer 115. The insulating layer 130 is provided so as to cover the end portion of the conductive layer 115. This can prevent the conductive layer 115 and the conductive layer 220 from shorting out.

[0424] 29B and 29C show an example in which the insulating layer 130 is patterned. As a result, the insulating layer 180, the insulating layer 280a, the insulating layer 280b, the insulating layer 280c, the insulating layer 250, the insulating layer 283, the insulating layer 285, etc. have regions that do not overlap with the insulating layer 130. Therefore, for example, when an opening reaching the conductive layer 110 is provided in the insulating layer to connect the conductive layer 110 to another conductive layer, there is no need to provide an opening in the insulating layer 130. This makes it possible to easily form an opening reaching the conductive layer 110.

[0425] 29B and 29C show an example in which the end of the insulating layer 130 coincides or substantially coincides with the end of the conductive layer 220. For example, by processing the insulating layer 130 and the conductive film that will become the conductive layer 220 using the same mask, the end of the insulating layer 130 can coincide or substantially coincides with the end of the conductive layer 220.

[0426] The end of the conductive layer 220 is preferably located outside the end of the conductive layer 115 (on the opposite side to the opening 190). With this configuration, the conductive layer 220 can be embedded in the opening 190. Furthermore, the area of ​​the conductive layer 220 in a plan view can be increased. This makes it easier to form the groove 290 so as to have an area that overlaps with the conductive layer 220.

[0427] 29B and 29C show an example in which the conductive layer 110 has a recess in the region overlapping the opening 190. Also, FIGS. 29B and 29C show an example in which the conductive layer 115 has a region 101 with rounded corners within the recess of the conductive layer 110. This makes it possible to suppress electric field concentration in the insulating layer 130 near the region 101, compared to when the region 101 is a right angle or an acute angle (having a corner). Furthermore, the end 103 of the conductive layer 115 is located at a position lower in height from the reference plane than the top surface of the insulating layer 180. This makes it possible to suppress electric field concentration in the insulating layer 130 near the end 103, compared to when the end 103 is located on the insulating layer 180. As described above, suppressing electric field concentration in the insulating layer 130 suppresses dielectric breakdown of the insulating layer 130, thereby providing a highly reliable memory device.

[0428] An insulating layer 280a, an insulating layer 280b, and an insulating layer 280c are arranged in this order on the capacitor 100. Here, in the memory cell 150, the insulating layer 280a is provided so as to cover the end of the insulating layer 130 and the top surface of the insulating layer 180. For example, the end of the insulating layer 130 is in contact with the insulating layer 280a. Furthermore, the top surface of the insulating layer 180 is in contact with the insulating layer 280a in a region that does not overlap with either the insulating layer 130 or the conductive layer 220. FIG. 29B illustrates an example in which the insulating layer 280a has a region in contact with the side surface 223 of the conductive layer 220 and a region in contact with the side surface 224 opposite to the side surface 223. Note that when the conductive layer 220 is a hexahedron having a bottom surface, a top surface, and four side surfaces, the insulating layer 280a can have a region in contact with each of the four side surfaces.

[0429] As described above, the formation of the groove 290 exposes at least a portion of the top surface of the conductive layer 220, while preventing, for example, the end of the insulating layer 130 from being exposed and removing a portion of the insulating layer 130. As described above, the insulating layer 130 has a region that functions as a dielectric for the capacitor 100. This prevents, for example, fluctuations in the electrical characteristics of the capacitor 100, thereby providing a highly reliable semiconductor device. Furthermore, since the manufacturing yield of the semiconductor device can be increased, a memory device that can be manufactured at low cost can be provided. Furthermore, for example, a material with a low etching selectivity with respect to the semiconductor layer 230 can be used for the insulating layer 130. This allows for a wider range of material options for the insulating layer 130. For example, it becomes easier to use a material with a high dielectric constant for the insulating layer 130. This allows for improved electrical characteristics of the capacitor 100. For example, the capacitance of the capacitor 100 can be increased.

[0430] As shown in FIG. 29B , the transistor 200 is provided so as to overlap with the capacitor 100. Furthermore, a groove 290 in which part of the structure of the transistor 200 is provided has a region that overlaps with an opening 190 in which part of the structure of the capacitor 100 is provided. With this configuration, the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cells 150, allowing the memory cells 150 to be arranged at a high density and increasing the storage capacity of the storage device. In other words, the storage device can be highly integrated.

[0431] FIG. 29B illustrates an example in which the width of the opening 190 in the X direction is equal to or approximately equal to the width of the groove 290. The relationship in size between the width of the opening 190 and the width of the groove 290 is not particularly limited. The width of the opening 190 can be smaller than the width of the groove 290. By making the width of the opening 190 in the X direction smaller than the width of the groove 290, the alignment accuracy between the end of the conductive layer 220 and the opening 190 can be reduced, making it relatively easy to process the conductive layer 220. Furthermore, miniaturization or high integration of the memory device can be achieved. Furthermore, the width of the opening 190 can be larger than the width of the groove 290 in the X direction. By making the width of the opening 190 larger than the width of the groove 290 in the X direction, the capacitance of the capacitor 100 can be increased. Note that, for example, as shown in FIG. 29B , the relationship in size between the two widths in the semiconductor device of one embodiment of the present invention can be confirmed by a cross section parallel to the Z direction.

[0432] Furthermore, by providing the transistor 200 above the capacitor 100, the transistor 200 is not affected by heat treatment during manufacturing of the capacitor 100. Therefore, in the transistor 200, deterioration of electrical characteristics such as a change in threshold voltage and an increase in parasitic resistance, as well as an increase in variation in electrical characteristics due to the deterioration of electrical characteristics, can be suppressed.

[0433] The conductive layer 110 can be formed as a single layer or a stacked layer using the conductive material described above in the section [Conductive Layer]. For example, the conductive layer 110 can be formed using a conductive material with high conductivity, such as tungsten.

[0434] The conductive layer 115 can be formed as a single layer or a stacked layer using the conductive material described in the above section [Conductive Layer]. The conductive layer 115 is preferably formed as a single layer or a stacked layer using a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. For example, titanium nitride, ITSO, or the like may be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may be used. Alternatively, for example, a structure in which tungsten is stacked on a first titanium nitride, and a second titanium nitride is stacked on the tungsten may be used. With such a structure, when an oxide is used for the insulating layer 130, the insulating layer 130 can prevent the conductive layer 115 from being oxidized. Furthermore, when an oxide is used for the insulating layer 180, the insulating layer 180 can prevent the conductive layer 115 from being oxidized.

[0435] It is preferable to use a material with a high relative dielectric constant as described above in the section [Insulating Layer] for the insulating layer 130. By using a material with a high relative dielectric constant for the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitor 100 can be increased.

[0436] Furthermore, the insulating layer 130 is preferably formed by stacking insulating layers made of a material with a high dielectric constant, and preferably by using a layered structure of a material with a high dielectric constant and a material with a higher dielectric strength than the material with a high dielectric constant. For example, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By stacking insulating layers with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor 100 can be suppressed.

[0437] Furthermore, the insulating layer 130 can be made of a material capable of exhibiting ferroelectricity as described above in the section [Insulating Layer]. For example, a metal oxide containing one or both of hafnium and zirconium is preferable for the insulating layer 130 because it can exhibit ferroelectricity even in a thin film of only a few nanometers. The thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). Furthermore, for example, the thickness of the insulating layer 130 is preferably 8 nm to 12 nm. By using a ferroelectric layer that can be thinned, the capacitor 100 can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device.

[0438] Furthermore, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 130. For example, when the area (occupied area) of the ferroelectric layer in a plan view is 100 μm ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２ Even if the thickness is less than 10,000 nm, the film can still have ferroelectricity. ２ or less than 1000 nm ２ Even if the thickness is less than 100 Å, the ferroelectric layer may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor 100 can be reduced.

[0439] Yttrium can also be added to metal oxides containing either or both of hafnium and zirconium. For example, adding yttrium to hafnium zirconium oxide can enhance ferroelectricity.

[0440] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitor (hereinafter, sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitor 100, the memory device described in this embodiment functions as a ferroelectric memory.

[0441] Since the insulating layer 180 functions as an interlayer insulating film, it preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer insulating film, the parasitic capacitance generated between wirings can be reduced. As the insulating layer 180, an insulating layer containing a material with a low dielectric constant can be used in a single layer or a stacked layer. Silicon oxide and silicon oxynitride are preferable because they are thermally stable. Note that the insulating layer 180 can use an insulating material that can be used for the insulating layer 280b.

[0442] 30A and 30B are diagrams showing an example in which the end of insulating layer 130 in Figures 29B and 29C is located outside (on the opposite side from opening 190) the end of conductive layer 220. For example, after processing a conductive film that will become conductive layer 220 to form conductive layer 220, insulating layer 280a can be formed without processing insulating layer 130, thereby forming insulating layer 130 shown in Figures 30A and 30B.

[0443] 30A and 30B, an insulating layer 280a is provided to cover the top surface of the insulating layer 130. For example, the top surface of the insulating layer 130 is in contact with the insulating layer 280a in a region that does not overlap with the conductive layer 220.

[0444] FIG. 31A is a plan view showing a configuration example of a memory device in which a plurality of memory cells 150 shown in FIG. 29A are arranged. FIG. 32 is a cross-sectional view taken along dashed dotted line E1-E2 shown in FIG. 31A. FIG. 31A shows an example in which 2×2 memory cells 150 are arranged in the X and Y directions. Note that in FIGS. 31A and 32, the conductive layers 240a and 240b are collectively referred to as conductive layer 240A. Furthermore, the conductive layers 240a1 and 240b1 are collectively referred to as conductive layer 240A1. Furthermore, the conductive layers 240a2 and 240b2 are collectively referred to as conductive layer 240A2.

[0445] 31A and 32 , a conductive layer 240A can be shared between two adjacent memory cells 150. A conductive layer 245 extending in the X direction can connect multiple conductive layers 240A arranged in the X direction to each other. A conductive layer 260 extending in the Y direction can be shared between multiple memory cells 150 arranged in the Y direction.

[0446] 31A and 32, the semiconductor layer 230 can be shared between two memory cells 150 adjacent in the X direction. Furthermore, as shown in FIG. 31A, a plurality of semiconductor layers 230 can be provided in one groove 290.

[0447] 31B is a circuit diagram showing a configuration example of 2×2 memory cells 150. As described above, the memory cell 150 includes a transistor 200 and a capacitor 100. One of the source and the drain of the transistor 200 is connected to one of a pair of electrodes of the capacitor 100. The other of the source and the drain of the transistor 200 is connected to a wiring BIL. The gate of the transistor 200 is connected to a wiring WOL. The other of the pair of electrodes of the capacitor 100 is connected to a wiring CAL.

[0448] Here, the wiring BIL corresponds to the conductive layer 245. The wiring WOL corresponds to the conductive layer 260. The wiring CAL corresponds to the conductive layer 110.

[0449] As shown in Figures 31A and 32, it is preferable that the conductive layer 245 is provided extending in the X direction, and the conductive layer 260 is provided extending in the Y direction. With this configuration, the wiring BIL and the wiring WOL are provided so as to intersect with each other. In the example shown in Figures 31A and 32, the wiring CAL is provided parallel to the wiring BIL. However, the present invention is not limited to this. The wiring CAL may be provided parallel to the wiring WOL, for example.

[0450] The memory cells will be described in detail in a later embodiment.

[0451] 33A is a diagram showing an example in which end 103 shown in FIG. 29B is located on insulating layer 180. In the example shown in FIG. 33A, insulating layer 180 has a region 102 between the top surface and the side surface of opening 190, which has a curved portion. Also, in the example shown in FIG. 33A, end 103 has a tapered shape. By having region 102 have a curved portion and end 103 have a tapered shape, even when end 103 is located on insulating layer 180, electric field concentration in insulating layer 130 near region 102 and near end 103 can be suppressed. This suppresses dielectric breakdown of insulating layer 130, making it possible to provide a highly reliable memory device.

[0452] 33B is a diagram showing an example in which an insulating layer 187 is provided on the insulating layer 130 shown in FIG. 33A , for example, in a region of the insulating layer 130 that overlaps with the insulating layer 180. By providing the insulating layer 187, electric field concentration on the insulating layer 130 can be preferably suppressed in some cases.

[0453] A memory cell array can be configured by arranging the memory cells 150 in a three-dimensional matrix.

[0454] The memory device shown in FIG. 34 has n memory layers 160. Specifically, a memory layer 160[2] is provided on the memory layer 160[1], and (n-2) memory layers are further provided on the memory layer 160[2], with the memory layer 160[n] provided at the top. The number of memory cells included in one memory layer 160 is not particularly limited, and two or more memory cells may be included. The conductive layers 247, 248, 249, and the like connect the memory cells included in the n memory layer 160 to a sense amplifier (not shown) provided below the n memory layer 160. In this case, the conductive layers 245, 248, 249, and the like function as part of the wiring BIL. In this way, by providing a memory device or the like above or below the memory device shown in FIG. 29B, the memory capacity per unit area can be increased.

[0455] Note that the conductive layer 247, the conductive layer 248, the conductive layer 249, etc. may function as plugs or wirings for connecting circuit elements such as switches, transistors, capacitors, inductors, resistors, and diodes, wirings, electrodes, or terminals to the memory cell 150.

[0456] 34 shows an example in which the conductive layer 247 and the conductive layer 249 are in contact with the bottom surface of the conductive layer 245, and the conductive layer 248 is in contact with the top surface of the conductive layer 245. The conductive layer 247, the conductive layer 248, and the conductive layer 249 are provided in openings formed in the insulating layer 140, the insulating layer 180, the insulating layer 280a, the insulating layer 280b, the insulating layer 280c, the insulating layer 250, the insulating layer 283, the insulating layer 285, or the like. Note that the conductive layer 247, the conductive layer 248, the conductive layer 249, or the like can be formed using a conductive material or the like that can be used for the conductive layer 240a and the conductive layer 240b.

[0457] 34 shows an example in which the insulating layer 130 is patterned. This eliminates the need to provide, for example, an opening in which the conductive layer 247 is provided, an opening in which the conductive layer 248 is provided, and an opening in which the conductive layer 249 is provided, in the insulating layer 130. This makes it possible to easily form the above-mentioned openings.

[0458] As shown in Figure 34, by stacking multiple memory cells, cells can be integrated and arranged without increasing the area occupied by the memory cell array. In other words, a 3D memory cell array can be configured. This allows for a larger memory capacity per unit area.

[0459] FIG. 35 shows an example of a cross-sectional configuration of a memory device in which a layer having memory cells is stacked over a layer in which a driver circuit including a sense amplifier is provided.

[0460] In FIG. 35, a memory cell 150 (a transistor 200 and a capacitor 100 ) is provided above a transistor 300 .

[0461] The transistor 300 is one of the transistors included in the sense amplifier.

[0462] For the memory cell 150 shown in FIG. 35, the description of the memory cell 150 described above can be referred to.

[0463] 35, the bit lines can be shortened by providing a sense amplifier so as to overlap the memory cells 150. This reduces the bit line capacitance, enabling the memory device to be driven at high speed.

[0464] 35 can correspond to the semiconductor device 900 described in Embodiment 3. Specifically, the transistor 300 corresponds to a transistor included in a sense amplifier 927 in the semiconductor device 900. The memory cell 150 corresponds to a memory cell 950.

[0465] The transistor 300 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel or n-channel transistor. The substrate 311 preferably contains a silicon-based semiconductor, specifically, single-crystal silicon.

[0466] Here, in the transistor 300 shown in FIG. 35 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that contacts the top of the convex portion and functions as a mask for forming the convex portion may be provided. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0467] Note that the transistor 300 illustrated in FIG. 35 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0468] Between each structure, a wiring layer provided with an interlayer insulating film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductive layer functioning as a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0469] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer insulating film over the transistor 300. A conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as plugs or wirings.

[0470] The insulating layer 322 may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0471] A wiring layer may be provided on the insulating layer 326 and the conductive layer 330. For example, in Fig. 35, an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 functions as a plug or a wiring.

[0472] The insulating layer 352, the insulating layer 354, and the like which function as interlayer insulating films can be formed using the insulating layer that can be used in the above-described semiconductor device or memory device.

[0473] Conductive layers functioning as plugs or wirings, such as the conductive layer 328, the conductive layer 330, and the conductive layer 356, can be formed using a conductive material applicable to the conductive layer 240a and the conductive layer 240b. A high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity is preferably used, and tungsten is preferred. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.

[0474] The conductive layer 240a and the conductive layer 240b of the transistor 200 are connected to the low-resistance region 314b functioning as a source region or a drain region of the transistor 300 through the conductive layer 643, the conductive layer 645, the conductive layer 646, the conductive layer 356, the conductive layer 330, and the conductive layer 328.

[0475] The conductive layer 643 is embedded in the insulating layer 285, the insulating layer 283, the insulating layer 250, the insulating layer 280c, the insulating layer 280b, the insulating layer 280a, and the insulating layer 180. The conductive layer 645 is embedded in the insulating layer 180. The conductive layer 645 can be manufactured using the same material and in the same process as the conductive layer 110. The conductive layer 646 is embedded in the insulating layer 649. The insulating layer 649 insulates the transistor 300 from the conductive layer 110.

[0476] This embodiment mode can be combined with other embodiment modes and examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0477] In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described. The oxide semiconductor layer of one embodiment of the present invention has a stacked-layer structure. Note that, as will be described later, it may be difficult to identify boundaries between stacked films.

[0478] [Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0479] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution TEM image (also referred to as a multi-beam interference image), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, the oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0480] For example, the CAAC structure is formed so that the c-axis is perpendicular or substantially perpendicular to the surface or surface of the oxide semiconductor layer on which the oxide semiconductor layer is to be formed. In the CAAC structure, metal atoms are arranged in layers parallel or substantially parallel to the surface on which the oxide semiconductor layer is to be formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the oxide semiconductor layer is to be formed.

[0481] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for the analysis.

[0482] When the oxide semiconductor layer has a CAAC structure, a group of bright spots (specifically, bright spots arranged in layers) reflecting the layered arrangement of metal atoms is observed in a cross section of the oxide semiconductor layer observed using a TEM image. Specifically, the bright spots are observed to be arranged in layers in a direction parallel or approximately parallel to the surface on which the oxide semiconductor layer is formed.

[0483] When electron diffraction is performed on an oxide semiconductor layer having a CAAC structure, spots (bright points) indicating c-axis orientation are observed in the electron diffraction pattern.

[0484] Furthermore, an FFT pattern obtained by subjecting a TEM image to a fast Fourier transform (FFT) process reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0485] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is acquired, and an FFT process is performed on each region in the cross-sectional TEM image to create an FFT pattern. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of a line segment connecting two spots that have high brightness and are approximately equidistant from the center among the spots observed in the created FFT pattern is defined as the crystal axis direction. A region in which the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface on which the film is formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered to have a CAAC structure.

[0486] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to a surface where the oxide semiconductor layer is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the a-b plane, and the oxide semiconductor layer has crystallinity.

[0487] Note that the crystallinity of the metal oxide included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0488] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. The metal oxide preferably contains two or three elements selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide may contain indium and zinc as main components and may further contain element M. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more elements selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may also include metalloid elements.

[0489] Examples of metal oxides that can be used according to one embodiment of the present invention include In—Zn oxide, ITO, indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), In—Ga—Zn oxide, ITSO, indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, Ga—Zn oxide, Al—Zn oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), or the like can be used. Indium oxide can be used as the metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, or the like can be used as the metal oxide according to one embodiment of the present invention.

[0490] By increasing the content of indium in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0491] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a higher period number in the periodic table, the field-effect mobility of a transistor may be improved. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0492] The metal oxide may contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0493] Furthermore, by increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0494] Furthermore, by increasing the content of element M in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0495] In the present embodiment, an In-M-Zn oxide may be used as an example of the metal oxide.

[0496] [Method for Forming Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention can be formed by forming a metal oxide by two film formation methods, for example. That is, the oxide semiconductor layer of one embodiment of the present invention can be formed by forming a metal oxide by a first film formation method and a second film formation method.

[0497] For example, when the oxide semiconductor layer has a two-layer structure of a first layer and a second layer over the first layer, the oxide semiconductor layer can be manufactured by forming the first layer on a surface to be formed by the second film formation method and then forming the second layer above the first layer by the first film formation method.

[0498] For example, when the oxide semiconductor layer has a three-layer structure including a first layer, a second layer over the first layer, and a third layer over the second layer, the oxide semiconductor layer can be manufactured by forming the first layer on a surface to be formed by the second film formation method, then forming the second layer by the first film formation method, and then forming the third layer by the second film formation method.

[0499] The second film formation method is preferably a film formation method that causes less damage to the surface on which the oxide semiconductor layer is formed than the first film formation method. This can suppress the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer on which the oxide semiconductor layer is formed. Furthermore, since impurities such as silicon can be prevented from being mixed into the second layer formed on the first layer, the crystallinity of the oxide semiconductor layer can be further improved in some cases.

[0500] Examples of the second film formation method include ALD, CVD, and MBE. Examples of CVD methods include plasma CVD, thermal CVD, photo-CVD, and MOCVD. The MBE method is a film formation method that grows a thin film with a crystalline structure that reflects the crystalline system of the substrate, and can be said to be one of the film formation methods that causes little damage to the surface on which the film is formed. Also, a wet method can be used as the second film formation method. The wet method is one of the film formation methods that causes little damage to the surface on which the film is formed. Examples of the wet method include spray coating.

[0501] The first film formation method is preferably a method capable of forming a crystalline metal oxide film. In this case, it is particularly preferable that the metal oxide film formed has a CAAC structure. Examples of the first film formation method include a sputtering method and a PLD method. Since a metal oxide film formed by a sputtering method is likely to have crystallinity, the sputtering method is suitable as the first film formation method.

[0502] When a metal oxide is formed on a surface to be formed using the first film formation method, damage to the surface to be formed may cause alloying between components contained in the metal oxide and components contained in the layer on the surface to be formed. This alloying may result in the formation of a mixed layer at the interface between the metal oxide and the layer on the surface to be formed. This mixed layer may also be referred to as an alloyed region. The formation of the mixed layer may also be referred to as alloying.

[0503] For example, when a sputtering method is used as the first film-forming method, a mixed layer may be formed by particles (also referred to as sputtering particles) emitted from a target or the like, or energy imparted to a substrate by the sputtering particles or the like. Specifically, when a metal oxide film is formed by the first film-forming method using an insulating layer containing silicon, such as a silicon oxide film, as a formation surface, silicon may be mixed into the metal oxide. There is a concern that the inclusion of impurities such as silicon into the metal oxide may inhibit the crystallization of the metal oxide. Furthermore, there is a concern that using an oxide semiconductor layer containing impurities in a transistor may adversely affect the initial characteristics or reliability of the transistor. Furthermore, even when heat treatment, which will be described later, is performed, it is difficult to enhance the crystallinity of the alloyed region.

[0504] Therefore, as described above, by forming a metal oxide by the second film formation method before forming a metal oxide by the first film formation method, it is possible to prevent impurities from being mixed into the oxide semiconductor layer. Furthermore, alloying can be suppressed. Therefore, the initial characteristics and reliability of the transistor can be improved. Furthermore, the crystallinity of the oxide semiconductor layer can be further increased.

[0505] The ALD method is suitable as the second film formation method because it can suppress damage to the formation surface compared to the sputtering method. Furthermore, the ALD method is a film formation method with better coverage than the sputtering method, and by using the ALD method as the film formation method for the first layer and the third layer, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well covered on steps, openings, etc. with a high aspect ratio.

[0506] Here, a method for forming an In-M-Zn oxide as the first layer or the third layer by ALD will be described.

[0507] First, a source gas containing an indium precursor is introduced into a reaction chamber, and the precursor is adsorbed onto the surface to be formed. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby removing components other than indium while leaving indium adsorbed onto the substrate, thereby forming a layer in which indium and oxygen are combined.

[0508] Next, a source gas containing a precursor having element M is introduced into the reaction chamber and is adsorbed onto the layer in which indium and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer in which element M and oxygen are bonded.

[0509] Next, a source gas containing a zinc-containing precursor is introduced into the reaction chamber and adsorbed onto the layer in which the element M and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer in which zinc and oxygen are bonded.

[0510] By repeating the above-described method, an In-M-Zn oxide can be formed as an oxide semiconductor layer on a layer that is a formation surface by an ALD method.

[0511] When an oxide semiconductor layer is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H２ O) and the like can be used. ３ ), oxygen (O ２ By using an oxidizing agent such as HCl, the amount of hydrogen mixed into the oxide semiconductor layer can be reduced.

[0512] Here, the temperature to which the substrate is heated when the precursor is introduced into the reaction chamber is defined as a first temperature, and the temperature to which the substrate is heated when the oxidizing agent is introduced into the reaction chamber is defined as a second temperature.

[0513] The first temperature is preferably set to a temperature corresponding to the decomposition temperature of the precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, triethylgallium as the gallium-containing precursor, and diethylzinc as the zinc-containing precursor, the first temperature is, for example, 100° C. or higher and 350° C. or lower, preferably 150° C. or higher and 300° C. or lower.

[0514] Note that the second temperature is preferably higher than the first temperature. For example, when the oxidizing agent contains ozone, the second temperature is preferably higher than 200° C. and lower than 450° C., more preferably higher than or equal to 250° C. and lower than or equal to 400° C., and further preferably higher than or equal to 300° C. and lower than or equal to 350° C. With such a configuration, the hydrogen concentration in the oxide semiconductor layer can be reduced. Furthermore, by setting the first temperature lower than the second temperature, particles generated by decomposition of the precursor can be suppressed.

[0515] It is preferable that the reaction chamber into which the precursor is int...

Claims

a semiconductor layer, a conductive layer, a first insulating layer, and a second insulating layer; the first insulating layer contacts at least a portion of a first side surface of the conductive layer and at least a portion of a second side surface opposite to the first side surface; the second insulating layer is located on the first insulating layer and on the conductive layer; the first insulating layer has a first groove; the second insulating layer has a second groove overlapping the first groove; the first groove portion has a region that reaches the conductive layer and a region that is provided as a recess; The semiconductor layer has a region in contact with the conductive layer and a region along a part of a side surface of the second insulating layer in the second trench. 　 In claim 1, The semiconductor device, wherein the thickness of the first insulating layer in a region where the first groove is not provided and where the first insulating layer does not overlap with the conductive layer is 0.5 times or more the thickness of the conductive layer. 　 In claim 2, a fourth insulating layer; the fourth insulating layer is located on the second insulating layer; the fourth insulating layer has a third groove overlapping the first groove and the second groove; The semiconductor device, wherein the thickness of the fourth insulating layer is less than the thickness of the first insulating layer in a region where the first groove portion is not provided and where the fourth insulating layer does not overlap with the conductive layer. 　 In claim 2, The first insulating layer has a region in contact with an upper surface of the conductive layer. 　 In claim 4, The semiconductor device, wherein the thickness of the first insulating layer in the region overlapping with the conductive layer is less than the thickness of the conductive layer. 　 a transistor, a first insulating layer, and a second insulating layer; the transistor includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a third insulating layer; the first insulating layer contacts at least a portion of a first side surface of the first conductive layer and at least a portion of a second side surface opposite to the first side surface; the second insulating layer is located on the first insulating layer and on the first conductive layer; the second conductive layer is located on the second insulating layer; the first insulating layer has a first groove; the second insulating layer has a second groove overlapping the first groove; the first groove portion has a region that reaches the first conductive layer and a region that is provided as a recess; the semiconductor layer has a region in contact with the first conductive layer, a region in contact with the second conductive layer, and a region along a part of a side surface of the second insulating layer in the second groove portion; the third insulating layer is provided on the semiconductor layer so as to have a region located within the second trench; The third conductive layer has a region facing the semiconductor layer in the second trench with the third insulating layer sandwiched therebetween. 　 In claim 6, A semiconductor device, wherein the thickness of the first insulating layer in a region where the first groove portion is not provided and where the first insulating layer does not overlap with the first conductive layer is 0.5 times or more the thickness of the first conductive layer. 　 In claim 7, a fourth insulating layer; the fourth insulating layer is located on the second insulating layer; the second conductive layer is located on the fourth insulating layer; the fourth insulating layer has a third groove overlapping the first groove and the second groove; The thickness of the fourth insulating layer is less than the thickness of the first insulating layer in a region where the first groove portion is not provided and where the fourth insulating layer does not overlap with the first conductive layer. 　 In claim 7, The first insulating layer has a region in contact with an upper surface of the first conductive layer. 　 In claim 9, A semiconductor device, wherein the thickness of the first insulating layer in the region overlapping with the first conductive layer is less than the thickness of the first conductive layer. 　 In claim 6, It has a capacity the capacitor includes the first conductive layer, a fourth conductive layer, and a fifth insulating layer; the fifth insulating layer is located on the fourth conductive layer; the first conductive layer is located on the fifth insulating layer; The semiconductor device, wherein the first insulating layer has a region in contact with the fifth insulating layer. 　 In any one of claims 1 to 11, The semiconductor device, wherein the semiconductor layer contains indium. 　 forming a first conductive layer; forming a first insulating layer so as to cover a side surface and an upper surface of the first conductive layer; performing a planarization process on the first insulating layer; forming a second insulating layer on the first insulating layer and on the first conductive layer; forming a second conductive layer on the second insulating layer; forming a first groove portion in the first insulating layer so as to have a region reaching the first conductive layer and a region provided as a recess; forming a second groove in the second insulating layer; forming a semiconductor film so as to cover the first groove portion and the second groove portion; forming a semiconductor layer having a region in contact with the first conductive layer and a region in contact with the second conductive layer by processing the semiconductor film, and exposing a part of a side surface of the second insulating layer in the second groove portion; forming a third insulating layer on the semiconductor layer so as to have a region located within the second trench; a third conductive layer formed in the second trench so as to have a region facing the semiconductor layer with the third insulating layer interposed therebetween; 　 In claim 13, forming a fourth insulating layer on the second insulating layer; forming the second conductive layer on the fourth insulating layer; a method for manufacturing a semiconductor device, comprising forming a third groove in the fourth insulating layer after forming the second conductive layer and before forming the first groove and the second groove, a thickness of the fourth insulating layer being less than a thickness of the first insulating layer in a region where the first groove is not provided and where the fourth insulating layer does not overlap with the first conductive layer; 　 In claim 13 or claim 14, The method for manufacturing a semiconductor device includes processing the semiconductor film under first conditions, and then processing the semiconductor film under second conditions that are more isotropic than the first conditions.

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