Imaging device and imaging method

Abstract

The present invention makes it possible to select operation or non-operation of a buffer used for input of a reference signal to a comparator while suppressing an increase in imbalance of output of the buffer.　This imaging device comprises: a pixel array unit in which pixels are arranged in a matrix in a row direction and a column direction; an analog-to-digital (AD) conversion unit which performs AD conversion on pixel signals for each column on the basis of the result of a comparison between the pixel signal read from each pixel and a reference signal; a buffer which inputs the reference signal to the AD conversion unit for each column; and a buffer control unit which selects operation or non-operation of the buffer for each column.

Description

Imaging device and imaging method

[0001] The present technology relates to an imaging device and an imaging method, and more particularly, to an imaging device and an imaging method in which a buffer is used for inputting a reference signal that is referred to in AD (Analog to Digital) conversion.

[0002] An imaging device may be provided with an AD conversion circuit to AD-convert and output pixel signals read from pixels. For example, a technology has been disclosed in which, based on the result of brightness / darkness determination of light received by a unit pixel, execution or stop of AD conversion processing by the AD conversion circuit for a pixel signal subsequently read out is selectively controlled (see, for example, Patent Document 1). Here, a comparator is used to compare the pixel signal with a reference signal to perform AD conversion of the pixel signal. In this case, a buffer may be used for each column to input the reference signal to the comparator in order to suppress kickback to the reference signal when the comparator output is inverted.

[0003] Japanese Patent Application Laid-Open No. 2022-25515

[0004] However, depending on the selection of whether the buffer is operational or inoperative for each column, there is a risk that imbalance in buffer output between columns may increase.

[0005] This technology was developed in light of these circumstances, and aims to enable the selection of whether to operate or not operate the buffer while suppressing an increase in imbalance in the output of the buffer used to input the reference signal to the comparator.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an imaging device including: a pixel array unit in which pixels are arranged in a matrix in row and column directions; an AD conversion unit that performs AD (Analog to Digital) conversion of pixel signals read from the pixels for each column based on a comparison result between the pixel signals and a reference signal; a buffer that inputs the reference signal to the AD conversion unit for each column; and a buffer control unit that selects whether the buffer operates or does not operate for each column. This brings about an effect that the reference signal is input to the AD conversion unit for each column via the buffer while enabling selection of whether the buffer operates or does not operate.

[0007] In the first aspect, the buffer control unit may select whether to operate or not operate the buffer for each column based on a load on the buffer, thereby providing an effect of selectively realizing operation or non-operation of the buffer while suppressing imbalance in the load of the buffer output.

[0008] In the first aspect, the buffer control unit may select operation or non-operation of the buffer for each column so that a relationship between the driving force of the buffer selected for operation and the load on the buffer is kept constant, thereby achieving an effect of selectively realizing operation or non-operation of the buffer while equalizing the load on the buffer output.

[0009] In the first aspect, the buffer control unit may select whether to operate or not operate the buffer based on the selection of whether to perform or stop AD conversion by the AD conversion unit, thereby providing an effect that selectively operates or not operates the buffer while selectively performing or stopping AD conversion.

[0010] In the first aspect, the buffer control unit may select the operation of the buffer of the column for which the execution of the AD conversion is selected and may select the non-operation of the buffer of the column for which the stop of the AD conversion is selected, thereby achieving an effect of selecting the execution of AD conversion and the operation of the buffer while reducing power consumption of the AD conversion unit and the buffer.

[0011] In the first aspect, the pixel circuit may further include a connection line connecting outputs of the buffers of different columns, thereby providing a buffer for each column and averaging out variations in buffer output for each column.

[0012] In the first aspect, the buffer control unit may turn on the buffers independently of whether the AD conversion unit is performing or stopping AD conversion, thereby achieving an effect of averaging out variations in buffer output among columns while equalizing loads on the buffer outputs.

[0013] In the first aspect, the buffer control unit may select operation or non-operation of the buffer in units of a block that includes a plurality of the columns, thereby providing an effect that a combination of selection of operation or non-operation of the buffer is set in units of a block.

[0014] In the first aspect, the buffer control unit may simultaneously select the operation of a plurality of buffers in at least one of the blocks, regardless of whether the AD conversion unit is performing or stopping AD conversion, thereby achieving an effect of averaging out variations in buffer output among columns while equalizing loads on the buffer outputs.

[0015] In the first aspect, the buffer control unit may select the operation of at least one buffer in the block, regardless of whether the AD conversion unit is performing or stopping AD conversion, thereby achieving an effect of averaging out variations in buffer output among columns while equalizing loads on the buffer outputs.

[0016] In the first aspect, the semiconductor memory device may further comprise a switch for switching connection of the outputs of the buffers in different columns, thereby providing an effect that connection and disconnection of the outputs of the buffers in different columns can be selected.

[0017] In the first aspect, the buffer control unit may disconnect the output of the buffer of the column selected to be inoperative from the output of the buffer of the column adjacent to the column selected to be inoperative via the switch, thereby providing an effect that the operation or non-operation of the buffer is selected while suppressing crosstalk between the buffers of different columns.

[0018] In the first aspect, the buffer control unit may connect the outputs of the buffers of the adjacent columns for which the operation has been selected via the switch, thereby enabling selection of whether the buffers are operating or not, and averaging out variations in the buffer outputs for each column.

[0019] In addition, in the first aspect, the image sensor may further include an AD conversion control unit that selects whether to perform AD conversion by the AD conversion unit based on a result of determining the illuminance of light incident on the pixel, thereby reducing the power consumption of the AD conversion unit based on the illuminance of light incident on the pixel.

[0020] In the first aspect, the buffer control unit may select whether to operate the buffer based on a result of determining the illuminance of light incident on the pixel, thereby reducing the power consumption of the buffer based on the illuminance of light incident on the pixel.

[0021] In addition, in the first aspect, the buffer control unit may select the operation of the buffer only for a column for which AD conversion by the AD conversion unit is selected based on a determination result of illuminance of light incident on the pixel, thereby achieving an effect of reducing power consumption of the AD conversion unit and the buffer based on illuminance of light incident on the pixel.

[0022] In addition, in the first aspect, the buffer control unit may select the buffer operation of all columns included in a block that groups together multiple columns when the number of columns for which the buffer operation has been selected is less than n (n is a positive integer), thereby improving the uniformity of the load on the buffer output.

[0023] In addition, in the first aspect, when the number of columns for which the buffer operation has been selected is less than m (m is a positive integer) in a block of the plurality of columns, the buffer control unit may additionally select the operation of the buffer for a column for which the stop of AD conversion by the AD conversion unit has been selected based on a determination result of illuminance of light incident on the pixel, thereby improving the uniformity of the load on the buffer output.

[0024] A second aspect is an imaging method including: selecting operation or non-operation of a buffer for each column that inputs a reference signal to an AD converter that performs AD (Analog to Digital) conversion on the pixel signals for each column based on a comparison result between a reference signal and pixel signals read from pixels arranged in a matrix in the row and column directions; and AD converting the pixel signals based on a comparison result between the reference signal input via the buffer whose operation has been selected. This provides the effect of allowing selection of operation or non-operation of the buffer while inputting the reference signal to the AD converter for each column via the buffer.

[0025] In addition, in the second aspect, the buffer may be selected to operate or not operate based on a selection of whether to perform or stop AD conversion by the AD conversion unit, and the pixel signal may be AD converted based on a comparison result between a reference signal input via the buffer whose operation has been selected. This brings about an effect that the buffer is selectively operated or not operated while selectively performing or stopping AD conversion.

[0026] 1 is a block diagram showing a configuration example of an imaging device according to a first embodiment. FIG. 2 is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment. FIG. 3 is a diagram showing a circuit configuration example of a pixel provided in the solid-state imaging device according to the first embodiment. FIG. 4 is a block diagram showing a configuration example for each column of the solid-state imaging device according to the first embodiment. FIG. 5 is a block diagram showing a configuration example of an AD conversion unit and a ramp source follower unit according to a second embodiment. FIG. 6 is a block diagram showing a first operation example of the AD conversion unit and the ramp source follower unit according to the second embodiment. FIG. 7 is a flowchart showing a first operation example of the ramp source follower unit according to the second embodiment. FIG. 8 is a block diagram showing a second operation example of the AD conversion unit and the ramp source follower unit according to the second embodiment. FIG. 9 is a flowchart showing a second operation example of the ramp source follower unit according to the second embodiment. FIG. 10 is a block diagram showing a configuration example of an AD conversion unit and a ramp source follower unit according to a third embodiment. FIG. 11 is a block diagram showing an operation example of the AD conversion unit and the ramp source follower unit according to the third embodiment. FIG. 12 is a block diagram showing a configuration example of an AD conversion unit and a ramp source follower unit according to a fourth embodiment. FIG. 13 is a block diagram showing an operation example of the AD conversion unit and the ramp source follower unit according to the fourth embodiment. FIG. 10 is a block diagram showing a configuration example of an AD conversion unit and a ramp source follower unit according to a fifth embodiment. FIG. 11 is a block diagram showing an operation example of an AD conversion unit and a ramp source follower unit according to the fifth embodiment. FIG. 12 is a perspective view showing an example of a stack of a solid-state imaging device according to a sixth embodiment. FIG. 13 is a block diagram showing a schematic configuration example of a vehicle control system. FIG. 14 is an explanatory diagram showing an example of an installation position of an imaging unit.

[0027] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example in which operation or non-operation of a buffer is selected for each column, which inputs a reference signal to an AD conversion unit that performs AD conversion on a pixel signal for each column based on a comparison result between a pixel signal and a reference signal) 2. Second embodiment (an example in which connection lines are provided to connect the outputs of buffers of different columns, and operation or non-operation of a buffer is selected for each column in units of a block that groups multiple columns based on selection of whether to perform or stop AD conversion) 3. Third embodiment (an example in which connection lines are provided to connect the outputs of buffers of different columns, and operation or non-operation of a buffer that inputs a reference signal to an AD conversion unit for each column is selected for each column, independently of selection of whether to perform or stop AD conversion) 4. Fourth embodiment (an example in which buffer outputs are separated for each column, and operation or non-operation of a buffer that inputs a reference signal to an AD conversion unit for each column is selected for each column based on selection of whether to perform or stop AD conversion) 5. 5. Fifth embodiment (an example in which a switch is provided to switch the connection of buffer outputs of different columns, and operation or non-operation of a buffer that inputs a reference signal to an AD conversion unit for each column is selected for each column based on the selection of whether to perform or stop AD conversion) 6. Sixth embodiment (an example in which pixel array units are stacked) 7. Example of application to a moving body

[0028] 1. First Embodiment FIG. 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment.

[0029] In the figure, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to one another via a bus 108. The imaging device 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, a vehicle, or a drone.

[0030] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0031] The solid-state imaging device 102 converts an optical image formed on the light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. Single-slope AD conversion can be used to digitize the electrical signal. In this case, the solid-state imaging device 102 may support CDS (Correlated Double Sampling) readout or DDS readout. Each pixel may include a single photodiode or multiple photodiodes with different sensitivities. The solid-state imaging device 102 is, for example, a complementary metal oxide semiconductor (CMOS) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor. The solid-state imaging device 102 may also be a LOFIC image sensor.

[0032] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on instructions from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.

[0033] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 104 may include a processor that executes processing based on software.

[0034] The storage unit 105 stores images captured by the solid-state imaging device 102 and stores imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store a program that operates the imaging device 100 based on software. The storage unit 105 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0035] The display unit 106 displays captured images and various information that supports the image capturing operation, etc. The display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.

[0036] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0037] Depending on the configuration of the imaging device 100, some of the above functions may not be present, or conversely, the imaging device 100 may further include functions that are not disclosed.

[0038] FIG. 2 is a block diagram showing an example of the configuration of the solid-state imaging device according to the first embodiment.

[0039] In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.

[0040] The pixel array unit 111 includes a plurality of pixels PX. The pixels PX are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). Each pixel PX can form a source follower with the column readout circuit 113 when reading out a signal. Each pixel PX is connected to a horizontal drive line HSL for each row and to a vertical signal line VSL for each column. The horizontal drive line HSL drives each pixel PX for each row when reading out a signal from each pixel PX. The vertical signal line VSL transmits the pixel signals read out from the pixels PX to the column signal processing unit 114 for each column.

[0041] Each pixel PX may be a single pixel, a four-pixel shared pixel, or an eight-pixel shared pixel. The pixels PX may be arranged in a Bayer array or a quad-Bayer array. The light received by each pixel PX may be visible light, near infrared light (NIR), short wavelength infrared light (SWIR), ultraviolet light, X-rays, or the like.

[0042] The vertical scanning circuit 112 scans the pixels PX to be read in the column direction. The vertical scanning circuit 112 may be configured to include a vertical register. Here, when reading out signals from each pixel PX, the vertical scanning circuit 112 can drive each pixel PX row by row via a horizontal drive line HSL.

[0043] The column readout circuit 113 can form a source follower with each pixel PX when reading out a signal from the pixel PX. At this time, the column readout circuit 113 can change the potential of the vertical signal line VSL for each column based on the charge held in each pixel PX.

[0044] The column signal processing unit 114 processes signals transmitted in the column direction from each pixel PX. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel PX. The column signal processing unit 114 can also perform analog-to-digital (AD) conversion processing based on the signals transmitted in the column direction from each pixel PX, and output an image pickup signal Gout. The column signal processing unit 114 includes a ramp source follower unit 114A and a column ADC unit 114B.

[0045] The ramp source follower unit 114A inputs the reference signal REF to the column ADC unit 114B for each column based on the source follower of the reference signal REF. At this time, the ramp source follower unit 114A can configure a ramp source follower for each column.

[0046] The column ADC unit 114B can perform AD conversion processing in parallel for each column, based on the comparison result between the pixel signal read from the pixel PX and the reference signal REF input via the ramp source follower unit 114A.

[0047] The horizontal scanning circuit 115 scans the pixels PX to be read in the row direction. The horizontal scanning circuit 115 may be configured to include a horizontal register.

[0048] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114. At this time, the control circuit 116 can coordinate the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame.

[0049] FIG. 3 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.

[0050] 1, a pixel PX includes a photodiode PD, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion FD. The transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125 can be MOS (Metal Oxide Semiconductor) transistors.

[0051] The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode PD is connected to the floating diffusion FD via the transfer transistor 122. The floating diffusion FD is connected to the power supply VDD via the reset transistor 123. The power supply VDD is connected to the vertical signal line VSL via the series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion FD.

[0052] A transfer signal TGL is applied to the gate of the transfer transistor 122. A reset signal RST is applied to the gate of the reset transistor 123. A selection signal SEL is applied to the gate of the selection transistor 125. The transfer signal TGL, reset signal RST, and selection signal SEL can be transmitted to each pixel PX via the horizontal drive line HSL in FIG.

[0053] When the transfer transistor 122 is turned on, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD. When the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes depending on the potential of the floating diffusion FD. The source potential of the amplification transistor 124 is applied to the vertical signal line VSL via the selection transistor 125 and transmitted via the vertical signal line VSL. When the reset transistor 123 is turned on, the charge accumulated in the floating diffusion FD is discharged.

[0054] 4 is a block diagram showing a configuration example of a signal readout unit according to the first embodiment. Although the figure shows vertical signal lines VSL1 and VSL2 for two columns, the present invention can be similarly applied to a case where there are more vertical signal lines.

[0055] 2, the solid-state imaging device 102 further includes a reference signal generating section 131, a buffer control section 132, an auto-zero control section 133, an AD conversion control section 134, and flag holding sections FG1 and FG2.

[0056] The pixels PX1 and PX2 are connected to the vertical signal lines VSL1 and VSL2, respectively. At this time, the amplification transistors 124 of the pixels PX1 and PX2 are connected to the vertical signal lines VSL1 and VSL2 via the selection transistors 125, respectively.

[0057] The column readout circuit 113 includes current sources LM1 and LM2. The current sources LM1 and LM2 are provided for each column. Each current source LM1 and LM2 is connected to a vertical signal line VSL1 or VSL2, respectively. During signal readout, each current source LM1 or LM2 can form a source follower with each pixel PX1 or PX2 via the vertical signal line VSL1 or VSL2, respectively. Each current source LM1 or LM2 may be a MOS transistor.

[0058] The reference signal generation unit 131 generates a reference signal REF. The reference signal REF may include a ramp wave and a reference signal. The ramp wave included in the reference signal REF may be used for single-slope AD conversion. The reference signal included in the reference signal REF may be used to determine the illuminance of light incident on each pixel PX. In this case, the reference signal included in the reference signal REF may provide a threshold value indicating whether the illuminance of light incident on each pixel PX is low or high. The reference signal REF may be shared by all columns. The reference signal REF is input to the column ADC unit 114B via the ramp source follower unit 114A.

[0059] The ramp source follower unit 114A includes buffers RB1 and RB2 for each column. Each buffer RB1 and RB2 is connected between the reference signal generator 131 and each comparator CM1 and CM2. At this time, each buffer RB1 and RB2 makes the potential of the reference signal REF input to the column ADC unit 114B follow the potential of the reference signal REF output from the reference signal generator 131 for each column, thereby making these potentials approximately equal. Furthermore, each buffer RB1 and RB2 can suppress kickback to the reference signal REF when each comparator CM1 and CM2 is inverted.

[0060] The buffer control unit 132 selects whether each of the buffers RB1 and RB2 is in operation or not for each column. At this time, the buffer control unit 132 inputs a buffer selection signal SCB to each of the buffers RB1 and RB2, thereby switching between activation and deactivation of each of the buffers RB1 and RB2.

[0061] Here, the buffer control unit 132 can select whether to operate each of the buffers RB1 and RB2 for each column based on the load on each of the buffers RB1 and RB2. Alternatively, the buffer control unit 132 can select whether to operate each of the buffers RB1 and RB2 for each column so that the relationship between the driving force of the buffers RB1 and RB2 selected for operation and the load on the buffers RB1 and RB2 is kept constant.

[0062] Furthermore, the buffer control unit 132 can select whether to operate or not operate each of the buffers RB1 and RB2 independently of whether the column ADC unit 114B is performing or stopping AD conversion for each column. Alternatively, the buffer control unit 132 can select whether to operate or not operate each of the buffers RB1 and RB2 in coordination with whether the column ADC unit 114B is performing or stopping AD conversion for each column.

[0063] For example, the buffer control unit 132 may select the operation of the buffers RB1 and RB2 of a column for which the column ADC unit 114B is selected to perform AD conversion, and may select the non-operation of the buffers RB1 and RB2 of a column for which the column ADC unit 114B is selected to stop AD conversion. Alternatively, the buffer control unit 132 may simultaneously select the operation of multiple buffers RB1 and RB2, regardless of whether the column ADC unit 114B is performing or stopping AD conversion. Alternatively, the buffer control unit 132 may simultaneously select the operation of the buffers RB1 and RB2 of all columns, regardless of whether the column ADC unit 114B is performing or stopping AD conversion.

[0064] The column ADC unit 114B includes comparators CM1 and CM2 and counters CN1 and CN2 for each column. The column ADC unit 114B can set a determination period and an AD conversion period for each horizontal scanning period. During the determination period, a reference signal can be set as the reference signal REF. During the AD conversion period, a ramp wave can be set as the reference signal REF.

[0065] Comparators CM1 and CM2 are provided for each column. Comparator CM1 compares a pixel signal transmitted via vertical signal line VSL1 with a reference signal REF output via buffer RB1. Comparator CM2 compares a pixel signal transmitted via vertical signal line VSL2 with a reference signal REF output via buffer RB2.

[0066] An auto-zero signal AZ is input to each of the comparators CM1 and CM2. The auto-zero signal AZ activates the auto-zero operation during the auto-zero period. At this time, a DC-blocking capacitor CA1 is connected to the non-inverting input terminal of the comparator CM1, and a DC-blocking capacitor CB1 is connected to the inverting input terminal. Furthermore, a DC-blocking capacitor CA2 is connected to the non-inverting input terminal of the comparator CM2, and a DC-blocking capacitor CB2 is connected to the inverting input terminal.

[0067] In the auto-zero operation, the charges stored in the DC blocking capacitors CA1 and CB1 are controlled so that the non-inverting and inverting inputs of the comparator CM1 are balanced, and in the auto-zero operation, the charges stored in the DC blocking capacitors CA2 and CB2 are controlled so that the non-inverting and inverting inputs of the comparator CM2 are balanced.

[0068] The auto-zero control unit 133 outputs an auto-zero signal AZ to each of the comparators CM1 and CM2 to control the auto-zero operation of each of the comparators CM1 and CM2. The auto-zero signal AZ can be shared by all columns.

[0069] The AD conversion control unit 134 selects whether to perform or stop AD conversion by the column ADC unit 114B for each column based on the determination result of the illuminance of light incident on each pixel PX. At this time, the AD conversion control unit 134 inputs an AD conversion selection signal SCA to each comparator CM1, CM2, and can individually switch between activation and deactivation of each comparator CM1, CM2.

[0070] Here, the AD conversion control unit 134 can refer to the flags F1 and F2 stored in the flag storage units FG1 and FG2 to obtain the determination result of the illuminance of light incident on each pixel PX. When the illuminance of light incident on each pixel PX is low, the AD conversion control unit 134 can select to stop AD conversion by the column ADC unit 114B for that column. Furthermore, when the illuminance of light incident on each pixel PX is high, the AD conversion control unit 134 can select to perform AD conversion by the column ADC unit 114B for that column. This allows the AD conversion control unit 134 to select whether to perform AD conversion by the column ADC unit 114B based on the determination result of the illuminance of light incident on each pixel PX, thereby achieving digitization of pixel signals while reducing power consumption.

[0071] Each counter CN1, CN2 performs a counting operation for each column until the level of the pixel signal read from each pixel PX matches the level of the ramp wave of the reference signal REF, and holds the digital values ​​D1, D2 of the pixel signal read from each pixel PX for each column. At this time, the pixel signals read from each pixel PX can be digitized for each row in each comparator CM1, CM2. The digital values ​​D1, D2 held in each counter CN1, CN2 can be updated for each row.

[0072] At this time, in each comparator CM1, CM2, during an AD conversion period provided in each horizontal scanning period, the pixel signal read out from each pixel PX is compared with the ramp wave included in the reference signal REF for each column. Then, based on the comparison results of each comparator CM1, CM2 during that AD conversion period, digital values ​​D1, D2 of the pixel signal read out from each pixel PX are held in each counter CN1, CN2.

[0073] Each flag holding unit FG1, FG2 holds a flag F1, F2 for each column, which indicates the illuminance of light incident on each pixel PX. Each flag F1, F2 can indicate whether the light incident on each pixel PX is low or high illuminance. At this time, the illuminance of light incident on each pixel PX can be determined for each row by each comparator CM1, CM2. The values ​​of the flags F1, F2 held in each flag holding unit FG1, FG2 can be updated for each row.

[0074] In each comparator CM1, CM2, a pixel signal read from each pixel PX is compared with a reference signal included in a reference signal REF for each column during a determination period provided in each horizontal scanning period. Then, based on the comparison results of each comparator CM1, CM2 during that determination period, flags F1, F2 corresponding to the determination results of the illuminance of light incident on each pixel PX are held in the respective flag holding units FG1, FG2.

[0075] As described above, in the first embodiment, the operation or non-operation of each of the buffers RB1 and RB2 can be individually selected via the buffer control unit 132. This improves the controllability of selecting the operation or non-operation of each of the buffers RB1 and RB2. This makes it possible to suppress an increase in imbalance in the outputs of the buffers RB1 and RB2 between columns, and to suppress deviations in the AD conversion characteristics between columns.

[0076] 2. Second Embodiment In the first embodiment described above, it is possible to individually select whether each of the buffers RB1 and RB2 is operational or non-operational via the buffer control unit 132. In this second embodiment, connection lines are provided that connect the outputs of the buffers of different columns, and the operation or non-operation of the buffer is selected for each column in units of a block that groups together multiple columns, based on the selection of whether to perform or stop AD conversion.

[0077] 5 is a block diagram showing an example of the configuration of an AD conversion unit and a ramp source follower unit according to the second embodiment. While vertical signal lines VSL1 to VSL8 for eight columns are shown in the figure, the present invention can be applied to a case where there are more vertical signal lines. Also, the figure shows only a portion of the configuration shown in FIG. 4.

[0078] In the figure, this solid-state imaging device includes buffer control units 132A and 132B instead of the buffer control unit 132 of the first embodiment described above. Also, this solid-state imaging device has a connection line 201 added to the solid-state imaging device of the first embodiment described above. Other configurations of the solid-state imaging device of the second embodiment are similar to those of the solid-state imaging device of the first embodiment described above.

[0079] The pixels PX are connected to the vertical signal lines VSL1 to VSL8 for each column. At this time, the amplification transistor 124 of each pixel PX is connected to each of the vertical signal lines VSL1 to VSL8 via the selection transistor 125.

[0080] The ramp source follower unit 114A includes buffers RB1 to RB8 for each column. A reference signal REF generated by a reference signal generator 131 is input to each of the buffers RB1 to RB8. The outputs of the buffers RB1 to RB8 are connected via connection lines 201. The buffers RB1 to RB8 are unitized into blocks that group together multiple columns. For example, buffers RB1 to RB4 may belong to block BK1, and buffers RB5 to RB8 may belong to block BK2. While the diagram shows an example in which four buffers belong to each of blocks BK1 and BK2, each of blocks BK1 and BK2 may have a different number of buffers. Furthermore, the number of buffers belonging to each of blocks BK1 and BK2 may differ from each other.

[0081] Comparators CM1 to CM8 are provided for each column corresponding to each of the buffers RB1 to RB8. Each of the comparators CM1 to CM8 compares a pixel signal transmitted via each of the vertical signal lines VSL1 to VSL8 with a reference signal REF output via each of the buffers RB1 to RB8.

[0082] Flag holding units FG1 to FG8 are provided for each column corresponding to each comparator CM1 to CM8. The flag holding units FG1 to FG8 hold flags F1 to F8 relating to the illuminance of light incident on each pixel PX for each column.

[0083] The buffer control unit 132A selects whether each of the buffers RB1 to RB4 in the block BK1 is active or inactive for each column. At this time, the buffer control unit 132A inputs a buffer selection signal SCB1 to each of the buffers RB1 to RB4, thereby switching between activation and deactivation of each of the buffers RB1 to RB4. The buffer control unit 132B selects whether each of the buffers RB5 to RB8 in the block BK2 is active or inactive for each column. At this time, the buffer control unit 132B inputs a buffer selection signal SCB2 to each of the buffers RB5 to RB8, thereby switching between activation and deactivation of each of the buffers RB5 to RB8.

[0084] Here, the buffer control units 132A and 132B can perform selection operations independently of each other. The buffer control unit 132A may select whether to operate or not operate the buffers RB1 to RB4 for each column based on whether the column ADC unit 114B performs or stops AD conversion. The buffer control unit 132B may select whether to operate or not operate the buffers RB5 to RB8 for each column based on whether the column ADC unit 114B performs or stops AD conversion.

[0085] For example, the buffer control unit 132A may simultaneously select the operation of multiple buffers RB1 to RB4 in block BK1, regardless of whether the column ADC unit 114B is performing or stopping AD conversion. Alternatively, the buffer control unit 132A may simultaneously select the operation of buffers RB1 to RB4 in all columns of block BK1, regardless of whether the column ADC unit 114B is performing or stopping AD conversion. Alternatively, the buffer control unit 132A may select the operation of buffers RB1 to RB4 in the column for which the column ADC unit 114B is selected to perform AD conversion, and may select the non-operation of buffers RB1 to RB4 in the column for which the column ADC unit 114B is selected to stop AD conversion.

[0086] The buffer control unit 132B may simultaneously select the operation of multiple buffers RB5 to RB8 in block BK2, regardless of whether the column ADC unit 114B is performing or stopping AD conversion. Alternatively, the buffer control unit 132B may simultaneously select the operation of buffers RB5 to RB8 in all columns of block BK2, regardless of whether the column ADC unit 114B is performing or stopping AD conversion. Alternatively, the buffer control unit 132B may select the operation of buffers RB5 to RB8 in the column for which the column ADC unit 114B is selected to perform AD conversion, and may select the non-operation of buffers RB5 to RB8 in the column for which the column ADC unit 114B is selected to stop AD conversion.

[0087] 6 is a block diagram showing a first operation example of the AD conversion unit and the ramp source follower unit according to the second embodiment. In the figure, gray hatching indicates activation of buffers RB1 to RB8 and comparators CM1 to CM8, and white hatching indicates deactivation of buffers RB1 to RB8 and comparators CM1 to CM8.

[0088] In the figure, for example, flag F2 indicates that the illuminance of light incident on each pixel PX is high, and flags F1, F3, and F4 indicate that the illuminance of light incident on each pixel PX is low. At this time, comparator CM2 is activated based on the value of flag F2, and comparators CM1, CM3, and CM4 are deactivated based on the values ​​of flags F1, F3, and F4. Here, the buffer control unit 132A selects the operation of buffer RB2 corresponding to the column of activated comparator CM2.

[0089] On the other hand, for example, flags F6 and F8 indicate that the illuminance of light incident on each pixel PX is high, and flags F5 and F7 indicate that the illuminance of light incident on each pixel PX is low. At this time, comparators CM6 and CM8 are activated based on the values ​​of flags F6 and F8, and comparators CM5 and CM7 are deactivated based on the flag values ​​F5 and F7. Here, the buffer control unit 132B selects the operation of buffers RB6 and RB8 corresponding to the columns of activated comparators CM6 and CM8.

[0090] Here, if the buffer operation is selected only for the column for which AD conversion is selected, the number of buffers for which operation is selected may decrease. In this case, the load on the buffer for which operation is selected increases, the ramp wave of the reference signal REF output through the buffer becomes dull, and there is a risk of the AD conversion accuracy decreasing.

[0091] At this time, each buffer control unit 132A, 132B determines whether the number of buffers operating in all columns is equal to or greater than n (n is a positive integer). n can be set to 3, for example. If the number of buffers operating in all columns is less than n, each buffer control unit 132A, 132B selects the operation of all buffers in a certain block. For example, the buffer control unit 132A can select the operation of all buffers RB1 to RB4 in block BK1.

[0092] This ensures that a certain number or more of buffers are selected for operation even when only a small number of columns are selected for AD conversion, thereby suppressing an increase in the load on the buffers for which operation is selected and suppressing dulling of the ramp wave of the reference signal REF output via the buffers, thereby preventing a decrease in AD conversion accuracy.

[0093] FIG. 7 is a flowchart showing a first operation example of the ramp source follower unit according to the second embodiment.

[0094] In the figure, each comparator CM1 to CM8 determines the illuminance of light incident on each pixel PX and stores flags F1 to F8 corresponding to the determination results in flag holding units FG1 to FG8, respectively (S101).Then, the AD conversion control unit 134 selects, for each column, whether to perform or stop AD conversion by the column ADC unit 114B based on the determination result of the illuminance of light incident on each pixel PX.

[0095] Next, each of the buffer control units 132A and 132B selects the operation of the buffers RB1 to RB8 only for the column for which the execution of AD conversion has been selected (S102).

[0096] Next, each buffer control unit 132A, 132B determines whether the number of buffers operated in all columns is n or more (S103). If the number of buffers operated in all columns is n or more, the column ADC unit 114B performs A / D conversion only on the columns selected for A / D conversion (S104).

[0097] On the other hand, if the number of buffers operated in all columns is less than n, each of the buffer control units 132A and 132B selects the operation of all buffers in one block (S105), and returns the process to S103.

[0098] 8 is a block diagram showing a second operation example of the AD conversion unit and the ramp source follower unit according to the second embodiment. In the figure, gray hatching indicates activation of buffers RB1 to RB8 and comparators CM1 to CM8, and white hatching indicates deactivation of buffers RB1 to RB8 and comparators CM1 to CM8.

[0099] In the figure, for example, flag F2 indicates that the illuminance of light incident on each pixel PX is high, and flags F1, F3, and F4 indicate that the illuminance of light incident on each pixel PX is low. At this time, comparator CM2 is activated based on the value of flag F2, and comparators CM1, CM3, and CM4 are deactivated based on the values ​​of flags F1, F3, and F4. Here, the buffer control unit 132A selects the operation of buffer RB2 corresponding to the column of activated comparator CM2.

[0100] At this time, the buffer control unit 132A determines whether the number of buffers operating in block BK1 is equal to or greater than m (m is a positive integer). m can be set to 3, for example. If the number of buffers operating in block BK1 is less than m, the buffer control unit 132A selects an additional buffer for operation in block BK1. For example, the buffer control unit 132A can select an additional buffer RB1 for operation in block BK1.

[0101] On the other hand, for example, flags F6 and F8 indicate that the illuminance of light incident on each pixel PX is high, and flags F5 and F7 indicate that the illuminance of light incident on each pixel PX is low. At this time, comparators CM6 and CM8 are activated based on the values ​​of flags F6 and F8, and comparators CM5 and CM7 are deactivated based on the flag values ​​F5 and F7. Here, the buffer control unit 132B selects the operation of buffers RB6 and RB8 corresponding to the columns of activated comparators CM6 and CM8.

[0102] At this time, the buffer control unit 132B determines whether the number of buffers operating in block BK2 is m or more. If the number of buffers operating in block BK2 is less than m, the buffer control unit 132B selects an additional buffer for operation in block BK2. For example, the buffer control unit 132B may select an additional buffer RB5 for operation in block BK2.

[0103] This prevents a drastic decrease in the number of buffers for which an operation is selected, even when only a small number of columns are selected for AD conversion execution. This prevents a drastic increase in the load on the buffers for which an operation is selected, and also prevents an increase in the power consumption of the ramp source follower unit 114A, while suppressing dulling of the ramp wave of the reference signal REF output via the buffer.

[0104] FIG. 9 is a flowchart showing a second operation example of the ramp source follower unit according to the second embodiment.

[0105] In the figure, each comparator CM1 to CM8 determines the illuminance of light incident on each pixel PX, and stores flags F1 to F8 corresponding to the determination results in flag holding units FG1 to FG8, respectively (S201).Then, the AD conversion control unit 134 selects, for each column, whether to perform or stop AD conversion by the column ADC unit 114B, based on the determination result of the illuminance of light incident on each pixel PX.

[0106] Next, each of the buffer control units 132A and 132B selects the operation of the buffers RB1 to RB8 only for the column for which AD conversion has been selected (S202).

[0107] Next, each buffer control unit 132A, 132B determines whether the number of buffers operated in one block is m or more (S203). If the number of buffers operated in one block is m or more, the column ADC unit 114B performs A-D conversion only on the columns selected for A-D conversion (S204).

[0108] On the other hand, if the number of buffers operating in one block is less than m, each buffer control unit 132A, 132B selects an additional buffer for operation in the column where AD conversion is stopped (S205), and returns the process to S203.

[0109] As described above, in the second embodiment, connection lines 201 are provided to connect the outputs of buffers RB1 to RB8 of different columns. This allows buffers RB1 to RB8 to be provided for each column, while averaging out column-to-column variations in the outputs of buffers RB1 to RB8, thereby reducing noise generated in each of the buffers RB1 to RB8. The column-to-column variations include fixed components, which are caused by variations in the threshold voltages of the transistors in each of the buffers RB1 to RB8, and random components, which are caused by temporal fluctuations in the outputs of each of the buffers RB1 to RB8 due to random noise that occurs independently in each column.

[0110] Furthermore, based on the selection of whether to perform or stop AD conversion, operation or non-operation of buffers RB1 to RB8 is selected for each column in units of blocks BK1 and BK2, which group together multiple columns. This allows the combination of selection of operation or non-operation of buffers RB1 to RB8 to be set in units of blocks BK1 and BK2, and enables the uniformity of the loads on the outputs of buffers RB1 to RB8 to be improved while reducing the power consumption of the ramp source follower unit 114A.

[0111] 3. Third Embodiment In the second embodiment described above, connection lines 201 are provided to connect the outputs of buffers RB1 to RB8 in different columns, and operation or non-operation of buffers RB1 to RB8 is selected for each column in units of blocks BK1 and BK2. In this third embodiment, connection lines 201 are provided to connect the outputs of buffers RB1 to RB4 in different columns, and operation or non-operation of buffers RB1 to RB4 is selected for each column independently of the selection of whether to perform or stop AD conversion.

[0112] 10 is a block diagram showing an example of the configuration of an AD conversion unit and a ramp source follower unit according to the third embodiment. While the diagram shows vertical signal lines VSL1 to VSL4 for four columns, the present invention can be applied to a case where there are more vertical signal lines. Also, the diagram shows only a portion of the configuration shown in FIG. 4.

[0113] In the figure, this solid-state imaging device is the same as the solid-state imaging device of the first embodiment described above, except that a connection line 201 is added. Other configurations of the solid-state imaging device of the third embodiment are the same as those of the solid-state imaging device of the first embodiment described above.

[0114] The pixels PX are connected to the vertical signal lines VSL1 to VSL4 for each column. At this time, the amplification transistor 124 of each pixel PX is connected to each of the vertical signal lines VSL1 to VSL4 via the selection transistor 125.

[0115] The ramp source follower unit 114A includes buffers RB1 to RB4 for each column. A reference signal REF generated by a reference signal generator 131 is input to each of the buffers RB1 to RB4. The outputs of the buffers RB1 to RB4 are connected via connection lines 201.

[0116] Comparators CM1 to CM4 are provided for each column corresponding to each buffer RB1 to RB4. Each comparator CM1 to CM4 compares a pixel signal transmitted via each vertical signal line VSL1 to VSL4 with a reference signal REF output via each buffer RB1 to RB4. At this time, the reference signals REF output via each buffer RB1 to RB4 are averaged via a connection line 201.

[0117] The buffer control unit 132 selects whether to operate the buffers RB1 to RB4 for each column, independently of whether to perform or stop AD conversion by the column ADC unit 114B. For example, the buffer control unit 132 can simultaneously select the operation of the buffers RB1 to RB4 for all columns, regardless of whether to perform or stop AD conversion by the column ADC unit 114B. In this case, when the execution of AD conversion by the column ADC unit 114B is selected for at least one column, the buffer control unit 132 can simultaneously select the operation of the buffers RB1 to RB4 for all columns.

[0118] 11 is a block diagram showing an example of the operation of the AD conversion unit and the ramp source follower unit according to the third embodiment. In the figure, gray hatching indicates activation of the buffers RB1 to RB4 and the comparators CM1 to CM4, and white hatching indicates deactivation of the buffers RB1 to RB4 and the comparators CM1 to CM4.

[0119] In the figure, comparator CM2 is activated and comparators CM1, CM3, and CM4 are deactivated based on the determination result of the illuminance of light incident on each pixel PX. Here, the buffer control unit 132 simultaneously selects the operation of buffers RB1 to RB4 for all columns even when comparators CM1, CM3, and CM4 for some columns are deactivated.

[0120] As described above, in the third embodiment, the connection lines 201 are provided to connect the outputs of the buffers RB1 to RB4 of different columns, and the operation or non-operation of the buffers RB1 to RB4 is selected for each column independently of the selection of whether to perform or stop A / D conversion. This makes it possible to equalize the load on the outputs of the buffers RB1 to RB4, average out the variations in the outputs of the buffers RB1 to RB4 for each column, and reduce the power consumption of the column ADC unit 114B according to the illuminance of light incident on each pixel PX.

[0121] 4. Fourth Embodiment In the above-described third embodiment, connection lines 201 are provided to connect the outputs of buffers RB1 to RB4 of different columns, and operation or non-operation of buffers RB1 to RB4 is selected for each column independently of whether AD conversion is performed or stopped. In this fourth embodiment, the outputs of buffers RB1 to RB4 are separated for each column, and operation or non-operation of buffers RB1 to RB4 is selected for each column based on whether AD conversion is performed or stopped.

[0122] 12 is a block diagram showing an example of the configuration of an AD conversion unit and a ramp source follower unit according to the fourth embodiment. While the diagram shows vertical signal lines VSL1 to VSL4 for four columns, the present invention can be applied to a case where there are more vertical signal lines. Also, the diagram shows only a portion of the configuration shown in FIG. 4.

[0123] In the figure, this solid-state imaging device is the same as the solid-state imaging device of the third embodiment except that the connection line 201 has been removed. At this time, the outputs of buffers RB1 to RB4 are separated for each column. Other configurations of the solid-state imaging device of the fourth embodiment are the same as those of the solid-state imaging device of the third embodiment.

[0124] 13 is a block diagram showing an example of the operation of the AD conversion unit and the ramp source follower unit according to the fourth embodiment. In the figure, gray hatching indicates activation of the buffers RB1 to RB4 and the comparators CM1 to CM4, and white hatching indicates deactivation of the buffers RB1 to RB4 and the comparators CM1 to CM4.

[0125] In the figure, comparator CM2 is activated and comparators CM1, CM3, and CM4 are deactivated based on the determination result of the illuminance of light incident on each pixel PX. Here, the buffer control unit 132 can select whether to operate each of buffers RB1 to RB4 in cooperation with the execution or stop of AD conversion for each column by the column ADC unit 114B. In this case, the buffer control unit 132 can select the operation of buffer RB2 based on the activation of comparator CM2, and can select the non-operation of buffers RB1, RB3, and RB4 based on the deactivation of comparators CM1, CM3, and CM4.

[0126] As described above, in the fourth embodiment, the outputs of the buffers RB1 to RB4 are separated for each column, and the operation or non-operation of the buffers RB1 to RB4 is selected for each column based on the selection of whether to perform or stop AD conversion. This makes it possible to suppress imbalances in the loads on the buffers RB1 to RB4, regardless of the ratio of operation or non-operation of the buffers RB1 to RB4 for each column. Therefore, it is possible to suppress deviations in the AD conversion characteristics for each column, while reducing the power consumption of the lamp source follower unit 114A and the column ADC unit 114B in accordance with the illuminance of light incident on each pixel PX.

[0127] 5. Fifth Embodiment In the above-described fourth embodiment, the outputs of buffers RB1 to RB4 are separated for each column, and the operation or non-operation of buffers RB1 to RB4 is selected for each column based on the selection of whether to perform or stop AD conversion. In this fifth embodiment, switches are provided to switch the connection of the outputs of buffers RB1 to RB8 of different columns, and the operation or non-operation of buffers RB1 to RB8 is selected for each column based on the selection of whether to perform or stop AD conversion.

[0128] 14 is a block diagram showing an example of the configuration of an AD conversion unit and a ramp source follower unit according to the fifth embodiment. While vertical signal lines VSL1 to VSL8 for eight columns are shown in the figure, the present invention can be applied to a case where there are more vertical signal lines. Also, the figure shows only a portion of the configuration shown in FIG. 4.

[0129] In the figure, this solid-state imaging device is the same as the solid-state imaging device of the fourth embodiment except that switches SW1 to SW7 are added. The other configurations of the solid-state imaging device of the fifth embodiment are the same as those of the solid-state imaging device of the fourth embodiment.

[0130] Each of the switches SW1 to SW7 switches the connection of the outputs of buffers RB1 to RB8 in different columns. In this case, switch SW1 is connected between the outputs of buffers RB1 and RB2. Switch SW2 is connected between the outputs of buffers RB2 and RB3. Switch SW3 is connected between the outputs of buffers RB3 and RB4. Switch SW4 is connected between the outputs of buffers RB4 and RB5. Switch SW5 is connected between the outputs of buffers RB5 and RB6. Switch SW6 is connected between the outputs of buffers RB6 and RB7. Switch SW7 is connected between the outputs of buffers RB7 and RB8. Each of the switches SW1 to SW7 is individually turned on and off based on a switching signal SCW.

[0131] The buffer control unit 132 can select whether to operate or not operate each of the buffers RB1 to RB8 based on whether AD conversion for each column is performed or stopped by the column ADC unit 114B. For example, the buffer control unit 132 may select to operate the buffers RB1 to RB8 of a column for which AD conversion by the column ADC unit 114B is selected to be performed, and may select to not operate the buffers RB1 to RB8 of a column for which AD conversion by the column ADC unit 114B is selected to be stopped.

[0132] The buffer control unit 132 can also individually control the on / off of each switch SW1 to SW7 based on whether the column ADC unit 114B is performing or stopping AD conversion for each column. For example, the buffer control unit 132 can disconnect the outputs of buffers RB1 to RB8 of a column selected to be inactive from the outputs of buffers RB1 to RB8 of a column adjacent to the column selected to be inactive. The buffer control unit 132 can also connect the outputs of buffers RB1 to RB8 of adjacent columns selected to be active.

[0133] 15 is a block diagram showing an example of the operation of the AD conversion unit and the ramp source follower unit according to the fifth embodiment. In the figure, gray hatching indicates activation of buffers RB1 to RB8 and comparators CM1 to CM8, and white hatching indicates deactivation of buffers RB1 to RB8 and comparators CM1 to CM8.

[0134] In the figure, comparators CM2, CM5 to CM7 are activated and comparators CM1, CM3, CM4, and CM8 are deactivated based on the determination result of the illuminance of light incident on each pixel PX. Here, the buffer control unit 132 can select whether to operate each of buffers RB1 to RB8 in cooperation with the execution or stop of AD conversion for each column by the column ADC unit 114B. In this case, the buffer control unit 132 can select whether to operate buffers RB2, RB5 to RB7 based on the activation of comparators CM2, CM5 to CM7, and can select whether to deactivate buffers RB1, RB3, RB4, and RB8 based on the deactivation of comparators CM1, CM3, CM4, and CM8.

[0135] The buffer control unit 132 can also turn off switches SW1 to SW4 and SW7 to disconnect the outputs of buffers RB1, RB3, RB4 and RB8 of a column selected to be inactive from the outputs of buffers RB2, RB5 and RB7 of columns adjacent to that column.The buffer control unit 132 can also turn on switches SW5 and SW6 to connect the outputs of buffers RB5 to RB7 of adjacent columns selected to be active.

[0136] As described above, in the fifth embodiment, switches SW1 to SW7 are provided to switch the connection of the outputs of buffers RB1 to RB8 in different columns, and the operation or non-operation of buffers RB1 to RB8 is selected for each column based on the selection of whether to perform or stop AD conversion, and switches SW1 to SW7. This makes it possible to average out the variations in the outputs of buffers RB1 to RB8 for each column while suppressing crosstalk between buffers RB1 to RB8 in different columns, and also to reduce the power consumption of the lamp source follower unit 114A and the column ADC unit 114B according to the illuminance of light incident on each pixel PX.

[0137] 6. Sixth Embodiment In the first embodiment described above, it is possible to individually select whether each of the buffers RB1 and RB2 is operational or inoperative via the buffer control unit 132. In this sixth embodiment, semiconductor chips each having a pixel array unit in which pixels are arranged in a matrix are stacked.

[0138] FIG. 16 is a perspective view showing an example of a stack of pixel array units according to the sixth embodiment.

[0139] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921.

[0140] A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0141] A peripheral circuit 924 is formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, a control circuit 928, and a ramp source follower unit 929 are formed in the peripheral circuit 924. The column readout circuit 925, the column ADC 926, and the ramp source follower unit 929 may be formed to correspond to positions on both sides of the pixel array unit 923 in the column direction. The ramp source follower unit 929 may be provided with any of the configurations of the first to fifth embodiments described above. The control circuit 928 may be provided with a buffer control unit 132 and an AD conversion control unit 134.

[0142] The semiconductor chips 921 and 922 may be directly bonded to each other. Hybrid bonding can be used for directly bonding the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu bonding. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0143] As described above, in the sixth embodiment, the semiconductor chip 922 on which the pixel array unit 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0144] 7. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0145] FIG. 17 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0146] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 17, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0147] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0148] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0149] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0150] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0151] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0152] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0153] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0154] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0155] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 17, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0156] FIG. 18 is a diagram showing an example of the installation position of the imaging unit 12031.

[0157] In FIG. 18, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0158] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0159] 18 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0160] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0161] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0162] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0163] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0164] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, for example, the imaging devices according to the first to sixth embodiments described above can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to reduce the power consumption of the imaging unit 12031 while suppressing a decrease in the AD conversion accuracy of the imaging unit 12031.

[0165] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0166] The present technology may also be configured as follows: (1) An imaging device including: a pixel array unit in which pixels are arranged in a matrix in the row and column directions; an AD conversion unit that performs AD (Analog to Digital) conversion on each column of pixel signals based on a comparison result between pixel signals read from the pixels and a reference signal; a buffer that inputs the reference signal to the AD conversion unit for each column; and a buffer control unit that selects operation or non-operation of the buffer for each column. (2) The imaging device described in (1), in which the buffer control unit selects operation or non-operation of the buffer for each column based on a load on the buffer. (3) The imaging device described in (1) or (2), in which the buffer control unit selects operation or non-operation of the buffer for each column so that a relationship between the driving force of the buffer whose operation is selected and the load on the buffer is maintained constant. (4) The imaging device described in any of (1) to (3), in which the buffer control unit selects operation or non-operation of the buffer for each column based on selection of execution or stop of AD conversion by the AD conversion unit. (5) The imaging device according to (4), wherein the buffer control unit selects operation of the buffer of a column for which the execution of the AD conversion has been selected, and selects non-operation of the buffer of a column for which the stop of the AD conversion has been selected. (6) The imaging device according to any of (1) to (5), further including a connection line connecting outputs of the buffers of different columns. (7) The imaging device according to any of (1) to (6), wherein the buffer control unit simultaneously selects operation of the buffer of all columns, regardless of whether the AD conversion unit performs or stops it. (8) The imaging device according to any of (1) to (7), wherein the buffer control unit selects operation or non-operation of the buffer for each column in block units that group together a plurality of the columns. (9) The imaging device according to (8), wherein the buffer control unit simultaneously selects operation of the plurality of buffers of at least one of the blocks, regardless of whether the AD conversion unit performs or stops it.(10) The imaging device according to (8), wherein the buffer control unit selects operation of at least one buffer of the block independent of whether the AD conversion unit is performing or stopping AD conversion. (11) The imaging device according to any one of (1) to (10), further comprising: a switch for switching connection of outputs of the buffers of different columns. (12) The imaging device according to (11), wherein the buffer control unit disconnects, via the switch, the output of the buffer of the column for which the non-operation has been selected and the output of the buffer of a column adjacent to the column for which the non-operation has been selected. (13) The imaging device according to (11), wherein the buffer control unit connects, via the switch, the outputs of the buffers of adjacent columns for which the operation has been selected. (14) The imaging device according to any one of (1) to (13), further comprising: an AD conversion control unit for selecting whether to perform or stop AD conversion by the AD conversion unit based on a determination result of illuminance of light incident on the pixel. (15) The imaging device described in (14), wherein the buffer control unit selects whether to operate the buffer for each column based on a determination result of the illuminance of light incident on the pixel. (16) The imaging device described in (15), wherein the buffer control unit selects the operation of the buffer only for columns for which AD conversion by the AD conversion unit has been selected based on a determination result of the illuminance of light incident on the pixel. (17) The imaging device described in (16), wherein the buffer control unit selects the operation of the buffer for all columns included in a block formed by grouping multiple columns when the number of columns for which the buffer operation has been selected is less than n (n is a positive integer). (18) The imaging device described in (16), wherein the buffer control unit additionally selects the operation of the buffer for a column for which AD conversion by the AD conversion unit has been selected to stop based on a determination result of the illuminance of light incident on the pixel when the number of columns for which the buffer operation has been selected in a block formed by grouping multiple columns is less than m (m is a positive integer).(19) An imaging method comprising: selecting operation or non-operation of a buffer that inputs a reference signal to an AD converter that performs AD (Analog to Digital) conversion on a column-by-column basis based on a comparison result between a pixel signal read from pixels arranged in a matrix in the row and column directions and a reference signal; and AD converting the pixel signal based on a comparison result between the reference signal input via the buffer whose operation has been selected. (20) The imaging method according to (19), comprising selecting operation or non-operation of the buffer based on a selection of execution or stop of AD conversion by the AD converter; and AD converting the pixel signal based on a comparison result between the reference signal input via the buffer whose operation has been selected.

[0167] 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Memory unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel array unit 112 Vertical scanning circuit 113 Column readout circuit 114 Column signal processing unit 114A Ramp source follower unit 114B Column ADC unit 115 Horizontal scanning circuit 116 Control circuit PX Pixel HSL Horizontal drive line VSL Vertical signal line PD Photodiode FD Floating diffusion 122 Transfer transistor 123 Reset transistor 124 Amplifying transistor 125 Selection transistor LM1, LM2 Current source RB1, RB2 Buffer CM1, CM2 Comparator CN1, CN2 Counter FG1, FG2 Flag holding unit 131 Reference signal generating unit 132 Buffer control unit 133 Auto-zero control unit 134 AD conversion control unit

Claims

1. An imaging device comprising: a pixel array section in which pixels are arranged in a matrix in the row and column directions; an AD conversion section that performs AD (Analog to Digital) conversion of pixel signals read from the pixels for each column based on the comparison result between the pixel signals and a reference signal; a buffer that inputs the reference signal to the AD conversion section for each column; and a buffer control section that selects whether the buffer operates or does not operate for each column.

2. The imaging device according to claim 1, wherein the buffer control unit selects whether the buffer operates or does not operate for each column based on the load on the buffer.

3. The imaging device according to claim 1, wherein the buffer control unit selects operation or non-operation of the buffer for each column so that the relationship between the driving force of the buffer selected for operation and the load on the buffer is kept constant.

4. The imaging device according to claim 1, wherein the buffer control unit selects whether the buffer operates or does not operate for each column based on the selection of whether the AD conversion unit performs or stops AD conversion.

5. The imaging device according to claim 4, wherein the buffer control unit selects operation of the buffer of the column for which the execution of the AD conversion is selected, and selects non-operation of the buffer of the column for which the stop of the AD conversion is selected.

6. The imaging device according to claim 1, further comprising a connection line connecting outputs of the buffers in different columns.

7. The imaging device according to claim 6, wherein the buffer control unit simultaneously selects the operation of the buffers for all columns, regardless of whether the AD conversion unit is performing or stopping AD conversion.

8. The imaging device according to claim 6, wherein the buffer control unit selects whether the buffer operates or does not operate for each column in units of a block that groups together a plurality of the columns.

9. The imaging device according to claim 8, wherein the buffer control unit simultaneously selects the operation of a plurality of buffers in at least one of the blocks, regardless of whether the AD conversion unit is performing or stopping AD conversion.

10. The imaging device according to claim 8, wherein the buffer control unit selects the operation of at least one buffer of the block, regardless of whether the AD conversion unit is performing or stopping AD conversion.

11. The imaging device according to claim 1, further comprising a switch for switching the connection of the outputs of the buffers of different columns.

12. The imaging device according to claim 11, wherein the buffer control unit disconnects, via the switch, the output of the buffer of the column selected to be inoperative from the output of the buffer of the column adjacent to the column selected to be inoperative.

13. The imaging device according to claim 12, wherein the buffer control unit connects the outputs of the buffers of adjacent columns for which the operation has been selected via the switch.

14. The imaging device according to claim 1, further comprising an AD conversion control unit that selects whether to perform AD conversion by said AD conversion unit based on the result of determining the illuminance of light incident on said pixel.

15. The imaging device according to claim 14, wherein the buffer control unit selects whether the buffer operates or does not operate for each column based on the result of determining the illuminance of light incident on the pixel.

16. The imaging device according to claim 15, wherein the buffer control unit selects the operation of the buffer only for columns for which AD conversion by the AD conversion unit has been selected based on the determination result of the illuminance of light incident on the pixels.

17. The imaging device according to claim 16, wherein the buffer control unit selects buffer operations for all columns included in a block that groups together multiple columns when the number of columns for which the buffer operation is selected is less than n (n is a positive integer).

18. The imaging device described in claim 16, wherein when the number of columns for which the buffer operation has been selected in a block grouping a plurality of the columns is less than m (m is a positive integer), the buffer control unit additionally selects the operation of the buffer of a column for which the stop of AD conversion by the AD conversion unit has been selected based on the determination result of the illuminance of light incident on the pixel.

19. An imaging method comprising: selecting operation or non-operation of a buffer that inputs a reference signal to an AD converter that performs AD (Analog to Digital) conversion for each column based on a comparison result between a pixel signal read from pixels arranged in a matrix in the row and column directions and a reference signal; and AD converting the pixel signal based on a comparison result between the reference signal input via the buffer whose operation has been selected.

20. The imaging method according to claim 19, further comprising: selecting whether to operate or not operate the buffer based on the selection of whether to perform or stop AD conversion by the AD conversion unit; and AD converting the pixel signal based on the result of comparison between a reference signal input via the buffer whose operation has been selected and the pixel signal.

Images