Semiconductor device and inverter system

Abstract

This semiconductor device comprises: an insulating layer; a conductive layer positioned on the insulating layer in a first direction; a heat dissipation layer on the opposite side of the insulating layer to the conductive layer; a first semiconductor element having a first electrode and a second electrode; and a second semiconductor element having a third electrode and a fourth electrode. The second electrode is positioned on the opposite side to the first electrode in the first direction. The fourth electrode is positioned on the opposite side to the third electrode in the first direction. The second electrode and the third electrode have different polarities from each other. The second electrode and the third electrode are bonded to the conductive layer. When viewed in the first direction, the conductive layer overlaps the heat dissipation layer.

Description

Semiconductor device and inverter system

[0001] The present disclosure relates to a semiconductor device and an inverter system including the semiconductor device.

[0002] Conventionally, semiconductor devices equipped with multiple semiconductor elements having switching functions, such as MOSFETs and IGBTs, have been widely known. Such semiconductor devices are primarily used for power conversion. Patent Document 1 discloses an example of a semiconductor device equipped with multiple semiconductor elements having switching functions. In the semiconductor device, multiple wiring layers (metal patterns 4a, 4b) are arranged on the surface of an insulating substrate. Each of the multiple semiconductor elements is conductively joined to one of the multiple wiring layers. Furthermore, in the semiconductor device, multiple wiring relay regions are arranged on the surface of the insulating substrate. Each of the multiple wiring relay regions, together with the multiple wiring layers, constitutes a conductive path of the semiconductor device.

[0003] In this semiconductor device, a first parasitic capacitance is formed between one of the multiple wiring relay areas, which outputs AC power converted by the multiple semiconductor elements, and the insulating substrate supporting the wiring relay area. Since voltage changes over time are relatively significant in the wiring relay area, the charge stored in the first parasitic capacitance also fluctuates over time. In this case, a second parasitic capacitance is formed in each of the multiple semiconductor elements, with the electrode located on the opposite side from the side facing the multiple wiring layers as a conductor layer. If the relative magnitude of the second parasitic capacitance to the first parasitic capacitance is smaller, leakage current occurs from the conduction path of the DC power supply conducting to the multiple semiconductor elements. If the magnitude of the leakage current becomes larger, there is a concern about noise influence on the surrounding area of ​​the semiconductor device. Therefore, measures to suppress leakage current to the outside are desired.

[0004] JP 2009-158787 A

[0005] [Summary] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device capable of reducing noise caused by leakage current to the outside.

[0006] A semiconductor device provided by a first aspect of the present disclosure includes an insulating layer, a conductive layer located on one side of the insulating layer in a first direction, a heat dissipation layer located on the opposite side of the conductive layer with the insulating layer sandwiched therebetween, a first semiconductor element having a first electrode and a second electrode, and a second semiconductor element having a third electrode and a fourth electrode. The first semiconductor element and the second semiconductor element are located on the opposite side of the insulating layer with the conductive layer sandwiched therebetween. The second electrode is located on the opposite side of the first electrode in the first direction. The fourth electrode is located on the opposite side of the third electrode in the first direction. The polarity of the second electrode and the polarity of the third electrode are mutually different. The second electrode and the third electrode are each conductively bonded to the conductive layer. When viewed in the first direction, the conductive layer overlaps the heat dissipation layer.

[0007] A second aspect of the present disclosure provides an inverter system including a plurality of semiconductor devices, a motor, and a drive circuit. Each of the plurality of semiconductor devices further includes a sealing resin, a first power terminal, a second power terminal, a first signal terminal, a first signal wiring, and a second signal terminal in addition to the configuration of the semiconductor device provided by the first aspect of the present disclosure. The motor is electrically connected to a conductive layer included in each of the plurality of semiconductor devices. The drive circuit is electrically connected to the first signal terminal and the second signal terminal included in each of the plurality of semiconductor devices.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view corresponding to FIG. 1 , seen through the sealing resin. FIG. 3 is a plan view corresponding to FIG. 2 , further seen through the first power terminal and the second power terminal. FIG. 4 is a bottom view of the semiconductor device shown in FIG. 1 . FIG. 5 is a cross-sectional view taken along line V-V in FIG. 2 . FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 2 . FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 2 . FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 2 . FIG. 9 is a partial enlarged view of FIG. 5 , showing a first semiconductor element and its vicinity. FIG. 10 is a partial enlarged view of FIG. 6 , showing the first semiconductor element and its vicinity. FIG. 11 is a partial enlarged view of FIG. 5 , showing a second semiconductor element and its vicinity. FIG. 12 is a circuit block diagram of an inverter system including a plurality of semiconductor devices shown in FIG. 1 . FIG. 13 is a plan view of a semiconductor device according to a second embodiment of the present disclosure, showing the first power terminal, the second power terminal, and the sealing resin through a see-through view. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 13 . FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 13 . FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 13 . FIG. 17 is a plan view of a semiconductor device according to a third embodiment of the present disclosure, showing the first power terminal, the second power terminal, and the sealing resin through a see-through view. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 17 . FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 17 . FIG. 20 is a partially enlarged view of FIG. 18 . FIG. 21 is a plan view of a first semiconductor element included in the semiconductor device shown in FIG. 17 . FIG. 22 is a bottom view of the first semiconductor element included in the semiconductor device shown in FIG. 17 . 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 21. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 21. FIG. 25 is a cross-sectional view taken along line XXV-XXV in FIG. 21. FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 21. FIG. 27 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present disclosure, corresponding to FIG. 5. FIG. 28 is a cross-sectional view of the semiconductor device shown in FIG. 27, corresponding to FIG. 7. FIG. 29 is a cross-sectional view of a semiconductor device according to a modified example of the fourth embodiment of the present disclosure, corresponding to FIG. 27. FIG. 30 is a cross-sectional view of the semiconductor device shown in FIG. 29, corresponding to FIG. 28.

[0010] DETAILED DESCRIPTION The present disclosure will be described in detail with reference to the accompanying drawings.

[0011] First Embodiment: A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 11 . The semiconductor device A10 includes an insulating layer 11, a conductive layer 12, a heat dissipation layer 13, a plurality of first semiconductor elements 31, a plurality of second semiconductor elements 32, a first power terminal 41, a second power terminal 42, a third power terminal 43, a first signal terminal 44 to a fourth signal terminal 47, and a sealing resin 60. The semiconductor device A10 further includes first signal wiring 21 to a fourth signal wiring 24, a plurality of first relay wiring 28, a plurality of second relay wiring 29, and a first wire 51 to an eighth wire 58. For ease of understanding, FIG. 2 shows the sealing resin 60 in a see-through manner. For ease of understanding, FIG. 3 shows the first power terminal 41 and the second power terminal 42 in a see-through manner compared to FIG. 2. In FIGS. 2 and 3 , the see-through sealing resin 60 is indicated by an imaginary line (double-dashed line). In FIG. 3, the first power terminal 41 and the second power terminal 42 are shown in phantom lines.

[0012] In the description of the semiconductor device A10, for convenience, the normal direction to the mounting surface 121 of the conductive layer 12, which will be described later, is referred to as the "first direction z." The direction perpendicular to the first direction z is referred to as the "second direction x." The direction perpendicular to both the first direction z and the second direction x is referred to as the "third direction y." Furthermore, in the description of the semiconductor device A10, "overlapping" refers to two different elements, and includes cases where one element entirely overlaps the other, as well as cases where one element partially overlaps the other.

[0013] The semiconductor device A10 converts DC power applied to the first power terminal 41 and the second power terminal 42 into AC power using a plurality of first semiconductor elements 31 and a plurality of second semiconductor elements 32. The converted AC power is input to a power supply target (for example, a motor 89 described below) from the third power terminal 43. The semiconductor device A10 constitutes part of a power conversion circuit such as an inverter.

[0014] As shown in FIGS. 5 to 8 , the sealing resin 60 covers the plurality of first semiconductor elements 31 and the plurality of second semiconductor elements 32. The sealing resin 60 has electrical insulation properties. The sealing resin 60 is made of a material containing, for example, black epoxy resin. The sealing resin 60 has a first surface 61, a second surface 62, a first side surface 63, a second side surface 64, a third side surface 65, and a fourth side surface 66.

[0015] 5 to 8, the first surface 61 and the second surface 62 face in opposite directions in the first direction z. Of these, the second surface 62 faces the same side in the first direction z as a mounting surface 121 of the conductive layer 12, which will be described later.

[0016] As shown in Figures 1 and 4 to 6, the first side surface 63 and the second side surface 64 face opposite each other in the second direction x. The first side surface 63 and the second side surface 64 are connected to the first surface 61 and the second surface 62, respectively. As shown in Figures 1, 4, 7, and 8, the third side surface 65 and the fourth side surface 66 face opposite each other in the third direction y. The third side surface 65 and the fourth side surface 66 are connected to the first surface 61 and the second surface 62, respectively.

[0017] As shown in FIGS. 5 to 8 , the insulating layer 11 includes a conductive layer 12, first signal wiring 21 to fourth signal wiring 24, a plurality of first relay wirings 28, and a plurality of second relay wirings 29. The elements including the insulating layer 11, conductive layer 12, heat dissipation layer 13, first signal wiring 21 to fourth signal wiring 24, a plurality of first relay wirings 28, and a plurality of second relay wirings 29 are formed from a substrate formed by, for example, active metal brazing (AMB). The dimension of the insulating layer 11 in the first direction z is smaller than the dimensions of the conductive layer 12 and the heat dissipation layer 13 in the first direction z. The insulating layer 11 is covered with a sealing resin 60.

[0018] As shown in FIGS. 5 to 8 , the conductive layer 12 is located on one side of the insulating layer 11 in the first direction z. The conductive layer 12 is bonded to the insulating layer 11. The conductive layer 12 mounts a plurality of first semiconductor elements 31 and a plurality of second semiconductor elements 32. The conductive layer 12 contains copper (Cu). The conductive layer 12 is covered with a sealing resin 60. As shown in FIG. 3 , the conductive layer 12 overlaps the heat dissipation layer 13 as viewed in the first direction z. As shown in FIGS. 5 to 8 , the conductive layer 12 has a mounting surface 121 facing the opposite side from the side facing the insulating layer 11 in the first direction z.

[0019] As shown in FIGS. 5 to 8 , the heat dissipation layer 13 is located on the opposite side of the conductive layer 12 in the first direction z, with the insulating layer 11 sandwiched therebetween. The heat dissipation layer 13 is bonded to the insulating layer 11. As shown in FIG. 4 , the heat dissipation layer 13 is exposed to the outside from a first surface 61 of the sealing resin 60. When the semiconductor device A10 is in use, the heat dissipation layer 13 is bonded to a heat sink (not shown). The composition of the heat dissipation layer 13 includes copper. When viewed in the first direction z, the heat dissipation layer 13 is located inward of the periphery 111 of the insulating layer 11.

[0020] As shown in Figures 5 and 6, the first signal wiring 21 is located on the opposite side of the heat dissipation layer 13 in the first direction z, with the insulating layer 11 sandwiched therebetween. The first signal wiring 21 is bonded to the insulating layer 11. As shown in Figures 2 and 3, the first signal wiring 21 is located on one side of the conductive layer 12 in the second direction x. The first signal wiring 21 extends in the third direction y. The first signal wiring 21 contains copper. The first signal wiring 21 is covered with a sealing resin 60. When viewed in the first direction z, the first signal wiring 21 overlaps the heat dissipation layer 13.

[0021] As shown in Figures 5 and 6, the second signal wiring 22 is located on the opposite side of the heat dissipation layer 13 in the first direction z, with the insulating layer 11 sandwiched therebetween. The second signal wiring 22 is bonded to the insulating layer 11. As shown in Figures 2 and 3, the second signal wiring 22 is located on the opposite side of the conductive layer 12 in the second direction x, with the first signal wiring 21 sandwiched therebetween. The second signal wiring 22 extends in the third direction y. The second signal wiring 22 contains copper. The second signal wiring 22 is covered with a sealing resin 60. As viewed in the first direction z, the second signal wiring 22 overlaps the heat dissipation layer 13.

[0022] As shown in Figures 5 and 6, the third signal wiring 23 is located on the opposite side of the heat dissipation layer 13 in the first direction z, with the insulating layer 11 sandwiched therebetween. The second signal wiring 22 is bonded to the insulating layer 11. As shown in Figures 2 and 3, the third signal wiring 23 is located on the opposite side of the first signal wiring 21 in the second direction x, with the conductive layer 12 sandwiched therebetween. The third signal wiring 23 extends in the third direction y. The third signal wiring 23 contains copper. The third signal wiring 23 is covered with a sealing resin 60. As viewed in the first direction z, the third signal wiring 23 overlaps the heat dissipation layer 13.

[0023] As shown in FIGS. 5 and 6 , the fourth signal wiring 24 is located on the opposite side of the heat dissipation layer 13 in the first direction z, with the insulating layer 11 sandwiched therebetween. The fourth signal wiring 24 is bonded to the insulating layer 11. As shown in FIGS. 2 and 3 , the fourth signal wiring 24 is located on the opposite side of the conductive layer 12 in the second direction x, with the third signal wiring 23 sandwiched therebetween. The fourth signal wiring 24 extends in the third direction y. The fourth signal wiring 24 contains copper. The fourth signal wiring 24 is covered with a sealing resin 60. As viewed in the first direction z, the fourth signal wiring 24 overlaps the heat dissipation layer 13.

[0024] As shown in FIGS. 5 and 6 , the multiple first relay wirings 28 are located on the opposite side of the heat dissipation layer 13 in the first direction z, with the insulating layer 11 sandwiched therebetween. The multiple first relay wirings 28 are bonded to the insulating layer 11. As shown in FIG. 3 , the multiple first relay wirings 28 are located between the conductive layer 12 and the first signal wiring 21 in the second direction x. The multiple first relay wirings 28 are arranged in the third direction y. Each of the multiple first relay wirings 28 extends in the second direction x. The length of each of the multiple first relay wirings 28 is shorter than the length of the first signal wiring 21. As viewed in the first direction z, the multiple first relay wirings 28 individually overlap the multiple first semiconductor elements 31 and also overlap the first power terminal 41. The composition of the multiple first relay wirings 28 includes copper. The multiple first relay wirings 28 are covered with a sealing resin 60. When viewed in the first direction z, the multiple first relay wires 28 overlap the heat dissipation layer 13 .

[0025] As shown in FIGS. 5 and 6 , the multiple second relay wirings 29 are located on the opposite side of the heat dissipation layer 13 in the first direction z, with the insulating layer 11 sandwiched therebetween. The multiple second relay wirings 29 are bonded to the insulating layer 11. As shown in FIG. 3 , the multiple second relay wirings 29 are located between the conductive layer 12 and the first signal wirings 21 in the second direction x. The multiple second relay wirings 29 are arranged in the third direction y. Each of the multiple second relay wirings 29 is located adjacent to one of the multiple first relay wirings 28 in the third direction y. Each of the multiple second relay wirings 29 extends in the second direction x. The length of each of the multiple second relay wirings 29 is shorter than the length of the first signal wirings 21. As viewed in the first direction z, the multiple second relay wirings 29 individually overlap the multiple first semiconductor elements 31 and also overlap the first power terminal 41. The composition of the multiple second relay wirings 29 includes copper. The second relay wires 29 are covered with the sealing resin 60. When viewed in the first direction z, the second relay wires 29 overlap the heat dissipation layer 13.

[0026] As shown in FIGS. 5 to 7 , the multiple first semiconductor elements 31 are bonded to the mounting surface 121 of the conductive layer 12. Each of the multiple first semiconductor elements 31 is the same element. The multiple first semiconductor elements 31 are, for example, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Alternatively, the multiple first semiconductor elements 31 may be field-effect transistors including MISFETs (Metal-Insulator-Semiconductor Field-Effect Transistors) or bipolar transistors such as IGBTs (Insulated Gate Bipolar Transistors). In the description of the semiconductor device A10, the multiple first semiconductor elements 31 are n-channel MOSFETs with a vertical structure. The multiple first semiconductor elements 31 include a compound semiconductor substrate. The compound semiconductor substrate contains silicon carbide (SiC). The multiple first semiconductor elements 31 are arranged along the third direction y.

[0027] As shown in FIGS. 9 and 10, each of the plurality of first semiconductor elements 31 has a first electrode 311 , a second electrode 312 and a first control electrode 313 .

[0028] 9 and 10 , the first electrode 311 is located on the side of the conductive layer 12 opposite to the side facing the mounting surface 121 in the first direction z. A current corresponding to the power before being converted by the first semiconductor element 31 flows through the first electrode 311. In other words, the first electrode 311 corresponds to the drain of the first semiconductor element 31.

[0029] As shown in FIGS. 9 and 10 , the second electrode 312 is located on the opposite side of the first electrode 311 in the first direction z. The second electrode 312 faces the mounting surface 121 of the conductive layer 12. A current corresponding to the power converted by the first semiconductor element 31 flows through the second electrode 312. That is, the second electrode 312 corresponds to the source of the first semiconductor element 31. The second electrode 312 is conductively bonded to the mounting surface 121 of the conductive layer 12 via a conductive bonding layer 39. As a result, the second electrode 312 of each of the multiple first semiconductor elements 31 is electrically connected to the conductive layer 12. Furthermore, the second electrode 312 of each of the multiple first semiconductor elements 31 is individually conductively bonded to the multiple second relay wirings 29 via the conductive bonding layer 39. As a result, the second electrode 312 of each of the multiple first semiconductor elements 31 is individually electrically connected to the multiple second relay wirings 29. The conductive bonding layer 39 is, for example, solder. Alternatively, the conductive bonding layer 39 may be a sintered body of metal particles, in which case the metal particles contain, for example, silver (Ag).

[0030] As shown in Fig. 9 , the first control electrode 313 is located on the same side as the second electrode 312 in the first direction z. A gate voltage for driving the first semiconductor element 31 is applied to the first control electrode 313. As shown in Fig. 3 , the area of ​​the first control electrode 313 is smaller than the area of ​​the second electrode 312 when viewed in the first direction z. As shown in Fig. 9 , the first control electrode 313 of each of the multiple first semiconductor elements 31 is individually conductively bonded to the multiple first relay wires 28 via a conductive bonding layer 39. As a result, the first control electrode 313 of each of the multiple first semiconductor elements 31 is individually conductively connected to the multiple first relay wires 28.

[0031] 5, 6, and 8, the multiple second semiconductor elements 32 are conductively bonded to the mounting surface 121 of the conductive layer 12. Each of the multiple second semiconductor elements 32 is the same element as each of the multiple first semiconductor elements 31. Therefore, the multiple second semiconductor elements 32 are n-channel MOSFETs with a vertical structure. The multiple second semiconductor elements 32 are arranged along the third direction y.

[0032] As shown in FIG. 11 , each of the plurality of second semiconductor elements 32 has a third electrode 321 , a fourth electrode 322 and a second control electrode 323 .

[0033] 11 , the third electrode 321 faces the mounting surface 121 of the conductive layer 12. A current corresponding to the power before being converted by the second semiconductor element 32 flows through the third electrode 321. That is, the third electrode 321 corresponds to the drain of the second semiconductor element 32. Therefore, the polarity of the third electrode 321 is different from the polarity of the second electrode 312 of each of the multiple first semiconductor elements 31. The third electrode 321 is conductively bonded to the mounting surface 121 via the conductive bonding layer 39. As a result, the third electrode 321 of each of the multiple second semiconductor elements 32 is electrically connected to the conductive layer 12.

[0034] 11 , the fourth electrode 322 is located on the opposite side to the third electrode 321 in the first direction z. A current corresponding to the power converted by the second semiconductor element 32 flows through the fourth electrode 322. In other words, the fourth electrode 322 corresponds to the source of the second semiconductor element 32.

[0035] 11 , the second control electrode 323 is located on the same side as the fourth electrode 322 in the first direction z. A gate voltage for driving the second semiconductor element 32 is applied to the second control electrode 323. As shown in FIG. 3 , the area of ​​the second control electrode 323 is smaller than the area of ​​the fourth electrode 322 when viewed in the first direction z.

[0036] As shown in FIGS. 2 , 9 , and 10 , the first power terminal 41 is conductively bonded to the first electrodes 311 of the first semiconductor elements 31 via a conductive bonding layer 39. This electrically connects the first power terminal 41 to the first electrodes 311 of the first semiconductor elements 31. The first power terminal 41 is a P terminal (positive electrode) to which DC power to be converted is applied. The first power terminal 41 contains copper. As shown in FIGS. 2 and 7 , the first power terminal 41 has a first inner portion 411 and a first outer portion 412. The first inner portion 411 is conductively bonded to the first electrodes 311 of the first semiconductor elements 31. The first inner portion 411 extends in the third direction y. When viewed in the first direction z, the first inner portion 411 overlaps the first electrodes 311 of the first semiconductor elements 31. The first outer part 412 is connected to one side in the third direction y of the first inner part 411. The first outer part 412 protrudes from the third side surface 65 of the sealing resin 60 to the outside.

[0037] As shown in FIGS. 5 and 7 , the dimension d1 in the first direction z of the portion of the sealing resin 60 sandwiched between the first inner portion 411 and the second surface 62 of the sealing resin 60 is larger than the dimension in the first direction z of the insulating layer 11. Here, the semiconductor device A10 has a first parasitic capacitance C1 and a second parasitic capacitance C2. The first parasitic capacitance C1 has the conductive layer 12 and the heat dissipation layer 13 as conductor layers and the insulating layer 11 as a dielectric layer. The second parasitic capacitance C2 has the first inner portion 411 as one conductor layer and the sealing resin 60 including the second surface 62 as a dielectric layer. The other conductor layer of the second parasitic capacitance C2 is a metal member located outside the semiconductor device A10 and adjacent to the second surface 62. With this configuration, the second parasitic capacitance C2 is smaller than the first parasitic capacitance C1. In the semiconductor device A10, the second parasitic capacitance C2 is 50% or less of the first parasitic capacitance C1. Furthermore, in the semiconductor device A10, it is more preferable that the second parasitic capacitance C2 is 20% or less of the first parasitic capacitance C1 in terms of the effects of the semiconductor device A10 described later.

[0038] As shown in FIGS. 2 and 11 , the second power terminal 42 is conductively bonded to the fourth electrodes 322 of the second semiconductor elements 32 via the conductive bonding layer 39. This electrically connects the second power terminal 42 to the fourth electrodes 322 of the second semiconductor elements 32. The second power terminal 42 is an N-terminal (negative electrode) to which DC power to be converted is applied. The second power terminal 42 contains copper. As shown in FIGS. 2 and 8 , the second power terminal 42 has a second inner portion 421 and a second outer portion 422. The second inner portion 421 is conductively bonded to the fourth electrodes 322 of the second semiconductor elements 32. The second inner portion 421 extends in the third direction y. When viewed in the first direction z, the second inner portion 421 overlaps the fourth electrodes 322 of the second semiconductor elements 32. The second outer part 422 is connected to one side of the second inner part 421 in the third direction y. The second outer part 422 is located adjacent to the second outer part 422 of the first power terminal 41 in the second direction x. The second outer part 422 protrudes outward from the third side surface 65 of the sealing resin 60.

[0039] As shown in FIGS. 5 and 8 , the dimension d2 in the first direction z of the portion of the sealing resin 60 sandwiched between the second outer portion 422 and the second surface 62 of the sealing resin 60 is larger than the dimension in the first direction z of the insulating layer 11. Here, a third parasitic capacitance C3 is formed in the semiconductor device A10. The third parasitic capacitance C3 has the second inner portion 421 as one conductor layer and the sealing resin 60 including the second surface 62 as a dielectric layer. The other conductor layer of the third parasitic capacitance C3 is a metal member located outside the semiconductor device A10 and adjacent to the second surface 62. With this configuration, the third parasitic capacitance C3 is smaller than the first parasitic capacitance C1 described above. In the semiconductor device A10, the third parasitic capacitance C3 is 50% or less of the first parasitic capacitance C1. Furthermore, in the semiconductor device A10, it is more preferable that the third parasitic capacitance C3 be 20% or less of the first parasitic capacitance C1 in terms of the effects of the semiconductor device A10 described below.

[0040] 2 and 7 , the third power terminal 43 is conductively bonded to the conductive layer 12. This electrically connects the third power terminal 43 to the conductive layer 12, the second electrode 312 of each of the first semiconductor elements 31, and the third electrode 321 of each of the second semiconductor elements 32. The third power terminal 43 is located on the opposite side of the first outer portion 412 of the first power terminal 41 and the second outer portion 422 of the second power terminal 42 relative to the first semiconductor elements 31 and the second semiconductor elements 32 in the third direction y. A portion of the third power terminal 43 protrudes from the fourth side surface 66 of the sealing resin 60. The AC power converted by the first semiconductor elements 31 and the second semiconductor elements 32 is output from the third power terminal 43. The third power terminal 43 contains copper.

[0041] 2 and 5 , the first signal terminal 44 is located on the opposite side of the first signal wiring 21 in the second direction x with the second signal wiring 22 as a reference. The first signal terminal 44 is electrically connected to the first control electrode 313 of each of the multiple first semiconductor elements 31. A gate voltage for driving the multiple first semiconductor elements 31 is applied to the first signal terminal 44. The first signal terminal 44 is a metal lead containing copper. The first signal terminal 44 includes a portion that protrudes to the outside from the first side surface 63 of the sealing resin 60. This portion includes a portion extending in the first direction z and a portion extending in the second direction x.

[0042] As shown in FIGS. 3 and 5 , the multiple first wires 51 are individually conductively bonded to the multiple first relay wires 28 and are also conductively bonded to the first signal wires 21. As shown in FIGS. 3 and 5 , the third wire 53 is conductively bonded to the first signal terminal 44 and the first signal wire 21. As a result, the first signal terminal 44 is electrically connected to the first control electrode 313 of each of the multiple first semiconductor elements 31. The multiple first wires 51 and the third wires 53 are covered with a sealing resin 60. The composition of each of the multiple first wires 51 and the third wires 53 includes gold (Au). Alternatively, the composition of each of the multiple first wires 51 and the third wires 53 may include either aluminum or copper.

[0043] 2 and 6 , the second signal terminal 45 is located on the opposite side of the first signal wiring 21 in the second direction x with the second signal wiring 22 as a reference. The second signal terminal 45 is located next to the first signal terminal 44 in the third direction y. The second signal terminal 45 is electrically connected to the second electrodes 312 of each of the multiple first semiconductor elements 31. A voltage having the same potential as the voltage applied to the second electrodes 312 of each of the multiple first semiconductor elements 31 is applied to the second signal terminal 45. The second signal terminal 45 is a metal lead containing copper. The second signal terminal 45 includes a portion protruding to the outside from the first side surface 63 of the sealing resin 60. This portion includes a portion extending in the first direction z and a portion extending in the second direction x.

[0044] As shown in FIGS. 3 and 6 , the multiple second wires 52 are individually conductively bonded to the multiple second relay wires 29 and are also conductively bonded to the second signal wires 22. As shown in FIGS. 3 and 6 , the fourth wire 54 is conductively bonded to the second signal terminal 45 and the second signal wire 22. As a result, the second signal terminal 45 is electrically connected to the second electrodes 312 of the multiple first semiconductor elements 31. The multiple second wires 52 and the fourth wire 54 are covered with a sealing resin 60. The composition of each of the multiple second wires 52 and the fourth wire 54 includes gold. Alternatively, the composition of each of the multiple second wires 52 and the fourth wire 54 may include either aluminum or copper.

[0045] 2 and 5 , the third signal terminal 46 is located on the opposite side of the third signal wiring 23 in the second direction x with the fourth signal wiring 24 as a reference. The third signal terminal 46 is electrically connected to the second control electrodes 323 of each of the multiple second semiconductor elements 32. A gate voltage for driving the multiple second semiconductor elements 32 is applied to the third signal terminal 46. The third signal terminal 46 is a metal lead containing copper. The third signal terminal 46 includes a portion that protrudes to the outside from the second side surface 64 of the sealing resin 60. This portion includes a portion extending in the first direction z and a portion extending in the second direction x.

[0046] As shown in FIGS. 3 and 11 , the plurality of fifth wires 55 are individually conductively bonded to the second control electrodes 323 of the plurality of second semiconductor elements 32, and are also conductively bonded to the third signal wiring 23. As shown in FIGS. 3 and 5 , the seventh wire 57 is conductively bonded to the third signal terminal 46 and the third signal wiring 23. This allows the third signal terminal 46 to be electrically connected to the second control electrodes 323 of the plurality of second semiconductor elements 32. The plurality of fifth wires 55 and the seventh wire 57 are covered with a sealing resin 60. The composition of each of the plurality of fifth wires 55 and the seventh wire 57 includes gold. Alternatively, the composition of each of the plurality of fifth wires 55 and the seventh wire 57 may include either aluminum or copper.

[0047] 2 and 6 , the fourth signal terminal 47 is located on the opposite side of the fourth signal wiring 24 from the third signal wiring 23 in the second direction x. The fourth signal terminal 47 is located next to the third signal terminal 46 in the third direction y. The fourth signal terminal 47 is electrically connected to the fourth electrodes 322 of each of the multiple second semiconductor elements 32. A voltage having the same potential as the voltage applied to the fourth electrodes 322 of each of the multiple second semiconductor elements 32 is applied to the fourth signal terminal 47. The fourth signal terminal 47 is a metal lead containing copper. The fourth signal terminal 47 includes a portion protruding from the second side surface 64 of the sealing resin 60 to the outside. This portion includes a portion extending in the first direction z and a portion extending in the second direction x.

[0048] As shown in FIG. 3 , the sixth wires 56 are conductively bonded to the fourth electrodes 322 of the second semiconductor elements 32 and to the fourth signal wiring 24. As shown in FIGS. 3 and 6 , the eighth wire 58 is conductively bonded to the fourth signal terminal 47 and the fourth signal wiring 24. This allows the fourth signal terminal 47 to be electrically connected to the fourth electrodes 322 of the second semiconductor elements 32. The sixth wires 56 and the eighth wires 58 are covered with a sealing resin 60. The sixth wires 56 and the eighth wires 58 each contain gold. Alternatively, the sixth wires 56 and the eighth wires 58 may each contain either aluminum or copper.

[0049] Next, an example of an inverter system B including a plurality of semiconductor devices A10 will be described with reference to FIG.

[0050] As shown in FIG. 12 , the inverter system B includes three semiconductor devices A10, a wiring board 81, a control circuit 82, multiple drive circuits 83, a DC power supply 88, and a motor 89. The control circuit 82 and multiple drive circuits 83 are provided on the wiring board 81. The control circuit 82 is a microcomputer including a CPU and a memory. The control circuit 82 is electrically connected to the multiple drive circuits 83 and is also connected to the outside. The control circuit 82 generates control signals for driving the multiple drive circuits 83 based on input signals from the outside. For example, PWM (Pulse Width Modulation) control is performed to generate the control signals. The generated control signals are output individually to the multiple drive circuits 83.

[0051] Each of the plurality of drive circuits 83 generates a drive signal for driving one of the three semiconductor devices A10 based on a control signal input from the control circuit 82. The generated drive signal is output to either the first signal terminal 44 or the third signal terminal 46 of each of the three semiconductor devices A10.

[0052] 12 , the multiple drive circuits 83 include three first drive circuits 83A and three second drive circuits 83B. Each of the three first drive circuits 83A drives a plurality of first semiconductor elements 31 of one of the three semiconductor devices A10. The three first drive circuits 83A are individually connected to the first signal terminal 44 and the second signal terminal 45 of each of the three semiconductor devices A10. Each of the three second drive circuits 83B drives a plurality of second semiconductor elements 32 of one of the three semiconductor devices A10. The three second drive circuits 83B are individually connected to the third signal terminal 46 and the fourth signal terminal 47 of each of the three semiconductor devices A10.

[0053] 12 , the first power terminal 41 of each of the three semiconductor devices A10 is electrically connected to the positive electrode of a DC power supply 88. The second power terminal 42 of each of the three semiconductor devices A10 is electrically connected to the negative electrode of the DC power supply 88. This allows DC power to be input to each of the three semiconductor devices A10. Then, the multiple drive circuits 83 drive the multiple first semiconductor elements 31 and multiple second semiconductor elements 32 of each of the three semiconductor devices A10, thereby outputting three-phase AC power corresponding to the U phase, V phase, and W phase individually from the third power terminal 43 of each of the three semiconductor devices A10.

[0054] 12 , the motor 89 is electrically connected to the third power terminals 43 of the three semiconductor devices A10. The motor 89 is a three-phase induction motor. Three-phase AC power is input to the motor 89 from the third power terminals 43 of the three semiconductor devices A10. This drives the motor 89.

[0055] Next, the effects of the semiconductor device A10 will be described.

[0056] The semiconductor device A10 includes an insulating layer 11, a conductive layer 12, a heat dissipation layer 13, a first semiconductor element 31, and a second semiconductor element 32. The first semiconductor element 31 has a first electrode 311 and a second electrode 312. The second semiconductor element 32 has a third electrode 321 and a fourth electrode 322. The polarity of the second electrode 312 and the polarity of the third electrode 321 are mutually opposite. The second electrode 312 and the third electrode 321 are each conductively joined to the conductive layer 12. As viewed in the first direction z, the conductive layer 12 overlaps the heat dissipation layer 13. With this configuration, the semiconductor device A10 has the first parasitic capacitance C1 described above, a parasitic capacitance with the first electrode 311 as one of the conductor layers (corresponding to the second parasitic capacitance C2 described above), and a parasitic capacitance with the fourth electrode 322 as one of the conductor layers (corresponding to the third parasitic capacitance C3 described above). In this case, the parasitic capacitance of the first electrode 311 as one of the conductor layers and the parasitic capacitance of the fourth electrode 322 as one of the conductor layers are each set to be smaller than the first parasitic capacitance C1. This suppresses leakage current to the outside due to the conductive path to the first electrode 311 and the conductive path to the fourth electrode 322 in the semiconductor device A10. Therefore, with this configuration, it is possible to reduce noise due to leakage current to the outside in the semiconductor device A10.

[0057] The semiconductor device A10 further includes a sealing resin 60 that covers the first semiconductor element 31 and the second semiconductor element 32, and a first power terminal 41 that is electrically connected to a first electrode 311 of the first semiconductor element 31. The first power terminal 41 has a first inner portion 411 that is covered with the sealing resin 60. A dimension d1 in the first direction z of a portion of the sealing resin 60 that is sandwiched between the first inner portion 411 and a second surface 62 of the sealing resin 60 is larger than the dimension in the first direction z of the insulating layer 11. This configuration makes it possible to more effectively set the second parasitic capacitance C2 smaller than the first parasitic capacitance C1.

[0058] When viewed in the first direction z, the first inner portion 411 of the first power terminal 41 overlaps the first electrode 311 of the first semiconductor element 31. This configuration reduces the parasitic inductance caused by the conductive path from the first outer portion 412 of the first power terminal 41 to the first electrode 311, and also more effectively dissipates heat generated from the first electrode 311 to the outside.

[0059] The semiconductor device A10 further includes a second power terminal 42 that is electrically connected to the fourth electrode 322 of the second semiconductor element 32. The second power terminal 42 has a second inner portion 421 that is covered with the sealing resin 60. A dimension d2 in the first direction z of the portion of the sealing resin 60 that is sandwiched between the second inner portion 421 and the second surface 62 of the sealing resin 60 is larger than the dimension in the first direction z of the insulating layer 11. By adopting this configuration, the third parasitic capacitance C3 can be more effectively set smaller than the first parasitic capacitance C1.

[0060] The heat dissipation layer 13 is exposed from the first surface 61 of the sealing resin 60. This configuration makes it easy to join a heat sink to the heat dissipation layer 13 using solder or the like, thereby improving the heat dissipation performance of the semiconductor device A10.

[0061] The semiconductor device A10 further includes a first signal wiring 21 that is electrically connected to the first control electrode 313 of the first semiconductor element 31. The first signal wiring 21 is located on the opposite side of the heat dissipation layer 13 with the insulating layer 11 sandwiched therebetween. When viewed in the first direction z, the first signal wiring 21 overlaps the heat dissipation layer 13. This configuration makes it possible to suppress leakage current to the outside due to voltage changes in the first signal wiring 21 over time.

[0062] The semiconductor device A10 further includes a first relay wiring 28 located on the opposite side of the heat dissipation layer 13 with the insulating layer 11 sandwiched therebetween. The first control electrode 313 of the first semiconductor element 31 is conductively bonded to the first relay wiring 28. The first relay wiring 28 is electrically connected to the first signal wiring 21. With this configuration, even when the first control electrode 313 is located on the same side as the second electrode 312 in the first direction z and the second electrode 312 is conductively bonded to the conductive layer 12, the first control electrode 313 can be electrically connected to the first signal wiring 21.

[0063] Second Embodiment: A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Figures 13 to 16. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. For ease of understanding, Figure 13 shows the first power terminal 41, the second power terminal 42, and the sealing resin 60 in a see-through view. In Figure 13, the see-through first power terminal 41, the second power terminal 42, and the sealing resin 60 are each shown with imaginary lines.

[0064] The semiconductor device A20 differs from the semiconductor device A10 in that it does not have a second signal wiring 22, a plurality of second relay wirings 29, and a plurality of second wires 52, and in the configuration of the conductive layer 12, a plurality of first semiconductor elements 31, and a fourth wire 54.

[0065] 13 and 15 , the fourth wire 54 is conductively bonded to the second signal terminal 45 and the conductive layer 12. As a result, the second signal terminal 45 is electrically connected to the second electrode 312 of each of the multiple first semiconductor elements 31 via the conductive layer 12.

[0066] As shown in FIGS. 13 and 16 , both sides of each of the plurality of first relay wirings 28 in the third direction y face the conductive layer 12 .

[0067] Next, the effects of the semiconductor device A20 will be described.

[0068] The semiconductor device A20 includes an insulating layer 11, a conductive layer 12, a heat dissipation layer 13, a first semiconductor element 31, and a second semiconductor element 32. The first semiconductor element 31 has a first electrode 311 and a second electrode 312. The second semiconductor element 32 has a third electrode 321 and a fourth electrode 322. The polarity of the second electrode 312 and the polarity of the third electrode 321 are opposite to each other. The second electrode 312 and the third electrode 321 are each conductively bonded to the conductive layer 12. As viewed in the first direction z, the conductive layer 12 overlaps the heat dissipation layer 13. Therefore, with this configuration, the semiconductor device A20 can also reduce noise caused by leakage current to the outside. Furthermore, by incorporating a configuration common to the semiconductor device A10, the semiconductor device A20 achieves the same effects as the semiconductor device A10.

[0069] In the semiconductor device A20, the second signal terminal 45 is electrically connected to the second electrode 312 of the first semiconductor element 31 via the conductive layer 12. By adopting this configuration, the semiconductor device A20 does not include the second signal wiring 22, the plurality of second relay wirings 29, and the plurality of second wires 52. This makes it possible to reduce the dimension of the semiconductor device A20 in the second direction x and to reduce the number of components of the semiconductor device A20.

[0070] In the semiconductor device A20, both sides of the first relay wiring 28 face the conductive layer 12 in a direction perpendicular to the first direction z. This configuration further increases the bonding area of ​​the second electrode 312 of the first semiconductor element 31 with the conductive layer 12. This increases the current flowing from the second electrode 312 to the conductive layer 12, while more effectively dissipating heat generated from the second electrode 312 to the outside.

[0071] Third Embodiment: A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to Figures 17 to 20. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. For ease of understanding, Figure 17 shows the first power terminal 41, the second power terminal 42, and the sealing resin 60 in a see-through view. In Figure 17, the see-through first power terminal 41, the second power terminal 42, and the sealing resin 60 are each shown with imaginary lines.

[0072] The semiconductor device A30 differs from the semiconductor device A10 in that it does not have a plurality of first relay wirings 28 and a plurality of second relay wirings 29, and in the configuration of a plurality of first semiconductor elements 31, a plurality of first wires 51, and a plurality of second wires 52.

[0073] 17 , each of the multiple first semiconductor elements 31 has a first detection electrode 314. The first detection electrode 314 is located on the same side as the first electrode 311 and the first control electrode 313 in the first direction z. As will be described later, the first detection electrode 314 is electrically connected to the second electrode 312. Therefore, a voltage equivalent to the voltage applied to the second electrode 312 is applied to the first detection electrode 314. When viewed in the first direction z, the area of ​​the first detection electrode 314 is approximately equal to the area of ​​the first control electrode 313.

[0074] 17 , 18 , and 20 , the multiple first wires 51 are individually conductively bonded to the first control electrodes 313 of the multiple first semiconductor elements 31, and are also conductively bonded to the first signal wiring 21. As a result, the first signal terminal 44 is electrically connected to the first control electrodes 313 of the multiple first semiconductor elements 31. As shown in FIGS. 17 and 19 , the multiple second wires 52 are individually conductively bonded to the first detection electrodes 314 of the multiple second semiconductor elements 32, and are also conductively bonded to the second signal wiring 22. As a result, the first signal terminal 44 is electrically connected to the second electrodes 312 of the multiple first semiconductor elements 31.

[0075] Next, the configuration of each of the plurality of first semiconductor elements 31 included in the semiconductor device A10 will be described with reference to FIGS.

[0076] 21 and 22 , each of the plurality of first signal wirings 21 has, in addition to the above-mentioned first electrode 311, second electrode 312, first control electrode 313, and first detection electrode 314, a main body 315, a first rewiring 316, a second rewiring 317, a protective layer 318, and a covering layer 319. The plurality of first semiconductor elements 31 are packaged in resin.

[0077] The body 315 corresponds to a MOSFET separated from the wafer. The body 315 includes a first pad 315A and a second pad 315B. As shown in FIG. 9 , the first pad 315A and the second pad 315B are located on the side of the conductive layer 12 facing the mounting surface 121 in the first direction z. The first pad 315A corresponds to the source of the body 315. The second pad 315B corresponds to the gate of the body 315. The first electrode 311 is included in the body 315 as the drain of the body 315. Therefore, the polarity of the first electrode 311 and the polarity of the first pad 315A are different from each other. Furthermore, the first pad 315A and the second pad 315B are located on the opposite side of the first electrode 311 in the first direction z.

[0078] 23 to 26 , the protective layer 318 covers a part of the main body 315 and at least a part of each of the first redistribution lines 316 and the second redistribution lines 317. The first electrode 311, the second electrode 312, the first control electrode 313, and the first detection electrode 314 are exposed from the protective layer 318.

[0079] 23 to 25, the second electrode 312 is electrically connected to the first pad 315A of the main body 315. As shown in Fig. 21, when viewed in the first direction z, the second electrode 312 includes a portion that protrudes outward from the first electrode 311. When viewed in the first direction z, the area of ​​the second electrode 312 is larger than the area of ​​the first pad 315A.

[0080] 21 , 23 , and 24 , the first control electrode 313 and the first detection electrode 314 are located on the same side as the first electrode 311 in the first direction z. The first detection electrode 314 is spaced apart from the first control electrode 313 in the third direction y.

[0081] 21 to 23, the first rewiring 316 is electrically connected to the second pad 315B of the main body 315 and the first control electrode 313. This allows the first control electrode 313 to be electrically connected to the second pad 315B. A portion of the first rewiring 316 is covered with a protective layer 318.

[0082] 21 , 22 , and 24 , the second rewiring 317 is electrically connected to each of the second electrode 312 and the first detection electrode 314. As a result, the first detection electrode 314 is electrically connected to the second electrode 312. A portion of the second rewiring 317 is covered with a protective layer 318.

[0083] The first redistribution line 316, the second redistribution line 317, and the protective layer 318 can be formed by, for example, the laser direct structuring (LDS) method disclosed in U.S. Patent Application Publication No. 2010 / 0019370. In this case, the material of the protective layer 318 includes an additive containing a metal element. Each of the first redistribution line 316 and the second redistribution line 317 includes the metal element.

[0084] 22 to 24 and 26 , the covering layer 319 covers the portions of the first rewiring 316 and the second rewiring 317 that are exposed from the protective layer 318. The covering layer 319 is an insulator. The covering layer 319 is in contact with the first rewiring 316, the second rewiring 317, and the protective layer 318. The covering layer 319 is, for example, a solder resist.

[0085] Next, the effects of the semiconductor device A30 will be described.

[0086] The semiconductor device A30 includes an insulating layer 11, a conductive layer 12, a heat dissipation layer 13, a first semiconductor element 31, and a second semiconductor element 32. The first semiconductor element 31 has a first electrode 311 and a second electrode 312. The second semiconductor element 32 has a third electrode 321 and a fourth electrode 322. The polarity of the second electrode 312 and the polarity of the third electrode 321 are opposite to each other. The second electrode 312 and the third electrode 321 are each conductively bonded to the conductive layer 12. As viewed in the first direction z, the conductive layer 12 overlaps the heat dissipation layer 13. Therefore, with this configuration, the semiconductor device A30 can also reduce noise caused by leakage current to the outside. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A20 achieves the same effects as the semiconductor device A10.

[0087] In the semiconductor device A30, the first control electrode 313 of the first semiconductor element 31 is located on the same side as the first electrode 311 in the first direction z. By adopting this configuration, the semiconductor device A30 can be configured without the first relay wiring 28. Furthermore, conductivity between the first control electrode 313 and the first signal wiring 21 can be achieved only by the first wire 51.

[0088] In the semiconductor device A30, the first semiconductor element 31 has a first detection electrode 314 located on the same side as the first electrode 311 in the first direction z. The first detection electrode 314 is electrically connected to the second electrode 312 of the first semiconductor element 31. By adopting this configuration, the semiconductor device A30 can be configured without the second relay wiring 29. Furthermore, electrical connection between the first detection electrode 314 and the second signal wiring 22 can be achieved only by the second wire 52.

[0089] Fourth Embodiment: A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described with reference to Figures 27 and 28. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are designated by the same reference numerals, and duplicated descriptions will be omitted. Here, Figure 27 corresponds to Figure 5, which shows the semiconductor device A10. Figure 28 corresponds to Figure 7, which shows the semiconductor device A10.

[0090] In the semiconductor device A40, the configuration of the sealing resin 60 is different from that of the semiconductor device A10.

[0091] 27 and 28 , the sealing resin 60 includes a first layer 601 and a second layer 602. The first layer 601 has a first surface 61. The second layer 602 has a second surface 62 and is stacked on the first layer 601. The first layer 601 covers the plurality of first semiconductor elements 31, the plurality of second semiconductor elements 32, the first inner portion 411 of the first power terminal 41, and the second inner portion 421 of the second power terminal 42. The dimension of the second layer 602 in the first direction z is larger than the dimension of the insulating layer 11 in the first direction z.

[0092] The sealing resin 60 of the semiconductor device A40 is formed by forming a first layer 601 by molding, and then forming a second layer 602 by molding.

[0093] Next, a semiconductor device A41, which is a modification of the semiconductor device A40, will be described with reference to Figures 29 and 30. Here, Figure 29 corresponds to Figure 27 showing the semiconductor device A40. Figure 30 corresponds to Figure 28 showing the semiconductor device A40.

[0094] The semiconductor device A41 differs from the semiconductor device A30 in the configuration of the sealing resin 60. The configuration of the sealing resin 60 in the semiconductor device A41 is the same as the configuration of the sealing resin 60 in the semiconductor device A40.

[0095] Next, the effects of the semiconductor device A40 will be described.

[0096] The semiconductor device A40 includes an insulating layer 11, a conductive layer 12, a heat dissipation layer 13, a first semiconductor element 31, and a second semiconductor element 32. The first semiconductor element 31 has a first electrode 311 and a second electrode 312. The second semiconductor element 32 has a third electrode 321 and a fourth electrode 322. The polarity of the second electrode 312 and the polarity of the third electrode 321 are opposite to each other. The second electrode 312 and the third electrode 321 are each conductively bonded to the conductive layer 12. As viewed in the first direction z, the conductive layer 12 overlaps the heat dissipation layer 13. Therefore, with this configuration, the semiconductor device A40 can also reduce noise caused by leakage current to the outside. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A20 achieves the same effects as the semiconductor device A10.

[0097] In the semiconductor device A40, the sealing resin 60 includes a first layer 601 and a second layer 602. The second layer 602 is laminated on the first layer 601. The first inner portion 411 of the first power terminal 41 and the second inner portion 421 of the second power terminal 42 are each covered by the first layer 601. This configuration reduces warping of the sealing resin 60 around a direction perpendicular to the first direction z. Furthermore, defects occurring on the surface of the sealing resin 60 can be suppressed.

[0098] The dimension in the first direction z of the second layer 602 is larger than the dimension in the first direction z of the insulating layer 11. This configuration makes it possible to further increase the dimension in the first direction z of the portion of the sealing resin 60 sandwiched between the second surface 62 of the sealing resin 60 and each of the first inner portion 411 of the first power terminal 41 and the second inner portion 421 of the second power terminal 42. This makes it possible to more effectively set each of the second parasitic capacitance C2 and the third parasitic capacitance C3 described above smaller than the first parasitic capacitance C1.

[0099] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0100] The present disclosure includes embodiments described in the following appendices: Appendix 1. A semiconductor device (A10) comprising: an insulating layer (11); a conductive layer (12) located on one side of the insulating layer in a first direction (z); a heat dissipation layer (13) located on the opposite side of the conductive layer with the insulating layer sandwiched therebetween; a first semiconductor element (31) having a first electrode (311) and a second electrode (312) and located on the opposite side of the insulating layer with the conductive layer sandwiched therebetween; and a second semiconductor element (32) having a third electrode (321) and a fourth electrode (322) and located on the opposite side of the insulating layer with the conductive layer sandwiched therebetween, wherein the second electrode is located on the opposite side of the first electrode in the first direction, the fourth electrode is located on the opposite side of the third electrode in the first direction, the polarities of the second electrode and the third electrode are different from each other, and each of the second electrode and the third electrode is conductively joined to the conductive layer, and the conductive layer overlaps the heat dissipation layer as viewed in the first direction. The semiconductor device (A10) according to Appendix 1, wherein the conductive layer and the heat dissipation layer are each bonded to the insulating layer. Appendix 3. The semiconductor device (A10) according to Appendix 2, further comprising: a sealing resin (60) covering the first semiconductor element and the second semiconductor element, the sealing resin having a first surface (61) facing one side in the first direction, and the heat dissipation layer being exposed from the first surface. Appendix 4. The semiconductor device (A10) according to Appendix 3, further comprising: a first power terminal (41) conducting to the first electrode, the first power terminal having a first inner portion (411) covered by the sealing resin, the sealing resin having a second surface (62) facing the opposite side to the first surface in the first direction, and the dimension in the first direction of the portion of the sealing resin sandwiched between the first inner portion and the second surface being larger than the dimension in the first direction of the insulating layer. Appendix 5. The semiconductor device (A10) according to Appendix 4, wherein, when viewed in the first direction, the first inner portion overlaps the first electrode.Appendix 6. The semiconductor device (A10) according to Appendix 5, further comprising a second power terminal (42) conducting to the fourth electrode, the second power terminal having a second inner portion (421) covered with the sealing resin, and a dimension in the first direction of a portion of the sealing resin sandwiched between the second inner portion and the second surface is larger than a dimension in the first direction of the insulating layer. Appendix 7. The semiconductor device (A10) according to Appendix 6, wherein, when viewed in the first direction, the second inner portion overlaps the fourth electrode. Appendix 8. The semiconductor device (A10) according to Supplementary Note 7, further comprising: a first parasitic capacitance (C1) having the conductive layer and the heat dissipation layer as conductor layers and the insulating layer as a dielectric layer; a second parasitic capacitance (C2) having the first inner portion as one conductor layer and the sealing resin including the second surface as a dielectric layer; and a third parasitic capacitance (C3) having the second inner portion as one conductor layer and the sealing resin including the second surface as a dielectric layer, wherein each of the second parasitic capacitance and the third parasitic capacitance is 50% or less of the first parasitic capacitance.Supplementary Note 9. The semiconductor device (A10) according to Supplementary Note 7, further comprising: a first signal terminal (44), wherein the first semiconductor element has a first control electrode (313), and the first signal terminal is electrically connected to the first control electrode.Supplementary Note 10. The semiconductor device (A10) according to Appendix 9, further comprising a first signal wiring (21) located on the opposite side of the heat dissipation layer with the insulating layer sandwiched therebetween, wherein the first signal terminal and the first control electrode are each electrically connected to the first signal wiring, and wherein the first signal wiring overlaps the heat dissipation layer as viewed in the first direction. Appendix 11. The semiconductor device (A10) according to Appendix 10, further comprising a second signal terminal (45), wherein the second signal terminal is electrically connected to the second electrode. Appendix 12. The semiconductor device (A10) according to Appendix 11, wherein each of the first signal terminal and the second signal terminal includes a portion protruding in the first direction from the second surface.Appendix 13. The semiconductor device (A10) according to Appendix 11 or 12, further comprising a first relay wiring (28) located on the opposite side of the heat dissipation layer with the insulating layer sandwiched therebetween, the first control electrode being located on the same side as the second electrode in the first direction, the first control electrode being conductively joined to the first relay wiring, the first relay wiring being conductively connected to the first signal wiring, and the first relay wiring overlapping the heat dissipation layer as viewed in the first direction. Appendix 14. The semiconductor device (A10) according to Appendix 13, further comprising a second signal wiring (22) and a second relay wiring (29), each located on the opposite side of the heat dissipation layer with the insulating layer sandwiched therebetween, the second electrode being conductively joined to the second relay wiring, and each of the second signal terminal and the second relay wiring being conductively connected to the second signal wiring. Appendix 15. The semiconductor device (A20) according to Appendix 13, further comprising a second signal wiring (22) and a second relay wiring (29), each located on the opposite side of the heat dissipation layer with the insulating layer sandwiched therebetween, the second electrode being conductively joined to the second relay wiring, and each of the second signal terminal and the second relay wiring being conductively connected to the second signal wiring. Supplementary Note 16. The semiconductor device (A30) according to Supplementary Note 11 or 12, wherein the first control electrode is located on the same side as the first electrode in the first direction, the first semiconductor element has a body (315) including the first electrode, a first pad (315A) and a second pad (315B), and a first rewiring (316) electrically connected to the second pad, the polarity of the first electrode and the polarity of the first pad are different from each other, the first pad and the second pad are located on the opposite side to the first electrode in the first direction, the second electrode is electrically connected to the first pad, and the first control electrode is electrically connected to the first rewiring. Supplementary Note 17. The semiconductor device (A30) described in Appendix 16 further includes a second signal wiring (22) located on the opposite side of the heat dissipation layer with the insulating layer sandwiched therebetween, the second signal terminal being electrically connected to the second signal wiring, the first semiconductor element having a first detection electrode (314) electrically connected to the second signal wiring and a second rewiring (317) electrically connected to the first detection electrode, the first detection electrode being located on the same side as the first electrode in the first direction, and the second electrode being electrically connected to the second rewiring.Appendix 18. The semiconductor device (A40) according to Appendix 11 or 12, wherein the sealing resin includes a first layer (601) having the first surface and a second layer (602) having the second surface, the second layer being laminated on the first layer, and each of the first inner portion and the second inner portion being covered by the first layer. Appendix 19. The semiconductor device (A40) according to Appendix 18, wherein the dimension in the first direction of the second layer is larger than the dimension in the first direction of the insulating layer. Appendix 20. An inverter system (B) comprising: a plurality of semiconductor devices (A10), each having the same components as the semiconductor device according to Appendix 11; a motor (89) conducting to the conductive layer of each of the plurality of semiconductor devices; and a drive circuit (83) conducting to the first signal terminal and the second signal terminal of each of the plurality of semiconductor devices. Appendix 21. The semiconductor device (A10) according to Appendix 12, wherein the first power terminal has a first outer part (412) connected to the first inner part, the second power terminal has a second outer part (422) connected to the second inner part, the first inner part and the second inner part each protrude from the sealing resin, and the first outer part and the second outer part are adjacent to each other in a direction perpendicular to the first direction. Appendix 22. The semiconductor device according to Appendix 21 (A10), wherein the first signal wiring and the second signal wiring each overlap the heat dissipation layer when viewed in the first direction. Appendix 23. The semiconductor device (A10) according to Appendix 21, further comprising a third power terminal (43) electrically connected to the conductive layer, and a portion of the third power terminal protrudes from the sealing resin. Appendix 24. The semiconductor device (A10) according to Supplementary Note 23, wherein the third power terminal is located on the opposite side of the first outer part and the second outer part with respect to the first semiconductor element and the second semiconductor element in a direction perpendicular to the first direction.Supplementary Note 25. The semiconductor device (A20) according to Supplementary Note 15, further comprising a wire (54) conductively bonded to the second signal terminal and the conductive layer.Supplementary Note 26. The semiconductor device (A20) according to Supplementary Note 25, wherein both sides of the first relay wiring face the conductive layer in a direction perpendicular to the first direction.

[0101] A10 to A40, A41: semiconductor device B: inverter system 11: insulating layer 111: periphery 12: conductive layer 121: mounting surface 13: heat dissipation layer 21 to 24: first signal wiring to fourth signal wiring 28, 29: first relay wiring, second relay wiring 31: first semiconductor element 311, 312: first electrode, second electrode 313: first control electrode 314: first detection electrode 315: main body 315A, 315B: first pad, second pad 316, 317: first rewiring, second rewiring 318: protective layer 319: covering layer 32: second semiconductor element 321, 322: third electrode, fourth electrode 323: second control electrode 39: conductive bonding layer 41: first power terminal 411: first inner part 412: First outer part 42: Second power terminal 421: Second inner part 422: Second outer part 43: Third power terminal 44-47: First to fourth signal terminals 51-58: First to eighth wires 60: Sealing resin 61, 62: First surface, second surface 63-66: First to fourth side surfaces 80: Wiring board 81: Control circuit 82: Drive circuit 82A, 82B: First drive circuit, second drive circuit 88: DC power supply 89: Motor C1, C2, C3: First parasitic capacitance, second parasitic capacitance, third parasitic capacitance d1, d2: Dimensions z, x, y: First direction, second direction, third direction

Claims

1. A semiconductor device comprising: an insulating layer; a conductive layer located on one side of the insulating layer in a first direction; a heat dissipation layer located on the opposite side of the conductive layer with the insulating layer in between; a first semiconductor element having a first electrode and a second electrode and located on the opposite side of the insulating layer with the conductive layer in between; and a second semiconductor element having a third electrode and a fourth electrode and located on the opposite side of the insulating layer with the conductive layer in between, wherein the second electrode is located on the opposite side of the first electrode in the first direction; the fourth electrode is located on the opposite side of the third electrode in the first direction; the polarity of the second electrode and the polarity of the third electrode are mutually opposite; each of the second electrode and the third electrode is conductively joined to the conductive layer; and the conductive layer overlaps the heat dissipation layer as viewed in the first direction.

2. The semiconductor device according to claim 1, wherein each of said conductive layer and said heat dissipation layer is bonded to said insulating layer.

3. The semiconductor device according to claim 2, further comprising a sealing resin covering the first semiconductor element and the second semiconductor element, the sealing resin having a first surface facing one side of the first direction, and the heat dissipation layer being exposed from the first surface.

4. The semiconductor device described in claim 3, further comprising a first power terminal electrically connected to the first electrode, the first power terminal having a first inner portion covered with the sealing resin, the sealing resin having a second surface facing opposite the first surface in the first direction, and the dimension in the first direction of the portion of the sealing resin sandwiched between the first inner portion and the second surface being greater than the dimension in the first direction of the insulating layer.

5. The semiconductor device according to claim 4, wherein the first inner portion overlaps the first electrode when viewed in the first direction.

6. The semiconductor device described in claim 5, further comprising a second power terminal electrically connected to the fourth electrode, the second power terminal having a second inner portion covered with the sealing resin, and the dimension in the first direction of the portion of the sealing resin sandwiched between the second inner portion and the second surface being greater than the dimension in the first direction of the insulating layer.

7. The semiconductor device according to claim 6, wherein the second inner portion overlaps the fourth electrode when viewed in the first direction.

8. The semiconductor device according to claim 7, comprising: a first parasitic capacitance in which the conductive layer and the heat dissipation layer are conductor layers and the insulating layer is a dielectric layer; a second parasitic capacitance in which the first inner portion is one conductor layer and the sealing resin including the second surface is a dielectric layer; and a third parasitic capacitance in which the second inner portion is one conductor layer and the sealing resin including the second surface is a dielectric layer, wherein each of the second parasitic capacitance and the third parasitic capacitance is 50% or less of the first parasitic capacitance.

9. The semiconductor device according to claim 7, further comprising a first signal terminal, the first semiconductor element having a first control electrode, and the first signal terminal being electrically connected to the first control electrode.

10. The semiconductor device according to claim 9, further comprising a first signal wiring located on the opposite side of the heat dissipation layer with the insulating layer sandwiched therebetween, wherein the first signal terminal and the first control electrode are each electrically connected to the first signal wiring, and the first signal wiring overlaps the heat dissipation layer when viewed in the first direction.

11. The semiconductor device according to claim 10, further comprising a second signal terminal, said second signal terminal being electrically connected to said second electrode.

12. The semiconductor device according to claim 11, wherein each of the first signal terminal and the second signal terminal includes a portion that protrudes in the first direction from the second surface.

13. The semiconductor device described in claim 11 or 12, further comprising a first relay wiring located on the opposite side of the heat dissipation layer with the insulating layer sandwiched therebetween, wherein the first control electrode is located on the same side as the second electrode in the first direction, the first control electrode is conductively joined to the first relay wiring, the first relay wiring is electrically connected to the first signal wiring, and when viewed in the first direction, the first relay wiring overlaps the heat dissipation layer.

14. The semiconductor device according to claim 13, further comprising a second signal wiring and a second relay wiring, each of which is located on the opposite side of the heat dissipation layer with the insulating layer sandwiched therebetween, the second electrode being conductively joined to the second relay wiring, and each of the second signal terminal and the second relay wiring being electrically connected to the second signal wiring.

15. The semiconductor device according to claim 13, wherein said second signal terminal is electrically connected to said second electrode via said conductive layer.

16. The semiconductor device described in claim 11 or 12, wherein the first control electrode is located on the same side as the first electrode in the first direction, the first semiconductor element has a body including the first electrode, a first pad, and a second pad, and a first rewiring electrically connected to the second pad, the polarity of the first electrode and the polarity of the first pad are different from each other, the first pad and the second pad are located on the opposite side to the first electrode in the first direction, the second electrode is electrically connected to the first pad, and the first control electrode is electrically connected to the first rewiring.

17. The semiconductor device described in claim 16, further comprising a second signal wiring located on the opposite side of the heat dissipation layer with the insulating layer sandwiched therebetween, wherein the second signal terminal is electrically connected to the second signal wiring, the first semiconductor element has a first detection electrode that is electrically connected to the second signal wiring and a second rewiring that is electrically connected to the first detection electrode, the first detection electrode is located on the same side as the first electrode in the first direction, and the second electrode is electrically connected to the second rewiring.

18. The semiconductor device described in claim 11 or 12, wherein the sealing resin includes a first layer having the first surface and a second layer having the second surface, the second layer being laminated on the first layer, and each of the first inner portion and the second inner portion being covered by the first layer.

19. The semiconductor device according to claim 18, wherein the dimension of the second layer in the first direction is greater than the dimension of the insulating layer in the first direction.

20. An inverter system comprising: a plurality of semiconductor devices each having the same components as the semiconductor device recited in claim 11; a motor connected to the conductive layer of each of the plurality of semiconductor devices; and a drive circuit connected to the first signal terminal and the second signal terminal of each of the plurality of semiconductor devices.

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