Semiconductor device

Abstract

This semiconductor device includes a semiconductor layer, an insulating film, and a first electrode. The semiconductor layer has an element region and a terminal region. The insulating film is formed on a first main surface of the semiconductor layer across the element region and the terminal region. The first electrode is formed on part of the insulating film. The semiconductor layer includes a semiconductor region of a first conductivity type and a RESURF layer of a second conductivity type. The first electrode has an outer peripheral portion including the outer peripheral end that is a terminal-region-side end portion. The RESURF layer includes an intermediate region, an inner region formed continuously from the intermediate region to the inner side, and an outer region formed continuously from the intermediate region to the outer side. The intermediate region is positioned below the outer peripheral portion of the first electrode and is partially thinner.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Japanese Patent Application Laid-Open No. 2003-144222 discloses a technique for improving the breakdown voltage performance of a semiconductor device by providing a resurf layer in a termination region located around an element region in which an element structure is formed.

[0003] International Publication No. 2018 / 034127

[0004] [Summary] In semiconductor devices having a resurf layer, it is desirable to further improve the breakdown voltage performance of the devices.

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor layer having an element region in which an element structure is formed and a termination region located around the element region, an insulating film formed on a first main surface of the semiconductor layer spanning the element region and the termination region, and a first electrode formed on a portion of the insulating film, wherein the semiconductor layer includes a semiconductor region of a first conductivity type and a resurf layer of a second conductivity type, the first electrode having an outer peripheral portion including an outer peripheral end which is the end portion on the termination region side, and the resurf layer includes an intermediate region located below the outer peripheral portion of the first electrode and having a partially thinner thickness, an inner region formed continuously inward from the intermediate region, and an outer region formed continuously outward from the intermediate region.

[0006] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor layer having an element region in which an element structure is formed and a termination region located around the element region, an insulating film formed on a first main surface of the semiconductor layer spanning the element region and the termination region, and a first electrode formed on a portion of the insulating film, wherein the semiconductor layer includes a semiconductor region of a first conductivity type formed on the first main surface and a resurf layer of a second conductivity type, the first electrode having an outer peripheral portion including an outer peripheral end which is the end on the termination region side, and the resurf layer includes an inner region located on the element region side and an outer region located on the termination region side and surrounding the inner region, and the inner region and the outer region are spaced apart below the outer peripheral portion of the first electrode.

[0007] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view taken along line 2-2 of FIG. 1. FIG. 3 is a cross-sectional view taken along line 3-3 of FIG. 1. FIG. 4 is a partially enlarged view of the periphery of a resurf layer, schematically illustrating a first resurf structure. FIG. 5 is a partially enlarged view of the periphery of a resurf layer, schematically illustrating a second resurf structure. FIG. 6(a) is a partially enlarged view of the periphery of the resurf layer of a control example, and FIG. 6(b) is a schematic diagram illustrating simulation results for the control example. FIG. 7(a) is a partially enlarged view of the periphery of the resurf layer of Test Example 1, and FIG. 7(b) is a schematic diagram illustrating simulation results for Test Example 1. FIG. 8(a) is a partially enlarged view of the periphery of the resurf layer of Test Example 3, and FIG. 8(b) is a schematic diagram illustrating simulation results for Test Example 3. FIG. 9(a) is a partially enlarged view of the periphery of the resurf layer of Test Example 4, and FIG. 9(b) is a schematic diagram illustrating simulation results for Test Example 4. FIG. 10A is a partially enlarged view of the vicinity of the RESURF layer in Test Example 5, and FIG. 10B is a schematic diagram showing the simulation results of Test Example 5.

[0008] DETAILED DESCRIPTION Hereinafter, embodiments of a semiconductor device according to the present disclosure will be described with reference to the accompanying drawings. For simplicity and clarity of illustration and description, the components shown in the drawings are not necessarily drawn to scale. For simplicity and clarity of illustration, cross-sectional views may not include hatching. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be construed as limiting the present disclosure.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] 1 is a schematic plan view of an exemplary semiconductor device 10 according to one embodiment. The semiconductor device 10 includes a transistor 20. The transistor 20 is an insulated gate bipolar transistor (IGBT). The semiconductor device 10 is used, for example, as a switching element in an in-vehicle inverter device. In this case, a current of, for example, 5 A or more and 1000 A or less flows through the semiconductor device 10.

[0011] As shown in FIG. 1, the semiconductor device 10 is, for example, a rectangular flat plate. The semiconductor device 10 has a top surface 10s, a back surface 10r (see FIG. 2) located on the opposite side of the top surface 10s, and four side surfaces 10a to 10d formed between the top surface 10s and the back surface 10r. The side surfaces 10a to 10d are, for example, surfaces connecting the top surface 10s and the back surface 10r, and are perpendicular to both the top surface 10s and the back surface 10r. The top surface 10s is, for example, rectangular.

[0012] In the following description, the direction in which the device top surface 10s and device back surface 10r face is referred to as the "z direction." The z direction can also be said to be the height direction of the semiconductor device 10. Two mutually orthogonal directions perpendicular to the z direction are referred to as the "x direction" and "y direction." In this embodiment, the device side surfaces 10a and 10b constitute both end faces of the semiconductor device 10 in the x direction, and the device side surfaces 10c and 10d constitute both end faces of the semiconductor device 10 in the y direction. As used herein, the term "plan view" refers to viewing the semiconductor device 10 from above along the z direction, unless explicitly stated otherwise. Furthermore, plan view refers to viewing in the thickness direction of the semiconductor layer 30, which will be described later.

[0013] In a plan view, the semiconductor device 10 includes an element region A located in the central portion of the semiconductor device 10 and a termination region B located on the outer periphery of the semiconductor device 10. The element region A is a region in which elements such as the transistor 20 are formed. The termination region B is a region in which elements such as the transistor 20 are not formed. The termination region B is a region that surrounds the element region A in a plan view, and extends in a band shape along the periphery of the element region A. The termination region B is annular in shape that surrounds the element region A in a plan view.

[0014] A first electrode 11 and a second electrode 12 electrically connected to the transistor 20 are arranged on the device top surface 10s of the semiconductor device 10. The first electrode 11 is an electrode pad electrically connected to a base contact region 37 (described later) of the transistor 20. The second electrode 12 is an electrode pad electrically connected to an electrode material in a gate trench 23A (described later) of the transistor 20. Each of the first electrode 11 and the second electrode 12 may be made of any conductive material including, for example, at least one of copper (Cu), aluminum (Al), an AlCu alloy, tungsten (W), titanium (Ti), and titanium nitride (TiN).

[0015] As shown in Fig. 1, a protective insulating film 14 is provided on the device top surface 10s. The protective insulating film 14 is an organic protective film that protects the semiconductor device 10 and is formed of a material containing polyimide (PI), for example. The protective insulating film 14 is formed so as to expose a portion of each of the first electrode 11 and the second electrode 12 independently. Note that the protective insulating film 14 is not shown in Fig. 2 and subsequent figures.

[0016] [Transistor Configuration] FIG. 2 is a cross-sectional view taken along line 2-2 of FIG. 1, showing an example of the cross-sectional structure of the semiconductor device 10 in the element region A. As shown in FIG.

[0017] The semiconductor device 10 includes a semiconductor layer 30. The semiconductor layer 30 is, for example, － The semiconductor layer 30 is made of a material containing silicon (Si) and has a thickness of, for example, 50 μm or more and 200 μm or less.

[0018] The semiconductor layer 30 has a first major surface 30s and a second major surface 30r that face in opposite directions in the z direction. The semiconductor layer 30 has p ＋ a n-type collector layer 31, an n-type buffer layer 32, and an n-type － The semiconductor device 10 has a structure in which a semiconductor region 33 (drift layer) of a type is stacked on the second main surface 30r. A collector electrode 27 is formed on the second main surface 30r. The collector electrode 27 is formed over substantially the entire second main surface 30r. The surface of the collector electrode 27 opposite to the collector layer 31 constitutes the device back surface 10r of the semiconductor device 10.

[0019] The p-type dopant of the collector layer 31 may be, for example, boron (B) or aluminum (Al). The dopant concentration of the collector layer 31 is, for example, 1×10 １５ cm －３ 2 x 10 or more １９ cm －３ The following is the result.

[0020] The n-type dopant for the buffer layer 32 and the semiconductor region 33 may be, for example, N (nitrogen), P (phosphorus), or As (arsenic). The dopant concentration of the buffer layer 32 is, for example, 1×10 １５ cm －３ 5x10 or more １７ cm －３ The dopant concentration of the semiconductor region 33 is lower than that of the buffer layer 32, for example, 1×10 １３ cm －３ 5x10 or more １４ cm －３ The following is the result.

[0021] A p-type base region 34 is formed on the upper surface of the semiconductor region 33. The base region 34 is formed over substantially the entire first major surface 30s in the element region A. The dopant concentration of the base region 34 is, for example, 1×10 １６ cm －３ 1x10 or more １８ cm －３ The thickness of the base region 34 is, for example, not less than 1.0 μm and not more than 3.0 μm.

[0022] A plurality of trenches 35 are arranged side by side on the first main surface 30s in the element region A. Each trench 35 extends, for example, along the x direction and is spaced apart from one another in the y direction. The spacing between adjacent trenches 35 in the y direction (the center-to-center distance between the trenches 35) is, for example, 1.5 μm or more and 7.0 μm or less. The width of each trench 35 (the dimension of the trench 35 in the y direction) is, for example, 0.5 μm or more and 3.0 μm or less. Each trench 35 penetrates the base region 34 in the z direction and extends partway into the semiconductor region 33.

[0023] The upper surface (first major surface 30s) of the base region 34 in the element region A has n ＋ In the base region 34, emitter regions 36 are formed. The emitter regions 36 are arranged on both sides of the trench 35 in the y direction. In other words, it can be said that the emitter regions 36 are provided on both sides of the trench 35 in the arrangement direction of the trenches 35 in the base region 34. Therefore, two emitter regions 36 are arranged with a gap between them in the y direction between adjacent trenches 35 in the y direction. The depth of each emitter region 36 is, for example, 0.2 μm or more and 0.6 μm or less. The dopant concentration of each emitter region 36 is higher than that of the base region 34, for example, 1×10 １９ cm －３ 5x10 or more ２０ cm －３ The following is the result.

[0024] The upper surface (first major surface 30s) of the base region 34 in the element region A has p ＋ A base contact region 37 of a type is formed. The base contact region 37 is provided at a position adjacent to the emitter region 36 in the x direction. In other words, the base contact region 37 is provided in the y direction between two emitter regions 36 provided between the y direction of adjacent trenches 35 in the y direction. Each base contact region 37 may be formed deeper than the emitter region 36. The depth of each base contact region 37 is, for example, 0.2 μm or more and 1.6 μm or less. The dopant concentration of each base contact region 37 is higher than that of the base region 34, for example, 5×10 １８ cm－３ 1x10 or more ２０ cm －３ The following is the result.

[0025] A first insulating layer 38 is integrally formed on both the inner surface of each trench 35 and the first main surface 30s. The first insulating layer 38 is made of, for example, silicon oxide (SiO ２ The thickness of the first insulating layer 38 is, for example, not less than 1100 Å and not more than 1300 Å.

[0026] An electrode material containing, for example, polysilicon is filled into each trench 35 via the first insulating layer 38. The electrode material filled into each trench 35 is electrically connected to either the first electrode 11 or the second electrode 12. In other words, the electrode material filled into each trench 35 forms a gate trench 23A and an emitter trench 21A. In this embodiment, the gate trenches 23A and the emitter trenches 21A are alternately provided in the arrangement direction of the multiple trenches 35. In this embodiment, both the gate trenches 23A and the emitter trenches 21A are filled up to the opening end of each trench 35.

[0027] A second insulating layer 39 is formed on the first insulating layer 38 provided on the first main surface 30s. The second insulating layer 39 is made of, for example, SiO ２ The first electrode 11 is formed on the second insulating layer 39. In other words, the second insulating layer 39 is an interlayer insulating film that fills the space between the first electrode 11 and the gate trench 23A. The thickness of the second insulating layer 39 is not less than 3000 Å and not more than 15000 Å.

[0028] The first insulating layer 38 and the second insulating layer 39 are provided with a plurality of contact holes 39a that penetrate both the first insulating layer 38 and the second insulating layer 39 in the z-direction. The contact holes 39a are provided at positions that overlap the base contact regions 37 in a plan view. The first electrode 11 is connected to the base contact regions 37 via the contact holes 39a.

[0029] There is no particular limitation on the gate wiring for electrically connecting the electrode material embedded in the gate trench 23A to the second electrode 12. An example of the gate wiring is wiring made of the electrode material that extends from the electrode material embedded in the gate trench 23A. Alternatively, the gate wiring may be metal wiring such as a gate finger made of a metal or the like that is formed on the second insulating layer 39.

[0030] 3 is a cross-sectional view taken along line 3-3 in FIG. 1, and shows the cross-sectional structure of the semiconductor region 33 near the first main surface 30s from the outer periphery of the element region A to the termination region B. Hereinafter, the element region A side may be referred to as the inside, and the termination region B side may be referred to as the outside.

[0031] In the peripheral portion of the element region A, an insulating film 40 is formed on the first main surface 30s of the semiconductor region 33, spanning both the element region A and the termination region B. The insulating film 40 is made of silicon oxide (SiO ２ )

[0032] In the peripheral portion of the element region A, the first electrode 11 has an overlapping portion 41 that rides up onto the insulating film 40. The end of the overlapping portion 41 is a peripheral end 41A that is the end of the first electrode 11 on the termination region B side.

[0033] In the peripheral portion of the element region A, a reduced surface field (RESURF) layer 42 is formed on the first main surface 30s of the semiconductor region 33. The RESURF layer 42 is formed of a p-type impurity region. The RESURF layer 42 is formed in a ring shape along the peripheral edge 41A of the first electrode 11 and is formed to straddle the first electrode 11 and the insulating film 40. The RESURF layer 42 is in contact with the first electrode 11 at a portion located on the element region A side and in contact with the insulating film 40 at a portion located on the termination region B side. The RESURF layer 42 has an end 42A located on the termination region B side. The end 42A of the RESURF layer 42 is formed at a position spaced apart from the device side surface 10c. Therefore, a peripheral region where the RESURF layer 42 is not formed is provided on the peripheral side (device side surface) of the termination region B.

[0034] [Detailed Structure of the RESURF Layer] The RESURF layer 42 has either a first RESURF structure 43A or a second RESURF structure 43B. The first RESURF structure 43A is a structure in which the thickness of the RESURF layer 42 is locally thin in a region located directly below the first electrode 11. The second RESURF structure 43B is a structure in which two RESURF layers 42 are spaced apart in a region located directly below the first electrode 11.

[0035] (First RESURF Structure) Fig. 4 is an enlarged view of a portion of the RESURF layer 42 located directly below the first electrode 11 (the portion surrounded by the dashed line in Fig. 3). Fig. 4 shows a simplified view of the first RESURF structure 43A. The first RESURF structure 43A includes an intermediate region 44, an inner region 45, and an outer region 46.

[0036] The intermediate region 44 is located below the outer peripheral portion 11A of the first electrode 11 and is a region with a locally thin thickness. The intermediate region 44 is a region in which impurity diffusion in the direction from the first major surface 30s of the semiconductor region 33 toward the second major surface 30r is locally small. The intermediate region 44 can also be said to be a region with a locally low impurity concentration. Therefore, the impurity concentration of the intermediate region 44 is lower than that of the inner region 45 and the outer region 46. The outer peripheral portion 11A of the first electrode 11 is a region having a predetermined width from the outer peripheral end 41A of the first electrode 11 toward the element region A. The width is, for example, 1,000 nm or more and 30,000 nm or less.

[0037] The inner region 45 is a region formed continuously inward from the intermediate region 44. The outer region 46 is a region formed continuously outward from the intermediate region 44. The inner region 45 and the outer region 46 have the same thickness.

[0038] The thickness T1 of the inner region 45 and the outer region 46 is, for example, 2000 nm or more, preferably 4000 nm or more, and more preferably 5000 nm or more. The thickness T1 is, for example, 10000 nm or less, preferably 9000 nm or less, and more preferably 8500 nm or less.

[0039] The thickness of the inner region 45 may vary from region to region. An example of an inner region 45 with a shape that varies in thickness is a shape in which the thickness gradually decreases toward the center of the intermediate region 44, i.e., as the distance from the inner region 45 and the outer region 46 increases. Alternatively, the thickness of the inner region 45 may be constant.

[0040] The thickness of the thinnest portion 44A of the intermediate region 44 is defined as thickness T2. The ratio of thickness T2 to thickness T1 of the inner region 45 (T2 / T1) is, for example, 1 / 10 to 4 / 5, preferably 1 / 2 or less, and more preferably 1 / 4 or less. Furthermore, thickness T2 is, for example, 1000 nm to 3000 nm.

[0041] In one example of the first RESURF structure, the thickness T1 of the inner region 45 and the outer region 46 is thicker than the insulating film 40, and the thickness T2 of the thinnest portion 44A of the intermediate region 44 is thinner than the insulating film 40. The thickness of the insulating film 40 is, for example, not less than 1000 nm and not more than 2000 nm.

[0042] The thinnest portion 44A in the intermediate region 44 is located inside the outer peripheral edge 41A of the first electrode 11. The distance L1 from the outer peripheral edge 41A of the first electrode 11 to the thinnest portion 44A in the intermediate region 44 is, for example, 1 μm or more and 15 μm or less. The distance L1 is preferably 3 μm or more, and more preferably 5 μm or more. The distance L1 is preferably 10 μm or less, and more preferably 8 μm or less.

[0043] The width H1 of the intermediate region 44 is, for example, 10 μm or more, preferably 20 μm or more, and for example, 30 μm or less, preferably 25 μm or less.

[0044] The first RESURF structure 43A can be formed by using an ion implantation mask having a predetermined pattern when forming the RESURF layer 42. More specifically, the RESURF layer 42 is formed by performing a process of introducing p-type impurities into the first main surface 30s of the semiconductor region 33. When forming the first RESURF structure, an ion implantation mask is formed on the first main surface 30s of the semiconductor region 33 before the RESURF layer 42 is formed.

[0045] The ion implantation mask is formed as a pattern along the portion that will become the intermediate region 44 of the first RESURF structure. The pattern width of the ion implantation mask is set to be the same as or larger than the width H1 of the intermediate region 44. The pattern width of the ion implantation mask is, for example, not less than 5 μm and not more than 50 μm.

[0046] Next, p-type impurities are introduced into the semiconductor region 33 from both sides of the ion implantation mask on the first main surface 30s by ion implantation using the ion implantation mask. At this time, in a plan view, the diffusion regions where the p-type impurities are diffused in the portions where the ion implantation mask is not formed become the inner region 45 and the outer region 46. Then, below the portion where the ion implantation mask is formed, the diffusion regions where the p-type impurities are diffused laterally from both the inner region 45 and the outer region 46 are connected to form the intermediate region 44. This forms the first RESURF structure 43A having the intermediate region 44.

[0047] (Second RESURF Structure) Figure 5 is an enlarged view of a portion of the RESURF layer 42 located directly below the first electrode 11 (the portion surrounded by the dashed line in Figure 3). Note that Figure 5 shows a simplified view of the second RESURF structure 43B. The second RESURF structure 43B includes an inner region 47 located on the element region A side and an outer region 48 located on the termination region B side and surrounding the inner region 47. The inner region 47 and the outer region 48 are spaced apart below the outer peripheral portion 11A of the first electrode 11. The outer peripheral portion 11A of the first electrode 11 is similar to the outer peripheral portion of the first RESURF structure.

[0048] The inner region 47 includes an outer end 47A, which is an end located on the termination region B side. The outer end 47A of the inner region 47 is located directly below the first electrode 11. In other words, the outer end 47A of the inner region 47 is located closer to the element region A than the outer circumferential end 41A of the first electrode 11. The distance L2 from the outer circumferential end 41A of the first electrode 11 to the outer end 47A of the inner region 47 is, for example, 15 μm or more and 75 μm or less. The distance L2 is preferably 25 μm or more, and more preferably 30 μm or more. The distance L2 is preferably 60 μm or less, and more preferably 40 μm or less.

[0049] The outer region 48 includes an inner end 48A, which is an end located on the element region A side. The inner end 48A of the outer region 48 is located directly below the first electrode 11. In other words, the inner end 48A of the outer region 48 is located closer to the element region A than the outer peripheral end 41A of the first electrode 11. The distance L3 from the outer peripheral end 41A of the first electrode 11 to the inner end 48A of the outer region 48 is, for example, 1 μm or more and 15 μm or less. The distance L3 is preferably 3 μm or more, and more preferably 5 μm or more. The distance L3 is preferably 12 μm or less, and more preferably 10 μm or less.

[0050] As described above, the inner region 47 and the outer region 48 are spaced apart below the outer peripheral portion 11A of the first electrode 11. The separation width between the inner region 47 and the outer region 48, i.e., the distance L4 between the outer end 47A of the inner region 47 and the inner end 48A of the outer region 48, is, for example, 15 μm or more and 60 μm or less. The distance L4 is preferably 20 μm or more, and more preferably 25 μm or more. The distance L4 is preferably 50 μm or less, and more preferably 30 μm or less.

[0051] In the second RESURF structure 43B, the inner region 47 and the outer region 48 have the same thickness. The thicknesses of the inner region 47 and the outer region 48 are similar to the thickness T1 of the inner region 45 and the outer region 46 of the first RESURF structure 43A.

[0052] Like the first RESURF structure 43A, the second RESURF structure 43B can be formed by using an ion implantation mask having a predetermined pattern. Here, when forming the second RESURF structure 43B, the pattern width of the ion implantation mask is made larger than that when forming the first RESURF structure 43A. In this case, too, when p-type impurities are introduced into the semiconductor region 33 from both sides of the ion implantation mask on the first main surface 30s, the diffusion regions where the p-type impurities are diffused in the portions where the ion implantation mask is not formed become the inner region 47 and the outer region 48. Here, if the pattern width of the ion implantation mask is large, the diffusion stops in a state where the diffusion regions where the p-type impurities are diffused laterally from both the inner region 45 and the outer region 46 below the portions where the ion implantation mask is formed, without connecting and remaining separated. This results in the formation of the second RESURF structure 43B having the inner region 45 and the outer region 46 that are separated from each other.

[0053] [Operation] Next, the operation of the semiconductor device 10 according to the embodiment will be described. In the semiconductor device 10, the resurf layer 42 has either a first resurf structure 43A or a second resurf structure 43B. The first resurf structure 43A includes an intermediate region 44 located below the outer peripheral portion 11A of the first electrode 11 and having a partially reduced thickness, an inner region 45 extending inward from the intermediate region 44, and an outer region 46 extending outward from the intermediate region 44. The second resurf structure 43B includes an inner region 47 located on the element region A side and an outer region 48 located on the termination region B side and surrounding the inner region 47. The inner region 47 and the outer region 48 are spaced apart below the outer peripheral portion 11A of the first electrode 11. By providing the resurf layer 42 with the first resurf structure 43A or the second resurf structure 43B, the breakdown voltage performance of the semiconductor device 10 is improved.

[0054] The breakdown voltage performance when the first RESURF structure 43A or the second RESURF structure 43B was formed was determined by simulation. The results are shown in Tables 1 and 2. The control example shown in Table 1 is an example in which the entire RESURF layer 42 is formed with a constant thickness (8000 nm), as shown in FIG. 6( a). Comparative Example 1 is an example in which a field limiting ring (FLR) structure surrounding the outer periphery of the RESURF layer 42 is provided in addition to the control example. Test Examples 1 to 3 are examples in which the first RESURF structure 43A is provided in the RESURF layer 42 of the control example. Test Examples 1 to 3 differ from each other in the width H1 of the intermediate region 44. Test Examples 4 to 9 shown in Table 2 are examples in which the second RESURF structure 43B is provided in the RESURF layer 42 of the control example. Test Examples 4 to 9 differ from each other in the separation width (distance L4) between the inner region 47 and the outer region 48.

[0055] The initial breakdown voltages shown in Tables 1 and 2 are obtained when the interface between the first main surface 30s of the semiconductor layer 30 and the insulating film 40 is 0 C / cm ２ The breakdown voltage is a value that indicates the dielectric breakdown voltage when a positive charge of 5 × 10 is placed on the interface. １１ C / cm ２ These values ​​are corrected so that the initial breakdown voltage of the control example is 100.

[0056]

[0057] As shown in Table 1, the initial withstand voltage of Comparative Example 1, which was provided with an FLR, was lower than that of the control example. In contrast, the initial withstand voltages of Test Examples 1 to 3, which were provided with the first RESURF structure 43A, were approximately the same as that of the control example and higher than that of Comparative Example 1. Furthermore, the positive charge withstand voltages of Test Examples 1 to 3 were higher than that of Comparative Example 1. In particular, the positive charge withstand voltages of Test Examples 2 and 3, in which the width H1 of the intermediate region 44 was increased, were higher. These results show that providing the first RESURF structure 43A has the effect of increasing the positive charge withstand voltage while maintaining the initial withstand voltage, and that this effect becomes more pronounced by increasing the width H1 of the intermediate region 44.

[0058] As shown in Table 2, the initial withstand voltages of Test Examples 4 to 9, which were provided with the second RESURF structure 43B, were equal to or greater than that of Comparative Example 1. It can be seen that the initial withstand voltages of Test Examples 4 to 9 tended to decrease as the separation width increased. Furthermore, the positive charge withstand voltages of Test Examples 4 to 9 were higher than that of Comparative Example 1. These results show that providing the second RESURF structure 43B has the effect of increasing the positive charge withstand voltage while maintaining the initial withstand voltage, and that this effect becomes more pronounced by reducing the separation width L4.

[0059] 6 to 10 (a) are schematic diagrams of the RESURF layers 42 of the control example and test examples 1, 3, 4, and 5. The diagrams of 6 to 10 (b) are schematic diagrams of the RESURF layers 42 of test examples 1, 3, 4, and 5, in which 5×10 １１ C / cm ２ 10 is a schematic diagram showing a simulation result of the impact ionization rate for each portion of the semiconductor layer 30 located near the outer circumferential edge 41A of the first electrode 11 when a charge of 1000 kJ / cm is placed thereon.

[0060] As shown in each of (b) of Figures 6 to 8, the provision of the first RESURF structure 43A reduces the region where the impact ionization rate is high. Similarly, as shown in each of (b) of Figures 6, 9, and 10, the provision of the second RESURF structure 43B reduces the region where the impact ionization rate is high. These results also show that the provision of the first RESURF structure 43A or the second RESURF structure 43B improves the breakdown voltage performance of the semiconductor device 10.

[0061] [Effects] The semiconductor device 10 of the embodiment provides the following effects. (1) The semiconductor device 10 includes a semiconductor layer 30 having an element region A in which an element structure is formed and a termination region B located around the element region A, an insulating film 40 formed on a first main surface 30s of the semiconductor layer 30 across the element region A and the termination region B, and a first electrode 11 formed on a portion of the insulating film 40. The semiconductor layer 30 includes an n-type semiconductor region 33 and a p-type resurf layer 42. The first electrode 11 has a peripheral portion that includes an outer peripheral edge 41A that is the end on the termination region B side.

[0062] The RESURF layer 42 has a first RESURF structure 43A. The first RESURF structure 43A includes an intermediate region 44 located below the outer peripheral portion 11A of the first electrode 11 and having a partially reduced thickness, an inner region 45 formed continuously from the intermediate region 44 to the inside, and an outer region 46 formed continuously from the intermediate region 44 to the outside. This configuration can improve the breakdown voltage performance of the semiconductor device 10.

[0063] (2) The semiconductor device 10 includes a semiconductor layer 30 having an element region A in which an element structure is formed and a termination region B located around the element region A, an insulating film 40 formed on a first main surface 30s of the semiconductor layer 30 across the element region A and the termination region B, and a first electrode 11 formed on a portion of the insulating film 40. The semiconductor layer 30 includes an n-type semiconductor region 33 and a p-type resurf layer 42. The first electrode 11 has a peripheral portion including a peripheral edge 41A that is the end on the termination region B side.

[0064] The resurf layer 42 has a second resurf structure 43B. The second resurf structure 43B includes an inner region 47 located on the element region A side and an outer region 48 located on the termination region B side and surrounding the inner region 47. The inner region 47 and the outer region 48 are spaced apart below the outer peripheral portion 11A of the first electrode 11. This configuration can improve the breakdown voltage performance of the semiconductor device 10.

[0065] (3) The width H1 of the intermediate region 44 is 20 μm or more and 25 μm or less. With this configuration, the effect of (1) above is more pronounced. (4) In the second RESURF structure 43B, the separation width L4 between the inner region 47 and the outer region 48 is 25 μm or more and 45 μm or less. With this configuration, a decrease in the initial breakdown voltage of the semiconductor device 10 can be suppressed compared to a configuration in which an FLR is provided.

[0066] (5) In the first RESURF structure 43A, the thinnest portion 44A of the intermediate region 44 is located inside the outer circumferential edge 41A of the first electrode 11. With this configuration, the effect of (1) above can be more significantly achieved.

[0067] [Modifications] The above embodiment can be modified as follows: The RESURF layer 42 may be provided with both the first RESURF structure 43A and the second RESURF structure 43B.

[0068] A breakdown voltage structure such as an FLR or an equipotential ring (EQR) may be provided in the peripheral region where the RESURF layer 42 is not formed. The first electrode 11 is not limited to a base electrode connected to the base contact region 37 via the contact hole 39a. For example, the first electrode 11 may be a field plate electrode formed on the first main surface 30s of the semiconductor layer 30 in the peripheral portion of the element region A and spaced apart from the base electrode. In this case, the potential of the field plate electrode serving as the first electrode 11 is not particularly limited and may be, for example, the base potential or the emitter potential.

[0069] In the above embodiment, an example has been described in which the "first conductivity type" is "n-type" and the "second conductivity type" is "p-type." However, a structure in which the "first conductivity type" is "p-type" and the "second conductivity type" is "n-type" may also be employed.

[0070] In the above embodiment, the semiconductor device 10 is embodied as an IGBT. However, the present invention is not limited to this. The semiconductor device 10 may be a reverse conducting IGBT, a SiC MOSFET (metal-oxide-semiconductor field-effect transistor), or a Si MOSFET.

[0071] One or more of the various examples described herein can be combined to the extent that they are not technically inconsistent. In this specification, the phrase "at least one of A and B" should be understood to mean "only A, or only B, or both A and B."

[0072] As used herein, the term "on" includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0073] Directional terms used herein, such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "front," "rear," "longitudinal," "lateral," "left," "right," "front," "rear," etc., depend on the particular orientation of the device being described and illustrated. Various alternative orientations are contemplated in this disclosure, and therefore these directional terms should not be construed narrowly.

[0074] For example, the Z-axis direction used in this specification does not necessarily have to be the vertical direction, and does not have to completely coincide with the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0075] [Notes] The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the notes are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each note should not be limited to the components indicated by the reference numerals.

[0076] [Supplementary Note 1] A semiconductor layer (30) having an element region (A) in which an element structure is formed, and a termination region (B) located around the element region (A), an insulating film (40) formed on a first main surface (30s) of the semiconductor layer (30) across the element region (A) and the termination region (B), and a first electrode (11) formed on a part of the insulating film (40), the semiconductor layer (30) including a semiconductor region (33) of a first conductivity type and a resurf layer (42) of a second conductivity type, the first electrode (11) having an outer circumferential portion including an outer circumferential end (41A) which is an end on the termination region (B) side, the resurf layer (42) including: an intermediate region (44) located below the outer circumferential portion of the first electrode (11) and partially thinner; and an inner region (45) formed continuously inward from the intermediate region (44), an outer region (46) formed continuously outward from the intermediate region (44).

[0077] [Supplementary Note 2] A semiconductor layer (30) having an element region (A) in which an element structure is formed, and a termination region (B) located around the element region (A), an insulating film (40) formed on a first main surface (30s) of the semiconductor layer (30) across the element region (A) and the termination region (B), and a first electrode (11) formed on a part of the insulating film (40), wherein the semiconductor layer (30) includes a semiconductor region (33) of a first conductivity type and a resurf layer (42) of a second conductivity type, the first electrode (11) having an outer peripheral portion including an outer peripheral end (41A) which is an end on the termination region (B) side, and the resurf layer (42) includes an inner region (47) located on the element region (A) side, and an outer region (48) located on the termination region (B) side and surrounding the inner region (47), The semiconductor device (10) comprises an inner region (47) and an outer region (48) spaced apart below the outer peripheral portion of the first electrode (11).

[0078] [Supplementary Note 3] The semiconductor device (10) according to Supplementary Note 1, wherein the width (H1) of the intermediate region (44) is 20 μm or more and 25 μm or less.

[0079] [Supplementary Note 4] The semiconductor device (10) according to Supplementary Note 2, wherein a separation width (L4) between the inner region (47) and the outer region (48) is 15 μm or more and 60 μm or less.

[0080] [Supplementary Note 5] The semiconductor device (10) according to Supplementary Note 1 or Supplementary Note 3, wherein the impurity concentration of the intermediate region (44) is lower than that of the inner region (45) and the outer region (46).

[0081] [Appendix 6] The semiconductor device (10) according to any one of Appendices 1, 3, and 5, wherein the portion (44A) of the intermediate region (44) that is thinnest in thickness is located inside the outer peripheral edge (41A) of the first electrode (11).

[0082] [Supplementary Note 7] The semiconductor device (10) according to Supplementary Note 2 or Supplementary Note 4, wherein an end (48A) of the outer region (48) facing the inner region (47) is located more inward than the outer peripheral edge (41A) of the first electrode (11).

[0083] [Appendix 8] The semiconductor device (10) according to any one of Appendices 1, 3, 5, and 6, wherein the thinnest portion (44A) of the intermediate region (44) is located in a range of 1 μm to 15 μm inward from the outer peripheral edge (41A) of the first electrode (11).

[0084] [Appendix 9] The semiconductor device (10) according to any one of Appendices 2, 4, and 7, wherein an end (48A) of the outer region (48) facing the inner region (47) is located in a range of 3 μm to 15 μm inward from the outer peripheral end (41A) of the first electrode (11).

[0085] [Appendix 10] The semiconductor device (10) according to any one of Appendices 1, 3, 5, 6, and 8, wherein a ratio (T2 / T1) of a thickness (T2) of the thinnest part (44A) of the intermediate region (44) to a thickness (T1) of the inner region (45) is 1 / 10 or more and 4 / 5 or less.

[0086] [Appendix 11] The semiconductor device (10) according to any one of Appendices 1, 3, 5, 6, 8, and 10, wherein a thickness of the inner region (45) and a thickness of the outer region (46) are greater than that of the insulating film (40), and a thickness (T2) of a portion (44A) of the intermediate region (44) having the thinnest thickness is thinner than that of the insulating film (40).

[0087] A...element region B...termination region H1...width L1 to L4...distances T1 to T2...thickness 10...semiconductor device 10a to 10d...side surface of device 11...first electrode 11A...periphery of first electrode 12...second electrode 14...protective insulating film 20...transistor 21A...emitter trench 23A...gate trench 27...collector electrode 30...semiconductor layer 30r...second main surface 30s...first main surface 31...collector layer 32...buffer layer 33...drift layer 34...base region 35...trench 36...emitter region 37...base contact region 38...first insulating layer 39...second insulating layer 39a...contact hole 40...insulating film 41...overlap portion 41A...periphery edge 42...resurf layer 42A...edge of resurf layer 43A... First resurf structure 43B... Second resurf structure 44... Intermediate region 44A... Thinnest part of intermediate region 45, 47... Inner regions 47A... Outer end of inner region 46, 48... Outer regions 48A... Inner end of outer region

Claims

1. A semiconductor device comprising: a semiconductor layer having an element region in which an element structure is formed, and a termination region located around the element region; an insulating film formed on a first main surface of the semiconductor layer spanning the element region and the termination region; and a first electrode formed on a portion of the insulating film, wherein the semiconductor layer comprises a semiconductor region of a first conductivity type and a resurf layer of a second conductivity type, the first electrode having a peripheral portion including a peripheral edge which is the end on the termination region side, and the resurf layer comprising: an intermediate region located below the peripheral portion of the first electrode and partially thinner, an inner region formed continuously inward from the intermediate region, and an outer region formed continuously outward from the intermediate region.

2. A semiconductor device comprising: a semiconductor layer having an element region in which an element structure is formed, and a termination region located around the element region; an insulating film formed on a first main surface of the semiconductor layer spanning the element region and the termination region; and a first electrode formed on a part of the insulating film, wherein the semiconductor layer comprises a semiconductor region of a first conductivity type formed on the first main surface, and a resurf layer of a second conductivity type, wherein the first electrode has a peripheral portion including a peripheral edge which is the end on the termination region side, and the resurf layer comprises: an inner region located on the element region side, and an outer region located on the termination region side and surrounding the inner region, and the inner region and the outer region are spaced apart below the peripheral portion of the first electrode.

3. The semiconductor device according to claim 1, wherein the width of said intermediate region is not less than 20 μm and not more than 25 μm.

4. The semiconductor device according to claim 2, wherein the separation width between said inner region and said outer region is 15 μm or more and 60 μm or less.

5. The semiconductor device according to claim 1 or 3, wherein the impurity concentration of said intermediate region is lower than that of said inner region and said outer region.

6. The semiconductor device according to any one of claims 1, 3 and 5, wherein the portion of said intermediate region that is thinnest is located inside said outer peripheral edge of said first electrode.

7. The semiconductor device according to claim 2 or 4, wherein an end of said outer region facing said inner region is located inside said outer peripheral edge of said first electrode.

8. The semiconductor device according to any one of claims 1, 3, 5 and 6, wherein the portion of said intermediate region that is thinnest is located within a range of 1 μm to 15 μm inward from said outer peripheral edge of said first electrode.

9. A semiconductor device according to any one of claims 2, 4 and 7, wherein the end of the outer region facing the inner region is located within a range of 1 μm to 15 μm inward from the outer peripheral edge of the first electrode.

10. The semiconductor device according to any one of claims 1, 3, 5, 6 and 8, wherein the ratio of the thickness of the thinnest part of said intermediate region to the thickness of said inner region is 1 / 10 or more and 4 / 5 or less.

11. A semiconductor device according to any one of claims 1, 3, 5, 6, 8 and 10, wherein the thickness of the inner region and the thickness of the outer region are greater than that of the insulating film, and the thickness of the thinnest part of the intermediate region is thinner than that of the insulating film.

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