Method for designing base graph of low-density parity-check code in communication system, said base graph, and encoding / decoding method and apparatus therefor

Abstract

The present disclosure relates to a method for designing a base graph of a low-density parity-check code in a communication system, said base graph, and an encoding / decoding method and apparatus therefor. A communication device for performing encoding by using an LDPC code in a communication system, according to an embodiment of the present disclosure, may: identify a base graph to be used among a first base graph and a second base graph of the LDPC code, on the basis of the length and a code rate of information to be transmitted; and when the identified base graph is the second base graph, identify a plurality of index values constituting a parity check matrix on the basis of the second base graph. The plurality of index values are identified on the basis of row indices and column indices of a matrix corresponding to the second base graph, and lifting set indices for lifting of the base graph, and index values corresponding to at least one column index mapped to a specific row index among the row indices may be further used for the encoding.

Description

Method for designing a base graph of a low-density parity check code in a communication system, the base graph, and an encoding / decoding method and device therefor

[0001] The present disclosure relates to a base graph design of a low-density parity-check (LDPC) code and an encoding / decoding technique therefor.

[0002] Looking back at the evolution of wireless communication over successive generations, technologies have primarily been developed for human-facing services such as voice, multimedia, and data. With the commercialization of the 5G (5th Generation) communication system, an explosive increase in connected devices is expected to be connected to communication networks. Examples of networked objects include vehicles, robots, drones, home appliances, displays, smart sensors installed in various infrastructures, construction equipment, and factory equipment. Mobile devices are also expected to evolve into diverse form factors, such as augmented reality glasses, virtual reality headsets, and holographic devices. In the 6G (6th Generation) era, efforts are being made to develop improved 6G communication systems to connect hundreds of billions of devices and objects and provide diverse services. For this reason, 6G communication systems are often referred to as "beyond 5G."

[0003] The 6G communication system, expected to be realized around 2030, will have a maximum transmission speed of terabytes (i.e., 1,000 gigabits) per second (bps) and a wireless latency of 100 microseconds (μsec). In other words, compared to 5G, the transmission speed in a 6G communication system will be 50 times faster and the wireless latency will be reduced to one-tenth.

[0004] To achieve these high data rates and ultra-low latency, 6G communication systems are being considered for implementation in the terahertz (THz) band (e.g., from 95 gigahertz (GHz) to 3 terahertz (THz)). Compared to the millimeter wave (mmWave) band introduced in 5G, the terahertz band is expected to have more severe path loss and atmospheric absorption, making it more important to develop technologies that can guarantee signal reach, or coverage. Key technologies to ensure coverage include Radio Frequency (RF) components, antennas, new waveforms that offer better coverage than Orthogonal Frequency Division Multiplexing (OFDM), beamforming, and multiple antenna transmission technologies such as massive Multiple-Input and Multiple-Output (MIMO), Full Dimensional MIMO (FD-MIMO), array antennas, and large-scale antennas. In addition, new technologies such as metamaterial-based lenses and antennas, high-dimensional spatial multiplexing using Orbital Angular Momentum (OAM), and Reconfigurable Intelligent Surface (RIS) are being discussed to improve the coverage of terahertz band signals.

[0005] In addition, in order to improve frequency efficiency and system network, 6G communication systems are developing full duplex technology that utilizes the same frequency resources at the same time for uplink and downlink; network technology that integrates satellites and HAPS (High-Altitude Platform Stations); network structure innovation technology that supports mobile base stations and enables optimization and automation of network operation; dynamic spectrum sharing technology through collision avoidance based on spectrum usage prediction; AI-based communication technology that utilizes AI (Artificial Intelligence) from the design stage and internalizes end-to-end AI support functions to realize system optimization; and next-generation distributed computing technology that realizes services with complexity that exceeds the limits of terminal computing capabilities by utilizing ultra-high-performance communication and computing resources (Mobile Edge Computing (MEC), cloud, etc.). In addition, efforts are being made to further strengthen connectivity between devices, further optimize networks, promote softwareization of network entities, and increase the openness of wireless communications through the design of new protocols to be used in 6G communication systems, the implementation of hardware-based security environments, the development of mechanisms for the safe use of data, and the development of technologies for maintaining privacy.

[0006] Research and development of these 6G communication systems are expected to enable a new level of hyper-connected experience through the hyper-connectivity of 6G communication systems, which encompass not only connections between things but also connections between people and things. Specifically, 6G communication systems are expected to enable services such as truly immersive eXtended Reality (XR), high-fidelity mobile holograms, and digital replicas. Furthermore, services such as remote surgery, industrial automation, and emergency response, which are provided through 6G communication systems through enhanced security and reliability, will be applied in diverse fields such as industry, medicine, automobiles, and home appliances.

[0007] LDPC codes play a key role in modern communication systems, significantly contributing to improving their reliability and performance. LDPC codes are a class of codes whose performance approaches their theoretical performance limits / capacity as their length increases. Furthermore, the belief propagation (BP) algorithm, known as a representative LDPC decoder, has a structure highly suitable for parallel implementation, making it highly suitable for systems requiring high throughput and stable reliability. Recently, the 3rd Generation Partnership Project (3GPP), a communications standardization organization, adopted LDPC codes as the 5G new radio (NR) standard and is being used as a data channel coding technology.

[0008] The present disclosure provides a method for designing a base graph of an efficient LDPC code in a communication system.

[0009] The present disclosure provides a base graph structure with non-zeroing of an efficient LDPC code in a communication system.

[0010] The present disclosure provides a method for encoding / decoding using a base graph of an efficient LDPC code in a communication system, and a communication device for performing the encoding / decoding method.

[0011] A method for generating an LPDC code in a communication system according to an embodiment of the present disclosure may include, when the length of information to be transmitted using the LPDC code is 3824 bits, the number of parity blocks related to the LPDC code is 4, and the number of codeword blocks is 14, a process of generating the LDPC code based on the base graph 2 in which, for a region where the row index i and the column index j of the base graph 2 related to the LPDC code are 1≤i≤4 and 1≤j≤14, the number of columns having a column weight of 2 or less among 14 columns in the region is 2 or less.

[0012] In one embodiment, the column weight represents the number of "1"s in each column of the 14 columns, and among the 14 columns, excluding the columns with the column weights less than or equal to 2, 3 columns among the remaining columns are NZ1 to NZ when the row index i is 5. 10 corresponds to one of them, and the column weights of the three columns may be 3.

[0013]

[0014] In one embodiment, the communication system includes at least one of a terminal and a base station, and the channel to which the LDPC code is applied may include at least one of an uplink shared channel (UL-SCH), a downlink shared channel (DL-SCH), and a paging channel (PCH).

[0015] In one embodiment, a plurality of index values ​​constituting a parity check matrix for the LDPC code can be identified based on row indices, column indices of a matrix corresponding to the base graph 2, and lifting set indices for lifting the base graph 2.

[0016] In a communication system according to an embodiment of the present disclosure, a communication device for performing encoding using an LDPC code may include a transceiver, and a processor configured to identify a base graph to be used among a first base graph and a second base graph of the LDPC code based on a length of information to be transmitted and a code rate, identify a parity check matrix for the identified base graph, generate an LDPC codeword including information bits and parity bits of the information to be transmitted using the parity check matrix, and transmit a transport block including the generated LDPC codeword through the transceiver, wherein when the identified base graph is the second base graph, the processor may identify a plurality of index values ​​constituting the parity check matrix based on the second base graph, and the plurality of index values ​​are identified based on row indices, column indices, and lifting set indices for lifting of the base graph of a matrix corresponding to the second base graph, and may be configured to further use index values ​​corresponding to at least one column index mapped to a specific row index among the row indices for the encoding.

[0017] In a communication system according to an embodiment of the present disclosure, a communication device for performing decoding using an LDPC code includes a processor configured to verify a base graph of an LDPC code used in encoding an LDPC codeword received through a transceiver and the transceiver, verify a parity check matrix for the verified base graph, and restore information bits from the LDPC codeword using the parity check matrix, wherein when the verified base graph is the second base graph, the processor verifies a plurality of index values ​​constituting the parity check matrix based on the second base graph, and the plurality of index values ​​are verified based on row indices, column indices, and lifting set indices for lifting of the base graph of a matrix corresponding to the second base graph, and further uses index values ​​corresponding to at least one column index mapped to a specific row index among the row indices for the decoding.

[0018] FIG. 1 is a diagram showing an example of a method for selecting a base graph (BG) of an LDPC code based on the length of information to be transmitted and the code rate.

[0019] Figure 2 is a diagram schematically showing an example of a parity check matrix of an LDPC code.

[0020] Figure 3 is a diagram showing an example of an exponential matrix of a parity check matrix of an LDPC code.

[0021] Fig. 4 is a diagram showing an example of an extended parity check matrix according to the lifting size in an LDPC code.

[0022] Fig. 5 is a diagram showing an example of an active part in a parity check matrix (or base graph) of an LDPC code.

[0023] Fig. 6 is a diagram showing an example of a simulation result of the change in BLER versus SNR for BG2 of an LDPC code.

[0024] Figure 7 is a diagram showing an example of a configuration of a base graph of an LDPC code.

[0025] FIG. 8 is a diagram illustrating an example of a method for applying non-zeroing to specific columns corresponding to the minimum column weight among columns in the core information portion of LDPC BG2 according to an embodiment of the present disclosure;

[0026] FIG. 9 is a diagram showing an example of a method for substituting / inserting specific exponent values ​​in a complementary region within a base graph of an LDPC code when applying non-zeroing according to an embodiment of the present disclosure;

[0027] FIGS. 10A to 10J are diagrams showing examples of setting complementary areas according to various combinations of elements selected from candidate areas for de-zeroing in BG2 of an LDPC code according to embodiments of the present disclosure.

[0028] FIG. 11 is a diagram showing an example of a parity check matrix generated from BG2 to which non-zeroing is applied according to an embodiment of the present disclosure;

[0029] FIG. 12 is a diagram showing an example of an LDPC encoding method using BG2 with non-zero applied according to an embodiment of the present disclosure;

[0030] FIG. 13 is a diagram showing an example of an LDPC decoding method using BG2 with non-zero applied according to an embodiment of the present disclosure;

[0031] FIG. 14 is a diagram showing an example of a simulation result showing performance improvement when using BG2 with non-zero applied according to an embodiment of the present disclosure, and

[0032] FIG. 15 is a diagram showing an example of a configuration of a communication device in a communication system according to an embodiment of the present disclosure.

[0033] The operating principles of the present disclosure are described in detail below with reference to the attached drawings. In the following description of the present disclosure, detailed descriptions of related known functions or configurations will be omitted if they are deemed to unnecessarily obscure the gist of the present disclosure. Furthermore, the terms described below are defined based on the functions of the present disclosure and may vary depending on the intent or custom of the user or operator. Therefore, their definitions should be based on the overall content of this specification.

[0034] The advantages and features of the present disclosure, and methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below and may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present disclosure is complete and to fully inform those skilled in the art of the scope of the invention, and the present disclosure is defined only by the scope of the claims. Like reference numerals designate like elements throughout the specification.

[0035] At this time, it will be understood that each block of the processing flow diagrams and combinations of the flow diagrams can be performed by computer program instructions.

[0036] Additionally, each block may represent a module, segment, or portion of code that contains one or more executable instructions for performing a specific logical function(s). It should also be noted that in some alternative implementation examples, the functions described in the blocks may occur out of order. For example, two blocks depicted in succession may actually be executed substantially concurrently, or the blocks may sometimes be executed in reverse order, depending on their respective functions.

[0037] Here, the term '~ part' used in this embodiment means software or hardware components such as FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit), and the '~ part' performs certain roles. However, the '~ part' is not limited to software or hardware. The '~ part' may be configured to be on an addressable storage medium or may be configured to play one or more processors. Therefore, as an example, the '~ part' includes components such as software components, object-oriented software components, class components, and task components, processes, functions, properties, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided within the components and '~ parts' may be combined into a smaller number of components and '~ parts' or further separated into additional components and '~ parts'. Additionally, the components and '~parts' may be implemented to activate one or more CPUs within a device or secure multimedia card. In addition, in an embodiment, the '~parts' may include one or more processors.

[0038] In this disclosure, phrases such as "A / B", "A or B", "A and / or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" can each include any one of the items listed together in that phrase, or all possible combinations thereof. Terms such as "first", "second", or "first" or "second" may be used merely to distinguish the corresponding component from other corresponding components and do not limit the corresponding components in any other respect (e.g., importance or order).

[0039] In the present disclosure, a base station (BS) is a network entity that performs resource allocation of a terminal and can communicate with the terminal via a wireless network, and may be at least one of an eNode B, a Node B, a gNB, a RAN (Radio Access Network), an AN (Access Network), a RAN node, an IAB (Integrated Access / Backhaul) node, a radio access unit, a base station controller, a node on a network, or a TRP (transmission reception point). A user equipment (UE) may be at least one of a terminal, an MS (Mobile Station), a cellular phone, a smartphone, a computer, or a multimedia system capable of performing a communication function.

[0040] 5G NR LDPC codes mainly adopt quasi-cyclic (QC) and raptor-like structures, and are codes that support various code lengths and code rates while providing stable error correction performance by utilizing the base graph (BG), which is the basis of the parity-check matrix (PCM) that defines the LDPC code. In addition, the quasi-cyclic structure enables the application of layered scheduling to the belief propagation (BP) decoding algorithm used for decoding LDPC codes, providing a structure that is even more suitable for parallel implementation, thereby enabling one-step lower latency communication. In addition, the combination of HARQ (Hybrid Automatic Repeat and request) technology and a block interleaver provides robust and stable performance in various channel environments such as 5G NR data channels.

[0041] The superior performance, low decoding complexity, and low latency of 5G NR LDPC codes can be achieved through highly sophisticated code design. LDPC code design refers to the sequential design of the base graph and parity check matrix. LDPC codes can be designed comprehensively by considering various factors, such as the weight distribution, minimum distance between codewords, minimum cycle length (girth), and extrinsic message degree (EMD), which are key characteristics of the Tanner graph, which is another representation of the parity check matrix, starting from the low density matrix of the most basic LDPC parity check matrix.

[0042] LDPC code, which is currently adopted in the 5G NR communication standard and is well known as an encoding method for data channels, selects one of two base graphs (e.g., BG1, BG2) depending on the length or code rate of the data to be transmitted, constructs a parity check matrix, and performs encoding at the transmitter and decoding at the receiver. For example, referring to LDPC base graph selection in sections 6.2.2 and 7.2.2 of 3GPP standard TS 38.212 Rel.16, a method of selecting one of BG1 and BG2 based on the length A of information to be transmitted in the uplink and downlink and the code rate R is disclosed. Generally, BG1 is selected in a transmission environment where the length of information to be transmitted is relatively long and the code rate is high, and BG2 is selected in a transmission environment where the length of information to be transmitted is short and the code rate is low, and each has an advantage in error rate performance in the corresponding transmission environment. However, assuming a communication environment using the same code parameters, in the case of BG2, the level of blocks that can be processed at once by the receiver's decoder can differ by up to twice compared to BG1 depending on the situation, so there is a relative difference in the level of parallelism, and when this is taken into account, if the error rate performance is not considered, there is an advantage in that a relatively high processing rate can be provided when BG2 is selected.

[0043] According to 3GPP standard TS 38.212, first, the transport block size (TBS), which is the length of information to be transmitted, or the size of the input sequence A, is determined through a series of processes, and then the coding rate R is determined based on the modulation and coding scheme (MCS), and then BG1 or BG2 is determined among the two base graphs through the conditional expressions in [Table 1] below. [Table 1] below shows an example of the conditional expression for BG selection.

[0044] [Table 1]

[0045]

[0046] Figure 1 is a diagram illustrating an example of a method for selecting an LDPC base graph (BG) based on the length of information to be transmitted and the code rate. The example in Figure 1 is a diagrammatic representation of the example in [Table 1].

[0047] Referring to Figure 1, if the length of information to be transmitted (or the transmission block size) A is 292 bits or less, BG2 is selected regardless of the code rate R. If A is greater than 292 bits and 3824 bits or less, and R is 0.67 or less, BG2 is selected. And if R is 0.25 or less, BG2 is selected regardless of A. And in all other cases, BG1 is selected.

[0048] As above, in a communication environment where an LDPC BG is selected, it is assumed that the number of code blocks (CB) is 1. As in the example of [Table 1] or Fig. 1, an LDPC BG is selected, and in order to define a parity check matrix based on the selected BG, the lifting set index, which is a parameter of the quasi-cyclic structure that is the structural core of the 5G NR LDPC code, is used. and lifting size is determined by the following method: the concatenated length of the code-block cyclic redundancy check (CB-CRC) code. When the length of information considering is B, B is the concatenation length of the transmission block size A and the CB-CRC code. The sum of can be expressed as B=A+L.

[0049] A set of lifting sizes of LDPC codes Length parameters associated with For example, if it is BG1, =22 is determined as such, and in the case of BG2, , , , can be determined as follows. The determined length parameter A set of all possible candidate lifting sizes based on (hereinafter referred to as the lifting size set) middle If we find the smallest value that satisfies , then that value is the lifting size is determined by the lifting size Index of the lifting set to which it belongs Find all possible candidate lifting sizes. and lifting set index An example of the relationship between them can be represented as shown in [Table 2] below.

[0050] [Table 2]

[0051]

[0052] The lifting set index determined as above and lifting size Using , a parity check matrix based on the base graph is defined. As in the 3GPP standard, the example in [Table 3] below is for the LDPC base graph 1 (BG1) of size 46×68. ) and related The relationship between the values ​​of (where row index i=0, 1, …, 45 and column index j=0, 1, …, 67) is briefly shown, and the example in [Table 4] below is LDPC base graph 2 (BG2) of size 42×52. )and The relationship between the values ​​is briefly shown (where row index i = 0, 1, … 41 and column index j = 0, 1, … 51). In [Table 3] and [Table 4] is the row index i, column index j, and the lifting set index for lifting the base graph. This is an example of an exponent value or circularly lifting size, which is a value for constructing a parity check matrix according to .

[0053] [Table 3]

[0054]

[0055] [Table 4]

[0056]

[0057] Figure 2 is a diagram briefly illustrating an example of a parity check matrix of an LDPC code, which illustrates a 3×4 sized base graph (BG) for constructing a parity check matrix.

[0058] The example in Fig. 2 illustrates a base graph of size 3×4 for convenience of explanation instead of the base graph of size 46×68 or 42×52 defined in the 3GPP standard. The elements at row index i and column index j of the base graph in Fig. 2 are as shown in Table 5. Each corresponds to . is an index value or circular lifting size for constructing a parity check matrix, where i is a row index and j is a column index, and the elements in row i and column j of the base graph are correspond to each of [Table 5]. In , i and j are represented as integers greater than or equal to 1 for convenience, but as in the examples in [Table 3] and [Table 4], In , i and j can be represented as integers greater than or equal to 0. A base graph (BG) of size 3×4, such as the example in Fig. 2 ( ) is given, the position corresponding to the nonzero value "1" among the elements of the base graph is The values ​​can be exemplified as in [Table 5]. In Fig. 2, “# of VNs” means the number of variable nodes (VNs) in the base graph, and “# of CNs” means the number of check nodes (CNs) in the base graph.

[0059] [Table 5]

[0060]

[0061] Referring to the above [Table 5], a base graph such as the example of Fig. 2 can be defined, and each "1" in the base graph is an element value for forming a parity check matrix at the corresponding position, which is a specific value. This means that it is substituted.

[0062] The parity check matrix of an LDPC code can be expressed using an exponent matrix, and Fig. 3 shows an example of an exponent matrix according to the example of [Table 5]. Fig. 3 (a) shows the exponent values ​​according to the row index i and column index j of the exponent matrix. (where, i and j are integers greater than or equal to 1), and (b) of Figure 3 shows each index value exemplified in [Table 5]. is illustrated. For example, if the row index of the exponential matrix is ​​i=3 and the column index j=2, the exponential value V 3,2 =2. In the exponential matrix of Fig. 3 (b), the exponential value is the lifting size at that location According to × This is a value indicating how many times the identity matrix of the size is circularly lifted, and is an exponential value. Lifting size The remainder P_i,j divided by is called the shift index. For example, the lifting size If the value is 5, If the parity check matrix is ​​expanded according to the value, it is as shown in the example of Fig. 4.

[0063] Fig. 4 shows the lifting size in LDPC code. As an example of an extended parity check matrix according to the lifting size, Fig. 4 An example of an extended parity check matrix of size (3×5) × (4×5) is shown when the value is 5. In the example of Fig. 4, a zero matrix is ​​inserted into the empty part. Each area separated by a thick solid line in Fig. 4 corresponds to the value '1' of the base graph, and the elements of the identity matrix in each area are lifted in size and exponent values The shift index P_i,j is shifted by the value determined by V. For example, V 3,2 =2 We can see that the elements of the identity matrix in the region are shifted by 2, which is the remainder of dividing 2 by 5.

[0064] Considering the length of the codeword to be transmitted using an LDPC code, instead of using the parity check matrix as it is, a partial matrix (submatrix) can be used. In the present disclosure, a specific part corresponding to the partial matrix in the extended parity check matrix is ​​conveniently referred to as an active part. The active part in the parity check matrix can be referred to by various terms. In the actual LDPC code encoding process, various encoding methods can be selectively used, such as generating a codeword using the entire size of the parity check matrix, adjusting the codeword to an appropriate size, or using a necessary partial matrix in the LDPC code encoding process.

[0065] Figure 5 illustrates an example of an active part in a base graph of an LDPC code, for example, a case where an active part of size 22×32 is set in a base graph of size 42×52.

[0066] [Table 6] below shows an example of how to determine the parity bit length, the number of parity blocks, and the number of codeword blocks to determine the active part of the base graph. In [Table 6] below, A is the length of the information to be transmitted, R is the code rate, is the lifting size, B is the transmission block size A and the concatenation length of the CB-CRC code. The sum of B=A+L.

[0067] [Table 6]

[0068]

[0069] Referring to the above [Table 6], (the number of codeword blocks) × (the number of parity blocks) becomes the size of the active part in the predetermined base graph. What can be seen here is that since the number of message blocks in [Table 6] is a variable that has already been determined for each base graph, the code rate, which is the main factor that ultimately determines the number of parity blocks, has the greatest influence on determining the size of the active part. As the code rate increases, the active part becomes smaller, and as the code rate decreases, the active part becomes larger. In other words, the size of the active part in the base graph is inversely proportional to the code rate. However, even if the active part becomes smaller as the code rate increases, the minimum size of the active part can be determined, and the size of the active part can be different for each type of base graph, BG1 and BG2 (for example, the size of the active part can be determined in the range of 4×26 to 46×68 when the difference between the number of rows and the number of columns is 22 for BG1, and can be determined in the range of 4×14 to 42×52 when the difference between the number of rows and the number of columns is 10 for BG2). However, a problem can occur when the code rate is very large and the active part is close to the minimum size or when the active part is slightly larger than the minimum size.

[0070] In the following, the present disclosure describes problems related to determining the size of an active portion and proposes solutions.

[0071] The problem of determining the size of the active part can occur regardless of the type of base graph, but the applicant's research suggests that determining the size of the active part can be more problematic in BG2 compared to BG1.

[0072] FIG. 6 shows an example of a simulation result of the change in BLER versus Es / No (the ratio of the average energy transmitted per channel symbol to the average noise power) for BG2 of an LDPC code. For example, in the case of BG2, BPSK modulation, A=3824, and R=3 / 4, the simulation result of the change in BLER versus Es / No (the ratio of the average energy transmitted per channel symbol to the average noise power) is shown. The Es / No is a value corresponding to the signal-to-noise ratio (SNR), and is explained below by replacing it with SNR.

[0073] Referring to Figure 6, for example, in BG2, the transport block size (TBS) A is the maximum size = When it is close to 3824 and the code rate is greater than 0.5, the slope of the BLER versus SNR does not increase or remain constant, but decreases as shown in the illustrated part of reference number 610 based on a certain threshold. This means that the SNR required for the error rate performance to be achieved (required SNR) is greater than expected. This phenomenon is called the error floor phenomenon. The error floor phenomenon mainly occurs when an iterative decoding method such as trust propagation decoding is used in a linear code based on a sparse (low density) graph. The cause of the error floor phenomenon includes a small minimum distance or a trapping set, but the important point here is that the error floor phenomenon is a problem that is occurring in the 5G NR LDPC code adopted and used in the 3GPP standard, and the problem of the error floor phenomenon becomes more serious when a code rate greater than the code rate used in the current 3GPP standard is used in the LDPC code. The error floor phenomenon is not simply a problem occurring in a single code block; in communication environments where a transport block consists of multiple code blocks, it can pose a significant challenge in relation to the required SNR. Furthermore, the error floor problem can be even more problematic in communication scenarios such as ultra-reliability communications, which require extremely low block error rates.

[0074] The problem of error floor phenomenon in LDPC codes is a problem that can be found in currently commercialized communication systems, and considering the scalability and universality of LDPC codes, there is a need to solve the problem that occurs at code rates that are likely to be used in wireless communication systems in the future. In this disclosure, as a solution to the error floor phenomenon, we focus on the column weight distribution of the base graph from a fundamental perspective. To this end, this disclosure proposes a base graph design method and device for LDPC codes that can effectively reduce the error floor phenomenon by analyzing the column weight distribution of the base graph, and thereby proposes a new LDPC code that provides stable error rate performance.

[0075] In this disclosure, we propose a base graph of an LDPC code having a new structure capable of effectively reducing the error floor phenomenon by analyzing the column weight distribution in the base graph of an LDPC code used in a 5G NR system as an example, and a base graph design method of an LDPC code for the same.

[0076] Hereinafter, a method for designing a base graph of an LDPC code according to the present disclosure will be described with reference to FIG. 7.

[0077] Fig. 7 illustrates an example configuration of a base graph of an LDPC code according to the present disclosure. The example of Fig. 7 illustrates an example of a 14×24 sized submatrix in which the difference between the number of rows and the number of columns in the base graph is 10.

[0078] Referring to FIG. 7, the base graph (700) may include a core information portion (710), a core parity portion (720), and a single parity portion (730). The core information portion (710) is a portion related to information bits of an LDPC code and may be referred to as an information portion. The core parity portion (720) is located in the same rows as the core information portion (710) in the matrix of the base graph (700) and is a portion related to parity bits calculated based on the information bits. The core parity portion (720) may be referred to as a first parity portion. The single parity portion (730) is located in different rows and different columns from the core parity portion (720) in the matrix of the base graph (700) and is a portion related to parity bits configured as an identity matrix to reduce the complexity of LDPC encoding. The single parity portion (730) may be referred to as a second parity portion.

[0079] 1. Analysis of column weight distribution in the base graph of LDPC codes used in 5G NR systems.

[0080] When comparing BG1 and BG2 of LDPC codes used in the 5G NR system, the biggest difference between BG1 and BG2 can be said to be the size of the core information part (710) in the base graph (700). Here, the name of the core information part is an example, and the core information part can be called by various names. As an example of the core information part, in the case of BG1, a sub-matrix having a size of 4 × 22 may be set in the upper left, and in the case of BG2, a sub-matrix having a size of 4 × 10 may be set in the upper left, as in the example of 710 in FIG. 7. In this way, BG1 and BG2 have core information parts of different sizes. In the present disclosure, we focus on the distribution of column weights in the core part, including the core information part (710) and core parity part (720) of BG2 compared to BG1. The size of the core part may be, for example, BG1 may have a size of 4×26, and BG2 may have a size of 4×14. The column weight is defined as the number of “1”s in each column of the sub-matrix corresponding to the core part including the core information part (710) and the core parity part (720). For example, if the number of “1”s is 3, such as the first column of the core part of the base graph (700), the column weight of the first column is 3, and if the number of “1”s is 2, such as the third column, the column weight of the third column is 2. In the LPDC code, the core part of the base graph (700) may have a minimum column weight, and the number of “1”s in each column of the core part must be at least greater than or equal to the minimum column weight.

[0081] In the 5G NR LPDC code, the minimum column weight of the core information part of BG1 is 3, and the minimum column weight of the core information part of BG2 is 2. In addition, the number of columns in the core information part of BG2 whose column weights are equal to the minimum column weight is as many as 3. In the case of BG2, a relatively smaller minimum column weight is applied compared to BG1, and the application of such a smaller minimum column weight causes the minimum distance characteristic of the codeword in the LDPC code to deteriorate. In addition to the case where the core information part (710) becomes the active part described above, even when the code rate is relatively small starting from the core information part (710) and the active part increases, there are still columns with a column weight of 2, which negatively affects the encoding and decoding performance of the LDPC code in various cases. The reason why the error floor phenomenon occurs more frequently in BG2 than in BG1 can be analyzed as described above.

[0082] 2. A proposal to solve the problem of relatively small column weight distribution in BG2 of LDPC codes used in 5G NR systems.

[0083] In order to solve the problem identified through the analysis of the column weight distribution in BG2 of the LPDC code, it may be considered to apply nonzeroing to specific columns whose column weights are 2, which is equal to the minimum column weight, in the core information portion (710) of the base graph (700), or to apply a method expressed as edge addition in a Tanner graph that is isomorphic to the corresponding submatrix. In this disclosure, a method of applying nonzeroing to solve the problem of the column weight distribution in BG2 is proposed.

[0084] 3. A method of applying non-zeroing to the area adjacent to specific columns corresponding to the minimum column weight in the core information part of BG2 of the LDPC code.

[0085] Various factors must be considered when applying de-zeroing within the base graph (700) of a 5G NR LDPC code. In LDPC codes, pre-encoding and post-encoding operations are separated to reduce encoding complexity, utilizing structural characteristics. In the pre-encoding process, parity bits corresponding to the core information portion (710) are generated, and in the post-encoding process, a simple encoding process is performed using the parity bits generated in the pre-encoding process.

[0086] In the present disclosure, we propose a method of maintaining the pre-coding and post-coding operations of the 5G NR LDPC code described above, while excluding the core information part (710) and the core parity part (720) of the base graph (700) from the application target for de-zeroing. In this case, the limitations of the core information part (710) and the core parity part (720) in relation to the application of de-zeroing according to the present disclosure in BG1 and BG2 are as follows [Restriction 1].

[0087] [Restriction 1]

[0088]

[0089] Considering the possibility of future structural changes and development of LDPC codes, the above [limitation 1] is not essential, and as an optional embodiment, it may be possible to apply non-zeroing to the core information part (710) and / or the core parity part (720) in the 5G NR LDPC code.

[0090] In addition, since the single parity part (730) composed of the identity matrix in the post-coding process of the LDPC code is also a region that utilizes the structural characteristics of the LDPC code, we propose a method of not including the single parity part (730) of the base graph (700) in the target of application for de-zeroing. In relation to the application of de-zeroing, the limitations of the single parity part (730) are as follows [Restriction 2].

[0091] [Restriction 2]

[0092]

[0093] Likewise, considering the possibility of future structural changes and development of LDPC codes, the above [limitation 2] is not essential, and as an optional embodiment, it may be possible to apply non-zeroing to a single parity part (730) in a 5G NR LDPC code.

[0094] Additionally, since the region within the base graph where the error floor phenomenon occurs in LDPC codes and where problems in reaching a certain performance occur at high code rates, it can be seen that nonzeroing should be applied to at least one row and / or at least one column immediately adjacent to the core part, including the core information part and the core parity part, and in the case of BG2, it can be seen that it should be applied to certain columns whose column weights are 2, which correspond to the minimum column weights.

[0095] As an example, when applying [Restriction 1] and [Restriction 2] to BG2, a (candidate) region to which non-zeroing can be applied to solve the problem of the error floor phenomenon in the base graph (700) of BG2 according to the present disclosure can be exemplified as in the following [Mathematical Formula 1].

[0096] [Mathematical Formula 1]

[0097]

[0098] The example of the above [Mathematical Formula 1] shows an example of applying non-zeroing to specific columns whose column weight is 2, which corresponds to the minimum column weight, among the elements in the 5th row immediately adjacent to the core information portion (710) in BG2 of the 5G NR LDPC code.

[0099] As in the above-described embodiment, a method for designing a base graph of an LPDC code in a communication system may include a process of identifying at least one column whose column weight, defined as the number of "1"s in each column of columns belonging to a submatrix corresponding to an information portion of the base graph, is equal to a predetermined minimum column weight, and a process of applying non-zeroing to elements of at least one row adjacent to the information portion in the identified at least one column.

[0100] As in the above-described embodiment, the structure of the base graph for the LDPC code in the communication system may include an information part related to information bits of the LDPC code, a first parity part related to parity bits calculated based on the information bits, and a second parity part related to parity bits formed as an identity matrix in the base graph. Here, non-zeroing may be applied to elements of at least one row adjacent to the information part in at least one column in which a column weight defined by the number of "1"s in each column of columns belonging to a submatrix corresponding to the information part is equal to a predetermined minimum column weight.

[0101] FIG. 8 is a diagram illustrating an example of a method for applying non-zeroing to specific columns corresponding to the minimum column weight among the columns in the core part of LDPC BG2 according to an embodiment of the present disclosure. The example of FIG. 8 shows an example of a sub-matrix of size 5×15 in which the difference between the number of rows and the number of columns in BG2 is 10, and exemplifies a method for applying non-zeroing to the corresponding element(s) of the 5th row belonging to at least one of the specific columns corresponding to the minimum column weight 2 among the columns in the 5th row adjacent to the 4th row of the core part having the size of 4×14 in BG2. Here, the element may be referred to as various names such as entry.

[0102] Referring to FIG. 8, among the elements of (i, j) (where i is a row index and j is a column index) constituting the matrix of BG2, the elements corresponding to [Mathematical Formula 1] correspond to elements of reference numerals 801 to 805 in FIG. 8. In the present disclosure, dezeroing can be applied to at least one of the elements (801, …, 805) of BG2 to improve the error floor phenomenon. In other words, although the elements (801, …, 805) of BG2 in FIG. 8 are illustrated with a value of “0” as in BG2 of the 5G NR standard, dezeroing can be applied to set the value of at least one of the elements (801, …, 805) of BG2 to a value of “1”. Through this, dezeroing can be applied to at least one of the elements (801, …, 805) of BG2 for at least one column among specific columns in which the column weight is equal to the minimum column weight in the core part of BG2.

[0103] Considering the possibility of future structural changes and developments of LDPC codes, the application of dezeroing according to the present disclosure is not limited to the example of [Mathematical Formula 1], and it may be possible to apply dezeroing not only to the specific columns in BG2 but also to at least one additional column, or to apply dezeroing not only to the 5th row of BG2 but also to at least one additional row (e.g., the 6th row, the 7th row, etc.). Here, dezeroing may be applied to a row immediately adjacent to a core part, such as the 5th row, the 6th row, or the 7th row. That is, dezeroing may not be applied to two or more rows in a specific column, but may be limited to be applied to a row immediately adjacent to a core part.

[0104] As an example, the above-described embodiment of applying non-zeroing in BG2 of the LDPC code of the present disclosure may also be applied in the same / similar manner in BG1.

[0105] According to the present disclosure, the region in the base graph (BG) of the LDPC code to which non-zeroing is applied is referred to as a complementary region for convenience. The region to which the non-zeroing is applied may be referred to by various names, such as a specific region. Once the complementary region is determined, specific index value(s) must be assigned / inserted to non-zero element(s) in the complementary region within the base graph, and the specific index value(s) are lifting set indices. can be defined for each. The above specific index value(s) can be defined in various ways according to various combinations of elements of the complementary area to which non-zeroing is applied among the elements of the candidate area of ​​the above [Mathematical Formula 1].

[0106] For example, after selecting a base graph to be used among BG1 and BG2, a specific index value must be assigned / inserted to a non-zero element in the base graph to construct a parity check matrix, as in the example of [Table 3] or [Table 4], and this can be defined for each lifting set index.

[0107] FIG. 9 illustrates an example of a method for assigning / inserting specific exponent values ​​to non-zero elements in a complementary region within a base graph when applying non-zeroing according to an embodiment of the present disclosure.

[0108] Referring to Figure 9, for each element modified due to non-zeroing in the base graph, a lifting set index is provided, as in the example of Figure 9 (a). Each of the eight specific values ​​can be determined / defined. And the lifting set index, as in the example of (b) of Fig. 9 In the range of 0 and less than or equal to the maximum exponent value, random (or predetermined) exponent values ​​can be assigned / inserted for non-zeroing application in the same area as [Mathematical Formula 1].

[0109] FIGS. 10A to 10J illustrate examples of setting complementary areas according to various combinations of elements selected from a candidate area for de-zeroing in BG2 of an LDPC code according to embodiments of the present disclosure, wherein the setting examples illustrate various examples of complementary areas that can be set according to combinations of three elements selected from a candidate area of ​​five elements of [Mathematical Formula 1] to which de-zeroing can be applied. The complementary area may be called by various names, such as a specific area for de-zeroing. Specifically, the examples of FIGS. 10A to 10J illustrate various examples of a 5×15 sized sub-matrix in BG2 in which the difference between the number of rows and the number of columns is 10, and the complementary areas (NZ1 to NZ) selected for de-zeroing in a candidate area immediately adjacent to a 4×10 sized core information part (or active part) located at the upper left in BG2 of a 5G NR LDPC 10 ) are various examples. The candidate area is the same as the example of [Mathematical Formula 1] above.

[0110] Referring to FIG. 10a, an example is shown in which non-zeroing is applied, as indicated by reference number 1001, to a first complementary region (NZ1 = {(5, 3), (5, 6), (5, 8)}) including three elements among five elements included in the candidate region of [Mathematical Formula 1] in BG2.

[0111] Referring to FIG. 10b, an example is shown in which non-zeroing is applied to a second complementary region (NZ2 = {(5, 3), (5, 6), (5, 13)}) including three elements among the five elements included in the candidate region of [Mathematical Formula 1] in BG2, as indicated by reference number 1002.

[0112] Referring to FIG. 10c, an example is shown in which non-zeroing is applied to a third complementary region (NZ3 = {(5, 3), (5, 6), (5, 14)}) including three elements among the five elements included in the candidate region of [Mathematical Formula 1] in BG2, as indicated by reference number 1003.

[0113] Referring to FIG. 10d, an example is shown in which non-zeroing is applied to a fourth complementary region (NZ4 = {(5, 3), (5, 8), (5, 13)}) including three elements among the five elements included in the candidate region of [Mathematical Formula 1] in BG2, as indicated by reference number 1004.

[0114] Referring to FIG. 10e, an example is shown in which non-zeroing is applied to a fifth complementary region (NZ5 = {(5, 3), (5, 8), (5, 14)}) including three elements among five elements included in the candidate region of [Mathematical Formula 1] in BG2, as indicated by reference number 1005.

[0115] Referring to FIG. 10f, an example is shown in which non-zeroing is applied to the sixth complementary region (NZ6 = {(5, 3), (5, 13), (5, 14)}) including three elements among the five elements included in the candidate region of [Mathematical Formula 1] in BG2, as indicated by reference number 1006.

[0116] Referring to FIG. 10g, an example is shown in which non-zeroing is applied to the seventh complementary region (NZ7 = {(5, 6), (5, 8), (5, 13)}) including three elements among the five elements included in the candidate region of [Mathematical Formula 1] in BG2, as indicated by reference number 1007.

[0117] Referring to FIG. 10h, an example is shown in which non-zeroing is applied to the 8th complementary region (NZ8 = {(5, 6), (5, 8), (5, 14)}) including 3 elements among 5 elements included in the candidate region of [Mathematical Formula 1] in BG2, as indicated by reference number 1008.

[0118] Referring to FIG. 10i, an example is shown in which non-zeroing is applied to the ninth complementary region (NZ9 = {(5, 6), (5, 13), (5, 14)}) including three elements among the five elements included in the candidate region of [Mathematical Formula 1] in BG2, as indicated by reference number 1008.

[0119] Referring to FIG. 10j, a tenth complementary region (NZ) including three elements among the five elements included in the candidate region of [Mathematical Formula 1] in BG2 10 = {(5, 8), (5, 13), (5, 14)}) shows an example where non-zeroing is applied, as shown in reference number 1008.

[0120] The above application of dezeroing is not limited to the examples of FIGS. 10A to 10J, and it would also be possible to further apply dezeroing to at least one additional column in BG2 in addition to the specific columns in the examples of FIGS. 10A to 10J, and / or to further apply dezeroing to at least one additional row (e.g., the 6th row, the 7th row, etc.) in addition to the 5th row of BG2.

[0121] In the examples of Figs. 10a to 10j, applying dezeroing to the base graph is briefly explained as modifying the values ​​of elements in the complementary region from "0" to "1", but the modification according to applying dezeroing to the parity check matrix extended from the base graph requires setting the index values ​​for eight different lifting set indices. For example, as in the example of Fig. 10b, from the base graph to the elements in the complementary region When applying non-zeroing by selecting , the parity check matrix can be represented as in the example of Fig. 11.

[0122] FIG. 11 illustrates an example of a parity check matrix generated from BG2 to which non-zeroing is applied according to an embodiment of the present disclosure.

[0123] In the example of Fig. 11, reference number 1110 is an element of the complementary area in the base graph. Apply non-zeroing to each lifting set index Here, an example of the index values ​​in the parity check matrix is ​​shown when the index values ​​are arbitrarily set as described in FIG. 9. The index values ​​of reference number 1110 in FIG. 11 are values ​​added / determined to the parity check matrix through the application of non-zeroing, which has the same meaning as the insertion of additional index values ​​in the parity check matrix and the addition of new branches in the Tanner graph. In the same manner, a new parity check matrix including the indicator values ​​added through the application of non-zeroing can be generated / configured for the examples of FIGS. 10a to 10j. Although the embodiments of FIGS. 10a to 10j and the embodiment of FIG. 11 illustrate cases in which non-zeroing is applied under conditions that satisfy [Restriction 1] and [Restriction 2], it may be possible to apply non-zeroing even when the conditions are not satisfied.

[0124] In a communication system according to an embodiment of the present disclosure, a method for generating an LPDC code using at least one of the embodiments of FIGS. 7 to 11 may include, when the length of information to be transmitted using the LPDC code is 3824 bits, the number of parity blocks related to the LPDC code is 4, and the number of codeword blocks is 14, a process of generating the LDPC code based on the base graph 2 in which, for an area where the row index i and the column index j of the base graph 2 related to the LPDC code are 1≤i≤4 and 1≤j≤14, the number of columns having a column weight of 2 or less among 14 columns in the area is 2 or less.

[0125] In one embodiment, the column weight represents the number of "1"s in each column of the 14 columns, and among the 14 columns, excluding the columns with the column weights less than or equal to 2, 3 columns among the remaining columns are NZ1 to NZ when the row index i is 5. 10 corresponds to one of them, and the column weights of the three columns may be 3.

[0126]

[0127] In one embodiment, the communication system includes at least one of a terminal and a base station, and the channel to which the LDPC code is applied may include at least one of an UL-SCH, a DL-SCH, and a PCH.

[0128] In one embodiment, a plurality of index values ​​constituting a parity check matrix for the LDPC code can be identified based on row indices, column indices of a matrix corresponding to the base graph 2, and lifting set indices for lifting the base graph 2.

[0129] When using the base graph formed / configured through the base graph design method proposed in the embodiments of the present disclosure, a more stable error rate performance can be achieved compared to using the base graph defined in the existing 5G NR standard as is. That is, according to the embodiments of the present disclosure, a BLER-SNR graph having a stable slope can be obtained without experiencing an error floor phenomenon. In addition, the complexity of LDPC encoding / decoding generated through branches (edges) added to the tenor graph according to the present disclosure is negligible, and the embodiments of the present disclosure can be easily applied to the existing 5G NR system by a simple operation of filling numbers in empty spaces in the base graph simply by adding branches.

[0130] FIG. 12 illustrates an example of an LDPC encoding method using BG2 with non-zero applied according to an embodiment of the present disclosure.

[0131] Referring to FIG. 12, in step 1201, the transmitting device can identify a base graph to be used among the first base graph and the second base graph of the LDPC code based on the length of information to be transmitted and the code rate. Here, the second base graph can use the base graph 2 (BG2) described / exemplified in the embodiments of FIGS. 7 to 11. When the identified base graph is the second base graph, the transmitting device can identify a plurality of index values ​​constituting the parity check matrix based on the second base graph, and the plurality of index values ​​can be identified based on row indices, column indices, and lifting set indices for lifting of the base graph of the matrix corresponding to the second base graph.

[0132] In step 1202, the transmitting device can check the parity check matrix based on the lifting set index and lifting size for the confirmed base graph. Then, in step 1203, the transmitting device can generate an LDPC codeword including information bits and parity bits of the information to be transmitted using the parity check matrix. In the present disclosure, the transmitting device can further use index values ​​corresponding to at least one column index mapped to a specific row index among the row indices of the matrix corresponding to the second base graph for the encoding.

[0133] FIG. 13 illustrates an example of an LDPC decoding method using BG2 with non-zero applied according to an embodiment of the present disclosure.

[0134] Referring to FIG. 13, in step 1301, the receiving device can check the base graph of the LDPC code used in encoding the received LDPC codeword. Here, the second base graph can use the base graph 2 (BG2) described / exemplified in the embodiments of FIGS. 7 to 11. When the checked base graph is the second base graph, the receiving device can check a plurality of index values ​​constituting the parity check matrix based on the second base graph, and the plurality of index values ​​can be checked based on row indices, column indices of a matrix corresponding to the second base graph, and lifting set indices for lifting the base graph.

[0135] In step 1302, the receiving device can verify the parity check matrix based on the lifting set index and lifting size for the verified base graph. Then, in step 1303, the receiving device can restore the information bits from the LDPC codeword using the parity check matrix. In the present disclosure, the transmitting device can further use index values ​​corresponding to at least one column index mapped to a specific row index among the row indices of the matrix corresponding to the second base graph for the decoding.

[0136] FIG. 14 shows an example of a simulation result showing performance improvement when using BG2 with non-zero applied according to an embodiment of the present disclosure.

[0137] (a) of Figure 14 is, for example, the length of information to be transmitted in an LDPC code A = 3824, modulation order Q m =2, code rate R=0.667 (i.e. R=2 / 3), the simulation results are shown, and (b) of Fig. 14 shows, for example, the length of information to be transmitted in an LDPC code A=3824, modulation order Q m =2, and the simulation results are shown when the code rate R=0.750 (i.e. R=3 / 4). Q m =2 modulation order corresponds to QPSK (Quadrature Phase Shift Keying).

[0138] In (a) and (b) of FIG. 14, reference numbers 1401 and 1411 indicate signal-to-noise ratio (SNR) (i.e., E) when using BG2 defined in the existing 5G NR standard to which de-zeroing according to the present disclosure is not applied. s / N0) represents the block error rate (BLER) compared to the reference numbers 1402 and 1412, and the signal-to-noise ratio (SNR) (E) in the case of using BG2 with non-zeroing applied according to the present disclosure, such as the examples of FIGS. 10a to 10j. s / N0) compared to the block error rate (BLER). Referring to the performance graphs at reference numbers 1402 and 1412 in (a) and (b) of FIG. 14, it can be seen that the error floor phenomenon is significantly alleviated compared to the performance graphs of the existing 5G NR BG2 at reference numbers 1401 and 1411. This can be explained by the performance gain that can be obtained without any additional computational complexity when using the BG2 with non-zeroing applied designed according to the present disclosure.

[0139] FIG. 15 is a diagram illustrating an example configuration of a communication device in a communication system according to an embodiment of the present disclosure. The communication device of FIG. 15 may be a transmitting device (base station or terminal) that performs encoding using an LDPC code, or a receiving device (terminal or base station) that performs decoding using an LDPC code. The communication device of FIG. 15 may perform LDPC encoding / decoding using a base graph to which non-zeroing is applied according to at least one of the embodiments of FIGS. 7 to 14.

[0140] The communication device of FIG. 15 may include a processor (1530), a transceiver (1510), and a memory (1520). The processor (1530), the transceiver (1510), and the memory (1520) of the communication device of FIG. 15 may operate according to at least one of the embodiments of FIGS. 7 to 14. However, the components of the communication device are not limited to the examples described above. For example, the communication device may include more or fewer components than the components described above. In addition, the processor (1530), the transceiver (1510), and the memory (1520) may be implemented in the form of a single chip. The transceiver (1510) is a general term for a receiver and a transmitter of the communication device and may transmit and receive signals with a counterpart communication device. At this time, the transmitted and received signals may include at least one of control information and data. To this end, the transceiver (1510) may include a wired or wireless transceiver and may include various configurations for transmitting and receiving signals. The transceiver (1510) may receive a signal, output it to the processor (1530), and transmit the signal output from the processor (1530).

[0141] In addition, the transceiver (1510) can receive a communication signal and output it to the processor (1530), and transmit the signal output from the processor (1530) to the counterpart communication device through the network. The memory (1520) can store programs and data required for the operation of the base station according to at least one of the embodiments of FIGS. 7 to 14. In addition, the memory (1520) can store control information or data included in a signal acquired from the base station. The memory (1520) can be configured as a storage medium or a combination of storage media, such as a ROM, a RAM, a hard disk, a CD-ROM, and a DVD. In addition, the processor (1530) can control a series of processes so that the communication device can operate according to at least one of the embodiments of FIGS. 7 to 14.

[0142] The methods according to the embodiments described in the claims or specification of the present disclosure may be implemented in the form of hardware, software, or a combination of hardware and software.

[0143] When implemented in software, a computer-readable storage medium storing one or more programs (software modules) may be provided. The one or more programs stored in the computer-readable storage medium are configured for execution by one or more processors within a communication / electronic device. The one or more programs include instructions that cause the electronic device to execute methods according to the embodiments described in the claims or specification of the present disclosure.

[0144] These programs (software modules, software) may be stored in random access memory, non-volatile memory including flash memory, read only memory (ROM), electrically erasable programmable read only memory (EEPROM), magnetic disc storage device, compact disc ROM (CD-ROM), digital versatile discs (DVDs) or other forms of optical storage device, magnetic cassette. Or, they may be stored in a memory configured as a combination of some or all of these. In addition, each configuration memory may be included in multiple numbers.

[0145] Additionally, the program may be stored in an attachable storage device that is accessible via a communication network such as the Internet, an intranet, a local area network (LAN), a wide local area network (WLAN), a storage area network (SAN), or a combination thereof. Such a storage device may be connected to a device performing an embodiment of the present disclosure via an external port. Additionally, a separate storage device on the communication network may be connected to a device performing an embodiment of the present disclosure.

[0146] In the specific embodiments of the present disclosure described above, components included in the invention are expressed in the singular or plural form, depending on the specific embodiment presented. However, the singular or plural expressions are selected to suit the presented situation for convenience of explanation, and the present disclosure is not limited to singular or plural components. Components expressed in the plural form may be composed of singular elements, or components expressed in the singular form may be composed of plural elements.

[0147] While the detailed description of this disclosure has described specific embodiments, it should be understood that various modifications are possible without departing from the scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the described embodiments, but should be defined not only by the scope of the claims described below, but also by equivalents thereof.

Claims

1. A method for generating a LPDC (low-density parity-check) code in a communication system, When the length of information to be transmitted using the above LPDC code is 3824 bits, the number of parity blocks related to the above LPDC code is 4, and the number of codeword blocks is 14, A method comprising a process of generating the LDPC code based on the base graph 2, wherein, for a region where the row index i and the column index j of the base graph 2 related to the LPDC code are 1≤i≤4 and 1≤j≤14, the number of columns having a column weight of 2 or less among 14 columns in the region is 2 or less.

2. In paragraph 1, The above column weight represents the number of "1"s in each column of the 14 columns, and among the 14 columns, excluding the columns with the column weights less than or equal to 2, 3 columns among the remaining columns are NZ1 to NZ when the row index i is 5. 10 corresponds to one of them, and the column weights of the three columns are 3, .

3. In paragraph 1, The above communication system includes at least one of a terminal and a base station, A method in which a channel to which the above LDPC code is applied includes at least one of an UL-SCH (uplink shared channel), a DL-SCH (downlink shared channel), and a PCH (paging channel).

4. In paragraph 1, A method in which a plurality of index values ​​constituting a parity check matrix for the above LDPC code are verified based on row indices, column indices of a matrix corresponding to the above base graph 2 and lifting set indices for lifting the above base graph 2.

5. In a communication device that performs encoding using a LPDC (low-density parity-check) code in a communication system, Transmitter and receiver; and Based on the length of the information to be transmitted and the code rate, the base graph to be used among the first base graph and the second base graph of the LDPC code is determined, Check the parity check matrix for the above-mentioned base graph, Using the above parity check matrix, an LDPC codeword including information bits and parity bits of the information to be transmitted is generated, A processor configured to transmit a transmission block including the generated LDPC codeword through the transceiver, A communication device configured to, when the confirmed base graph is the second base graph, confirm a plurality of index values ​​constituting the parity check matrix based on the second base graph, and the plurality of index values ​​are confirmed based on row indices, column indices, and lifting set indices for lifting of the base graph of a matrix corresponding to the second base graph, and further use index values ​​corresponding to at least one column index mapped to a specific row index among the row indices for the encoding.

6. In paragraph 5, When the length of the information to be transmitted using the above LPDC code is 3824 bits, the number of parity blocks related to the LPDC code is 4, and the number of codeword blocks is 14, A communication device in which the above-mentioned confirmed base graph is the second base graph, and in a region where the row index i and the column index j of the second base graph are 1≤i≤4 and 1≤j≤14, the number of columns having a column weight of 2 or less among 14 columns in the region is 2 or less.

7. In paragraph 6, The above column weight represents the number of "1"s in each column of the 14 columns, and among the 14 columns, excluding the columns with the column weights less than or equal to 2, 3 columns among the remaining columns are NZ1 to NZ when the row index i is 5. 10 corresponds to one of them, and the column weights of the three columns are 3, .

8. In paragraph 5, A communication device in which the channel to which the above LDPC code is applied includes at least one of an UL-SCH (uplink shared channel), a DL-SCH (downlink shared channel), and a PCH (paging channel).

9. In paragraph 5, The above second base graph is the information part, A first parity portion associated with parity bits calculated based on the above information bits, and In the second base graph, a second parity part related to parity bits composed of an identity matrix is ​​further included, A communication device wherein the index values ​​corresponding to the at least one column index are related to the specific row index of a specific row adjacent to the information portion and the first parity portion in the submatrix of the second base graph.

10. In a communication device that performs decryption using a LPDC (low-density parity-check) code in a communication system, Transmitter and receiver; and Check the base graph of the LDPC code used in encoding the LDPC codeword received through the above transceiver, Check the parity check matrix for the above-mentioned base graph, A processor configured to restore information bits from the LDPC codeword using the parity check matrix, A communication device configured to, when the confirmed base graph is the second base graph, confirm a plurality of index values ​​constituting the parity check matrix based on the second base graph, and the plurality of index values ​​are confirmed based on row indices, column indices, and lifting set indices for lifting of the base graph of a matrix corresponding to the second base graph, and further use index values ​​corresponding to at least one column index mapped to a specific row index among the row indices for the decryption.

11. In paragraph 10, When the length of the received information using the above LPDC code is 3824 bits, the number of parity blocks related to the LPDC code is 4, and the number of codeword blocks is 14, A communication device in which the above-mentioned confirmed base graph is the second base graph, and in a region where the row index i and the column index j of the second base graph are 1≤i≤4 and 1≤j≤14, the number of columns having a column weight of 2 or less among 14 columns in the region is 2 or less.

12. In paragraph 11, The above column weight represents the number of "1"s in each column of the 14 columns, and among the 14 columns, excluding the columns with the column weights less than or equal to 2, 3 columns among the remaining columns are NZ1 to NZ when the row index i is 5. 10 corresponds to one of them, and the column weights of the three columns are 3, .

13. In paragraph 10, A communication device in which the channel to which the above LDPC code is applied includes at least one of an UL-SCH (uplink shared channel), a DL-SCH (downlink shared channel), and a PCH (paging channel).

14. In paragraph 10, The above second base graph is the information part, A first parity portion associated with parity bits calculated based on the above information bits, and In the second base graph, a second parity part is further included, which is related to parity bits composed of an identity matrix, A communication device wherein the index values ​​corresponding to the at least one column index are related to the specific row index of a specific row adjacent to the information portion and the first parity portion in the submatrix of the second base graph.

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