Display panel and display device

Abstract

The present application relates to the technical field of display, and discloses a display panel and a display device. The display panel comprises a base substrate, a plurality of pixel units, and a plurality of gate signal lines. The gate signal lines comprise main body portions extending in a first direction, and bending portions connected to the main body portions and located in a target transparent area close to a peripheral area in a display area of the base substrate. Since the path of bending portions is long, invasion paths of water vapor or oxygen invading pixel units is long, thereby effectively reducing the possibility of the water vapor or oxygen entering the pixel units, improving the yield of a display panel, and ensuring the display effect of the display panel.

Description

Display panel and display device

[0001] The present disclosure claims priority to the Chinese patent application No. 202410465765.6, filed on April 17, 2024, and entitled "Display panel and display device", the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0003] The display panel generally includes a plurality of pixel units arranged in an array on a display region of a substrate, and a gate signal line (generally referred to as a Gate trace) for providing a gate driving signal for each pixel unit.

[0004] SUMMARY

[0005] The present application provides a display panel and a display device, and the technical solutions are as follows:

[0006] In one aspect, a display panel is provided, and the display panel includes:

[0007] A substrate includes a display region and a peripheral region surrounding the display region, the display region includes a plurality of pixel light-emitting areas and a plurality of transparent areas, and the plurality of transparent areas includes at least one target transparent area arranged in a first direction.

[0008] A plurality of pixel units are located on the substrate and in the pixel light-emitting areas.

[0009] A plurality of gate signal lines are arranged in a second direction, the second direction intersects the first direction, the gate signal lines include a first portion located in the peripheral region and a second portion located in the display region, the second portion includes a main body portion extending in the first direction, and a bending portion connected to the main body portion, the bending portion is located in the target transparent area, and a path length of the bending portion is greater than a length of the target transparent area in the first direction.

[0010] Optionally, the display panel further includes a protection pattern and a first insulating layer located between the protection pattern and the gate signal lines.

[0011] The protection pattern is located in the target transparent region, the orthographic projection of the bending part on the substrate substrate is located on one side of the orthographic projection of the protection pattern on the substrate substrate, and the orthographic projection of the protection pattern on the substrate substrate and the orthographic projection of the bending part on the substrate substrate partially overlap.

[0012] Optionally, the bending part comprises a first bending part, a second bending part and a third bending part connected in sequence, and the plurality of gate signal lines constitute a plurality of signal line groups, each of the signal line groups comprises two adjacent gate signal lines.

[0013] The first bending part of the two adjacent gate signal lines is located on the side of the protection pattern away from the peripheral region, and the third bending part of the two adjacent gate signal lines is located on the side of the protection pattern close to the peripheral region.

[0014] The orthographic projection of the second bending part of the first gate signal line on the substrate substrate is located on the first side of the orthographic projection of the protection pattern on the substrate substrate, and the orthographic projection of the second bending part of the first gate signal line on the substrate substrate and the orthographic projection of the protection pattern on the substrate substrate partially overlap, the orthographic projection of the second bending part of the second gate signal line on the substrate substrate is located on the second side of the orthographic projection of the protection pattern on the substrate substrate, and the orthographic projection of the second bending part of the second gate signal line on the substrate substrate and the orthographic projection of the protection pattern on the substrate substrate partially overlap; the first side and the second side are two sides of the orthographic projection of the protection pattern on the substrate substrate arranged along the second direction.

[0015] Optionally, the orthographic projection of the bending part of the two gate signal lines on the substrate substrate surrounds the orthographic projection of the protection pattern on the substrate substrate.

[0016] Optionally, the bending part of the two gate signal lines encloses a first annular region.

[0017] The part of the first gate signal line located in the pixel light-emitting region has a second annular region, and the part of the second gate signal line located in the pixel light-emitting region has a third annular region.

[0018] Among them, the area of the first annular region is greater than the area of the second annular region, and greater than the area of the third annular region.

[0019] Optionally, the plurality of target transparent regions comprises a first target transparent region, and the first target transparent region is closer to the peripheral region than the plurality of pixel light-emitting regions.

[0020] For the first annular region surrounded by the bending portions of the two gate signal lines in the first target transparent region, a distance between the first annular region and the pixel light-emitting region is greater than a distance between the first annular region and the peripheral region.

[0021] Optionally, the protection pattern is a strip pattern extending along the second direction, and a length of the protection pattern along the second direction is greater than the distance between the first annular region of the first target transparent region and the pixel light-emitting region.

[0022] Optionally, the plurality of target transparent regions further includes a second target transparent region, and the second target transparent region is located between two adjacent pixel light-emitting regions.

[0023] For the first annular region surrounded by the bending portions of the two gate signal lines in the second target transparent region, distances between the first annular region and the two adjacent pixel light-emitting regions are equal.

[0024] Optionally, a second bending portion of the first gate signal line has a first protrusion on a side close to the protection pattern, and a normal projection of a first end portion of the protection pattern on the substrate and a normal projection of the first protrusion on the substrate overlap.

[0025] A second bending portion of the second gate signal line has a second protrusion on a side close to the protection pattern, and a normal projection of a second end portion of the protection pattern on the substrate and a normal projection of the second protrusion on the substrate overlap.

[0026] Optionally, the display panel includes a pixel unit layer, and the pixel unit layer includes a plurality of pixel units; and the pixel unit layer further includes a semiconductor layer between the substrate and the first insulating layer.

[0027] The protection pattern is located in the semiconductor layer, and a material of the first end portion and the second end portion of the protection pattern is a semiconductor material.

[0028] Optionally, the display panel includes a pixel unit layer, and the pixel unit layer includes a plurality of pixel units; and the pixel unit layer includes a gate layer, a second insulating layer, and a cathode layer which are sequentially stacked in a direction away from the substrate.

[0029] The plurality of gate signal lines are located in the gate layer, and a normal projection of the second insulating layer on the substrate covers normal projections of the plurality of gate signal lines on the substrate and covers a normal projection of the protection pattern on the substrate.

[0030] Optionally, the second insulating layer has a solid material region including an insulating material and a hollow region not including the insulating material.

[0031] The solid material region is located in the pixel light emitting region, and a normal projection of the solid material region on the substrate substrate covers a normal projection of the protection pattern on the substrate substrate, and covers a normal projection of the gate signal line on the substrate substrate.

[0032] The hollow region is located on a side of the normal projection of the gate signal line on the substrate substrate away from the normal projection of the protection pattern on the substrate substrate, between the normal projection of the gate signal line on the substrate substrate and the normal projection of the protection pattern on the substrate substrate, and in other regions of the plurality of transparent regions except the region where the normal projection of the gate signal line on the substrate substrate is located.

[0033] Optionally, the second insulating layer at least includes a first sub-insulating layer and a second sub-insulating layer stacked in sequence in a direction away from the substrate substrate.

[0034] The boundary of the normal projection of the first sub-insulating layer on the substrate substrate and the boundary of the normal projection of the second sub-insulating layer on the substrate substrate do not overlap.

[0035] Optionally, the pixel light emitting region and the transparent region are both strip-shaped regions extending in the second direction, and the plurality of pixel light emitting regions and the plurality of transparent regions are arranged alternately in the first direction; the plurality of transparent regions include two target transparent regions, and the plurality of pixel light emitting regions and the plurality of transparent regions except the two target transparent regions are located between the two target transparent regions.

[0036] The gate signal line includes two bending portions, one of which is connected to one end of the main body portion and located in one of the target transparent regions, and the other of which is connected to the other end of the main body portion and located in the other target transparent region.

[0037] Optionally, the plurality of pixel units are arranged in an array, and the plurality of pixel units include a plurality of first pixel unit groups arranged in the second direction, each of which includes a plurality of pixel units arranged in the first direction.

[0038] Each of the gate signal lines is connected to a plurality of pixel units included in one of the first pixel unit groups, and the plurality of pixel units included in each of the first pixel unit groups are connected to two gate signal lines in one of a plurality of signal line groups formed by the plurality of gate signal lines.

[0039] Optionally, the pixel unit comprises a first group of sub-pixels and a second group of sub-pixels arranged along the second direction, the first group of sub-pixels comprises at least one sub-pixel, and the second group of sub-pixels comprises at least one sub-pixel.

[0040] The main body part of the two gate signal lines connected to the plurality of pixel units in each first pixel unit group is located between the first group of sub-pixels and the second group of sub-pixels.

[0041] Optionally, the main body part comprises a first main channel line and a plurality of first sub-channel lines.

[0042] Both ends of the plurality of first sub-channel lines are connected to the first main channel line, the first main channel line is connected to at least one sub-pixel of the first group of sub-pixels of the plurality of pixel units in one first pixel unit group, and each first sub-channel line is connected to at least one sub-pixel of the second group of sub-pixels of one pixel unit.

[0043] Optionally, the plurality of pixel units comprise a plurality of second pixel unit groups arranged along a first direction, and each second pixel unit group comprises a plurality of pixel units arranged along a second direction.

[0044] The display panel further comprises a plurality of first power lines corresponding to the plurality of second pixel unit groups, and a plurality of auxiliary electrode lines corresponding thereto, each first power line comprises a main power line and a plurality of branch power lines, the plurality of branch power lines are connected to the main power line, the main power line is located on one side of a corresponding second pixel unit group, the first power line is connected to sub-pixels in the plurality of pixel units in the second pixel unit group, and each auxiliary electrode line is located on the other side of a corresponding second pixel unit group and is connected to a cathode layer in the pixel unit.

[0045] For the main power line of one first power line and one auxiliary electrode line corresponding to the second pixel unit group, one connection of the two ends of the first sub-channel line connected to the first main channel line is located on the side of the main power line away from the auxiliary electrode line, and the other connection is located on the side of the auxiliary electrode line away from the main power line.

[0046] Optionally, the plurality of pixel units comprise a plurality of second pixel unit groups arranged along a first direction, and each second pixel unit group comprises a plurality of pixel units arranged along a second direction.

[0047] The display panel comprises a plurality of first power lines corresponding to the plurality of second pixel unit groups, and a plurality of auxiliary electrode lines corresponding thereto, each of the first power lines comprises a main power line and a plurality of branch power lines, the plurality of branch power lines are connected to the main power line, the main power line is located on one side of a corresponding one of the second pixel unit groups, the first power line is connected to a plurality of pixel units in the second pixel unit group, and each of the auxiliary electrode lines is located on the other side of the corresponding one of the second pixel unit groups and connected to a cathode layer in the pixel unit.

[0048] For the main power line of a first power line corresponding to a second pixel unit group and one auxiliary electrode line, both of the two connection points where the first sub-channel line is connected to the first main channel line are located between the main power line and the auxiliary electrode line.

[0049] The main body part further comprises a plurality of second sub-channel lines and a plurality of third sub-channel lines, both ends of the plurality of second sub-channel lines are connected to the first main channel line, the two connection points where the second sub-channel line is connected to the first main channel line are located on both sides of the main power line, both ends of the plurality of third sub-channel lines are connected to the first main channel line, and the two connection points where the third sub-channel line is connected to the first main channel line are located on both sides of the auxiliary electrode line.

[0050] Optionally, the first group of sub-pixels comprises a first sub-pixel and a second sub-pixel, and the second group of sub-pixels comprises a third sub-pixel and a fourth sub-pixel; the display panel further comprises a plurality of data signal line groups corresponding to the plurality of second pixel unit groups, each of the data signal line groups comprises a plurality of data signal lines arranged along a first direction, a target data signal line in the plurality of data signal lines is located between the first sub-pixel and the second sub-pixel and between the third sub-pixel and the fourth sub-pixel, and the target data signal line is at least one of the plurality of data signal lines.

[0051] The branch power line comprises a second main channel line and a fourth sub-channel line, both ends of the fourth sub-channel line are connected to the second main channel line, and the two connection points where the fourth sub-channel line is connected to the second main channel line are located on both sides of the target data signal line.

[0052] Optionally, the data signal line group comprises a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line; the display panel further comprises a sensing signal line.

[0053] The first data signal line, the sensing signal line and the second data signal line are arranged along the first direction and are located between the first sub-pixel and the second sub-pixel and between the third sub-pixel and the fourth sub-pixel, the first data signal line is connected with the first sub-pixel, and the second data signal line is connected with the second sub-pixel;

[0054] The third data signal line is located on one side of the corresponding second pixel unit group and is connected with the third sub-pixel.

[0055] The fourth data signal line is located on the other side of the corresponding second pixel unit group and is connected with the fourth sub-pixel.

[0056] Optionally, the plurality of pixel units comprises a plurality of second pixel unit groups arranged along a first direction, each of the second pixel unit groups comprises a plurality of pixel units arranged along a second direction.

[0057] The display panel further comprises a second power supply line connected with the cathode layer in the pixel unit.

[0058] The main power supply line and the second power supply line have at least one data signal line therebetween.

[0059] Optionally, two gate signal lines in one signal line group formed by the pixel unit and the plurality of signal line groups are connected, the two gate signal lines comprise a first gate signal line and a second gate signal line; the sub-pixel comprises a pixel circuit and a light emitting unit; the pixel circuit comprises:

[0060] A first transistor, a gate of the first transistor is connected with the first gate signal line, a first pole of the first transistor is connected with a data signal line, and a second pole of the first transistor is connected with a first node;

[0061] A second transistor, a gate of the second transistor is connected with the second gate signal line, a first pole of the second transistor is connected with a sensing signal line, and a second pole of the second transistor is connected with a second node;

[0062] A third transistor, a gate of the third transistor is connected with the first node, a first pole of the third transistor is connected with a first power supply line, and a second pole of the third transistor is connected with the second node;

[0063] And a storage capacitor, a first pole of the storage capacitor is connected with the first node, and a second pole of the storage capacitor is connected with the second node.

[0064] Optionally, a distance between the first annular region surrounded by the bending portions of the two gate signal lines included in the second node and signal line group and the pixel light-emitting region is greater than or equal to a distance between the first annular region and the pixel light-emitting region.

[0065] In another aspect, a display device is provided, including a power supply component and a display panel as in the above aspects;

[0066] The power supply component is connected to the display panel and is configured to supply power to the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0068] FIG. 1 is a structural schematic diagram of a display panel according to an embodiment of the present application;

[0069] FIG. 2 is a partial structural schematic diagram of the display panel shown in FIG. 1;

[0070] FIG. 3 is a partial structural schematic diagram of a display panel according to an embodiment of the present application;

[0071] FIG. 4 is a partial structural schematic diagram of another display panel according to an embodiment of the present application;

[0072] FIG. 5 is a schematic diagram of a protection pattern and a bending portion of a gate signal line according to an embodiment of the present application;

[0073] FIG. 6 is a partial structural schematic diagram of yet another display panel according to an embodiment of the present application;

[0074] FIG. 7 is a partial structural schematic diagram of a first sub-insulating layer according to an embodiment of the present application;

[0075] FIG. 8 is a partial structural schematic diagram of a second sub-insulating layer according to an embodiment of the present application;

[0076] FIG. 9 is a partial structural schematic diagram of a first sub-insulating layer and a second sub-insulating layer according to an embodiment of the present application;

[0077] FIG. 10 is a schematic diagram of a pixel unit according to an embodiment of the present application;

[0078] FIG. 11 is an equivalent circuit diagram of a pixel circuit of a sub-pixel according to an embodiment of the present application;

[0079] FIG. 12 is a partial cross-sectional view of a display panel according to an embodiment of the present application;

[0080] FIG. 13 is a partial schematic view of a light shielding layer according to an embodiment of the present application;

[0081] FIG. 14 is a partial schematic view of a semiconductor layer according to an embodiment of the present application;

[0082] FIG. 15 is a partial schematic view of a light shielding layer and a semiconductor layer according to an embodiment of the present application;

[0083] FIG. 16 is a partial schematic view of a gate layer in a display panel according to an embodiment of the present application;

[0084] FIG. 17 is a partial schematic view of a light shielding layer, a semiconductor layer and a gate layer in a display panel according to an embodiment of the present application;

[0085] FIG. 18 is a partial schematic view of an interlayer dielectric layer according to an embodiment of the present application;

[0086] FIG. 19 is a partial schematic view of another interlayer dielectric layer according to an embodiment of the present application;

[0087] FIG. 20 is a partial schematic view of a light shielding layer, a semiconductor layer, a gate layer and an interlayer dielectric layer in a display panel according to an embodiment of the present application;

[0088] FIG. 21 is a partial schematic view of a source-drain layer according to an embodiment of the present application;

[0089] FIG. 22 is a partial schematic view of a light shielding layer, a semiconductor layer, a gate layer, an interlayer dielectric layer and a source-drain layer in a display panel according to an embodiment of the present application;

[0090] FIG. 23 is a partial schematic view of a planarization layer according to an embodiment of the present application;

[0091] FIG. 24 is a partial schematic view of a light shielding layer, a semiconductor layer, a gate layer, an interlayer dielectric layer, a source-drain layer and a planarization layer in a display panel according to an embodiment of the present application;

[0092] FIG. 25 is a partial schematic view of a passivation layer according to an embodiment of the present application;

[0093] FIG. 26 is a partial schematic view of a light shielding layer, a semiconductor layer, a gate layer, an interlayer dielectric layer, a source-drain layer, a passivation layer and a planarization layer in a display panel according to an embodiment of the present application;

[0094] FIG. 27 is a partial schematic view of a first anode film layer in an anode layer according to an embodiment of the present application;

[0095] FIG. 28 is a partial superimposed schematic view of a light shielding layer, a semiconductor layer, a gate layer, an interlayer dielectric layer, a source-drain layer, a passivation layer, a planarization layer, and a first anode film layer in a display panel according to an embodiment of the present application;

[0096] FIG. 29 is a partial schematic view of a second anode film layer in an anode layer according to an embodiment of the present application;

[0097] FIG. 30 is a partial superimposed schematic view of a light shielding layer, a semiconductor layer, a gate layer, an interlayer dielectric layer, a source-drain layer, a passivation layer, a planarization layer, a first anode film layer, and a second anode film layer in a display panel according to an embodiment of the present application;

[0098] FIG. 31 is a partial schematic view of a third anode film layer in an anode layer according to an embodiment of the present application;

[0099] FIG. 32 is a partial superimposed schematic view of a light shielding layer, a semiconductor layer, a gate layer, an interlayer dielectric layer, a source-drain layer, a passivation layer, a planarization layer, a first anode film layer, a second anode film layer, and a third anode film layer in a display panel according to an embodiment of the present application;

[0100] FIG. 33 is a partial schematic view of a pixel definition layer according to an embodiment of the present application;

[0101] FIG. 34 is a partial superimposed schematic view of a light shielding layer, a semiconductor layer, a gate layer, an interlayer dielectric layer, a source-drain layer, a passivation layer, a planarization layer, a first anode film layer, a second anode film layer, a third anode film layer, and a pixel definition layer in a display panel according to an embodiment of the present application;

[0102] FIG. 35 is a schematic view of a water vapor or oxygen intrusion path according to an embodiment of the present application;

[0103] FIG. 36 is a schematic view of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0104] To make the objectives, technical solutions, and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0105] In related technologies, a substrate includes a display area and a peripheral area surrounding the display area. Two ends of a gate signal line are located in the peripheral area and are used to connect a gate driving circuit. A middle portion of the gate signal line is located in the display area and is used to connect a pixel unit. Generally, in order to avoid a large parasitic capacitance caused by a too small distance between the gate signal line and a cathode layer of the pixel unit in a vertical direction, an organic layer needs to be designed between the gate signal line and the cathode layer. Since the organic layer has a certain thickness, the presence of the organic layer can increase the distance between the gate signal line and the cathode layer of the pixel unit in the vertical direction. The vertical direction is perpendicular to a bearing surface of the substrate.

[0106] However, the material for forming the organic layer is generally a hydrophilic material, and the organic layer is in contact with both ends of the gate signal line in the peripheral area, while the organic layer is also in the display area. Therefore, the two ends of the gate signal line in the peripheral area can introduce water vapor or oxygen along the organic layer into the pixel unit, affecting the display effect of the display panel.

[0107] FIG. 1 is a structural schematic diagram of a display panel provided by an embodiment of the present application. FIG. 2 is a partial structural schematic diagram of the display panel shown in FIG. 1. In combination with FIGS. 1 and 2, the display panel 100 includes a substrate 101, a plurality of pixel units 102, and a plurality of gate signal lines 103.

[0108] The substrate 101 includes a display area 101a and a peripheral area 101b surrounding the display area 101a. The display area 101a includes a plurality of pixel light-emitting regions 101a1 and a plurality of transparent regions 101a2. The plurality of transparent regions 101a2 includes at least one target transparent region 101a21 arranged in a first direction X. The target transparent region 101a21 can be located between the peripheral area 101b and the pixel light-emitting region 101a1, or between two adjacent pixel light-emitting regions 101a1.

[0109] The plurality of pixel units 102 are located on the substrate 101 and in the pixel light-emitting regions 101a1, and the pixel units 102 are configured to emit light. Correspondingly, since the transparent regions 101a2 are not provided with the pixel units 102, the transparent regions 101a2 can achieve a certain light transmission effect. Such a display panel 100 can be referred to as a transparent display panel.

[0110] In addition, the plurality of gate signal lines 103 are arranged along a second direction Y. The second direction Y and the first direction X intersect. Optionally, the second direction Y and the first direction X are perpendicular, for example, the first direction X is the pixel row direction of the display panel 100, and the second direction Y is the pixel column direction of the display panel 100.

[0111] Referring to FIG. 2, the gate signal line 103 includes a first part 1031 located in the peripheral area 101b and a second part 1032 located in the display area 101a. The second part 1032 includes a main body part 10321 extending along the first direction X, and a bending part 10322 connected to the main body part 10321. The bending part 10322 is located in the target transparent region 101a21, and the path length of the bending part 10322 is greater than the length of the target transparent region 101a21 in the first direction X.

[0112] In the embodiment of the present application, since the part of the gate signal line 103 located in the target transparent area 101a21 is the bending part 10322, and the path length of the bending part 10322 is relatively long, in the process of water vapor and oxygen invading the pixel unit 102 from the peripheral area 101b along the gate signal line 103, the water vapor and oxygen need to pass through the long transmission path of the bending part 10322 to invade the pixel unit 102, and the invasion path is relatively long. That is, by making the gate signal line 103 include the bending part 10322, the invasion path of water vapor or oxygen invading the pixel unit 102 can be lengthened, the possibility of water vapor or oxygen entering the pixel unit 102 can be reduced, the yield of the display panel 100 can be improved, and the display effect of the display panel 100 can be ensured.

[0113] In summary, the embodiment of the present application provides a display panel, which includes a substrate, a plurality of pixel units, and a plurality of gate signal lines. The gate signal line includes a main body part extending along a first direction, and a bending part connected with the main body part and located in a target transparent area close to a peripheral area in a display area of the substrate. Since the path length of the bending part is relatively long, the invasion path of water vapor or oxygen invading the pixel unit is relatively long, the possibility of water vapor or oxygen entering the pixel unit is effectively reduced, the yield of the display panel is improved, and the display effect of the display panel is ensured.

[0114] FIG. 3 is a schematic diagram of a partial structure of a display panel provided by an embodiment of the present application. Referring to FIG. 3, the display panel further includes a protection pattern 104 and a first insulating layer (not shown in FIG. 3) between the protection pattern 104 and the gate signal line 103. The protection pattern 104 can also be referred to as an electro-static discharge (ESD) structure.

[0115] The protection pattern 104 is located in the target transparent area 101a21, the orthographic projection of the bending part 10322 of the gate signal line 103 on the substrate 101 is located on one side of the orthographic projection of the protection pattern 104 on the substrate 101, and the orthographic projection of the protection pattern 104 on the substrate 101 and the orthographic projection of the bending part 10322 of the gate signal line 103 on the substrate 101 partially overlap. (The overlap is not shown in FIG. 3).

[0116] The protection pattern 104 is configured to protect the gate signal line 103 from a voltage that is too high to affect the yield of the gate signal line 103. If the protection pattern 104 is arranged in the peripheral area 101b, the frame width of the display panel 100 is wide. Therefore, in the embodiment, the protection pattern 104 is arranged in the target transparent area 101a21 of the display area 101a, and does not occupy the peripheral area 101b. Therefore, the frame width of the display panel 100 can be reduced, and the narrow frame product can be implemented.

[0117] The bending part 10322 of the gate signal line 103 includes a first bending part 103221, a second bending part 103222 and a third bending part 103223 connected in sequence. The plurality of gate signal lines 103 form a plurality of signal line groups 103a, and each signal line group 103a includes two gate signal lines 103.

[0118] The first bending part 103221 of the two gate signal lines 103 is located on the side of the protection pattern 104 away from the peripheral area 101b. The third bending part 103223 of the two gate signal lines 103 is located on the side of the protection pattern 104 close to the peripheral area 101b.

[0119] The second bending part 103222 of one of the two gate signal lines 103 is located on the first side of the projection of the protection pattern 104 on the substrate 101. The second bending part 103222 of the other of the two gate signal lines 103 is located on the second side of the projection of the protection pattern 104 on the substrate 101. The first side and the second side are two sides of the projection of the protection pattern 104 on the substrate 101 arranged along the second direction Y.

[0120] That is, in the embodiment, the bending part 10322 of the gate signal line 103 and the protection pattern 104 are both arranged in the target transparent area 101a21. In order to implement the design of the bending part 10322 of the gate signal line 103 and the protection pattern 104, the bending part 10322 needs to bypass the protection pattern 104 from the side of the protection pattern 104 close to the peripheral area 101b and then connect with the pixel unit 102 of the display area 101a.

[0121] Optionally, the normal projection on the substrate 101 of the protection pattern 104 surrounding the normal projection on the substrate 101 of the bending part 10322 of the two gate signal lines 103 included in each signal line group 103a. In this case, the path length of each bending part 10322 can be greater than or equal to half of the circumference of the protection pattern 104. Such a design can maximize the path length of the bending part 10322 and prolong the intrusion path of water vapor or oxygen into the pixel unit 102.

[0122] In the embodiments of the present application, the bending part 10322 of the two gate signal lines 103 included in each signal line group 103a can enclose a first annular region H1. Wherein, the following embodiments of the present application are all examples with the first annular region H1 being a non-closed annular region. Of course, it can also be a closed annular region, which is not limited in the embodiments of the present application.

[0123] Referring to FIG. 4, the two gate signal lines 103 include a first gate signal line 103a1 and a second gate signal line 103a2. The first gate signal line 103a1 has a second annular region H2 in the part located in the pixel light-emitting area 101a1, and the second gate signal line 103a2 has a third annular region H3 in the part located in the pixel light-emitting area 101a1.

[0124] Wherein, the area of the first annular region H1 is greater than the area of the second annular region H2, and greater than the area of the third annular region H3. That is, the area of the first annular region H1 can be larger, and thus the bending part 10322 of the two gate signal lines 103 enclosing the first annular region H1 can be as long as possible, increasing the intrusion path of water vapor or oxygen.

[0125] In the embodiments of the present application, the plurality of target transparent regions 101a21 includes a first target transparent region 101a211. The first target transparent region 101a211 is closer to the peripheral region 101b than the plurality of pixel light-emitting areas 101a1. For example, the number of the first target transparent region 101a211 can be two, and the two first target transparent regions 101a211 can refer to the two most edge transparent regions (such as the leftmost and rightmost) in the plurality of transparent regions 101a2 in the first direction X, and any one of the two transparent regions is close to the side of the peripheral region without the pixel light-emitting area 101a1.

[0126] Further, the plurality of target transparent regions 101a21 also includes a second target transparent region 101a212. The second target transparent region 101a212 can be located between two adjacent pixel light-emitting areas 101a1. For example, the second target transparent region 101a212 can be a transparent region in the plurality of transparent regions 101a2 having one or more pixel light-emitting areas 101a1 between the first target transparent region 101a211.

[0127] For the first annular region surrounded by the first target transparent area 101a211 of the bending portion 10322 of the two gate signal lines 103, the distance d1 between the first annular region and the pixel light-emitting area 101a1 is greater than the distance d2 between the first annular region and the peripheral area 101b (see FIG. 27 described below). Such a design can avoid the bending portion 10322 from having a greater impact on the normal light emission of the pixel light-emitting area 101a1.

[0128] For the first annular region surrounded by the second target transparent area 101a212 of the bending portion 10322 of the two gate signal lines 103, the first annular region is located between two pixel light-emitting areas, and the distance between the first annular region and the two pixel light-emitting areas is equal. Such a design can make the impact of the bending portion 10322 on the two pixel light-emitting areas 101a consistent, thereby improving the display uniformity of the two pixel light-emitting areas 101a1.

[0129] In the embodiments of the present application, the protection pattern 104 can be a strip pattern extending along the second direction Y. The length d3 of the protection pattern 104 along the second direction Y is greater than the distance d1 between the first annular region H1 of the first target transparent area 101a211 and the pixel light-emitting area 101a1. That is, the length of the protection pattern 104 can be longer, thereby avoiding the protection pattern 104 from being broken down at a lower voltage to cause panel failure.

[0130] FIG. 5 is a schematic view of a protection pattern and a bending portion of a gate signal line according to an embodiment of the present application. Referring to FIG. 5, the second bending portion 103222 of one of the two gate signal lines 103 included in the signal line group 103a has a first protrusion A1 on a side close to the protection pattern 104. The orthographic projection of the first end of the protection pattern 104 on the substrate 101 overlaps the orthographic projection of the first protrusion A1 on the substrate 101. The second bending portion 103222 of the other of the two gate signal lines 103 included in the signal line group 103a has a second protrusion A2 on a side close to the protection pattern 104. The orthographic projection of the second end of the protection pattern 104 on the substrate 101 overlaps the orthographic projection of the second protrusion A2 on the substrate 101.

[0131] In the embodiments of the present application, since the first protrusion A1 and the second protrusion A2 both overlap with the protection pattern 104, the first protrusion A1 and the second protrusion A2 can realize electrical connection through the protection pattern 104 in the case of high voltage. For example, for two gate signal lines 103 in each signal line group 103a, when the voltage of one of the two gate signal lines 103 is high, the protrusion of the second bending part 103222 of the gate signal line 103 and the protection pattern 104 overlap, so the gate signal line 103 and the protection pattern 104 can be connected, and then the voltage can be transmitted to the other gate signal line 103 through the protection pattern 104. That is, through the arrangement of the protection pattern 104, the voltage of the two gate signal lines 103 can be balanced, and the yield of the two gate signal lines 103 can be ensured.

[0132] In the embodiments of the present application, the display panel 100 includes a pixel unit layer including a plurality of pixel units 102. The pixel unit layer further includes a semiconductor layer between the substrate 101 and a first insulating layer (the first insulating layer can be a gate insulating layer described later). The protection pattern 104 can be located in the semiconductor layer. The materials of the first end part and the second end part of the protection pattern 104 can be semiconductor materials. In addition, the material of the part between the first end part and the second end part of the protection pattern 104 can be a conductor material.

[0133] That is, in the conventional case, the first insulating layer between the gate signal line 103 and the protection pattern 104 realizes insulation. In the case of high voltage in the gate signal line 103, the semiconductor material of the first end part and the second end part of the protection pattern 104 can connect the protection pattern 104 and the gate signal line 103.

[0134] In the embodiments of the present application, the pixel unit layer N can include a gate layer, a second insulating layer and a cathode layer which are stacked in sequence in the direction away from the substrate 101. The plurality of gate signal lines 103 can be located in the gate layer. The second insulating layer has a normal projection on the substrate 101 covering the normal projection of the plurality of gate signal lines 103 on the substrate 101 and covering the normal projection of the protection pattern 104 on the substrate 101.

[0135] Generally, the cathode layer included in the pixel unit layer N is an integral film layer. If the second insulating layer is not designed between the gate signal line 103 or the protection pattern 104 and the cathode layer, the distance between the gate signal line 103 and the protection pattern 104 and the cathode layer in the direction perpendicular to the substrate 101 will be too close, which can easily generate a large parasitic capacitance, affecting the display stability of the display panel 100.

[0136] For the above reasons, by designing the second insulating layer between the gate signal line 103 and the protective pattern 104 and the cathode layer, the distance between the gate signal line 103 and the cathode layer in the direction perpendicular to the substrate 101 can be increased, and the distance between the protective pattern 104 and the cathode layer in the direction perpendicular to the substrate 101 can be increased. Thus, the parasitic capacitance between the gate signal line 103 and the cathode layer can be avoided, and the parasitic capacitance between the protective pattern 104 and the cathode layer can be avoided, and the display stability of the display panel 100 can be improved.

[0137] Optionally, the material of the cathode layer can be indium zinc oxide (IZO), and the preparation process can be sputtering. If the second insulating layer is not designed between the gate signal line 103 and the protective pattern 104 and the cathode layer, the gate signal line 103 and the protective pattern 104 will be at risk of static electricity during the preparation of the cathode layer.

[0138] FIG. 6 is a partial schematic view of another display panel provided by an embodiment of the present application. Referring to FIG. 6, the second insulating layer has a solid material area S including insulating material, and a hollow area W not including insulating material.

[0139] The solid material area S is located in the pixel light emitting area 101a1, and the orthographic projection of the solid material area S on the substrate 101 covers the orthographic projection of the protective pattern 104 on the substrate 101 and the orthographic projection of the gate signal line 103 on the substrate 101. Since the pixel light emitting area 101a1 is designed with the solid material area S of the second insulating layer, the related film layers of the pixel unit 102 in the pixel light emitting area 101a1 can be insulated. Since the gate signal line 103 and the protective pattern 104 are designed with the solid material area S of the second insulating layer, the distance between the gate signal line 103 (the protective pattern 104) and the cathode layer in the direction perpendicular to the substrate 101 can be increased, and the parasitic capacitance can be reduced.

[0140] In addition, the hollow area W of the second insulating layer can be located on the side of the orthographic projection of the gate signal line 103 on the substrate 101 away from the orthographic projection of the protective pattern 104 on the substrate 101, between the orthographic projection of the gate signal line 103 on the substrate 101 and the orthographic projection of the protective pattern 104 on the substrate 101, and in other areas of the plurality of transparent areas 101a2 except the area where the orthographic projection of the gate signal line 103 on the substrate 101 is located. That is, in addition to the pixel light emitting area 101a1, other areas designed with the protective pattern 104 and the gate signal line 103 can be the hollow area W.

[0141] It should be noted that the display panel 100 provided in the embodiments of the present application can be a transparent display panel. Since the display panel includes a large number of film layers, and each film layer will have a certain impact on the transparency of the display panel 100, in order to reduce the impact of the second insulating layer on the transparency of the display panel, the second insulating layer can have the hollowed-out area W, thereby reducing the number of film layers stacked in the display panel 100 and ensuring the transparent display effect of the display panel 100.

[0142] Optionally, referring to FIGS. 7-9, the second insulating layer includes at least a first sub-insulating layer Z1 and a second sub-insulating layer Z2 stacked in sequence in a direction away from the substrate substrate 101. The boundary of the orthographic projection of the first sub-insulating layer Z1 on the substrate substrate 101 and the boundary of the orthographic projection of the second sub-insulating layer Z2 on the substrate substrate 101 do not overlap. The boundary of the orthographic projection of the first sub-insulating layer Z1 on the substrate substrate 101 and the boundary of the orthographic projection of the second sub-insulating layer Z2 on the substrate substrate 101 do not overlap can mean that the boundary of the orthographic projection of the solid material area of the first sub-insulating layer Z1 on the substrate substrate 101 and the boundary of the orthographic projection of the solid material area of the second sub-insulating layer Z1 on the substrate substrate 101 do not overlap, and the boundary of the orthographic projection of the hollowed-out area of the first sub-insulating layer Z1 on the substrate substrate 101 and the boundary of the orthographic projection of the hollowed-out area of the second sub-insulating layer Z1 on the substrate substrate 101 do not overlap.

[0143] For example, the first sub-insulating layer Z1 can be a resin included in the display panel 100, and the second sub-insulating layer Z2 can be a pixel definition layer (PDL) included in the display panel 100. Since the boundaries of the two sub-insulating layers are not overlapped, the step difference of the film layer at the boundary of the sub-insulating layer can be avoided to affect the preparation of the cathode layer, and the cathode layer can be avoided to be broken.

[0144] In the embodiments of the present application, referring to FIG. 1, the pixel light-emitting area 101a1 and the transparent area 101a2 are both strip-shaped areas extending in the second direction Y. The plurality of pixel light-emitting areas 101a1 and the plurality of transparent areas 101a2 are arranged alternately in the first direction X. The plurality of transparent areas 101a2 include two target transparent areas 101a21. The transparent areas 101a2 other than the two target transparent areas 101a21 among the plurality of pixel light-emitting areas 101a1 and the plurality of transparent areas 101a2 are located between the two target transparent areas 101a21. That is, the areas on both sides of the display area 101a in the first direction X closest to the peripheral area 101b are both transparent areas 101a2.

[0145] The gate signal line 103 includes two bending portions 10322, one of which is connected with one end of the main body portion 10321 and located in one target transparent area 101a21, and the other of which is connected with the other end of the main body portion 10321 and located in the other target transparent area 101a21. That is, the two ends of the gate signal line 103 in the first direction X can be substantially symmetrical.

[0146] In the embodiment of the present application, each pixel unit 102 can be connected with two gate signal lines 103 in one signal line group 103a of a plurality of signal line groups 103a formed by a plurality of gate signal lines 103. The two gate signal lines 103 include a first gate signal line 103a1 and a second gate signal line 103a2. Referring to FIG. 10, each pixel unit 102 in the plurality of pixel units 102 included in the display panel 100 can include a plurality of sub-pixels 1021, and each sub-pixel 1021 can include a pixel circuit 10211 and a light emitting unit 10212.

[0147] For example, the plurality of sub-pixels 1021 included in each pixel unit 102 can include a red sub-pixel (red, R), a green sub-pixel (green, G), and a blue sub-pixel (blue, B). Further, the plurality of sub-pixels 1021 included in each pixel unit 102 can also include a white sub-pixel (white, W). The pixel unit shown in FIG. 10 includes four sub-pixels 1021.

[0148] For each sub-pixel 1021, the pixel circuit 10211 in the sub-pixel 1021 can be connected with the light emitting unit 10212 to provide a driving signal for the light emitting unit 10212. The light emitting unit 10212 is configured to emit light under the driving of the driving signal.

[0149] Optionally, the pixel circuit 10211 can include a plurality of thin film transistors (TFT) and at least one storage capacitor. For example, the pixel circuit 10211 in the embodiment of the present application includes 3 thin film transistors and 1 storage capacitor, that is, the pixel circuit 10211 can be a 3T1C pixel circuit. Alternatively, the pixel circuit 10211 can include other numbers of thin film transistors and other numbers of storage capacitors C. The number of thin film transistors included in the pixel circuit 10211 and the number of storage capacitors C included in the pixel circuit 10211 are not limited in the embodiment of the present application.

[0150] Each thin film transistor includes a gate, a source and a drain. The plurality of thin film transistors included in the pixel circuit 10211 are connected with each other to achieve the function of driving the light emitting unit 10212 to emit light.

[0151] FIG. 11 is an equivalent circuit diagram of a pixel circuit of a sub-pixel provided in an embodiment of the present application. Referring to FIG. 11, the pixel circuit 10211 includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor C.

[0152] The gate of the first transistor T1 is connected with a first gate signal line 103a1, the first electrode of the first transistor T1 is connected with a data signal line, and the second electrode of the first transistor T1 is connected with a first node J1.

[0153] The gate of the second transistor T2 is connected with a second gate signal line 103a2, the first electrode of the second transistor T2 is connected with a sensing signal line, and the second electrode of the second transistor T2 is connected with a second node J2.

[0154] The gate of the third transistor T3 is connected with the first node J1, the first electrode of the third transistor T3 is connected with a first power supply line 105, and the second electrode of the third transistor T3 is connected with the second node J2.

[0155] The first electrode of the storage capacitor C is connected with the first node J1, and the second electrode of the storage capacitor C is connected with the second node J2.

[0156] In the embodiment of the present application, the second transistor T2 can be referred to as a sensing transistor. The third transistor T3 can be referred to as a driving transistor. The sensing transistor is connected with the second node J2, and the driving transistor is also connected with the second node J2. The sensing transistor is used to reset the initial potential of the second node J2, and to detect the threshold voltage of the driving transistor in real time, so that the initial potential of the second electrode of the driving transistor can be kept stable, and after the threshold voltage of the driving transistor is detected, the threshold voltage of the driving transistor can be compensated, so that the luminous brightness of the light emitting unit 10212 is not affected by the threshold voltage of the driving transistor, and the luminous brightness of the light emitting unit 10212 is kept stable.

[0157] In the embodiment of the present application, the second node J2 can be a lap joint point of the pixel circuit 10211 and the anode pattern of the light emitting unit 10212. That is, the second node J2 is also connected with the anode pattern of the light emitting unit 10212.

[0158] Optionally, the distance between the second node J2 and the first annular region is greater than or equal to the distance between the first annular region and the pixel light emitting region. That is, the distance between the lap joint point and the first annular region can be large, thereby avoiding the water vapor or oxygen in the first annular region from entering the lap joint point and affecting the performance of the light emitting unit.

[0159] For the first target transparent area 101a211, the number of pixel light-emitting areas 101a1 adjacent to the first target transparent area 101a211 is one. Thus, for the first annular area of the first target transparent area 101a211, the distance between the second node J2 and the first annular area is greater than or equal to the distance between the first annular area and the adjacent pixel light-emitting area.

[0160] For the second target transparent area 101a212, the number of pixel light-emitting areas 101a1 adjacent to the second target transparent area 101a212 is two. Thus, for the first annular area H1 of the second target transparent area 101a212, the distance between the second node J2 and the first annular area is greater than or equal to the distance between the first annular area and any adjacent pixel light-emitting area.

[0161] Embodiments of the present application take the pixel unit 102 as an example, which includes one red sub-pixel, one green sub-pixel, one blue sub-pixel and one white sub-pixel, and each sub-pixel 1021 includes three thin film transistors and one storage capacitor C. In combination with FIG. 1 and FIG. 11, the plurality of pixel units 102 are arranged in an array, and the plurality of pixel units 102 include a plurality of first pixel unit groups 102a arranged along the second direction Y, each first pixel unit group 102a including a plurality of pixel units 102 arranged along the first direction X. Each first pixel unit group 102a includes a plurality of pixel units 102 arranged along the first direction X.

[0162] Each gate signal line 103 is connected to the plurality of pixel units 102 included in one first pixel unit group 102a, and the plurality of pixel units 102 included in each first pixel unit group 102a are connected to two gate signal lines 103 in one signal line group 103a formed by the plurality of gate signal lines 103.

[0163] The first pixel unit group 102a can refer to a row of pixel units, and each row of pixel units 102 can correspond to two gate signal lines 103 in one signal line group 103a. As shown in FIG. 11, the first transistor T1 of the pixel circuit 10211 is connected to the first gate signal line 103a1 in the signal line group 103a, and the second transistor T2 of the pixel circuit 10211 is connected to the second gate signal line 103a2 in the signal line group 103a.

[0164] In the embodiment of the present application, referring to FIG. 10, in order to facilitate the connection of each sub-pixel 1021 in the pixel unit 102 and the signal line group 103a, the pixel unit 102 can include a first group of sub-pixels 1021a and a second group of sub-pixels 1021b arranged along the second direction Y. The first group of sub-pixels 1021a includes at least one sub-pixel 1021, and the second group of sub-pixels 1021b includes at least one sub-pixel 1021. For example, the first group of sub-pixels 1021a and the second group of sub-pixels 1021b in FIG. 10 each include two sub-pixels 1021. The embodiment of the present application takes an example in which the first group of sub-pixels 1021a includes a red sub-pixel and a blue sub-pixel, and the second group of sub-pixels 1021b includes a white sub-pixel and a green sub-pixel.

[0165] Optionally, each sub-pixel 1021 in each pixel unit 102 needs to be connected to two gate signal lines 103 in the signal line group 103a corresponding to the pixel unit 102. For example, the white sub-pixel needs to be connected to the first gate signal line 103a1 and the second gate signal line 103a2, the green sub-pixel needs to be connected to the first gate signal line 103a1 and the second gate signal line 103a2, the red sub-pixel needs to be connected to the first gate signal line 103a1 and the second gate signal line 103a2, and the blue sub-pixel needs to be connected to the first gate signal line 103a1 and the second gate signal line 103a2.

[0166] In order to facilitate the connection of each sub-pixel 1021 and the two gate signal lines 103 in the signal line group 103a, referring to FIG. 11, the main body part 10321 of the two gate signal lines 103 connected by the plurality of pixel units 102 included in each first pixel unit group 102a can be located between the first group of sub-pixels 1021a and the second group of sub-pixels 1021b.

[0167] In addition, referring to FIG. 11, the main body part 10321 of the gate signal line 103 includes a first main channel line 103211 and a plurality of first auxiliary channel lines 103212. Both ends of the plurality of first auxiliary channel lines 103212 are connected to the first main channel line 103211. Each first auxiliary channel line 103212 and the first main channel line 103211 can form a ring-shaped area around the pixel light-emitting area 101a1.

[0168] For example, for the first gate signal line 103a1 in FIG. 11, the first sub-channel line 103212 and the first main-channel line 103211 can enclose a second annular area H2 around the pixel light-emitting area 101a1. For the second gate signal line 103a2 in FIG. 11, the first sub-channel line 103212 and the first main-channel line 103211 can enclose a third annular area H3 around the pixel light-emitting area 101a1. Referring to FIG. 11, the shapes and sizes of the second annular area H2 and the third annular area H3 can be different, of course, can also be the same, and the embodiments of the present application do not limit this.

[0169] Referring to FIG. 11, the first main-channel line 103211 of the gate signal line 103 is connected to the sub-pixels 1021 in the first group of sub-pixels 1021a of the plurality of pixel units 102 in the first pixel unit group 102a, and each first sub-channel line 103212 is connected to the sub-pixels 1021 in the second group of sub-pixels 1021b of a pixel unit 102.

[0170] For example, for the first gate signal line 103a1 in FIG. 11, the first main-channel line 103211 is closer to the first group of sub-pixels 1021a than the first sub-channel line 103212, and the first main-channel line 103211 can be connected to the red sub-pixels and the blue sub-pixels in the first group of sub-pixels 1021a. The first sub-channel line 103212 is closer to the second group of sub-pixels 1021b than the first main-channel line 103211, and the first sub-channel line 103212 can be connected to the white sub-pixels and the green sub-pixels in the second group of sub-pixels 1021b.

[0171] Similarly, for the second gate signal line 103a2 in FIG. 11, the first main-channel line 103211 is closer to the first group of sub-pixels 1021a than the first sub-channel line 103212, and the first main-channel line 103211 can be connected to the red sub-pixels and the blue sub-pixels in the first group of sub-pixels 1021a. The first sub-channel line 103212 is closer to the second group of sub-pixels 1021b than the first main-channel line 103211, and the first sub-channel line 103212 can be connected to the white sub-pixels and the green sub-pixels in the second group of sub-pixels 1021b.

[0172] Since the gate signal line 103 includes two channels, in the case that one of the channel lines of the gate signal line 103 and other signal lines are in short circuit, this channel line can be directly cut off. This will only affect the light-emitting of the sub-pixels 1021 connected to this channel line, and will not have any effect on other sub-pixels 1021, thereby maximizing the display effect of the display panel 100.

[0173] It should be noted that when cutting off the channel line, the first sub-channel line 103212 can be cut off at a position between the two ends of the first sub-channel line 103212 and the two connection points connected with the first main channel line 103211. If a short circuit occurs in the first sub-channel line 103212, the gate signal line 103 can transmit signals to the adjacent pixel unit 102 in the first direction X along the first main channel line 103211 by cutting off the first sub-channel line 103212 at any position between the two ends of the first sub-channel line 103212. If a short circuit occurs in the first main channel line 103211, the gate signal line 103 can transmit signals to the adjacent pixel unit 102 in the first direction X along the first sub-channel line 103212 by cutting off the first main channel line 103211 at any position between the two connection points.

[0174] In the embodiment of the present application, referring to FIG. 1, the plurality of pixel units 102 includes a plurality of second pixel unit groups 102b arranged in the first direction X. Each second pixel unit group 102b includes a plurality of pixel units 102 arranged in the second direction Y.

[0175] Further, the display panel 100 includes a plurality of first power lines 105 (may also be referred to as VDD traces) corresponding to the plurality of second pixel unit groups 102b, and a plurality of auxiliary electrode lines 106 corresponding thereto. One pixel unit 102, one first power line 105 and one auxiliary electrode line 106 are shown in FIG. 11.

[0176] Referring to FIG. 11, each first power line 105 includes a main power line 1051 and a plurality of branch power lines 1052. The plurality of branch power lines 1052 are connected with the main power line 1051. The main power line 1051 is located on one side of the corresponding second pixel unit group 102b, such as the left side of the second pixel unit group 102b in FIG. 11. The first power line 105 is connected with the sub-pixels 1021 in the plurality of pixel units 102 in the corresponding second pixel unit group 102b. That is, the first power line 105 provides a first power signal for each sub-pixel 1021 in the pixel unit 102 in the corresponding second pixel unit group 102b.

[0177] For example, the pixel unit 102 in FIG. 11 includes a first group of sub-pixels 1021a and a second group of sub-pixels 1021b, a total of two groups of sub-pixels. For each pixel unit 102, the pixel unit 102 corresponds to two branch power lines 1052, one branch power line 1052 is connected with the sub-pixels 1021 in the first group of sub-pixels 1021a, and the other branch power line 1052 is connected with the sub-pixels 1021 in the second group of sub-pixels 1021b.

[0178] In addition, each auxiliary electrode line 106 is located on the other side of the corresponding second pixel unit group 102b, such as the right side of the second pixel unit group 102b in FIG. 11. The auxiliary electrode line 106 can be connected with the cathode layer in the pixel unit 102.

[0179] As shown in FIG. 11, for the main power line 1051 of the first power line 105 corresponding to the second pixel unit group 102b and one auxiliary electrode line 106, one of the two connection points of the first sub-channel line 103212 of the first gate signal line 103al and the first main channel line 103211 is located on the side of the main power line 1051 away from the auxiliary electrode line 106, and the other connection point is located on the side of the auxiliary electrode line 106 away from the main power line 1051.

[0180] That is, in the area where the main power line 1051, the auxiliary electrode line 106, and other signal lines are located, the first gate signal line 103al has both the first main channel line 103211 and the first sub-channel line 103212. Since the main power line 1051, the auxiliary electrode line 106, and other signal lines can be short-circuited with the first gate signal line 103al, the double-channel design can effectively avoid short-circuiting.

[0181] As shown in FIG. 11, for the main power line 1051 of the first power line 105 corresponding to the second pixel unit group 102b and one auxiliary electrode line 106, the two connection points of the first sub-channel of the second gate signal line 103a2 and the first main channel line 103211 are both located between the main power line 1051 and the auxiliary electrode line 106.

[0182] That is, in the area where the main power line 1051 and the auxiliary electrode line 106 are located, the gate signal line 103 is designed as a single channel, and in the area where other signal lines are located between the main power line 1051 and the auxiliary electrode line 106, the gate signal line 103 can be designed as a double channel. In this way, if short-circuiting occurs between the gate signal line 103 and the main power line 1051 or the auxiliary electrode line 106, there is no way to avoid short-circuiting by cutting off one of the channels.

[0183] Thus, referring to FIG. 11, the main body portion 10321 further includes a plurality of second sub-channel lines 103213 and a plurality of third sub-channel lines 103214. The two ends of the plurality of second sub-channel lines 103213 are connected to the first main channel line 103211, and the two connection positions of the second sub-channel lines 103213 to the first main channel line 103211 are located on both sides of the main power line 1051. The two ends of the plurality of third sub-channel lines 103214 are connected to the first main channel line 103211, and the two connection positions of the third sub-channel lines 103214 to the first main channel line 103211 are located on both sides of the auxiliary electrode line 106.

[0184] That is, for the second gate signal line 103a2 shown in FIG. 11, the second sub-channel line 103213 and the third sub-channel line 103214 need to be additionally designed, so that the area where the main power line 1051 is located and the area where the auxiliary electrode line 106 is located are also designed as double-channel. In this way, in the case of short circuit between the gate signal line 103 and the main power line 1051, the short circuit can be avoided by cutting off the second sub-channel line 103213, or cutting off the part of the first main channel line 103211 between the two connection positions connected to the second sub-channel line 103213. In the case of short circuit between the gate signal line 103 and the auxiliary electrode line 106, the short circuit can be avoided by cutting off the third sub-channel line 103214, or cutting off the part of the first main channel line 103211 between the two connection positions connected to the third sub-channel line 103214.

[0185] In the embodiment of the present application, referring to FIG. 11, the display panel 100 further includes a plurality of data line groups 107 corresponding to the plurality of second pixel unit groups 102b. The data line group 107 includes a plurality of data signal lines arranged along the first direction X. The plurality of data signal lines all extend along the second direction Y.

[0186] Among them, in order to facilitate the layout design, part of the plurality of data signal lines included in the data line group 107 can be designed between the first sub-pixel 1021a1 and the second sub-pixel 1021a2, and between the third sub-pixel 1021b1 and the fourth sub-pixel 1021b2. In addition to the data signal lines designed in the middle, other data lines can be designed on both sides of the pixel unit 102.

[0187] For example, the pixel unit 102 of the embodiment of the present application has four different sub-pixels 1021, and the corresponding data line group 107 can include four data signal lines. Two of the data signal lines (which can be referred to as target data lines) can be located between the first sub-pixel 1021a1 and the second sub-pixel 1021a2, and between the third sub-pixel 1021b1 and the fourth sub-pixel 1021b2. One of the other two data signal lines is located on the side of the first sub-pixel 1021a1 away from the second sub-pixel 1021a2, and on the side of the third sub-pixel 1021b1 away from the fourth sub-pixel 1021b2. The other of the other two data signal lines is located on the side of the second sub-pixel 1021a2 away from the first sub-pixel 1021a1, and on the side of the fourth sub-pixel 1021b2 away from the third sub-pixel 1021b1.

[0188] Specifically, it is assumed that the four data signal lines included in the data line group 107 are a first data signal line (Data_R), a second data signal line (Data_B), a third data signal line (Data_w), and a fourth data signal line (Data_G).

[0189] The first data signal line (Data_R), the sense signal line (sense), and the second data signal line are arranged along the first direction X, and are all located between the first sub-pixel 1021a1 and the second sub-pixel 1021a2, and between the third sub-pixel 1021b1 and the fourth sub-pixel 1021b2. The first data signal line (Data_R) is connected to the first sub-pixel 1021a1, and is used to provide a data driving signal for the first sub-pixel 1021a1. The second data signal line (Data_B) is connected to the second sub-pixel 1021a2, and is used to provide a data driving signal for the second sub-pixel 1021a2.

[0190] The third data signal line (Data_w) is located on the side of the corresponding second pixel unit group 102b, and is connected to the third sub-pixel 1021b1, and is used to provide a data driving signal for the third sub-pixel 1021b1.

[0191] The fourth data signal line (Data_G) is located on the other side of the corresponding second pixel unit group 102b, and is connected to the fourth sub-pixel 1021b2, and is used to provide a data driving signal for the fourth sub-pixel 1021b2.

[0192] In addition, the sense signal line (sense) can be connected to the first sub-pixel 1021a1, the second sub-pixel 1021a2, the third sub-pixel 1021b1, and the fourth sub-pixel 1021b2, to provide a sense signal for the four sub-pixels 1021.

[0193] In the embodiment of the present application, since each first power supply line 105 needs to provide a first power supply signal for each sub-pixel 1021 in the plurality of pixel units 102 in the second pixel unit group 102b, the branch power supply line 1052 of the first power supply line 105 needs to cross the target data signal line and the sense signal line, and be connected to the sub-pixels 1021 on both sides of the target data signal line and the sense signal line.

[0194] Since a short circuit can also occur between the first power supply line 105 and the target data signal line and the sense signal line, the possibility of short circuit can also be reduced by the double-channel design.

[0195] Optionally, the branch power supply line 1052 includes a second main channel line 10521 and a fourth sub-channel line 10522. The two ends of the fourth sub-channel line 10522 are connected to the second main channel line 10521, and the two connection points of the fourth sub-channel line 10522 and the second main channel line 10521 are located on both sides of the target data signal line. That is, the first power supply line 105 is double-channel in the area where the target data signal line is located, and in the area where the sense signal line is located.

[0196] If one of the channel lines of the branch power supply line 1052 is in a short circuit state with the target data signal line (or the sense signal line), the channel line can be directly cut off. Since the other channel line is still conductive, it will not affect the transmission of the first power supply signal by the first power supply line 105.

[0197] It should be noted that when cutting off the channel line, the part between the two connection points of the two ends of the second sub-channel line 103213 and the fourth sub-channel line 10522 can be cut off. If the fourth sub-channel line 10522 is short-circuited, the fourth sub-channel line 10522 can be cut off at any position between the two ends of the fourth sub-channel line 10522, and the first power supply line 105 can transmit the first power supply signal to the sub-pixel 1021 along the second main channel line 10521. If the second main channel line 10521 is short-circuited, the second main channel line 10521 can be cut off at any position between the two connection points, and the gate signal line 103 can transmit the first power supply signal to the sub-pixel 1021 along the fourth sub-channel line 10522.

[0198] In the embodiment of the present application, the auxiliary electrode line in the display panel 100 can be a second power supply line (VSS trace), which can be connected with the cathode layer in the pixel unit 102 to provide a second power supply signal for the cathode layer. Optionally, at least one data signal line is provided between the main power supply line 1051 and the second power supply line. Since the potential difference between the first power supply line 105 and the second power supply line is relatively large, in order to avoid short circuit between the first power supply line 105 and the second power supply line, at least one data signal line can be designed between the first power supply line 105 and the second power supply line.

[0199] FIG. 12 is a partial cross-sectional view of a display panel according to an embodiment of the present application. As shown in FIG. 12, the display panel 10 can include a pixel unit layer N on the substrate 101. The pixel unit layer N includes a pixel circuit 10211 of a plurality of sub-pixels 1021, and a light emitting unit 10212 of the plurality of sub-pixels 1021.

[0200] Optionally, the pixel unit layer N includes, and is sequentially stacked in a direction away from the substrate 101, a light shielding layer n1, a buffer layer n2, a semiconductor layer n3, a gate insulator (GI) n4, a gate layer n5, an inter level dielectric (ILD) n6, a source-drain layer n7, a passivation layer (PVX) n8, a planarization layer (PLN) n9, an anode layer n10, a pixel defining layer n11, a light emitting layer n12, and a cathode layer n13. The protection pattern 104 can be located in the semiconductor layer, and the gate signal line 103 can be located in the gate layer.

[0201] Optionally, the anode layer n10 can include a first anode film layer n10a, a second anode film layer n10b, and a third anode film layer n10c which are sequentially stacked. The materials of the first anode film layer n10a and the second anode film layer n10b can be indium tin oxide (ITO), and the material of the third anode film layer n10c can include indium tin oxide (ITO) and copper (Cu). The third anode film layer n10c is specifically referred to as a reflective anode film layer.

[0202] It should be noted that FIG. 12 is only used to show the stacking relationship of each film layer, and is not used to represent the cross-sectional view of a specific part of the display panel and the connection relationship of the transistors of the pixel circuit 10211 in the display panel. FIG. 12 shows one thin film transistor and one storage capacitor C, and the storage capacitor C includes a first capacitor plate C1 located in the light shielding layer and the source-drain layer, and a second capacitor plate C2 located in the gate layer.

[0203] For the convenience of clearly showing the film layers in each display panel 100, the following will briefly introduce each film layer of the pixel circuit 10211 including 3 transistors and 1 storage capacitor C in the form of each single layer and step-by-step lamination.

[0204] FIG. 13 is a partial schematic view of a light shielding layer according to an embodiment of the present application. As shown in FIG. 13, the light shielding layer n1 includes a first capacitor plate C1 of the storage capacitor C and a light shielding portion n11. The light shielding portion n11 is used to shield the channel of the transistor to avoid the influence of light on the transistor. The first capacitor plate C1 further includes a capacitor connecting portion n12 which is used to be connected with the anode layer formed subsequently, i.e., to form the second node J2.

[0205] The display panel 100 includes a buffer layer n2 on the side of the light shielding layer away from the substrate 101, which is used to insulate the light shielding layer n1 from the semiconductor layer n3 formed subsequently.

[0206] FIG. 14 is a partial schematic view of a semiconductor layer according to an embodiment of the present application. FIG. 15 is a partial lamination schematic view of a light shielding layer and a semiconductor layer according to an embodiment of the present application. As shown in FIGS. 14 and 15, the semiconductor layer can have a curved or bent shape, and includes the semiconductor pattern (channel region) and the doped region pattern (source / drain doped region) of each transistor, and the semiconductor pattern and the doped region pattern of each transistor in the same pixel circuit 10211 are integrally arranged.

[0207] It should be noted that the semiconductor layer can include a low-temperature polysilicon layer, and the source region and the drain region can be made conductive by doping to realize the electrical connection of each structure. That is, the semiconductor layer of each transistor of each pixel circuit 10211 is a pattern formed by p-silicon, and each transistor in the same pixel circuit 10211 includes the doped region pattern (i.e., the source region and the drain region) and the semiconductor pattern, and the semiconductor patterns of different transistors are separated. As shown in FIG. 14, the semiconductor layer n3 includes the semiconductor pattern n31 of the first transistor T1, the semiconductor pattern n32 of the second transistor T2, and the semiconductor pattern n33 of the third transistor T3. In addition, the semiconductor pattern n32 of the second transistor T2 in two sub-pixels adjacent in the second direction Y in the pixel unit 102 can be an integral structure.

[0208] The semiconductor layer can be made of amorphous silicon, polysilicon, oxide semiconductor material, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0209] Further, the semiconductor layer further includes a protection pattern 104. The protection pattern 104 can be a strip structure extending along the second direction Y. In addition, the display panel includes a gate insulating layer located on a side of the semiconductor layer away from the substrate 101, for insulating the semiconductor layer from a subsequently formed gate layer.

[0210] FIG. 16 is a partial schematic view of a gate layer in a display panel according to an embodiment of the present application. FIG. 17 is a partial superimposed schematic view of a light shielding layer, a semiconductor layer and a gate layer in a display panel according to an embodiment of the present application. Referring to FIGS. 16 and 17, the gate layer n5 includes:

[0211] The gate layer b can include a second capacitor plate C2, a first gate portion n51, a second gate portion n52, a third gate portion n53, a fourth gate portion n54, a fifth gate portion n55, a sixth gate portion n56 and a seventh gate portion n57.

[0212] The first gate portion n51, the second gate portion n52 and the third gate portion n53 can be arranged at intervals along the second direction Y, for connecting with a first power line 105 formed subsequently on the source-drain layer n7. That is, the first power line 105 can be double-layered to reduce the resistance of the first power line 105. In addition, the interval between the first gate portion n51 and the second gate portion n52, and the interval between the second gate portion n52 and the third gate portion n53 are both for avoiding the capacitor connecting portion n12 in the light shielding layer n1, so that the orthographic projection does not overlap, and short circuiting due to overlapping is avoided.

[0213] The fourth gate portion n54, the fifth gate portion n55 and the sixth gate portion n56 can be arranged at intervals along the second direction Y, for connecting with an auxiliary electrode layer 106 formed subsequently on the source-drain layer n7. That is, the auxiliary electrode layer 106 can be double-layered to reduce the resistance of the auxiliary electrode layer 106. In addition, the interval between the fourth gate portion n54 and the fifth gate portion n55, and the interval between the fifth gate portion n55 and the sixth gate portion n56 are both for avoiding the capacitor connecting portion n12 in the light shielding layer n1, so that the orthographic projection does not overlap, and short circuiting due to overlapping is avoided.

[0214] The seventh gate portion n57 can serve as a gate pattern of the first transistor T1. In addition, the gate pattern of the first transistor T1 in two sub-pixels adjacent along the first direction X in the pixel unit 102 can be an integral structure.

[0215] FIG. 18 is a partial schematic view of an interlayer dielectric layer according to an embodiment of the present application. FIG. 19 is another partial schematic view of an interlayer dielectric layer according to an embodiment of the present application. FIG. 20 is a partial schematic view of a display panel according to an embodiment of the present application, showing the light-blocking layer, the semiconductor layer, the gate layer, and the interlayer dielectric layer.

[0216] In the embodiments of the present application, some of the patterns formed in the source-drain layer are connected through the via holes in the interlayer dielectric layer n6 and the patterns in the light-blocking layer n1, and some of the patterns are connected through the via holes in the interlayer dielectric layer n6 and the patterns in the semiconductor layer n3 or the patterns in the gate layer n5.

[0217] Since the distance between the light-blocking layer and the source-drain layer n7 in the direction perpendicular to the substrate 101 is large, the depth of the via hole required is deeper. Therefore, two masks can be used to form the via hole in the interlayer dielectric layer. The first via hole n61 is shown in FIG. 18, and the second via hole n62 is shown in FIG. 19. The purpose of the via hole n62 shown in FIG. 19 is to perform a second etching on some of the via holes n61 shown in FIG. 18, so as to form a via hole n62 with a depth deeper than that of the via hole n61.

[0218] It should be noted that the via holes are shown as circles in FIGS. 18-20, and the other areas represent the areas of the interlayer dielectric layer having a solid material.

[0219] FIG. 21 is a partial schematic view of a source-drain layer according to an embodiment of the present application. FIG. 22 is a partial schematic view of a display panel according to an embodiment of the present application, showing the light-blocking layer, the semiconductor layer, the gate layer, the interlayer dielectric layer, and the source-drain layer. Referring to FIGS. 21 and 22, the source-drain layer n7 includes the first power line 105, the third data signal line (Data_w), the first data signal line (Data_R), the sensing signal line (sense), the second data signal line (Data_B), the fourth data signal line (Data_G), the auxiliary electrode line 106, the first capacitor plate C1 of the storage capacitor C, the first source-drain portion n71, the second source-drain portion n72, the third source-drain portion n73, and the fourth source-drain portion n74.

[0220] The first capacitor plate C1 located in the source-drain layer n7 and the first capacitor plate C1 located in the light shielding layer n1 can be connected by the via 2. The first source-drain part n71 is used to connect the capacitor connection pattern n12 located in the light shielding layer n1 and the anode layer n10. The second source-drain part n72 is used to connect the second electrode of the second transistor T2 and the second capacitor plate C2 located in the gate layer n5, forming the second node J2 in FIG. 11. The third source-drain part n73 is used to connect the second gate signal line 103a2 and the gate of the second transistor T2. The fourth source-drain part n74 is used to connect the sensing signal line sense and the first electrode of the second transistor T2.

[0221] In the embodiment of the present application, after the source-drain layer n7 is formed, a passivation layer film layer can be formed, which is used to form the passivation layer n8. The material of the passivation layer n8 can be inorganic material, for example, silicon nitride. The passivation layer film layer is an integral film layer, and the passivation layer n8 includes a plurality of vias n81.

[0222] FIG. 23 is a partial schematic view of a planarization layer provided in an embodiment of the present application. FIG. 24 is a partial superimposed schematic view of a light shielding layer, a semiconductor layer, a gate layer, an interlayer dielectric layer, a source-drain layer and a planarization layer in a display panel provided in an embodiment of the present application. As shown in FIGS. 23 and 24, the planarization layer n9 has a solid material region S and a hollow region W. The solid material region S is located in the pixel light emitting region 101a1, covers the gate signal line 103 and covers the protection pattern 104. The hollow region W is located in the transparent region 101a2, the region where the gate signal line 103 is located and the region where the protection pattern 104 is located.

[0223] After the planarization layer n9 is formed, the passivation layer film layer can be processed to obtain a plurality of vias n81 shown in FIGS. 25 and 26, and then the passivation layer n8 is formed.

[0224] FIG. 27 is a partial schematic view of a first anode film layer in an anode layer provided in an embodiment of the present application. FIG. 28 is a partial superimposed schematic view of a light shielding layer, a semiconductor layer, a gate layer, an interlayer dielectric layer, a source-drain layer, a passivation layer, a planarization layer and a first anode film layer in a display panel provided in an embodiment of the present application. As shown in FIGS. 27 and 28, the first anode film layer includes a first anode pattern n10a1, a second anode pattern n10a2 and a third anode pattern n10a3. It should be noted that the second node J2 can be a lap joint of the second anode pattern n10a2 and the via n81 in the passivation layer n8.

[0225] The region where each sub-pixel 1021 is located corresponds to two first anode patterns n10a1, and the two first anode patterns n10a1 can be connected by a second anode pattern n10a2. Of course, the region where each sub-pixel 1032 is located corresponds to one first anode pattern n10a1, and in this case, the second anode pattern n10a2 does not need to be designed. The third anode pattern n10a3 is used to connect the auxiliary electrode line 106 and the subsequently formed cathode layer n13. The material of the first anode film layer n10a can be indium tin oxide (ITO).

[0226] FIG. 29 is a partial schematic view of a second anode film layer in an anode layer according to an embodiment of the present application. FIG. 30 is a partial superimposed schematic view of a light-blocking layer, a semiconductor layer, a gate layer, an interlayer dielectric layer, a source-drain layer, a passivation layer, a planarization layer, a first anode film layer, and a second anode film layer in a display panel according to an embodiment of the present application. Referring to FIGS. 28 and 29, the second anode film layer includes a fourth anode pattern n10b1. The fourth anode pattern n10b1 is used to connect the first anode film layer n10a and the third anode film layer n10c. The material of the second anode film layer n10b can be indium tin oxide (ITO).

[0227] FIG. 31 is a partial schematic view of a third anode film layer in an anode layer according to an embodiment of the present application. FIG. 32 is a partial superimposed schematic view of a light-blocking layer, a semiconductor layer, a gate layer, an interlayer dielectric layer, a source-drain layer, a passivation layer, a planarization layer, a first anode film layer, a second anode film layer, and a third anode film layer in a display panel according to an embodiment of the present application. Referring to FIGS. 31 and 32, the third anode film layer n10c includes a fifth anode pattern n10c1 and a sixth anode pattern n10c2. The fifth anode pattern n10c1 is used to connect the second anode pattern n10a2, and the sixth anode pattern n10c serves as a reflective anode of a sub-pixel and includes indium tin oxide (ITO) and copper (Cu).

[0228] FIG. 33 is a partial schematic view of a pixel definition layer n11 according to an embodiment of the present application. FIG. 34 is a partial superimposed schematic view of a light-blocking layer, a semiconductor layer, a gate layer, an interlayer dielectric layer, a source-drain layer, a passivation layer, a planarization layer, a first anode film layer, a second anode film layer, a third anode film layer, and a pixel definition layer in a display panel according to an embodiment of the present application. Referring to FIGS. 33 and 34, the pixel definition layer n11 can have a solid material region S and a hollow region W. The solid material region S is located in the pixel light-emitting region 101a1, covers the gate signal line 103, and covers the protection pattern 104. The hollow region W is located in the transparent region 101a2, the region where the gate signal line 103 is located, and the region where the protection pattern 104 is located.

[0229] In addition, the hollowed-out area W is also located in the pixel light-emitting area 101a1, and the hollowed-out area W provided by the pixel light-emitting area 101a1 is used to expose the sixth anode pattern n10c of the third anode film layer n10, so that the subsequently formed light-emitting layer can be in contact with the sixth anode pattern n10c, and the area of the light-emitting area is increased.

[0230] FIG. 35 is a schematic diagram of a water vapor or oxygen intrusion path according to an embodiment of the present application. As shown in FIG. 35, the water vapor or oxygen needs to pass through the bent part of the gate signal line 103 to intrude into the pixel unit 102, and the intrusion path is long, which enhances the reliability of the product and provides technical support for mass production.

[0231] It should be noted that the display panel 100 further includes a gate drive circuit located in the peripheral area 101b, or also referred to as a gate driven on array (GOA). The gate drive circuit can be connected with the first part 1031 of the gate signal line 103, and is used to provide a gate drive signal for the gate signal line 103. For example, the gate drive circuit can be located in the regions on the left and right sides in the peripheral area 101b.

[0232] In summary, the display panel provided by the embodiment of the present application includes a substrate, a plurality of pixel units, and a plurality of gate signal lines. The gate signal line includes a main body part extending along a first direction, and a bent part connected with the main body part and located in a target transparent area of the display area of the substrate close to the peripheral area. Since the path length of the bent part is long, the intrusion path of the water vapor or oxygen into the pixel unit is long, which effectively reduces the possibility of the water vapor or oxygen entering the pixel unit, improves the yield of the display panel, and ensures the display effect of the display panel.

[0233] FIG. 36 is a structural schematic diagram of a display device according to an embodiment of the present application. As shown in FIG. 36, the display device includes a power supply component 200 and the display panel 100 provided by the above-mentioned embodiment. The power supply component 200 is connected with the display panel 100, and is used to supply power for the display panel 100.

[0234] Optionally, the display panel can be an organic light-emitting diode (OLED) display panel, and the display device can be an OLED display device. For example, the display panel can be an active-matrix organic light-emitting diode (AMOLED) display panel, and the display device can be an AMOLED display device.

[0235] Optionally, the display device can be any suitable display device, including but not limited to a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, an e-book, or any product or component having a display function.

[0236] Since the display device can have substantially the same technical effects as the display panel described in the foregoing embodiments, for the purpose of brevity, the technical effects of the display device are not described again here.

[0237] The terms used in the embodiments of the present application are only used to explain the embodiments of the present application, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood as the usual meanings understood by those skilled in the art in the field of the present application.

[0238] The terms used in the embodiments of the present application are only used to explain the embodiments of the present application, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood as the usual meanings understood by those skilled in the art in the field of the present application. The terms "first", "second", "third", and the like used in the patent application specification and claims of the present application do not represent any order, number, or importance, but are only used to distinguish different components. Similarly, "one" or "a" and the like do not represent a quantity limitation, but represent the existence of at least one. "Include" or "contain" and the like mean that the elements or objects appearing before "include" or "contain" cover the elements or objects listed after "include" or "contain" and their equivalents, and do not exclude other elements or objects. "Connected" or "connected" and the like are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right", and the like are only used to represent relative positional relationships, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0239] The above is only an optional embodiment of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate substrate comprising a display area and a peripheral area surrounding the display area, the display area comprising a plurality of pixel light-emitting areas and a plurality of transparent areas, the plurality of transparent areas comprising at least one target transparent area arranged in a first direction; a plurality of pixel units on the substrate substrate and in the pixel light-emitting areas; a plurality of gate signal lines arranged along a second direction, the second direction intersecting the first direction, the gate signal lines comprising a first part in the peripheral area and a second part in the display area, the second part comprising a main part extending along the first direction, and a bending part connected to the main part, the bending part being located in the target transparent area, a path length of the bending part being greater than a length of the target transparent area in the first direction.

2. The display panel of claim 1, wherein, The display panel further comprises a protection pattern and a first insulating layer between the protection pattern and the gate signal lines; The protection pattern is located in the target transparent area, a normal projection of the bending part on the substrate substrate is located on one side of a normal projection of the protection pattern on the substrate substrate, and a normal projection of the protection pattern on the substrate substrate and a normal projection of the bending part on the substrate substrate partially overlap.

3. The display panel of claim 2, wherein, The bending part comprises a first bending part, a second bending part and a third bending part connected in sequence, the plurality of gate signal lines form a plurality of signal line groups, and each signal line group comprises two adjacent gate signal lines; The first bending part of the two adjacent gate signal lines is located on a side of the protection pattern away from the peripheral area, and the third bending part of the two adjacent gate signal lines is located on a side of the protection pattern close to the peripheral area; A normal projection of the second bending part of a first gate signal line in the two adjacent gate signal lines on the substrate substrate is located on a first side of a normal projection of the protection pattern on the substrate substrate, and a normal projection of the second bending part of the first gate signal line on the substrate substrate and a normal projection of the protection pattern on the substrate substrate partially overlap; A normal projection of the second bending part of a second gate signal line in the two adjacent gate signal lines on the substrate substrate is located on a second side of a normal projection of the protection pattern on the substrate substrate, and a normal projection of the second bending part of the second gate signal line on the substrate substrate and a normal projection of the protection pattern on the substrate substrate partially overlap; The first side and the second side are two sides of the normal projection of the protection pattern on the substrate substrate arranged along the second direction.

4. The display panel of claim 3, wherein, The normal projection of the bending part of the two gate signal lines on the substrate substrate surrounds the normal projection of the protection pattern on the substrate substrate.

5. The display panel of claim 4, wherein, The bending part of the two gate signal lines encloses a first annular area; The part of the first gate signal line in the pixel light-emitting area has a second annular area, and the part of the second gate signal line in the pixel light-emitting area has a third annular area; The first annular area has a larger area than the second annular area and a larger area than the third annular area.

6. The display panel of claim 5, wherein, The plurality of target transparent regions comprises a first target transparent region, and the first target transparent region is closer to the peripheral region than the plurality of pixel light-emitting regions. For the bending portions of the two gate signal lines, the distance between the first annular area surrounded by the first target transparent region and the pixel light-emitting region is greater than the distance between the first annular area and the peripheral region.

7. The display panel of claim 6, wherein, The protection pattern is a strip pattern extending along the second direction, and the length of the protection pattern along the second direction is greater than the distance between the first annular area of the first target transparent region and the pixel light-emitting region.

8. The display panel of claim 6, wherein, The plurality of target transparent regions further comprises a second target transparent region, and the second target transparent region is located between two adjacent pixel light-emitting regions. For the bending portions of the two gate signal lines, the distance between the first annular area surrounded by the second target transparent region and the two adjacent pixel light-emitting regions is equal.

9. The display panel of claim 3, wherein, The second bending portion of the first gate signal line has a first protrusion on the side close to one side of the protection pattern, and the orthographic projection of the first end portion of the protection pattern on the substrate and the orthographic projection of the first protrusion on the substrate overlap. The second bending portion of the second gate signal line has a second protrusion on the side close to one side of the protection pattern, and the orthographic projection of the second end portion of the protection pattern on the substrate and the orthographic projection of the second protrusion on the substrate overlap.

10. The display panel of claim 9, wherein, The display panel comprises a pixel unit layer, and the pixel unit layer comprises a plurality of pixel units; the pixel unit layer further comprises a semiconductor layer located between the substrate and the first insulating layer. The protection pattern is located in the semiconductor layer, and the materials of the first end portion and the second end portion of the protection pattern are semiconductor materials.

11. The display panel of claim 2, wherein, The display panel comprises a pixel unit layer, and the pixel unit layer comprises a plurality of pixel units; the pixel unit layer comprises a gate layer, a second insulating layer, and a cathode layer which are sequentially stacked away from the substrate; The plurality of gate signal lines are located in the gate layer, and the orthographic projection of the second insulating layer on the substrate covers the orthographic projection of the plurality of gate signal lines on the substrate and covers the orthographic projection of the protection pattern on the substrate.

12. The display panel of claim 11, wherein, The second insulating layer has a solid material area comprising insulating materials and a hollow area not comprising insulating materials; The solid material area is located in the pixel light-emitting region, and the orthographic projection of the solid material area on the substrate covers the orthographic projection of the protection pattern on the substrate and covers the orthographic projection of the gate signal line on the substrate; The hollow area is located on the side of the orthographic projection of the gate signal line on the substrate away from the orthographic projection of the protection pattern on the substrate, and is located on the side of the orthographic projection of the gate signal line on the substrate The intersection between the projection of the gate signal line on the substrate and the projection of the protection pattern on the substrate, and the intersection between the projection of the gate signal line on the substrate and the projection of the pixel light-emitting area on the substrate.

13. The display panel of claim 11, wherein, The second insulating layer comprises a first sub-insulating layer and a second sub-insulating layer stacked in sequence in a direction away from the substrate; The boundary of the projection of the first sub-insulating layer on the substrate and the boundary of the projection of the second sub-insulating layer on the substrate do not overlap.

14. The display panel of any of claims 1 to 13, wherein, The pixel light-emitting area and the transparent area are both strip-shaped areas extending in the second direction, and the plurality of pixel light-emitting areas and the plurality of transparent areas are arranged alternately in the first direction; the plurality of transparent areas comprise two target transparent areas, and the plurality of pixel light-emitting areas and the plurality of transparent areas other than the two target transparent areas are located between the two target transparent areas. The gate signal line comprises two bending portions, one of which is connected to one end of the main body portion and located in one of the target transparent areas, and the other of which is connected to the other end of the main body portion and located in the other target transparent area.

15. The display panel of any of claims 1 to 13, wherein, The plurality of pixel units are arranged in an array, and the plurality of pixel units comprise a plurality of first pixel unit groups arranged in the second direction, each of which comprises a plurality of pixel units arranged in the first direction; Each of the gate signal lines is connected to the plurality of pixel units of one of the first pixel unit groups, and the plurality of pixel units of each of the first pixel unit groups are connected to two gate signal lines in one of the plurality of signal line groups formed by the plurality of gate signal lines.

16. The display panel of claim 15, wherein, The pixel unit comprises a first group of sub-pixels and a second group of sub-pixels arranged in the second direction, the first group of sub-pixels comprises at least one sub-pixel, and the second group of sub-pixels comprises at least one sub-pixel; The main body portion of the two gate signal lines connected to the plurality of pixel units of each of the first pixel unit groups is located between the first group of sub-pixels and the second group of sub-pixels.

17. The display panel of claim 16, wherein, The main body portion comprises a first main channel line and a plurality of first auxiliary channel lines; Both ends of the plurality of first auxiliary channel lines are connected to the first main channel line, the first main channel line is connected to at least one sub-pixel of the first group of sub-pixels of the plurality of pixel units in one of the first pixel unit groups, and each of the first auxiliary channel lines is connected to at least one sub-pixel of the second group of sub-pixels of one pixel unit.

18. The display panel of claim 17, wherein, The plurality of pixel units comprise a plurality of second pixel unit groups arranged in the first direction, each of which comprises a plurality of pixel units arranged in the second direction; The display panel further comprises a plurality of first power lines corresponding to the plurality of second pixel unit groups, and a plurality of auxiliary electrode lines corresponding thereto, each of the first power lines comprises a main power line and a plurality of branch power lines, the plurality of branch power lines are connected to the main power line, the main power line is located on one side of a corresponding one of the second pixel unit groups, the first power line is connected to sub-pixels in a plurality of pixel units in the second pixel unit group, and each of the auxiliary electrode lines is located on the other side of a corresponding one of the second pixel unit groups and is connected to a cathode layer in the pixel unit. For the main power line of a first power line corresponding to a second pixel unit group and an auxiliary electrode line, two connection points at which the first sub-channel line is connected to the first main channel line are located on the side of the main power line away from the auxiliary electrode line and on the side of the auxiliary electrode line away from the main power line.

19. The display panel of claim 17, wherein, The plurality of pixel units comprises a plurality of second pixel unit groups arranged along a first direction, and each of the second pixel unit groups comprises a plurality of pixel units arranged along a second direction. The display panel further comprises a plurality of first power lines corresponding to the plurality of second pixel unit groups, and a plurality of auxiliary electrode lines corresponding thereto, each of the first power lines comprises a main power line and a plurality of branch power lines, the plurality of branch power lines are connected to the main power line, the main power line is located on one side of a corresponding one of the second pixel unit groups, the first power line is connected to sub-pixels in a plurality of pixel units in the second pixel unit group, and each of the auxiliary electrode lines is located on the other side of a corresponding one of the second pixel unit groups and is connected to a cathode layer in the pixel unit. For the main power line of a first power line corresponding to a second pixel unit group and an auxiliary electrode line, two connection points at which the first sub-channel line is connected to the first main channel line are located on the side of the main power line away from the auxiliary electrode line and on the side of the auxiliary electrode line away from the main power line. The main body further comprises a plurality of second sub-channel lines and a plurality of third sub-channel lines, two ends of each of the plurality of second sub-channel lines are connected to the first main channel line, two connection points at which the second sub-channel line is connected to the first main channel line are located on two sides of the main power line, two ends of each of the plurality of third sub-channel lines are connected to the first main channel line, and two connection points at which the third sub-channel line is connected to the first main channel line are located on two sides of the auxiliary electrode line. The first group of sub-pixels comprises a first sub-pixel and a second sub-pixel, and the second group of sub-pixels comprises a third sub-pixel and a fourth sub-pixel; the display panel further comprises a plurality of data signal line groups corresponding to the plurality of second pixel unit groups, each of the data signal line groups comprises a plurality of data signal lines arranged along a first direction, a target data signal line in the plurality of data signal lines is located between the first sub-pixel and the second sub-pixel and between the third sub-pixel and the fourth sub-pixel, and the target data signal line is at least one of the plurality of data signal lines.

20. The display panel of claim 18 or 19, wherein, ​ The branch power line comprises a second main channel line and a fourth sub-channel line, two ends of the fourth sub-channel line are connected with the second main channel line, and two connection positions of the fourth sub-channel line connected with the second main channel line are located on two sides of the target data signal line.

21. The display panel of claim 20, wherein, The data signal line group comprises a first data signal line, a second data signal line, a third data signal line and a fourth data signal line; the display panel further comprises a sensing signal line; The first data signal line, the sensing signal line and the second data signal line are arranged along the first direction, and are located between the first sub-pixel and the second sub-pixel and between the third sub-pixel and the fourth sub-pixel, the first data signal line is connected with the first sub-pixel, and the second data signal line is connected with the second sub-pixel; The third data signal line is located on one side of the corresponding second pixel unit group and is connected with the third sub-pixel; The fourth data signal line is located on the other side of the corresponding second pixel unit group and is connected with the fourth sub-pixel.

22. The display panel of claim 20, wherein, The plurality of pixel units comprises a plurality of second pixel unit groups arranged along a first direction, each second pixel unit group comprises a plurality of pixel units arranged along a second direction; The display panel further comprises a second power line connected with a cathode layer in the pixel unit; At least one data signal line is arranged between the main power line and the second power line.

23. The display panel of claim 16, wherein, Two gate signal lines in one signal line group of the plurality of signal line groups formed by the pixel unit and the plurality of gate signal lines are connected, the two gate signal lines comprise a first gate signal line and a second gate signal line; the sub-pixel comprises a pixel circuit and a light emitting unit; The pixel circuit comprises: A first transistor, a gate of the first transistor is connected with the first gate signal line, a first electrode of the first transistor is connected with a data signal line, and a second electrode of the first transistor is connected with a first node; A second transistor, a gate of the second transistor is connected with the second gate signal line, a first electrode of the second transistor is connected with a sensing signal line, and a second electrode of the second transistor is connected with a second node, the second node is also connected with an anode pattern of the light emitting unit; A third transistor, a gate of the third transistor is connected with the first node, a first electrode of the third transistor is connected with a first power line, and a second electrode of the third transistor is connected with the second node; And a storage capacitor, a first electrode of the storage capacitor is connected with the first node, and a second electrode of the storage capacitor is connected with the second node.

24. The display panel of claim 23, wherein, A distance between the second node and a first annular area surrounded by a bending part of the two gate signal lines in the signal line group is greater than or equal to a distance between the first annular area and a light emitting area of the pixel.

25. A display device comprising: The display device comprises a power supply assembly and the display panel as claimed in any one of claims 1 to 24; The power supply assembly is connected with the display panel, and the power supply assembly is used for supplying power to the display panel.

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