Semiconductor package

Abstract

Embodiments of the present disclosure provide a semiconductor package, comprising: a first semiconductor chip and a second semiconductor chip; and a first material layer arranged between the first semiconductor chip and the second semiconductor chip, wherein the first material layer comprises a non-conductive base material as well as a first-type filler and a second-type filler which are distributed in the non-conductive base material, and the average particle size of the first-type filler is different from the average particle size of the second-type filler. In the embodiments of the present disclosure, two types of fillers having a particle size difference are used in combination, thereby increasing the fill rate of the fillers and improving the CTE of the material layer.

Description

Semiconductor package

[0001] This application claims priority to the Chinese Patent Application No. 202410473944.4, filed on April 18, 2024, and entitled “Semiconductor package”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and in particular to a semiconductor package. BACKGROUND

[0003] 3D stacking technology is to stack multiple chips vertically together, and to realize communication and connection between chips through silicon interconnection and packaging technology. Taking a DRAM die including multiple vertically stacked layers as an example, each layer of die is connected with a logic chip through a through-silicon via technology (TSV), and 3D integration technology makes it possible to package 8, 12 or even more layers of die in a small volume space, thereby obtaining smaller size, higher bandwidth and higher reliability. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor package with higher reliability and performance.

[0005] The problems to be solved by the technical spirits of the present disclosure are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] According to an example embodiment of the present disclosure, a semiconductor package includes: a first semiconductor chip; a second semiconductor chip disposed on the first semiconductor chip; and a first material layer disposed between the first semiconductor chip and the second semiconductor chip, wherein the first material layer includes a non-conductive substrate and a first type of filler and a second type of filler distributed in the non-conductive substrate, and the average particle size of the first type of filler is different from the average particle size of the second type of filler.

[0007] In an example embodiment, the first type of filler does not contain a metal element, the second type of filler contains a metal element, and the average particle size of the first type of filler is greater than the average particle size of the second type of filler.

[0008] In an example embodiment, the average particle size of the first type of filler is 2-5 times the average particle size of the second type of filler.

[0009] In an example embodiment, the volume fraction of the first type of filler in the non-conductive substrate is greater than the volume fraction of the second type of filler in the non-conductive substrate.

[0010] In an example embodiment, the volume ratio of the first type of filler to the second type of filler ranges from 2 to 4.5.

[0011] In an example embodiment, a third material layer is further included, the third material layer is disposed on the first semiconductor chip, the third material layer includes a base material and a third type of filler distributed in the base material, the third type of filler has an average particle size greater than the average particle size of the first type of filler and the average particle size of the second type of filler, and the volume percentage of the third type of filler in the base material of the third material layer is less than the sum of the volume percentages of the first type of filler and the second type of filler in the non-conductive base material of the first material layer.

[0012] In an example embodiment, the third material layer has a first contact surface with the first material layer, and a second contact surface with the second semiconductor chip, the first contact surface has a surface area greater than the surface area of the second contact surface.

[0013] In an example embodiment, the third material layer is further disposed on the first material layer, and the first material layer has a portion not covered by the third material layer.

[0014] In an example embodiment, a third semiconductor chip is further included, the third semiconductor chip is disposed on the second semiconductor chip, the first material layer is not disposed between the third semiconductor chip and the second semiconductor chip, and the first material layer is disposed on a surface of the third semiconductor chip away from the second semiconductor chip.

[0015] In an example embodiment, a second material layer is disposed between the third semiconductor chip and the second semiconductor chip, the second material layer has the first type of filler distributed therein.

[0016] In an example embodiment, the third semiconductor chip and the second semiconductor chip are electrically connected through direct bonding.

[0017] In an example embodiment, the first material layer further has a conductive structure electrically connecting the first semiconductor chip and the second semiconductor chip disposed therein, and the first material layer at least surrounds a portion of the conductive structure.

[0018] In an example embodiment, the conductive structure includes a first contact pad connected to the first semiconductor chip, a second contact pad connected to the second semiconductor chip, and an intermediate interconnection structure connecting the first contact pad and the second contact pad, and the first material layer surrounds the intermediate interconnection structure.

[0019] According to another example embodiment of the present disclosure, a semiconductor package includes: a buffer chip; a core chip disposed on the buffer chip; a first material layer at least partially surrounding the buffer chip and the core chip; wherein the first material layer includes a non-conductive base material and a first type of filler and a second type of filler distributed in the non-conductive base material, the first type of filler has an average particle size different from the average particle size of the second type of filler. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the present disclosure.

[0021] FIG. 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure;

[0022] FIG. 2A is a schematic view of a first material layer according to an embodiment of the present disclosure;

[0023] FIG. 2B is a schematic view of another first material layer according to an embodiment of the present disclosure;

[0024] FIG. 3 is a schematic view of a semiconductor package according to an embodiment of the present disclosure;

[0025] FIG. 4A is a schematic view of a semiconductor package according to an embodiment of the present disclosure;

[0026] FIG. 4B is a schematic view of a semiconductor package according to an embodiment of the present disclosure;

[0027] FIG. 5A is a schematic view of a semiconductor package according to an embodiment of the present disclosure;

[0028] FIG. 5B is a schematic view of a semiconductor package according to an embodiment of the present disclosure;

[0029] FIG. 5C is a schematic view of a semiconductor package according to an embodiment of the present disclosure;

[0030] FIG. 6 is a schematic view of a semiconductor package according to an embodiment of the present disclosure;

[0031] FIG. 7A is a schematic view of a semiconductor package according to an embodiment of the present disclosure;

[0032] FIG. 7B is a schematic view of a semiconductor package according to an embodiment of the present disclosure;

[0033] FIG. 8A is a schematic view of a semiconductor package according to an embodiment of the present disclosure;

[0034] FIG. 8B is a schematic view of a semiconductor package according to an embodiment of the present disclosure;

[0035] FIG. 9 is a schematic view of a semiconductor package according to an embodiment of the present disclosure.

[0036] The above-described drawings help to show specific embodiments of the present disclosure, and more detailed descriptions will be given later. The drawings and the written description are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only for explaining the related disclosure, and not for limiting the disclosure. In addition, it should be noted that only the relevant parts are shown in the drawings for convenience of description. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure. In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first", "second", "third" involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that "first", "second", "third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described.

[0038] The embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0039] In an embodiment of the present disclosure, referring to FIG. 1, FIG. 1 provides a cross-sectional view of a semiconductor package, the semiconductor package 10 includes a first semiconductor chip 30 and a second semiconductor chip 20 located on the first semiconductor chip 30, a first material layer 40 is arranged between the first semiconductor chip 30 and the second semiconductor chip 20, and the first material layer 40 is used to realize fixed connection between the first semiconductor chip 30 and the second semiconductor chip 20.

[0040] In some embodiments, the first semiconductor chip 30 has a face opposite to the second semiconductor chip 20, and the first material layer 40 can be arranged in the form of a thin film on the face of the first semiconductor chip 30 opposite to the second semiconductor chip 20, thereby realizing fixed connection between the first semiconductor chip 30 and the second semiconductor chip 20.

[0041] In some embodiments, the second semiconductor chip 20 has a face opposite to the first semiconductor chip 30, and the first material layer 40 can be arranged in the form of a thin film on the face of the second semiconductor chip 20 opposite to the first semiconductor chip 30, thereby realizing fixed connection between the first semiconductor chip 30 and the second semiconductor chip 20.

[0042] In some embodiments, the first semiconductor chip 30 and the second semiconductor chip 20 are both provided with a partial first material layer 40 on the opposite surface, and the first semiconductor chip 30 and the second semiconductor chip 20 are fixedly connected through the partial first material layer 40 on the first semiconductor chip 30 and the partial first material layer 40 on the second semiconductor chip 20.

[0043] In some embodiments, the first semiconductor chip 30 and the second semiconductor chip 20 can be one of the following: gate array, cell base array, embedded array, structured ASIC, FPGA, CPLD, CPU, MPU, MCU, logic IC, AP, driver IC, RF chip, CMOS image sensor, and the like, and can also be a storage chip represented by DRAM and NAND, and the present disclosure is not limited thereto.

[0044] In some embodiments, the first semiconductor chip 30 and the second semiconductor chip 20 can be the same, for example, the first semiconductor chip 30 and the second semiconductor chip 20 are both storage chips or logic chips.

[0045] In some embodiments, the first semiconductor chip 30 and the second semiconductor chip 20 can also be different, for example, the first semiconductor chip 30 is a logic chip and the second semiconductor chip is a storage chip.

[0046] In some embodiments, referring to FIGS. 2A and 2B, the first material layer 40 includes a substrate 41, which can be a sealing material that bonds the first semiconductor chip 30 and the second semiconductor chip 20 to each other, such as a non-conductive material such as a silicon-based material, a thermosetting material, a thermoplastic material, a UV-cured material, and the like, in addition to which there are hardening agents, polymers, fluxes (soldering fluxes), and the like, additives that assist the first material layer 40 in achieving a sealing and bonding effect, which will not be described here.

[0047] The first material layer 40 also includes a first filler 42 and a second filler 43 distributed in the substrate 41. The first filler 42 and the second filler 43 are uniformly distributed in the substrate 41, and the first filler 42 and the second filler 43 are mainly used to control the coefficient of thermal expansion (CTE), viscosity, Young's modulus, and the like of the first material layer 40.

[0048] In some embodiments, the first filler 42 and the second filler 43 have different particle size distributions.

[0049] In some embodiments, referring to FIG. 2A, the average particle size of the first type of filler 42 is greater than the average particle size of the second type of filler 43, the first type of filler 42 includes a type of particles having substantially the same geometric structure, such as circular or approximately circular, and the particle sizes of these particles can be normally distributed; the second type of filler 43 includes particles 430a, 431a and 432a, the geometric structures of the particles 430a, 431a and 432a can be the same or different, for example, the particles 430a, 431a and 432a can have geometric structures of non-circular or irregular structures, and in some embodiments, the particle sizes of the three particles 430a, 431a and 432a are not normally distributed, i.e., the average particle sizes of the particles 430a, 431a and 432a are different from each other.

[0050] In some embodiments, the average particle size of the first type of filler 42 is about 2-5 times the average particle size of the second type of filler, in other some embodiments, the average particle size of the first type of filler 42 is about 2.5-3 times or 3-3.5 times the average particle size of the second type of filler.

[0051] In some embodiments, referring to FIG. 2B, the average particle size of the first type of filler 42 is less than the average particle size of the second type of filler 43. The first type of filler 42 includes a type of particles having substantially the same geometric structure, such as circular or elliptical, ellipsoidal, etc., and the particle sizes of these particles can be normally distributed; the second type of filler 43 includes particles 430b, 431b and 432b, the geometric structures of the particles 430b, 431b and 432b can be the same or different, for example, the particles 430b, 431b and 432b can have geometric structures of non-circular or irregular structures, such as planar, i.e., flake, irregular or prismatic, etc., and in some embodiments, the particle sizes of the three particles 430b, 431b and 432b are not normally distributed, i.e., the average particle sizes of the particles 430b, 431b and 432b are different from each other.

[0052] In some embodiments, the average particle size of the second type of filler 42 is about 2-5 times the average particle size of the first type of filler, in other some embodiments, the average particle size of the second type of filler 42 is about 2.5-3 times or 3-3.5 times the average particle size of the first type of filler.

[0053] In these embodiments, by setting the first type of filler and the second type of filler with different average particle sizes, the first material layer is superior to the material using the same type of filler in terms of coefficient of thermal expansion (CTE), viscosity, Young's modulus, and the like. As the packaging volume is further miniaturized, the distance between chips becomes smaller, and the density of the electrical connection portion between chips is further increased, the requirements for the CTE, viscosity, Young's modulus, and the like of the material layer between the fixed chips are higher. Generally, as the ratio of the filler in the material layer increases, the CTE of the material layer will decrease, which will help to improve the packaging reliability of the package, reduce the risk of delamination, and the like. The traditional way to increase the filler filling rate is to reduce the particle size of the filler. However, the reduction of the particle size, especially the filler with regular geometric structure at a small particle size, will increase the production cost. Therefore, in these embodiments of the present disclosure, two types of fillers with different particle sizes are used together. The large particle size filler drives the small particle size filler to flow in the substrate, improving the uniformity of the small particle size filler. The small particle size filler can be distributed in the gap formed by the large particle size filler, increasing the filling rate of the filler, and improving the CTE of the material layer. At the same time, the use of fillers with different particle sizes can not strictly require the filler to have a regular geometric structure, which can further reduce the cost.

[0054] In some embodiments, the first type of filler 42 and the second type of filler 43 can each be one or more of inorganic fillers, such as silicon dioxide, aluminum oxide, aluminum nitride, boron nitride, silicon nitride, silicon carbide, magnesium oxide, zinc oxide, and the like. In some embodiments, the first type of filler 42 can be a silicon-containing inorganic filler such as silicon dioxide, silicon nitride, silicon carbide, and the like, and preferably spherical silicon dioxide; and the second type of filler 43 can be a composite filler containing metal elements such as aluminum oxide, aluminum nitride, boron nitride, magnesium oxide, zinc oxide, and the like, and preferably magnesium oxide, zinc oxide, and aluminum nitride.

[0055] In some embodiments, by using the second type of filler containing metal elements, the thermal conductivity of the first material layer can be effectively increased; in some embodiments, by using the second type of filler containing metal elements with smaller particle size, the thermal conductivity of the first material layer can be increased and the CTE of the first material layer can be reduced at the same time.

[0056] In some embodiments, the volume ratio of the first type of filler 42 in the substrate 41 is greater than the volume ratio of the second type of filler 43 in the substrate 41.

[0057] In some embodiments, the volume ratio of the first type of filler 42 to the second type of filler 43 is in the range of 2-4.5, for example, the volume ratio of the two can be 2-3 or 3-4.

[0058] In these embodiments, by setting the volume ratio of the first type of filler in the substrate to be greater than the volume ratio of the second type of filler in the substrate, the first type of filler can be ensured to push the second type of filler to flow in the substrate during the flow of the first type of filler in the substrate, thereby improving the uniformity of the distribution of the second type of filler with irregular geometry in the substrate.

[0059] In some embodiments, the use of the second type of filler with relatively small volume ratio in combination with the first type of filler with higher volume ratio and better surface morphology can reduce the risk of the light transmittance of the first material layer being reduced due to the increased scattering of light transmitted through the substrate by the second type of filler with irregular geometry, which will make it difficult for the recognition of the pattern or position displayed by the camera when the first semiconductor chip and the second semiconductor chip are soldered and aligned.

[0060] In some embodiments, referring to FIG. 3, the chip area of the first semiconductor chip 30 is greater than the chip area of the second semiconductor chip 20, and the first material layer 40 between the first semiconductor chip 30 and the second semiconductor chip 20 does not completely cover the surface of the first semiconductor chip 30. In these embodiments, the semiconductor package 10 further comprises a third material layer 50 located on the first semiconductor chip 30, and the third material layer 50 covers the second semiconductor chip 20 and the first material layer 40 to further enhance the sealing effect on the first semiconductor chip 30 and the second semiconductor chip 20.

[0061] In some embodiments, the third material layer 50 comprises a substrate 51 and a filler 52 distributed in the substrate 51. The third material layer 50 can be an insulating layer such as a silicon material or an epoxy material, and the substrate 51 can be the same or different material as the substrate 41 of the first material layer 40, specifically, a material that can be treated by light, heat and / or pressure to realize the bonding of the first semiconductor chip and the second semiconductor chip, for example, an insulating material with sealing performance such as silicon material or epoxy resin. In some embodiments, the filler 52 can be one or a mixture of more than one of silicon dioxide, aluminum oxide, aluminum nitride, boron nitride, silicon nitride, silicon carbide, magnesium oxide, zinc oxide, etc.

[0062] In some embodiments, the filler 52 can comprise any suitable particle geometry, for example but not limited to spherical, elliptical, ellipsoidal and planar (i.e. flaky, irregular or prismatic) etc., and the flatness particle size of these particles is greater than the average particle size of the filler 42 and the filler 43 in the first material layer 40.

[0063] In some embodiments, the volume percentage of the filler 52 in the substrate 51 is less than the sum of the volume percentages of the filler 42 and the filler 43 in the non-conductive substrate 41. For example, in some embodiments, the volume percentage of the filler 52 in the substrate 51 is 20% to 60%, preferably 35%, 40% or 50%. The total volume percentage of the filler 42 and the filler 43 in the non-conductive substrate 41 is 35% to 70%, preferably 45%, 50% or 60%. In other embodiments, the volume percentage of the filler 52 in the substrate 51 is not less than 50% to 80% of the volume percentage of the filler 42 and the filler 43 in the non-conductive substrate 41. For example, in some embodiments, the total volume percentage of the filler 42 and the filler 43 in the non-conductive substrate 41 is 50% to 80%, then the volume percentage of the filler 52 in the substrate 51 is not less than 25% to 40%.

[0064] In some embodiments, the third material layer 50 can be filled by molding, reflow or other filling means after the first semiconductor chip 30 and the second semiconductor chip 20 are sealed by the first material layer 40, to cover the second semiconductor chip 20, the first material layer 40 and the exposed surface of the first semiconductor chip 30, forming a sealed package 10.

[0065] In these embodiments, by setting the third material layer with larger average filler particle size and smaller filler volume percentage to cover the first material layer and the parts of the first semiconductor chip and the second semiconductor chip not covered by the first material layer, on the one hand, the difference in filler particle size can increase the packaging stability of the entire package at a lower cost; on the other hand, the difference in filler volume percentage can balance the CTE imbalance between the various components during the sealing process. Prevent delamination between the first material layer, the third material layer and the semiconductor chip due to the large CTE difference between them during the heat treatment of the first material layer and the third material layer, affecting the reliability of the package.

[0066] To make the content of the present disclosure clearer, further description is made below in combination with the process of forming a semiconductor package.

[0067] In some embodiments, the process of forming a semiconductor package 10 includes the following steps:

[0068] S11, respectively providing a first type of filler and a second type of filler, mixing the first type of filler and the second type of filler into a non-conductive substrate, and mixing the first type of filler and the second type of filler uniformly in the non-conductive substrate by stirring or other means and solidifying to form a thin film of the first material layer.

[0069] S13, a wafer is provided, and one side of the thin film first material layer is attached to the surface of the wafer. In some embodiments, the surface of the wafer to which the first material layer is attached is provided with contacts for transmitting signals or power, which pass through the surface of the first material into the first material layer and do not protrude from the first material layer. In some embodiments, the wafer can be a wafer containing multiple dies, or a single die or other bearing structure, such as a carrier wafer.

[0070] S15, another wafer is provided, the wafer with the first material layer is flipped over, the other side of the first material layer is attached to one surface of the other wafer, and a hot pressing process is performed to fix the two wafers together via the first material layer. In some embodiments, the surface of the other wafer is provided with contacts for transmitting signals or power, and after the two wafers are attached, the contacts on the respective surfaces are combined with each other, and the first material layer surrounds the contacts combined with each other to achieve insulation between adjacent contacts.

[0071] In some embodiments, the wafer provided in S15 can be a wafer containing multiple dies, or a single die or other bearing structure, such as a carrier wafer.

[0072] In some embodiments, the wafer in S13 is a wafer containing multiple dies, and when this wafer is flipped over in S15, a cutting process is performed on the wafer with the first material layer to form multiple second semiconductor chips separated from each other; the wafer provided in S15 is a single die, i.e., a first semiconductor chip.

[0073] In some embodiments, the wafer in S13 is a wafer containing multiple dies, and when this wafer is flipped over in S15, a cutting process is performed on the wafer with the first material layer to form multiple second semiconductor chips separated from each other; the wafer provided in S15 is a wafer containing multiple dies, and after the step of S15 is completed, a singulation step is further performed, i.e., the other wafer provided in S15 is divided into multiple first semiconductor chips, i.e., the second semiconductor chips are attached first to the wafer containing the first semiconductor chips, and then the first semiconductor chips are separated, thereby obtaining a package combining the first semiconductor chips and the second semiconductor chips.

[0074] In these embodiments, the first semiconductor chips and the second semiconductor chips can be chips with different areas.

[0075] In some embodiments, the first material layer can also be formed on the first semiconductor chip or the wafer containing the first semiconductor chip first, and then attached between the second semiconductor chip or the wafer containing the second semiconductor chip via the first material layer.

[0076] The formation of the package of the present disclosure is not limited to this, and will not be described here.

[0077] In some embodiments, since the first material layer is formed on the first semiconductor chip or the second semiconductor chip first, the thermal compression bonding (TCB) process adopted in the process of bonding the first semiconductor chip and the second semiconductor chip involves temperature rising and falling and pressure changing, in which the first material layer has a certain flowability at a temperature lower than the hardening temperature of the first material layer, so as to realize the encapsulation of the first semiconductor chip and the second semiconductor chip, and then the first material layer is hardened at the hardening temperature of the first material layer. In this process, the first material layer has a part that overflows the first semiconductor chip or the second semiconductor chip. In the prior art, considering the problem of CTE mismatch between the chip and the material bonding the chip, more material overflowing to the surface of the chip not in direct contact with the chip is prevented by controlling the bonding pressure in the TCB process. However, for the sealing effect of the chip, more overflowing material can effectively ensure that there is enough amount of insulating sealing material between the dense contacts between the chip and the chip, and the first material layer provided by the embodiments of the present disclosure can well solve the CTE problem in the case of more overflow, and better packaging reliability is obtained.

[0078] Referring to FIGS. 4A and 4B, FIG. 4A shows a structural schematic diagram of the package 10 in which the first material layer is formed on the first semiconductor chip first. Since the first material layer 40 has been formed on the first semiconductor chip 30 before the first semiconductor chip 30 and the second semiconductor chip 20 are combined, the third material layer 50 formed after the combination of the first semiconductor chip 30 and the second semiconductor chip 20 has a first contact surface directly abutting the first material layer 40, and the second semiconductor chip 20 has a surface not covered by the first material layer 40. In some embodiments, the sidewall of the second semiconductor chip 20 can also be partially covered by the first material layer 40, that is, the part of the first material layer 40 at the outer periphery of the second semiconductor chip 20 has a protruding part, and the protruding part can encapsulate part of the sidewall surface of the second semiconductor chip 20.

[0079] In some embodiments, the third material layer 50 has a second contact surface directly contacting the second semiconductor chip 20, and the surface area of the first contact surface is greater than that of the second contact surface.

[0080] In some embodiments, as shown in FIG. 4A, the first material layer 40 can have an edge not covered by the third material layer 50.

[0081] Referring to FIG. 4B, a structure of the package 10 is shown, in which the first material layer 40 is formed on the second semiconductor chip 20. Since the first material layer 40 is formed on the second semiconductor chip 20 before the first semiconductor chip 30 and the second semiconductor chip 20 are bonded, the first material layer 40 has a portion that overflows the second semiconductor chip 20 during the TCB process of bonding the first semiconductor chip 30 and the second semiconductor chip 20. The third material layer 50 formed after the first material layer 40 has a first contact surface directly abutting the first material layer 40 and a third contact surface directly abutting the first semiconductor chip 30. The second semiconductor chip 20 has a surface that is not covered by the first material layer 40. In some embodiments, the sidewall of the second semiconductor chip 20 can also be partially covered by the first material layer 40, i.e., the first material layer 40 has a protruding portion at the periphery of the second semiconductor chip 20, which can cover part of the sidewall surface of the second semiconductor chip 20.

[0082] In some embodiments, the third material layer 50 has a second contact surface directly contacting the second semiconductor chip 20, and the first contact surface has a larger surface area than the second contact surface.

[0083] In some embodiments, the third contact surface has a smaller surface area than the first contact surface.

[0084] In these embodiments, since the CTEs of the provided first material layer and the third material layer are closer, the direct contact area between the first material layer and the third material layer is larger than the direct contact area between the third material layer and the second semiconductor chip after the heat pressing process, and thus the package has better packaging reliability.

[0085] In some embodiments, referring to FIGS. 5A, 5B, and 5C, the semiconductor package 10 further includes a plurality of third semiconductor chips 21 disposed on the second semiconductor chip 20. The third semiconductor chip 21 closest to the second semiconductor chip 20 is directly bonded to the second semiconductor chip 20, and the first material layer 40 is disposed on the surface of the third semiconductor chip 21 that is not bonded to the second semiconductor chip 20. The number of the third semiconductor chips 21 can be 3 or more, such as 7, 11, etc. The number of the third semiconductor chips 21 is 3 in the present disclosure as an example, but is not limited thereto. The third semiconductor chips 21 can be the same type or different type of chips as the second semiconductor chip 20. For example, the third semiconductor chips 21 and the second semiconductor chip 20 are both memory chips.

[0086] In some embodiments, referring to FIG. 5A, the second semiconductor chip 20 and the third semiconductor chip 21 are bonded by the first material layer 40. The third semiconductor chips 21 are also bonded by the first material layer 40, and the periphery of the third semiconductor chips 21 is also coated by the third material layer 50. In some embodiments, the first material layer partially covers the surface of the second semiconductor chip and the third semiconductor chip, i.e., the third material layer 50 also coats the periphery of the first material layer 40. In these embodiments, by using the overlapping of the first material layer and the third material layer, the stress caused by the multiple thermal compression processes in the multi-chip stacking is effectively balanced, and higher packaging reliability is obtained.

[0087] In some embodiments, referring to FIG. 5B, the second semiconductor chip 20 and the third semiconductor chip 21 are not bonded by the first material layer, but are bonded and fixed by direct surface bonding. For example, fusion bonding is used to bond the chips, or hybrid bonding is used to simultaneously bond and electrically connect the chips. In some embodiments, the adjacent group of third semiconductor chips 21 can also be bonded by direct bonding or by the first material layer. As shown in FIG. 5B, the first third semiconductor chip 21 and the second semiconductor chip 20 are bonded by direct bonding, the second third semiconductor chip 21 and the third semiconductor chip 21 are bonded by the first material layer 40, and the third third semiconductor chip 21 and the fourth third semiconductor chip 21 are bonded by direct bonding. The third material layer 50 coats the periphery of the second semiconductor chip 20 and the plurality of third semiconductor chips. In some embodiments, the first material layer partially covers the surface of the second semiconductor chip and the third semiconductor chip, i.e., the third material layer 50 also coats the periphery of the first material layer 40. In these embodiments, in addition to continuing to use the CTE-matched first material layer and the third material layer for sealing, at least two chips are bonded by direct bonding, which can further miniaturize the size of the package and increase the capacity of the package.

[0088] In some embodiments, referring to FIG. 5C, the second semiconductor chip 20 and the third semiconductor chip 21 are not bonded by the first material layer, but are bonded by the second material layer 60. The second material layer 60 includes a resin-based substrate and fillers dispersed in the substrate, and the fillers in the second material layer 60 can have the same particle size distribution, type, and volume ratio as the fillers 42 in the first material layer 40, which will not be repeated here. In some embodiments, the second material layer 60 is provided between at least two third semiconductor chips to bond them. FIG. 5C shows an embodiment in which the third semiconductor chips are bonded by the second material layer 60. The third material layer 50 covers the outer periphery of the second semiconductor chip 20 and each third semiconductor chip 21, and the outer periphery of the first material layer 40 and the second material layer 60 is also covered by the third material layer 50. In these embodiments, the use of the second material layer instead of part of the first material layer can further reduce costs.

[0089] The present disclosure also provides a package 10, which, in some embodiments, referring to FIG. 6, includes a first semiconductor chip 30, a second semiconductor chip 20, a plurality of third semiconductor chips 21, and a conductive structure 70 connecting the chips. The first semiconductor chip 30 and the second semiconductor chip 20 are bonded by the first material layer 40, the second semiconductor chip 20 and the third semiconductor chip 21 are bonded by the first material layer 40, and each third semiconductor chip 21 is bonded by the first material layer 40. The third material layer 50 covers the space between the chips that is not covered by the first material layer 40.

[0090] In some embodiments, the chips can also be bonded by the second material layer, and the positions of the first material layer and the third material layer can be set in the manner described above, which will not be particularly limited here.

[0091] Continuing to refer to FIG. 6, in some embodiments, the conductive structure 70 includes a contact pad 701 provided on the surface of the first semiconductor chip 30, the contact pad 701 connecting the circuit structure in the first semiconductor chip 20, the conductive structure 70 further includes a contact pad 703 provided in the surface dielectric layer 202 of the second semiconductor chip 20 and an intermediate interconnection structure 702 connecting the contact pad 703 and the contact pad 701, the contact pad 703 connecting the circuit structure in the second semiconductor chip 20. In these embodiments, the first material layer 40 covers the intermediate interconnection structure 702, and the contact pad 703 and the contact pad 701 are not covered by the first material layer 40.

[0092] In some embodiments, the first contact pad 701 and the second contact pad 703 can be a metal or an alloy such as copper (Cu), nickel (Ni), tungsten (W), aluminum (Al), etc.

[0093] In some embodiments, the intermediate interconnect structure 702 can be a solder containing one or more of tin (Sn), titanium (Ti), vanadium (V), antimony (Sb), lead (Pb), tungsten (W), chromium (Cr), copper (Cu), nickel (Ni), aluminum (Al), palladium (Pd), silver (Ag), and gold (Au).

[0094] With continued reference to FIG. 6, in some embodiments, the surface of the first semiconductor chip 30 is provided with a dielectric layer 301, and the contact pads 701 are disposed in the dielectric layer 301; the opposite surfaces of the second semiconductor chip 20 are respectively provided with a dielectric layer 201 and a dielectric layer 202, the contact pads 703 are disposed in the dielectric layer 202, and the contact pads 705 are disposed in the dielectric layer 201, and the contact pads 703 and the contact pads 705 are interconnected through the interconnect via 704 disposed in the second semiconductor chip 20, thereby realizing the electrical connection between the first semiconductor chip 30 and the second semiconductor chip 20. The other surface of the first semiconductor chip 30 is also provided with the solder balls 302, which are used to interconnect the first semiconductor chip 30 and other structures, such as a silicon interposer, a PCB circuit board, etc.

[0095] The beneficial effects of these embodiments will be further described below in detail with reference to FIGS. 7A-7B and 8A-8B.

[0096] FIGS. 7A and 7B are schematic diagrams of some embodiments of the present disclosure. As shown in FIG. 7A, before the chip 30’ and the chip 20’ are attached, the first material layer 40’ is disposed on the chip 20’; the contact pads 701’ are disposed in the dielectric layer 301’ on the surface of the chip 30’, and have portions protruding from the surface of the chip 30’, and the contact pads 703’ are disposed in the dielectric layer 202’ on the surface of the chip 20’, and have portions protruding from the surface of the chip 20’. The intermediate interconnect structure 702’ is formed on the contact pads 703’, and is covered by the first material layer 40’. As shown in FIG. 7B, under the action of a thermal compression bonding device, the chip 30’ and the chip 20’ are interconnected through the first material layer 40’, and the intermediate interconnect structure 702’ is connected to the contact pads 701’. During the thermal compression process, the intermediate interconnect structure 702’ will deform more relative to the contact pads 701’ and the contact pads 703’, forming interfaces protruding from the contact pads 701’ and the contact pads 703’, and the deformed interfaces and the portions of the contact pads will all be disposed in the first material layer 40’, which causes the force of the intermediate interconnect structure 702’ extruding the first material layer 40’ during the deformation process to simultaneously extrude the first material layer 40’ on the surfaces of the contact pads outward, as shown by the black arrows in FIG. 7B. This leads to the risk of peeling of the first material layer 40’ from the surfaces of the contact pads, thereby reducing the packaging reliability.

[0097] FIG. 8A-FIG. 8B are partial enlarged views of the area A in FIG. 6. As shown in FIG. 8A, before bonding, the contact pad 701 of the first semiconductor chip 30 and the contact pad 703 of the second semiconductor chip 20 are disposed in the dielectric layer 202 and the dielectric layer 301, respectively. The first material layer 40 is formed on the surface of the dielectric layer 202 of the second semiconductor chip 20 and covers the intermediate interconnection structure 702 formed on the contact pad 703. As shown in FIG. 8B, under the action of the thermal compression bonding equipment, since the contact pad 701 and the contact pad 703 are disposed in the dielectric layer on the surface of each chip and do not contact the first material layer 40, the sealing effect of the contact pad 701 and the contact pad 703 will not be affected during the deformation of the intermediate interconnection structure 702, avoiding the risk of large deformation of the intermediate interconnection structure 702. In addition, the first material layer 40 in the embodiment of the present disclosure adopts a composite filler, which has a lower CTE, can effectively resist the deformation of the intermediate interconnection structure 702, prevent the sealing problem caused by the interface between the first material layer 40 and the intermediate interconnection structure 702 becoming more complex, and prevent shorting between adjacent intermediate interconnection structures 702.

[0098] The above description of beneficial effects is only a presentation of one of the technical effects of the embodiments of the present disclosure and does not constitute any limitation on the technical solutions of these embodiments.

[0099] In some embodiments, as shown in FIG. 6, the first material layer 40 can be first disposed on the second semiconductor chip 20, and then the first third semiconductor chip 21 is stacked on the second semiconductor chip 20. Subsequently, the first material layer 40 is disposed on the surface of the first third semiconductor chip 21 away from the second semiconductor chip 20, and then the second third semiconductor chip 21 is stacked on the surface of the first third semiconductor chip 21 containing the first material layer, and so on, to realize the stacking of multiple third semiconductor chips 21.

[0100] In some embodiments, the first material layer 40 can be first disposed on the surface of the first third semiconductor chip 21 facing the second semiconductor chip 20, and then the surface is bonded towards the second semiconductor chip 20 to realize the bonding between the second semiconductor chip 20 and the first third semiconductor chip 21. Subsequently, the first material layer 40 is disposed on the surface of the second third semiconductor chip 21, and the surface is bonded towards the surface of the first third semiconductor chip 21 away from the second semiconductor chip 20 to realize the bonding between the first third semiconductor chip 21 and the second third semiconductor chip 21, and so on, to realize the stacking of multiple third semiconductor chips 21.

[0101] In some embodiments, the third material layer 50 is formed by one step injection filling after the first semiconductor chip 30, the second semiconductor chip 20 and the plurality of third semiconductor chips 21 are stacked. In some embodiments, the third material layer 50 can also be used to coat the chip stack in other ways known to those skilled in the art, which will not be described here.

[0102] In some embodiments, the package 10 further comprises interconnection structures connecting the second semiconductor chip 20 and the third semiconductor chip 21 and connecting each third semiconductor chip 21, which can adopt the same interconnection structure as the first semiconductor chip 30 and the second semiconductor chip 20. In other embodiments, other interconnection chip connection methods known to those skilled in the art can also be used, which will not be described here.

[0103] Some embodiments of the present disclosure also provide another semiconductor package 10, as shown in FIG. 9, comprising a buffer chip 11, a core chip 12 disposed on the buffer chip 11, and a first material layer 40 surrounding the buffer chip 11 and the core chip 12 at the same time, which is the first material layer 40 used in the above-mentioned embodiments.

[0104] In order to make the content of the semiconductor package 10 clearer, the following further describes the process of forming the semiconductor package 10.

[0105] In some embodiments, the formation of the semiconductor package 10 comprises the following steps:

[0106] S21, respectively providing a first type of filler and a second type of filler, mixing the first type of filler and the second type of filler into a non-conductive substrate, and mixing the first type of filler and the second type of filler in the non-conductive substrate by stirring or other methods to obtain the first material layer 40.

[0107] S23, providing the buffer chip 11 and the core chip 12, and the buffer chip 11 and the core chip 12 are provided with spaced-apart contacts on the surface, and the contacts of the buffer chip 11 and the core chip 12 are corresponded one by one to complete pre-bonding.

[0108] S25, filling the first material layer 40 into the gap between the pre-bonded buffer chip 11 and core chip 12 by reflow filling process, and then performing solidification process to complete the bonding between the buffer chip 11 and the core chip 12.

[0109] The first material layer 40 formed by the above steps will coat the buffer chip 11 and the core chip 12 at the same time. Since the prepared first material layer 40 has lower CTE and better thermal conductivity, the package formed by these embodiments shows good performance.

[0110] In some embodiments, the core chip 12 can be a stack of multiple core chips, and the first material layer 40 simultaneously coats the stack. In some embodiments, the buffer chip 11 can be a logic chip, such as a gate array, a cell base array, an embedded array, a structured application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a central processing unit (CPU), a micro processing unit (MPU), a micro controller unit (MCU), a logic IC, an application processor (AP), a driver IC, an RF chip, a CMOS image sensor, and the like. The core chip 12 can be a memory chip, such as a DRAM, which is not described herein.

[0111] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various modifications and modifications without departing from the spirit and scope of the embodiments of the present disclosure, and therefore the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A semiconductor package comprising: a first semiconductor chip; a second semiconductor chip disposed on the first semiconductor chip; a first material layer disposed between the first semiconductor chip and the second semiconductor chip; wherein the first material layer comprises a non-conductive substrate and a first type of filler and a second type of filler distributed in the non-conductive substrate, the first type of filler having an average particle size different from that of the second type of filler.

2. The semiconductor package of claim 1, wherein, The first type of filler contains no metal element, the second type of filler contains a metal element, and the average particle size of the first type of filler is greater than that of the second type of filler.

3. The semiconductor package of claim 2, wherein, The average particle size of the first type of filler is 2-3 times that of the second type of filler.

4. The semiconductor package of claim 1, wherein, The volume fraction of the first type of filler in the non-conductive substrate is greater than that of the second type of filler in the non-conductive substrate.

5. The semiconductor package of claim 4, wherein, The volume ratio of the first type of filler to the second type of filler ranges from 2 to 4.

5.

6. The semiconductor package of claim 1, wherein, Further comprising a third material layer disposed on the first semiconductor chip, the third material layer comprising a substrate and a third type of filler distributed in the substrate, the third type of filler having an average particle size greater than that of the first type of filler and that of the second type of filler.

7. The semiconductor package of claim 6, wherein, The third material layer has a first contact surface with the first material layer, and a second contact surface with the second semiconductor chip, the first contact surface having a surface area greater than that of the second contact surface.

8. The semiconductor package of claim 6, wherein, The third material layer is also disposed on the first material layer, and the first material layer has a portion not covered by the third material layer.

9. The semiconductor package of claim 1, wherein, Further comprising a third semiconductor chip disposed on the second semiconductor chip, the third semiconductor chip being free of the first material layer between the third semiconductor chip and the second semiconductor chip, and the third semiconductor chip being disposed with the first material layer away from a surface of the second semiconductor chip.

10. The semiconductor package of claim 9, wherein, The third semiconductor chip and the second semiconductor chip are disposed with a second material layer therebetween, the second material layer having the first type of filler distributed therein.

11. The semiconductor package of claim 9, wherein, The third semiconductor chip and the second semiconductor chip are electrically connected by direct bonding.

12. The semiconductor package of claim 1, wherein, The first material layer further comprises an electrically conductive structure electrically connecting the first semiconductor chip and the second semiconductor chip, and the first material layer at least surrounds part of the electrically conductive structure.

13. The semiconductor package of claim 12, wherein, The electrically conductive structure comprises a first contact pad connected to the first semiconductor chip, a second contact pad connected to the second semiconductor chip, and an intermediate interconnection structure connecting the first contact pad and the second contact pad, and the first material layer surrounds the intermediate interconnection structure. 14.A semiconductor package comprising: a buffer chip; a core chip disposed on the buffer chip; a first material layer at least partially surrounding the buffer chip and the core chip; wherein The first material layer includes a non-conductive substrate and a first type of filler and a second type of filler distributed in the non-conductive substrate, the average particle size of the first type of filler being different from the average particle size of the second type of filler.

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