Communication method and communication apparatus

Abstract

A communication method and a communication apparatus. The method comprises: a transmitting device determining a first base matrix, wherein the first base matrix is included among a plurality of LDPC base matrices, the number P of punctured columns of the first base matrix is different from the number of punctured columns of at least one remaining base matrix among the plurality of LDPC base matrices, 0≤P≤2, P=A / B, A is a non-negative integer, and B is related to a first lift value set; and on the basis of the number L of punctured bits in the first base matrix, processing a first information bit sequence to obtain a bit sequence to be transmitted, wherein the length of the first information bit sequence is K, K is equal to the product of kb and Zc, kb is the number of information columns included in the first base matrix, Zc is included in the first lift value set, and L is determined on the basis of P and Zc. In the above technical solution, LDPC codes with different numbers of punctured columns are provided, and thus, rate matching requirements of different communication systems can be satisfied.

Description

Communication method and communication apparatus

[0001] The present application claims priority to the Chinese Patent Application No. 202410463526.7, filed on April 16, 2024, and entitled “Communication method and communication apparatus”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of coding, and more particularly, to a communication method and a communication apparatus. BACKGROUND

[0003] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used channel coding schemes. Quasi-cyclic low density parity check (QC-LDPC) codes are a class of structured LDPC codes. Due to the unique structure of the check matrix, a simple feedback shift register can be used for encoding, which reduces the encoding complexity of LDPC codes.

[0004] Currently, the base graph (BG) of the QC-LDPC code described in the standard includes BG1 and BG2. The first two columns of BG1 and BG2 are fixed puncturing columns when rate matching. Taking BG1 as an example, in a scenario where a higher code rate is needed (such as a high-throughput scenario), the code rate needed is greater than the code rate corresponding to the core matrix of BG1. Therefore, part of the check columns need to be punctured additionally. Due to the excessive puncturing bits, the decoding threshold is poor, and the convergence speed is slow, which results in a large performance loss in scenarios where a higher code rate is needed. Therefore, the current single puncturing mode cannot meet the needs of all communication scenarios. SUMMARY

[0005] Embodiments of the present application provide a communication method and a communication apparatus, which can meet the rate matching needs of different communication scenarios.

[0006] In a first aspect, a communication method is provided, which can be executed by a sending end device. In the absence of special description, the “sending end device” in the present application can refer to the sending end device itself (for example, a network device, a terminal device), a component (for example, a processor, a chip, or a chip system, etc.) in the sending end device, or a logic module or software capable of realizing all or part of the functions of the sending end device.

[0007] The method comprises: determining a first base matrix, wherein the first base matrix is one base matrix in a plurality of low-density parity-check (LDPC) base matrices, a punctured column number P of the first base matrix is different from a punctured column number of at least one base matrix remaining in the plurality of LDPC base matrices, 0≤P≤2, P=A / B, A is a non-negative integer, and B is related to a first lifting value set; obtaining a first information bit sequence corresponding to the first base matrix, a length of the first information bit sequence is K, and K is equal to a product of kb and Zc, wherein kb is a column number of information columns contained in the first base matrix, and Zc is one lifting value contained in the first lifting value set; and processing the first information bit sequence based on a punctured bit number L of the first base matrix to obtain a to-be-sent bit sequence, the punctured bit number L being determined based on the punctured column number P of the first base matrix and Zc.

[0008] In the technical solution, the LDPC code with different punctured column numbers is given, thereby meeting the rate matching requirement of different communication systems. It can be understood that puncturing means that prior information is missing, and in the decoding process, the missing information needs to be filled first, and then iteration is performed. In the filling process, no mutual information of other nodes is improved, and thus the decoding threshold difference and slow convergence speed are caused. In the scheme, a fixed punctured number is not set, and puncturing is performed according to a scene and a code rate requirement, the maximum punctured column number (or punctured bit number) can be reduced, and thus the convergence speed is fast and the decoding threshold is good.

[0009] In a second aspect, a communication method is provided, which can be executed by a receiving end device. In the absence of special description, the receiving end device in the present application can refer to the receiving end device itself (for example, a network device or a terminal device), a component (for example, a processor, a chip, or a chip system) in the receiving end device, or a logic module or software capable of realizing all or part of the functions of the receiving end device.

[0010] The method comprises: obtaining a codeword sequence; obtaining a to-be-decoded sequence based on a punctured bit number L of a first base matrix and the codeword sequence, wherein the first base matrix is one base matrix in a plurality of low-density parity-check (LDPC) base matrices, a punctured column number P of the first base matrix is different from a punctured column number of at least one base matrix remaining in the plurality of LDPC base matrices, 0≤P≤2, P=A / B, A is a non-negative integer, and B is related to a first lifting value set; and decoding the to-be-decoded sequence based on the first base matrix to obtain a first information bit sequence, a length of the first information bit sequence being K, and K being equal to a product of kb and Zc, wherein kb is a column number of information columns contained in the first base matrix, and Zc is one lifting value contained in the first lifting value set.

[0011] The beneficial effects of the second aspect are described in the first aspect, and will not be repeated here.

[0012] In some implementations of the first aspect or the second aspect, L = P * Zc + P0, or, L = P * Zc + P0, or, L = P * Zc + P0, where P0 is a number of fixed punctured bits, and P0 is a non-negative integer.

[0013] In some implementations of the first aspect or the second aspect, any of the multiple lifting values included in the first set of lifting values is equal to a * 2 k , B is equal to 2 k1 , k1 is the k corresponding to any of the multiple lifting values, the multiple lifting values of the first set of lifting values are all integers greater than or equal to 2, or, any of the multiple lifting values included in the first set of lifting values is a * 3 k , B is equal to 3 k2 , k2 is the k corresponding to any of the multiple lifting values, where the multiple lifting values are all integers greater than or equal to 3.

[0014] In some implementations of the first aspect or the second aspect, k1 is 1 or 2, and k2 is 1 or 2.

[0015] In some implementations of the first aspect or the second aspect, P is one of the values in a first set, the first set is {0, 0.25, 0.5, 0.75, 1, 1.25, 1.5, 1.75}, or, the first set is {0, 0.5, 1, 1.5}, or, the first set is {0, 1 / 3, 2 / 3, 1, 4 / 3, 5 / 3}, or, the first set is {0, 2 / 3, 4 / 3}.

[0016] In some implementations of the first aspect or the second aspect, the multiple LDPC matrices further include a second base matrix, the second base matrix has a number of punctured columns Q, the code rate corresponding to the first base matrix is greater than the code rate corresponding to the second base matrix, or, the modulation order corresponding to the first base matrix is greater than the modulation order corresponding to the second base matrix, or, the coding and modulation scheme (MCS) level corresponding to the first base matrix is greater than the MCS level corresponding to the second base matrix, or, the length of a transport block (TB) corresponding to the first base matrix is greater than the length of a TB corresponding to the second base matrix, or, the number of coding blocks (CBs) corresponding to the first base matrix is greater than the number of CBs corresponding to the second base matrix, or, the number of multiple-input multiple-output (MIMO) streams corresponding to the first base matrix is greater than the number of MIMO streams corresponding to the second base matrix, or, the first base matrix corresponds to a LBRM enabled, and the second base matrix corresponds to a LBRM disabled, and P is less than Q.

[0017] In some implementations of the first aspect or the second aspect, P = 0, and Q = 0.5.

[0018] In some implementations of the first aspect or the second aspect, 0 < P ≤ 1, the P puncturing columns of the first base matrix are associated with a first puncturing column, where the first puncturing column is a first column of the first base matrix, or 1 < P ≤ 2, the P puncturing columns of the first base matrix are associated with a first puncturing column and a second puncturing column, where the first puncturing column and the second puncturing column are a first column and a second column of the first base matrix.

[0019] In the technical solution, the P puncturing columns of the first base matrix are sequentially selected from a first column (a first column) of the first base matrix, and the implementation is simple.

[0020] In some implementations of the first aspect or the second aspect, the to-be-sent bit sequence includes an Lth bit to a (K-1)th bit of the first information bit sequence.

[0021] It can be understood that the bit sequence in the first information bit sequence is numbered from 0, and the K bits of the first information bit sequence are the 0th bit to the Kth bit.

[0022] In the technical solution, the puncturing bits are sequentially punctured from a first bit (i.e., the 0th bit) of the first information bit sequence, and the rate matching is simple and easy to operate.

[0023] In some implementations of the first aspect or the second aspect, the puncturing columns of the first base matrix are determined based on a first matrix, where the first matrix is the first base matrix; the first matrix is a matrix corresponding to a lowest code rate supported by the first base matrix in a current communication scenario; the first matrix is a core matrix corresponding to the first base matrix; the first matrix is a matrix corresponding to a highest code rate supported by the first base matrix, and the highest code rate is a highest code rate indicated by the MCS.

[0024] In an example, the puncturing columns of the first base matrix can be determined based on a column weight of the first matrix and / or a position in which a value of the first matrix is 1.

[0025] In some implementations of the first aspect or the second aspect, 0 < P ≤ 1, the P puncturing columns of the first base matrix are associated with a first puncturing column, where the first puncturing column is a first column of the first base matrix, or 1 < P ≤ 2, the P puncturing columns of the first base matrix are associated with a first puncturing column and a second puncturing column, where the first puncturing column and the second puncturing column are a first column and a second column of the first base matrix.

[0026] In the technical solution, the information columns of the first matrix are punctured because the check bits corresponding to the check columns need to support the encoding structure and are not suitable for puncturing. In addition, the column with the largest column weight is selected, and the overall decoding threshold is better.

[0027] In some implementations of the first aspect or the second aspect, the first puncturing column is a k1th column of the first base matrix, the to-be-transmitted bit sequence includes 0th bit to K1-1th bit in the first information bit sequence, K1+Lth bit to K-1th bit, where K1=k1*Zc.

[0028] In the technical solution, the puncturing bits are punctured from the first bit corresponding to the first puncturing column in the first information bit sequence, which is simple in hardware implementation and easy to operate in rate matching.

[0029] In some implementations of the first aspect or the second aspect, 1

[0030] In the technical solution, the information columns of the first matrix are punctured because the check bits corresponding to the check columns are not suitable for puncturing to support the coding structure. In addition, the column with the largest column weight is selected, and the overall decoding threshold is better.

[0031] In some implementations of the first aspect or the second aspect, 1

[0032] In the technical solution, the information columns of the first matrix are punctured because the check bits corresponding to the check columns are not suitable for puncturing to support the coding structure. In addition, in the scenario where the first puncturing column has the largest column weight, the column having the least common check node with the first column is selected, which can minimize the rows having two puncturing columns and accelerate the convergence speed of decoding.

[0033] In some implementations of the first aspect or the second aspect, the first puncturing column is an xth column of the first base matrix, the second puncturing column is a yth column of the first base matrix, the number of puncturing bits L includes Zc bits in the first information bit sequence corresponding to the first puncturing column and (P-1)*Zc bits in the first information bit sequence corresponding to the second puncturing column, if x < y, the to-be-transmitted bit sequence includes 0th bit to (xZc-1)th bit in the first information bit sequence, (xZc+Zc)th bit to (yZc-1)th bit, (yZc+(P-1)*Zc)th bit to (K-1)th bit in the first information bit sequence, if x > y, the to-be-transmitted bit sequence includes 0th bit to (yZc-1)th bit in the first information bit sequence, (yZc+(P-1)*Zc)th bit to (xZc-1)th bit, (xZc+Zc)th bit to (K-1)th bit in the first information bit sequence.

[0034] In the technical solution, puncturing bits are punctured from the first bit in the first information bit sequence corresponding to the first puncturing column and the second puncturing column, and the hardware implementation is simple, and rate matching is simple and easy to operate.

[0035] In some implementations of the first aspect or the second aspect, the first base matrix is a base matrix of nested information columns, the first base matrix includes N information columns, N > 22 and N is an integer, the N information columns are located in the first N columns of the first base matrix, and a matrix composed of remaining columns of the first base matrix except the first 22 columns is a base matrix corresponding to BG1 defined in a protocol.

[0036] The technical solution can be compatible with a coding scheme of 5G, and standard changes are small.

[0037] In some implementations of the first aspect or the second aspect, the puncturing column of the first base matrix is included in a fourth column set, and the fourth column set is a column set corresponding to information columns that the first base matrix must include under any use condition.

[0038] The technical solution can ensure that the puncturing column is not changed in the case that the intercepted information column is different, and the implementation of the rate matching module is simple, and the unified puncturing column can ensure a good decoding threshold in a flexible rate case.

[0039] In some implementations of the first aspect or the second aspect, the first base matrix includes a base matrix corresponding to BG1, and the puncturing column of the first base matrix is included in a puncturing column corresponding to BG1.

[0040] The technical solution can be compatible with an existing communication scheme, changes are small, additional burdens on equipment are reduced, and performance benefits can be obtained.

[0041] In a third aspect, a communication apparatus is provided. The apparatus is configured to execute the method in any of the preceding aspects or implementation manners. Specifically, the apparatus can include units and / or modules for performing the method in any of the preceding aspects or implementation manners, such as a processing unit and / or a transceiving unit.

[0042] In an implementation manner, the apparatus is a sending device or a receiving device. When the apparatus is the sending device or the receiving device, the transceiving unit can be a transceiver, or an input / output interface, or a communication interface; and the processing unit can be at least one processor. Optionally, the transceiver is a transceiving circuit. Optionally, the input / output interface is an input / output circuit.

[0043] In another implementation manner, the apparatus is a chip, a chip system or a circuit for the sending device or the receiving device. When the apparatus is the chip, the chip system or the circuit for the sending device or the receiving device, the transceiving unit can be an input / output interface, an interface circuit, an output circuit, an input circuit, a pin or related circuit, etc. on the chip, the chip system or the circuit; and the processing unit can be at least one processor, a processing circuit or a logic circuit, etc.

[0044] In a fourth aspect, a communication apparatus is provided. The apparatus includes a memory configured to store a program; and at least one processor configured to execute the computer program or instructions stored in the memory to perform the method in any of the preceding aspects or implementation manners.

[0045] In an implementation manner, the apparatus is a sending device or a receiving device.

[0046] In another implementation manner, the apparatus is a chip, a chip system or a circuit for the sending device or the receiving device.

[0047] In a fifth aspect, a communication apparatus is provided. The apparatus includes at least one processor and a communication interface. The at least one processor is configured to acquire, through the communication interface, a computer program or instructions stored in a memory to perform the method in any of the preceding aspects or implementation manners. The communication interface can be implemented by hardware or software.

[0048] In an implementation manner, the apparatus further includes the memory.

[0049] In a sixth aspect, a processor is provided. The processor is configured to perform the method in any of the preceding aspects.

[0050] For the sending and obtaining / receiving operations involved by the processor, if no special description is made, or if it does not conflict with the actual role or internal logic in the related description, it can be understood as the processor output and receive, input, etc. Operation, but also can be understood as the sending and receiving operations performed by the radio frequency circuit and the antenna, and the present application does not limit this.

[0051] In a seventh aspect, a computer readable storage medium storing program code for execution by an apparatus is provided. The program code includes code for performing the method provided by any of the above aspects or implementation manners thereof.

[0052] In an eighth aspect, a computer program product containing instructions which, when the computer program product is executed on a computer, cause the computer to carry out the method provided by any of the above aspects or implementation manners thereof.

[0053] In a ninth aspect, a chip is provided. The chip includes a processor and a communication interface. The processor reads instructions stored on a memory through the communication interface and executes the method provided by any of the above aspects or implementation manners thereof. The communication interface can be implemented by hardware or software.

[0054] Optionally, as an implementation manner, the chip further includes a memory. The memory stores a computer program or instructions. The processor is configured to execute the computer program or instructions stored in the memory. When the computer program or instructions are executed, the processor is configured to execute the method provided by any of the above aspects or implementation manners thereof.

[0055] When the method provided by the present application is executed by a chip, the present application does not limit the number of chips that specifically implement the method of the present application. For example, the method can be executed by one chip, or by two or more chips. When the number of chips that implement the method of the present application is two or more, the chips can be from the same manufacturer or different manufacturers.

[0056] In a tenth aspect, a computer program is provided. When the computer program is executed on a computer, the method provided by any of the above aspects or implementation manners thereof is executed.

[0057] In an eleventh aspect, a communication system is provided. The communication system includes at least one of the above-described sending device or receiving device. BRIEF DESCRIPTION OF DRAWINGS

[0058] FIG. 1 is a schematic diagram of a network architecture to which embodiments of the present application can be applied.

[0059] FIG. 2 is a schematic diagram of a check matrix H of an LDPC.

[0060] FIG. 3 is a Tanner graph of a parity check matrix H of an LDPC code.

[0061] FIG. 4 is a schematic diagram of a structure of a parity check matrix.

[0062] FIG. 5 is a schematic diagram of a process of information transmission.

[0063] FIG. 6 is a schematic flowchart of a communication method 600 provided by the present application.

[0064] FIG. 7 is a schematic diagram of a base matrix corresponding to a base graph of a nested BG1.

[0065] FIG. 8 is a performance simulation diagram of a puncturing scheme provided by the present application.

[0066] FIG. 9 is a schematic block diagram of a communication apparatus 1000 provided by an embodiment of the present application.

[0067] FIG. 10 is a schematic block diagram of a communication apparatus 1100 provided by an embodiment of the present application. DETAILED DESCRIPTION

[0068] In order to facilitate understanding of the embodiments of the present application, the following points are explained before the embodiments of the present application are introduced.

[0069] "Indicative of" or "indicate" can include both direct and indirect indication, or "indicative of" or "indicate" can explicitly and / or implicitly indicate. The first, second, etc. various numerical designations are only for the convenience of description and do not limit the scope of the embodiments of the present application, for example, to distinguish different messages, different information, etc. "Predefined" can be achieved by pre-storing corresponding codes, tables or other means for indicating relevant information in the device, and the specific implementation manner is not limited in the present application. The "protocol" referred to can refer to a standard protocol in the communication field, which can include a long term evolution (LTE) protocol, a new radio (NR) protocol and a related protocol applied in a future communication system, and the present application is not limited thereto. The words "example", "for example", "exemplary", "as an example", etc. are used to indicate an example, illustration or description. Any embodiment or design scheme described as "example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. The terms "include", "contain", "have" and their variants mean "including but not limited to", unless otherwise specifically emphasized. "At least one" refers to one or more, and "multiple" refers to two or more. "At most one" refers to one or 0. "And / or", which describes the association relationship of the associated objects, means that there can be three kinds of relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b and c can represent: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple. The description related to the network element A sending a message, information or data to the network element B, and the network element B receiving the message, information or data from the network element A, is intended to indicate which network element the message, information or data is intended to send to, and does not limit whether they are directly sent or indirectly sent via other network elements. "When", "in the case of", "if" and "if" and other descriptions all refer to the objective situation in which the device will make corresponding processing, and are not limited by time, and do not require the device to have a judgment action when implemented, nor does it mean that there are other limitations.

[0070] In addition, the network architecture and service scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that, with the evolution of network architecture and the emergence of new service scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0071] The communication system to which the embodiments of the present application can be applied will be described below.

[0072] The embodiments of the present application can be applied to various communication systems, including but not limited to: a 5th generation (5G) system, an LTE system, a long term evolution-advanced (LTE-A) system, an LTE frequency division duplex (FDD) system, an LTE time division duplex (TDD) system, etc. It can also be applied to future communication systems, such as a 6th generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), an internet of things (IoT) communication system, a narrow band-internet of things (NB-IoT) system, or other communication systems. In addition, it can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and 3rd generation partnership project (3GPP) related communication systems, etc., without limitation.

[0073] The communication system to which the embodiments of the present application can be applied can include one or more transmitting end devices and one or more receiving end devices. Optionally, one of the transmitting end device and the receiving end device can be a terminal device, and the other can be a network device. Optionally, the transmitting end device and the receiving end device can both be terminal devices. Optionally, the transmitting end device and the receiving end device can both be network devices.

[0074] FIG. 1 is a schematic diagram of a network architecture to which embodiments of the present application are applicable. As shown in FIG. 1, embodiments of the present application are applicable to both uplink data transmission and downlink data transmission. In FIG. 1, only uplink data transmission or downlink data transmission between one network device and two terminal devices (e.g., terminal device 1 and terminal device 2) is taken as an example. In uplink data transmission, the transmitting terminal device is the terminal device and the receiving terminal device is the network device; conversely, in downlink data transmission, the transmitting terminal device is the network device and the receiving terminal device is the terminal device. In addition, embodiments of the present application are not limited to be applicable to other communication scenarios, for example, they can also be applied to sidelink communication.

[0075] The terminal device in the embodiments of the present application can also be referred to as a user equipment (UE), an access terminal, a user unit, a user station, a mobile station, a mobile station, a mobile terminal (MT), a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a drone, a wireless communication device, a user agent or a user apparatus, etc. The terminal device in the embodiments of the present application can refer to a device that provides voice and / or data connectivity to a user, and can be used to connect people, things and machines, such as handheld devices with wireless connection functions, vehicle-mounted devices, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, etc.

[0076] The network device of the present application can be a device with wireless transceiving function, which can be a device providing wireless communication function service, usually located at the network side, including but not limited to next generation base station (gNodeB, gNB) in 5G system, base station in sixth generation mobile communication system, base station in future mobile communication system, or access node in wireless fidelity (WiFi) system, evolved node B (eNB) in long term evolution (LTE) system, radio network controller (RNC), node B (NB), base station controller (BSC), home base station (such as home evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellite, unmanned aerial vehicle, etc. In one network structure, the network device can include a centralized unit (CU) node, or include a distributed unit (DU) node, or be a RAN device including CU node and DU node, or be a RAN device including control plane CU node and user plane CU node, and DU node, or the network device can also be a wireless controller in cloud radio access network (CRAN) scenario, relay station, vehicle-mounted device, wearable device, etc. In addition, the base station can be a macro base station, micro base station, relay node, donor node or combination thereof. The base station can also refer to a communication module, modem or chip for setting in the foregoing device or apparatus. The base station can also be a mobile switching center, and a device assuming base station function in D2D, V2X, M2M communication, a device assuming base station function in future communication system, etc. The base station can support networks of the same or different access technologies, without limitation.

[0077] Unless otherwise defined, the apparatuses used in the embodiments of the present application to realize the functions of the terminal device or the network device can refer to the terminal device or the network device itself, or can refer to an apparatus capable of supporting the terminal device or the network device to realize the functions, such as a chip system or a chip, specifically, a system on a chip (SoC) or a Modem. The apparatus can be installed in the terminal device or the network device. In the embodiments of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices.

[0078] It should also be noted that some embodiments in the present document take the 5G system as an example to introduce specific scheme details. It can be understood that when the scheme is used in other communication systems, for example, the LTE system, or future communication systems, the messages, channels or information in the scheme can be replaced by messages, channels or information capable of realizing corresponding functions in other communication systems, and the present application does not limit this.

[0079] In addition, the embodiments of the present application can be applied to various application scenarios, such as a high throughput scenario, a high reliability scenario, a low latency scenario, a high reliability low latency scenario, or a low power consumption scenario. Among them, the high throughput scenario can be, for example, an enhanced mobile broadband (eMBB) scenario, and the high reliability low latency scenario can be, for example, an ultra reliable low latency communication (URLLC) scenario.

[0080] In order to facilitate understanding of the embodiments of the present application, several concepts or terms related to the embodiments of the present application are briefly described. The concepts or terms described below are based on the concepts or terms defined in the protocol, but do not mean that the embodiments of the present application can only be applied to the existing system, and the concepts or terms related to the embodiments of the present application can be applied to future systems. And the specific name of the concept or term (for example, the concept or term related to the functional description) can be adjusted with the development of future systems.

[0081] 1、LDPC code

[0082] LDPC code is a kind of linear block code. Linear block code is to divide the information sequence to be coded into groups in units of q bits, and then linearly operate the q information bits by the encoder to obtain m check bits, and then combine the q information bits and the m check bits to obtain a code word with length n=q+m. The mapping relationship from the q-bit information bits to the n-bit code word is usually represented by a corresponding check matrix H. According to the check matrix H, the code word sequence can be generated to complete the coding process. After the code word sequence is transmitted through the channel, the receiving end device decodes the received signal to determine the original information bits.

[0083] The check matrix H of LDPC is a sparse matrix. The number of zero elements in the check matrix H is much larger than the number of non-zero elements, or in other words, the row weight (or column weight) of the check matrix is much smaller than the number of elements in each row (or each column) of the LDPC matrix. The LDPC code with the information bit sequence length equal to q and the code length equal to n can be uniquely determined by its check matrix H.

[0084] Tanner represented the check matrix H in the form of a graph in 1981. This graph is now called a Tanner graph, and the Tanner graph and the check matrix correspond one-to-one. The Tanner graph is composed of two types of vertices. One type of vertex represents a code word bit, which is called a variable node. The other type of vertex is a check node, which represents a check constraint relationship. Each check node represents a check constraint relationship. The following will be explained in conjunction with FIG. 2 and FIG. 3.

[0085] FIG. 2 is a schematic diagram of a check matrix H of an LDPC.

[0086] In FIG. 2, {V i} represents a set of variable nodes (VN), and {C i} represents a set of check nodes (CN). Each row of the check matrix H represents a check equation, each check equation corresponds to a check node, each column represents a code word bit, and each code word bit corresponds to a variable node. In FIG. 2, there are 8 variable nodes and 4 check nodes. If a code word bit is included in the corresponding check equation, a line is used to connect the variable node and the check node involved to obtain a Tanner graph.

[0087] FIG. 3 is a Tanner graph of a check matrix H of an LDPC.

[0088] As shown in FIG. 3, the Tanner graph represents the check matrix of the LDPC. For example, for a check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes, n variable nodes and m check nodes. The n variable nodes correspond to the n columns of the check matrix H, and the m check nodes correspond to the m rows of the check matrix H. A cycle in the Tanner graph is formed by a group of vertices connected to each other, a loop is formed by a vertex in the group of vertices serving as both a start point and an end point, and each node is passed only once. The length of the loop is defined as the number of edges contained in the loop, and the girth of the graph can also be referred to as the perimeter of the graph, which is defined as the minimum cycle length in the graph. As shown in FIG. 3, the girth is 4, as indicated by the black lines. Each variable node in the Tanner graph corresponds to each column of the check matrix H, that is, each code bit of the LDPC. Each check node in the Tanner graph corresponds to each row of the check matrix H, that is, each check bit of the LDPC. The connection between the two types of nodes corresponds to the value of the element in the H matrix. If there is a connection between the i th check node and the j th variable node, it means that the value of the element (i, j) in the H matrix is 1, and if there is no connection, the corresponding element is 0. The connection between the variable node and the check node can also be referred to as an edge. The connection between the check node and the variable node can also be described as: the check node and the variable node have a connection or an edge. The edge relationship between the check node and the variable node can include the existence of an edge or the non-existence of an edge. In addition, in the Tanner graph, a cycle refers to a closed loop formed by variable nodes, check nodes, and edges connected end to end.

[0089] 2. QC-LDPC code

[0090] The QC-LDPC code is a structured LDPC code. Due to the unique structure of the check matrix, a simple feedback shift register can be used for encoding, reducing the encoding complexity of the LDPC code. The QC-LDPC code actually used is represented by a base graph (BG). The elements in the BG are 0 or 1. The 1 and 0 in the BG are expanded, and the check matrix H obtained after the expansion can be used for encoding or decoding. In the embodiments of the present application, the BG can be written in the form of a matrix, which can be referred to as a base matrix H BG in the present application. BGThe middle element is 0, indicating that there is no edge in the base graph, and is 1, indicating that there is an edge in the base graph (or indicating that the corresponding check is associated with the corresponding variable). The NR LDPC code involves multiple base graph selection, and the current standard stores two base graphs BG1 and BG2. When the information length is less than or equal to 292, or the information length is less than or equal to 3824 and the code rate is less than or equal to 2 / 3, or the code rate is less than or equal to 0.25, BG2 is used, otherwise BG1 is used. The following describes the extension process of the base matrix.

[0091] Based on the base matrix and the lifting value Z c (lifting size), the base matrix can be extended to a complete check matrix for encoding or decoding. In this application, Z c may also be referred to as an extension factor, a lifting factor, an extension value, an extension coefficient, a lifting size, etc. The extension process is to lift all elements in the base matrix to a Z c ×Z c matrix, wherein 0 is lifted to a Z c ×Z c 0 matrix, and 1 is lifted to an identity matrix and cyclically shifted based on the shifting value (SV) corresponding to 1. The cyclic shift can be to the left or to the right, which is not limited in this application. It can be understood that each 1 in the base matrix corresponds to a shifting value. Taking a 4*4 identity matrix as an example, if the shifting values are 0, 1, and 3, the cyclic shift matrix after right cyclic shift is as shown in the following table:

[0092] (1) When the shifting value is 0 (i.e. remains unchanged), the corresponding matrix after cyclic shift is

[0093] (2) When the shifting value is 1, the corresponding matrix after cyclic shift is

[0094] (3) When the shifting value is 3, the corresponding matrix after cyclic shift is

[0095] It can also be understood that the complete check matrix H can be represented by an exponential matrix H b , where each element in H b corresponds to a Z c ×Z c submatrix, and each element identifies the number of times of cyclic shift of the corresponding submatrix from the identity matrix. Thus, the storage space required by the complete check matrix H is greatly reduced. The elements in the exponential matrix H b may also be referred to as QC blocks.

[0096] For example, the exponential matrix H of the QC-LDPC code is bAs shown below:

[0097] It can be seen that the exponential matrix H b The size of the exponential matrix H is 4 rows and 24 columns. b Each element i in represents a Z c square matrix of order represents the cyclic shift matrix, i represents the cyclic shift value of the cyclic shift matrix, and i is an integer. In addition, the exponential matrix H b The "-1" in represents an all-zero matrix, and "0" represents an identity matrix.

[0098] For example, As shown below:

[0099] Optional, exponential matrix H b In addition to "-1", the zero elements in can also have other representations, such as using "-" or null values ​​to represent an all-zero matrix.

[0100] It can be understood that the above exponential matrix H b The matrix corresponding to the position greater than or equal to 0 is changed to 1, and the position -1 is changed to 0 is the basis matrix. The 1 in the basis matrix is ​​expanded into a cyclic shift matrix based on the elements at the corresponding positions of the exponential matrix, and the 0 is expanded into a 0 matrix of the corresponding scale. After the expansion is completed, the check matrix is ​​obtained.

[0101] 3. Improvement value Z c (Lifting Size) and (Shifting Value)

[0102] The storage contents of the shifting values ​​of the 5G LDPC code include: (1) a lifting size list; and (2) a shifting value list that corresponds one-to-one to the rows of the lifting size list.

[0103] For example, the Lifting Size list is shown in Table 1.

[0104] Table 1

[0105] The jth row of the Lifting Size list contains where a j ∈{2,3,5,7,9,11,13,15}, max(k j)∈{7,7,6,5,5,5,4,4};Lifting Size's row index corresponds to Shifting Value's column index, i.e. each row in Lifting Size list corresponds to a group of Shifting Value.

[0106] For example, the Shifting Value list is shown in Table 2.

[0107] Table 2

[0108] For fixed lifting value index, one non-zero position in the base matrix corresponds to one shifting value. For example, in the base matrix H BG , the shifting value corresponding to the 0th row and 0th column in the base matrix H BG when lifting value index = 0 is 211, in the base matrix H BG , the shifting value corresponding to the 1st row and 6th column in the base matrix H

[0109] It can be understood that when LDPC encoding is performed, the lifting value needs to be determined first, and then the corresponding shifting value is determined based on the selected lifting value to construct the check matrix. For example, the determined lifting value is 40, and 40 corresponds to the lifting value index 2 in Table 1. Then, the check matrix can be constructed based on the shifting values in the column corresponding to the lifting value index = 2 in Table 2.

[0110] 4. Column weight and row weight

[0111] For a column of the matrix, the column weight can refer to the number of non-zero elements contained in the column. For a row of the matrix, the row weight can refer to the number of non-zero elements contained in the row. It can be understood that the matrix involved in the description of the row weight and the column weight is the check matrix H.

[0112] 5. Structure of the base matrix

[0113] FIG. 4 is a schematic diagram of the structure of the check matrix.

[0114] As shown in (a) of FIG. 4, the check matrix can include a high rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high rate region can include the A part and the B part shown in (b) of FIG. 4, where the A part corresponds to information bits (or information positions, system positions, etc.), and the B part is a square matrix and corresponds to core check bits (or core check positions), where the core check can be a check corresponding to the highest rate, or can be a check having a degree greater than or equal to 2, or can be a check node corresponding to a row set having a maximum row weight (a row weight significantly / higher than other rows). The all-zero region can correspond to the C part of (b) of FIG. 4, and is an all-zero matrix. The incremental redundancy region can correspond to the D part of (b) of FIG. 4. The raptor-like region can correspond to the E part of (b) of FIG. 4, and can be a unit matrix, corresponding to check bits for low rate extension.

[0115] The check matrix of the LDPC code shown in FIG. 4 adopts a "raptor-like" structure, and can be gradually extended to a low rate from a core matrix of a high rate. In actual use, as shown in (a) of FIG. 4, the first X rows and the first Y columns of the check matrix can be intercepted, and as the rate gradually decreases from high to low, X and Y gradually increase, and the region of the matrix used also gradually expands.

[0116] It should be noted that the check matrix can be represented by an LDPC base matrix, and thus the structure of the LDPC base matrix is similar to that of the check matrix, and will not be described in detail herein.

[0117] 6, Information columns and check columns

[0118] The columns of the LDPC base matrix are composed of information columns and check columns.

[0119] Information columns: correspond to information bits (or information positions, system positions, etc.), and are the columns corresponding to the A part.

[0120] Check columns: correspond to check bits (or check positions, etc.), and can include core check columns and extension check columns, where the core check columns are the columns corresponding to the B part, and the extension check columns are the columns corresponding to the C part or the E part. The extension check columns can also be referred to as raptor-like columns.

[0121] 7, Information length, code length, and code rate

[0122] The information length is the length (i.e., the number of bits contained) of the to-be-sent information bit sequence, which can be the length of the payload information bits or the length of the payload information bits added with cyclic redundancy check (CRC) bits, and the present application does not make a specific limitation.

[0123] The code length refers to the length of the to-be-sent bit sequence, which can be the to-be-sent bit sequence corresponding to the modulated symbol.

[0124] The code rate refers to the ratio of the length of the to-be-sent information bit sequence to the code length.

[0125] Optionally, the above three values can be pre-configured by high-layer signaling, media access control (MAC) layer or downlink physical layer signal, and can also be directly obtained or calculated by the transceiver. For example, the code length can be determined by the coding and the frame structure, the number of layers and the modulation scheme of the to-be-sent information bit sequence; the code rate can be indicated in the above manner or given in the modulation and coding scheme (MCS).

[0126] 8. Information transmission process

[0127] FIG. 5 is a schematic diagram of an information transmission process suitable for the present application. As shown in FIG. 5, information is sent out by a source, processed by source encoding, channel encoding, modulation, air interface transmission, demodulation, channel decoding, source recovery, etc., and reaches a sink, completing the transmission of information from the source to the sink. Among them, the processing shown in the upper layer of FIG. 5 (including source encoding, channel encoding and modulation, etc.) is executed at the sending end device, and the processing shown in the lower layer (including demodulation, channel decoding, source recovery, etc.) is executed at the receiving end device. Embodiments of the present application mainly relate to source encoding, channel encoding, channel decoding and source recovery shown in FIG. 5.

[0128] Currently, there are two base graphs described in the 5G communication protocol standard: BG1 and BG2. Different boosting values are needed to adapt the rate matching of different code lengths for the same base graph. Therefore, the storage of boosting value and shift value list is needed, and rate matching is performed based on this. Currently, the first two columns of the base matrix of BG1 and BG2 are puncturing columns. In terms of matrix characteristics, the weight of the first two columns is very large; in terms of transmission characteristics, the bits corresponding to the puncturing positions are not transmitted, and the receiving end has no information about this part, so the log-likelihood ratio (LLR) is set to 0, and is recovered through decoding. It can be understood that BG1 (or BG2) described in the following refers to the BG1 (or BG2) of 5G, or the BG1 (or BG2) of NR.

[0129] For the convenience of understanding the embodiments of the present application, the existing rate matching process is briefly described. The following steps are mainly included.

[0130] (1) Based on the given target code length, code rate, and communication scenario, determine the base graph and lifting value Zc to be used.

[0131] For example, the base graph to be used can be determined based on the target code length, code rate, and scenario.

[0132] For example, the lifting value Zc can be determined based on the information column number Kb of the base graph and the lifting value set, and the determined lifting value Zc satisfies the following conditions: the product of the lifting value Zc and the information column number Kb is greater than the length of the payload information bits of this time communication, and the lifting value Zc is the smallest lifting value in the lifting value set that satisfies the above condition.

[0133] (2) Determine the information bit sequence c based on the base graph and the lifting value Zc, wherein the length of the sequence c is K, K = Kb * Zc, wherein Kb is the column number of the information column corresponding to the base graph.

[0134] Specifically, if the base graph is BG1, then K = 22 * Zc; if the base graph is BG2, then K = 10 * Zc.

[0135] It can be understood that each column in the information column of the base graph corresponds to Zc consecutive bits in the sequence c.

[0136] It can also be understood that the length of the sequence c is not equal to the length of the payload information bits.

[0137] (3) Punch the sequence c according to the puncturing column of the base graph to obtain sequence #1.

[0138] As can be seen from the above, the puncturing column of the base graph is fixed as the first 2 columns, and the puncturing bit (or puncturing bit) corresponding to the sequence c is the first 2*Zc bits of the sequence c.

[0139] It can be understood that the to-be-sent bit sequence d is composed of two parts, one part is sequence #1, and the other part is determined by step (4), wherein sequence #1 is the part related to information bits in sequence d, and bit #2 determined in step (4) is the part related to check bits in sequence d.

[0140] The pseudo code for determining sequence #1 from sequence c in the current protocol is as follows:

[0141] Wherein, c k = Null means that this position is a shortened bit (shortened bit), which has a default symbol, such as all 0 by default. It can be understood that the specific meaning of the pseudo code is: if c k is not equal to Null, c kd is assigned a value of c k-2*Zc , if c k is equal to Null, 0 is assigned to c k , and Null is assigned to d k-2*Zc .

[0142] (4) Encoding according to the base graph and the sequence c to obtain sequence #2, which is the part of sequence d related to the check bits.

[0143] The check bits are w = [w0, …, wN+2*Zc-K-1] T , and the encoding process is to solve the equation to obtain w, and w is written in the d sequence in order, where H is the check matrix.

[0144] (5) Based on sequence #1 and sequence #2, the bit sequence d to be sent is obtained.

[0145] It can be understood that the entire base matrix is designed according to the lowest code rate. When different code rates need to be supported, different top-left partial regions of the base matrix shown by the dashed line in (a) of FIG. 4 can be used, as shown in FIG. 4. The AB region (which can be referred to as a core matrix in the present application) constitutes the highest code rate matrix. In the peak throughput scenario of 5G, the BG1 is fully implemented. The number of columns of the A part of the BG1 is 22, the number of columns of the B part is 4, and the number of punctured columns is 2. Therefore, the highest code rate supported by the core matrix of the BG1 is 22 / (22+4-2) = 11 / 12 ≈ 0.917.

[0146] The structure of the LDPC fixed puncturing column of 5G has good limit performance in a communication scenario where complexity is not a bottleneck, but the convergence speed is slow. For example, the highest use code rate specified in the current data channel MCS table is 948 / 1024 ≈ 0.926. The current 5G BG1 has a fixed puncturing column. When the code rate is higher than the code rate of the core matrix 22 / 24, the code rate can be slightly higher by puncturing part of the check column. For example, Table 3 shows the puncturing method of the BG1 when the code rate is higher than 22 / 24. The first 22 columns are information columns (i.e., the columns corresponding to the A part), and the remaining 4 columns are core check columns (i.e., the columns corresponding to the B part). The puncturing columns include the first 2 columns and the core check columns (here, the core check column is exemplified by the last column in Table 3). In this scenario, due to the additional puncturing check column, the number of puncturing bits is too large, the decoding threshold is poor, the convergence speed is slow, and the performance loss is very large.

[0147] Table 3

[0148] It can be seen that the current single base graph and fixed puncturing method cannot meet the needs of all communication systems. Therefore, the present application proposes a communication method that can effectively solve the above technical problems.

[0149] FIG. 6 is a schematic flowchart of a communication method 600 provided by the present application. The method comprises the following steps.

[0150] It can be understood that the method 600 can be executed by a sending-end device and a receiving-end device. Unless otherwise specified, the "sending-end device" or the "receiving-end device" can refer to the sending-end device or the receiving-end device itself, or can refer to an apparatus capable of supporting the sending-end device or the receiving-end device to implement the function. For the convenience of description, the sending-end device and the receiving-end device are used to describe the following. The sending-end device can be a terminal device or a network device, and the receiving-end device can be a terminal device or a network device.

[0151] S601, the sending-end device determines a first base matrix. The first base matrix is one of a plurality of LDPC base matrices, the number of punctured columns P of the first base matrix is different from the number of punctured columns of at least one of the remaining base matrices in the plurality of LDPC base matrices, 0≤P≤2, P=A / B, A is a non-negative integer, and B is related to a first lifting value set.

[0152] The relationship between B and the first lifting value set is illustrated by way of example as follows.

[0153] In a possible implementation, if any lifting value in the plurality of lifting values included in the first lifting value set is equal to a*2 k , then B is equal to 2 k1 , and k1 is a k corresponding to any lifting value in the plurality of lifting values, where the plurality of lifting values are integers greater than or equal to 2. For example, k1 can be 1 or 2.

[0154] For example, the first lifting value set can be the lifting value set shown in Table 1, k1 can be 0 to 7, and the value of B can correspond to 2 i , i is an integer from 0 to 7. Since B is related to the first lifting value set, for example, B can be B=2 2 , then P can be a value in set #1 or a value in a subset of set #1, set #1 being {0, 0.25, 0.5, 0.75, 1, 1.25, 1.5, 1.75, 2}; or B=2 1 , then P can be a value in set #2 or a value in a subset of set #2, set #2 being {0, 0.5, 1, 1.5, 2}; or B=2 0 , then P can be a value in set #3 or a value in a subset of set #3, set #3 being {0, 1, 2}.

[0155] In another possible implementation, any lifting value in the plurality of lifting values included in the first lifting value set is a*3k B equals 3 k2 k2 is a k corresponding to any one of a plurality of lifting values, wherein k = 1 or 2.

[0156] In this scenario, B is related to the first set of lifting values, for example, B can be B = 3 1 P can be a value in set #4 or a subset of set #4, set #4 is {0, 1 / 3, 2 / 3, 1, 4 / 3, 5 / 3, 2} or {0, 2 / 3, 4 / 3, 2}, or B can be B = 3 2 P can be a value in set #5 or a subset of set #5, set #5 is {0, 1 / 9, 2 / 9, 3 / 9, 4 / 9, 5 / 9, 6 / 9, 7 / 9, 8 / 9, 1, 10 / 9, 11 / 9, 12 / 9, 13 / 9, 14 / 9, 15 / 9, 16 / 9, 17 / 9, 2} or {0, 2 / 9, 4 / 9, 6 / 9, 8 / 9, 10 / 9, 12 / 9, 14 / 9, 16 / 9, 2}.

[0157] In yet another possible implementation, the first set of lifting values includes at least one lifting value in each of the above two implementations. In this implementation, if the selected lifting value is the lifting value described in the first implementation, B refers to the description in the first implementation, and if the selected lifting value is the lifting value described in the second implementation, B refers to the description in the second implementation, which will not be repeated here.

[0158] It can be understood that the values of P given in the above three scenarios are examples. In the above description, P (or B) is related to the first set of lifting values, and another definition of P is given below, in which 0 ≤ P ≤ 2, and the value of P can be any value in the range of P, that is, in this definition, P is not limited to be associated with the first set of lifting values.

[0159] For example, P can be a value in the first set or a value in a subset of the first set, where the first set is {0, 0.25, 0.5, 0.75, 1, 1.25, 1.5, 1.75, 2}, or {0, 0.5, 1, 1.5, 2}, or {0, 1, 2}, or {0, 1 / 3, 2 / 3, 1, 4 / 3, 5 / 3, 2}, or {0, 2 / 3, 4 / 3, 2}, or {0, 1 / 9, 2 / 9, 3 / 9, 4 / 9, 5 / 9, 6 / 9, 7 / 9, 8 / 9, 1, 10 / 9, 11 / 9, 12 / 9, 13 / 9, 14 / 9, 15 / 9, 16 / 9, 17 / 9, 2}, or {0, 2 / 9, 4 / 9, 6 / 9, 8 / 9, 10 / 9, 12 / 9, 14 / 9, 16 / 9, 2}.

[0160] Optionally, the plurality of LDPC base matrices includes BG1 and BG2, and the plurality of LDPC base matrices further includes at least one base matrix, which is a base matrix suitable for another communication scenario, and the at least one base matrix corresponds to a puncturing column number not equal to 2. For example, the other communication scenario can be a high-throughput scenario. In this application, the high-throughput scenario can also be referred to as a peak rate scenario.

[0161] It can be understood that the base graph and the base matrix can be replaced with each other in this application, which is not limited in this application.

[0162] For example, the at least one base matrix is two base graphs suitable for a high-throughput scenario, and the two base matrices are BG3 and BG4. Optionally, the puncturing column number of BG3 can be 0.5, and the puncturing column number of BG4 can be 0. That is, the plurality of LDPC base matrices includes BG1, BG2, BG3 and BG4, wherein the puncturing column numbers of BG1 and BG2 are 2, the puncturing column number of BG3 is 0.5, and the puncturing column number of BG4 is 0.

[0163] It can be understood that different base graphs can also generate additional puncturing due to rate matching. If not specially stated, the puncturing column number described in this application refers to the fixed puncturing column number. Taking the puncturing column numbers of the above examples of BG1 to BG4 as an example, the fixed puncturing column numbers of BG1 and BG2 are 2, the fixed puncturing column number of BG3 is 0.5, and the fixed puncturing column number of BG4 is 0.

[0164] It can be understood that if the maximum code rate corresponding to the first base matrix in the plurality of LDPC base matrices is greater than the maximum code rate corresponding to the second base matrix in the plurality of LDPC base matrices, or the maximum modulation order corresponding to the first base matrix is greater than the maximum modulation order corresponding to the second base matrix, or the maximum MCS level corresponding to the first base matrix is greater than the maximum MCS level corresponding to the second base matrix, or the maximum length corresponding to the maximum transmission block (TB) corresponding to the first base matrix is greater than the maximum length corresponding to the maximum TB corresponding to the second base matrix, or the maximum number of code blocks (CBs) corresponding to the first base matrix is greater than the maximum number of CBs corresponding to the second base matrix, or the maximum number of multiple-input multiple-output (MIMO) streams corresponding to the first base matrix is greater than the maximum number of MIMO streams corresponding to the second base matrix, then the fixed puncturing column number corresponding to the first base matrix is less than the fixed puncturing column number corresponding to the second base matrix.

[0165] It can also be understood that if the first base matrix corresponds to LBRM enabled and the second base matrix corresponds to LBRM not enabled, then the fixed puncturing column number corresponding to the first base matrix is less than the fixed puncturing column number corresponding to the second base matrix.

[0166] For example, the plurality of LDPC base matrices includes BG1, BG2, BG3, and BG4, where the puncturing column number of BG1 and BG2 is 2, the puncturing column number of BG3 is 0.5, and the puncturing column number of BG4 is 0. The first base matrix can be BG3, and the second base matrix can be BG1, or the first base matrix can be BG4, and the second base matrix can be BG1, or the first base matrix can be BG3, and the second base matrix can be BG2, or the first base matrix can be BG4, and the second base matrix can be BG2, or the first base matrix can be BG4, and the second base matrix can be BG3.

[0167] For example, in the high-throughput scenario, at least one of the following definitions can be satisfied:

[0168] a) The code rate is greater than or equal to a code rate threshold. For example, the code rate threshold can be any of 22 / 24, 22 / 25, 22 / 26, 948 / 1024, 910 / 1024, or 873 / 1024.

[0169] b) The modulation order is higher than or equal to an order threshold. For example, the order threshold can be any of quadrature amplitude modulation (QAM) 64, QAM 256, or QAM 1024.

[0170] c) MCS rank is higher than or equal to a rank threshold. For example, the rank threshold can be any of 26, 27, 28.

[0171] d) Length of the TB of the whole communication is greater than or equal to a length threshold. For example, the length threshold can be any of 8448, 16896, 25344, 33792, 42240.

[0172] e) Number of CBs is greater than or equal to a number threshold. For example, the number threshold can be any of 2, 3, 4, 5.

[0173] f) Number of MIMO streams is greater than or equal to a stream number threshold. For example, the stream number threshold can be 12, 24, 36, or 108.

[0174] g) When limited buffer rate matching (LBRM) is enabled.

[0175] S602, the sending device obtains a first information bit sequence corresponding to a first base matrix, the length of the first information bit sequence is K, K is equal to the product of kb and Zc, where kb is the column number of the information column contained in the first base matrix, and Zc is a lifting value contained in a first lifting value set.

[0176] S603, the sending device processes the first information bit sequence based on a puncturing bit number L of the first base matrix to obtain a to-be-sent bit sequence, the puncturing bit number L is determined based on a puncturing column number P of the first base matrix and Zc.

[0177] Optionally, the relationship between the puncturing bit number L of the first base matrix and P and Zc is relationship (1) or relationship (2):

[0178] (1) Linear relationship: L = P * Zc + P0, where P0 is the number of fixed puncturing bits, and P0 is a non-negative integer.

[0179] (2) Approximate linear relationship: Or, Wherein, P0 is defined as in (1), Denotes rounding down, Denotes rounding up.

[0180] It can be understood that since the puncturing bit number L is a non-negative integer, when P * Zc is an integer, the relationship corresponding to L can use relationship (1), and if P * Zc is a non-integer, the relationship corresponding to L can use relationship (2).

[0181] The following illustrates the relationship between the puncturing bit number L and P and Zc, with the first lifting value set being the lifting value set shown in Table 1.

[0182] Example one, when P is any value in the set {0, 0.5, 1, 1.5, 2}, if Zc is not the minimum value in the set of lifting values corresponding to the lifting value index j in Table 1, the relationship between L, P and Zc is relationship (1). Specifically, the minimum value Zc in the set of lifting values corresponding to the lifting value index j is Zc = 3, 5, 7, 9, 11, 13, 15 or Zc = 2, 3, 5, 7, 9, 11, 13, 15.

[0183] Example two, when P is any value in the set {0, 0.25, 0.5, 0.75, 1, 1.25, 1.5, 1.75, 2}, if Zc is not the minimum and second minimum values in the set of lifting values corresponding to the lifting value index j in Table 1, the relationship between L, P and Zc is relationship (1). Specifically, the minimum and second minimum values Zc in the set of lifting values corresponding to the lifting value index j are Zc = 2, 3, 6, 5, 10, 7, 14, 9, 18, 11, 22, 13, 26, 15, 30 or Zc = 2, 4, 3, 6, 5, 10, 7, 14, 9, 18, 11, 22, 13, 26, 15, 30.

[0184] Example three, no matter the value of Zc in Table 1, the relationship between L, P and Zc is relationship (2).

[0185] The following takes BG1, BG2, BG3 and BG4 in multiple LDPC base matrices as examples to illustrate the relationship between the base graph and the number of puncturing bits.

[0186] If the first base matrix is BG1 or BG2, L = 2*Zc.

[0187] If the first base matrix is BG3, L = 0.5*Zc, when 0.5*Zc is not an integer, or, +P0.

[0188] If the first base matrix is BG4, L = 0.

[0189] It can be understood that each column in the kb information columns of the first base matrix corresponds to Zc consecutive bits in the first information bit sequence, therefore, for relationship (1), the puncturing positions corresponding to the number of puncturing bits L include P*Zc bits in the first information bit sequence corresponding to the number of puncturing columns P. The following specifically describes the puncturing positions corresponding to the number of puncturing bits L when P is an integer or P is not an integer.

[0190] When P is an integer, specifically, P=0 means no puncturing, P=1 means that a puncturing column #1 is determined first, and the puncturing positions corresponding to the puncturing bit number L include Zc bits in the first information bit sequence corresponding to the puncturing column #1, P=2 means that two puncturing columns #1 and #2 are determined first, and the puncturing positions corresponding to the puncturing bit number L include Zc bits in the first information bit sequence corresponding to the puncturing column #1 and Zc bits in the first information bit sequence corresponding to the puncturing column #2.

[0191] When P is not an integer, specifically, 0

[0192] It can also be understood that if P0 is equal to 0, the puncturing positions corresponding to the puncturing bit number L are P*Zc bits in the first information bit sequence corresponding to the P puncturing columns; if P0 is not equal to 0, the puncturing positions corresponding to the puncturing bit number L include P*Zc bits and P0 bits in the first information bit sequence remaining bits except P*Zc bits. The position of the P0 bits is not limited in the present application, for example, the P0 bits can be P0 consecutive bits after the last puncturing bit in the P*Zc bits.

[0193] Similarly, for the relationship (2), the puncturing positions corresponding to the puncturing bit number L include (or ) bits in the first information bit sequence corresponding to the puncturing column number P. The description of the puncturing positions corresponding to the puncturing bit number L when P is an integer or P is not an integer only needs to replace P*Zc in the description corresponding to the relationship (1) with (or ), which will not be described here.

[0194] For ease of description, the following description takes L=P*Zc as an example.

[0195] In a possible implementation, the P puncturing columns of the first base matrix are selected from the first column (the first column) in turn.

[0196] In example one, 0

[0197] In example two, 1

[0198] Based on the above examples, the pseudo code for obtaining the part of the to-be-sent bit sequence (referred to as sequence d in the present application) related to the information bits from the first information bit sequence (referred to as sequence c in the present application) is as follows:

[0199] The specific meaning of the pseudo code is as follows: if c k is not equal to Null, the value of c k is assigned to d k-L , if c k is equal to Null, 0 is assigned to c k , and Null is assigned to d k-L .

[0200] In another possible implementation, the P puncturing columns of the first base matrix are selected in relation to the first matrix.

[0201] Optionally, the first matrix is the first base matrix; or, the first matrix is a matrix corresponding to the lowest code rate supported by the first base matrix in the current communication scenario; or, the first matrix is a core matrix (i.e., the AB region) corresponding to the first base matrix; or, the first matrix is a matrix corresponding to the highest code rate supported by the first base matrix, and the highest code rate is the highest code rate indicated by the MCS.

[0202] Optionally, the selection of the P puncturing columns of the first base matrix is related to the column weight of the first matrix and / or the positions with a value of 1 in the first matrix. The following examples are provided for illustration.

[0203] In example one, 0

[0204] Here, the column number of the first matrix and the bit number of the first information bit sequence are numbered from 0, and if the starting bit of the continuous P*Zc bits is the first bit in the Zc bits corresponding to the puncturing column #1 (i.e., the puncturing position corresponding to the puncturing bit number L includes the first P*Zc bits in the Zc bits corresponding to the puncturing column #1 of the first matrix), and the puncturing column #1 is the k1th column of the first matrix, then the starting position of the puncturing position corresponding to the puncturing bit number L is the K1th bit of the first information bit sequence, K1=k1*Zc. The pseudo code for obtaining the part related to the information bits in the to-be-sent bit sequence (which can be referred to as sequence d in the present application) from the first information bit sequence (which can be referred to as sequence c in the present application) is as follows:

[0205] It can be understood that if the numbering starts from 1, the k1th column of the first matrix needs to be replaced by the k1+1th column, and the K1th bit of the first information bit sequence needs to be replaced by the K1+1th bit. The same description is not repeated hereinafter.

[0206] Example two, 1

[0207] Example three, 1

[0208] In the above example two and example three, the puncturing position corresponding to the puncturing bit number L includes the continuous (P-1)*Zc bits in the Zc bits corresponding to the puncturing column #1 and the Zc bits corresponding to the puncturing column #2 of the first matrix. For example, the starting bit of the continuous (P-1)*Zc bits is the first bit in the Zc bits corresponding to the puncturing column #2, or the ending bit of the continuous P*Zc bits is the last bit in the Zc bits corresponding to the puncturing column #2, which is not limited in the present application.

[0209] Based on the second and third examples, here the column serial number of the first matrix and the bit serial number of the first information bit sequence are numbered from 0, if the starting bit of the continuous (P-1)*Z bits corresponding to the punctured column #2 is the first bit in the Zc bits corresponding to the punctured column #2 (i.e. the punctured position corresponding to the punctured bit number L includes the first (P-1)*Zc bits in the Zc bits corresponding to the punctured column #2 of the first matrix), assuming that the punctured column #1 is the x-th column of the first matrix and the punctured column #2 is the y-th column of the first matrix.

[0210] Then when x < y, the pseudo code for obtaining the part related to the information bits in the to-be-sent bit sequence (which can be referred to as sequence d in the present application) from the first information bit sequence (which can be referred to as sequence c in the present application) is as follows:

[0211] Specifically, when x = y-1, the pseudo code for obtaining the part related to the information bits in the to-be-sent bit sequence (which can be referred to as sequence d in the present application) from the first information bit sequence (which can be referred to as sequence c in the present application) is as follows:

[0212] Similarly, when x > y, the pseudo code for obtaining the part related to the information bits in the to-be-sent bit sequence (which can be referred to as sequence d in the present application) from the first information bit sequence (which can be referred to as sequence c in the present application) is as follows:

[0213] It can be seen that the punctured columns in the above description are all information columns of the first matrix, and the puncturing manner has the advantage that since the check bits corresponding to the check columns need to support the coding structure, they are not suitable for puncturing, and thus the information columns of the first matrix can be punctured.

[0214] Optionally, in some possible scenarios, the "information column of the first matrix" in the first, second and third examples in the implementation manner can be replaced by "check column of the first matrix" or "all columns of the first matrix". When replaced by all check columns of the first matrix, the puncturing manner has the advantage that the information bits can be guaranteed to be correct as much as possible, i.e. even in the case of overall decoding error, the information bits can be correct. When replaced by all columns of the first matrix, the puncturing manner has the advantage that the punctured bits are missing a priori, and rely on the decoding a posteriori information to obtain a good decoding threshold, and thus the column weight is the largest, and the overall decoding threshold is better.

[0215] Optionally, the first base matrix can be a base graph with nested information columns.

[0216] In one possible implementation, the base graph of the nested information column can store the connection relationship and the translation value of the maximum size base graph through a large table, and the number of information columns corresponding to the base graph of the nested information column is defined as the maximum number of information columns. For example, as shown in Table 4, the row number is used as an index to store all associated column numbers and the translation value corresponding to each group of positions. For the specific meaning of Table 4, refer to the description of Table 1, which will not be repeated here.

[0217] Table 4

[0218] When the actual number of information columns K' to be used is less than the maximum number of information columns, the connection relationship and the translation value of the matrix region corresponding to the first K' information columns and all the check columns of the base graph of the nested information column are intercepted to form a sub-matrix as the LDPC code matrix with the support information column number K'. The sub-matrix can be used for encoding and decoding.

[0219] Optionally, the interception sequence can be in order or in reverse order or the interception sequence can be specified as K' columns, or the interception sequence can be in other sequences specified by standards.

[0220] For example, the maximum number of information columns of the base graph of the nested information column is N, N>22, wherein the information of the column number 0 to 21 of any row number of the base graph of the nested information column includes the connection relationship and the translation value of the base graph of the information column part of BG1, the information of the column number of any row number of the base graph of the nested information column except 0 to 21 is the connection relationship and the translation value of the base graph of the additional information column part, and the information of the column number of any row number of the base graph of the nested information column except 0 to N-1 is the connection relationship and the translation value of the base graph of the check column part of BG1. For ease of description, the base graph of the nested information column of this type can be referred to as the base graph of the nested BG1 in this application.

[0221] For example, the base graph of the nested BG1 can be BG3 described above.

[0222] For example, the base graph of the nested BG1 supports the same lifting value set as BG1.

[0223] FIG. 7 is a matrix diagram of the base graph of the nested BG1 written as a matrix. As shown in FIG. 7, N=33, wherein the first 22 columns in the matrix shown in FIG. 7 are the information columns corresponding to BG1, the middle 11 columns can be additional information columns, and the remaining columns in the 33 columns are the check part corresponding to BG1.

[0224] Optionally, the information of the rows with column numbers 0 to 21 corresponding to any row number of the base graph of the nested BG1 is intercepted, that is, the edge relationship and the translation value of the base graph of the information column part of BG1 are obtained, and the information of the rows with column numbers other than 0 to N-1 corresponding to any row number of the base graph of the nested BG1 is intercepted, that is, the edge relationship and the translation value of the base graph of the check column part of BG1 are obtained. Specifically, taking FIG. 7 as an example, the base matrix corresponding to the intercepted base graph includes the BG1 information column part and the BG1 check part in FIG. 7. The advantage of this scheme is that it can be compatible with the coding scheme of 5G, and the standard change is small.

[0225] Optionally, the base graph of the nested BG1 is intercepted to obtain the intercepted base graph, and the row with column number 4 corresponding to any row number in the intercepted base graph does not have any edge, that is, the edge does not exist in the 5th row of the additional information column. The advantage of this scheme is that the code rate corresponding to the first 5 matrix regions of the intercepted base graph can match the degree distribution of 5G, and a good decoding threshold is obtained.

[0226] Similarly, the base matrix of the nested information column can also be the base graph of the nested BG2, and the specific description is not repeated here.

[0227] The punctured column of the base graph of the nested information column is described below.

[0228] Example 1: The punctured column of the base graph of the nested information column is set in the information column that must be included in the intercepted matrix under any use condition. For example, if the range of the information column used by the base graph of the nested BG1 under any use condition is columns 22 to 26, the punctured position is set in the information column of the base graph of the nested BG1 (that is, the first 22 columns of the base matrix corresponding to the base graph of the nested BG1). This scheme can ensure that the punctured column will not be changed under different conditions of the intercepted information column, and the advantage of this implementation mode is that the rate matching module is very simple, and the punctured column can guarantee the decoding threshold under the condition of flexible rate.

[0229] Example 2: When the base graph of the nested information column is the base graph of the nested BG1 or the base graph of the nested BG2, the punctured column is truly included in the punctured column of BG1. For example, when 0<P<1, the punctured column is selected to correspond to the first column of BG1; when 1<P<2, the punctured column is selected to correspond to the first and second columns of BG1.

[0230] As can be seen, the punctured column in the above example 1 and example 2 is the information column of the base graph of the nested information column. Optionally, in some possible scenarios, the punctured column of the base graph of the nested information column can also be the check column.

[0231] Example three, the puncturing column of the base graph of the nested information column is set in the check column that is certainly contained in the intercepted matrix under any use condition, the scheme does not need to consider the influence of the information column change on the puncturing bit at all, and the puncturing column can uniformly guarantee the decoding threshold in the case of flexible rate.

[0232] Example four, the puncturing column of the base graph of the nested information column is set in the core check column of the base graph of the nested information column, the scheme does not need to consider the influence of the information column change on the puncturing bit at all, and is the simplest to implement.

[0233] It can be understood that, based on the above description, the first information bit sequence is obtained by processing the first information bit sequence based on the number L of puncturing bits of the first base matrix and the position of the puncturing column, that is, the punctured sequence includes the part of the to-be-sent bit sequence related to the information bit, in addition, the part of the to-be-sent bit sequence related to the check bit also needs to be obtained, and then the to-be-sent bit sequence is finally obtained based on the part of the to-be-sent bit sequence related to the information bit and the part of the to-be-sent bit sequence related to the check bit.

[0234] S604, the receiving end device obtains a receiving sequence.

[0235] Optionally, the receiving end device obtains the receiving sequence, including: the sending end device sends the to-be-sent bit sequence to the receiving end device. Correspondingly, the receiving end device receives the receiving sequence from the sending end device.

[0236] It can be understood that, since the to-be-sent bit sequence will introduce channel noise signals in the transmission process, the to-be-sent bit sequence output or sent by the sending end device is different from the receiving sequence obtained by the receiving end device. In this step, the receiving sequence obtained by the receiving end device can be regarded as the sequence after the to-be-sent bit sequence is added with channel noise.

[0237] S605, the receiving end device obtains a to-be-decoded bit sequence based on the number L of puncturing bits of the first base matrix and the receiving sequence.

[0238] Since the bits corresponding to the puncturing bits are not sent, the receiving end device has no receiving information about this part, and therefore the LLR of this part can be set to 0, that is, 0 is supplemented in the receiving sequence corresponding to the L puncturing positions, so as to obtain the to-be-decoded bit sequence.

[0239] It can be understood that the base matrix used by the receiving end device for decoding is the same as the base matrix used by the sending end device for encoding, and the specific way in which the sending end device and the receiving end device determine the first base matrix is not limited in the present application.

[0240] S606, the receiving end device decodes the to-be-decoded bit sequence to obtain the first information bit sequence.

[0241] It can be understood that the decoding herein can be regarded as a de-noising operation.

[0242] In the technical solution, different punctured column number LDPC codes are introduced based on different communication scenarios and decoding requirements. The scheme has the advantages of fast convergence speed and good decoding threshold in a high throughput scenario.

[0243] FIG. 8 is a performance simulation diagram based on the puncturing scheme proposed in the present application. In FIG. 8, the horizontal axis is the number of iteration rounds, and the vertical axis is the signal to noise ratio (SNR) when the block error rate (BLER) is 10 -2 It can be seen that the performance of different matrices at different iteration numbers does not show a monotonous trend. The fewer the puncturing numbers, the faster the convergence speed, but the worse the ultimate performance (the performance at a high number of iteration rounds, the larger the vertical axis value, the worse the performance). The more the puncturing numbers, the slower the convergence speed, but the better the ultimate performance. Therefore, there is a trade-off between the convergence speed and the ultimate performance for different puncturing column numbers. A single puncturing mode cannot meet the needs of all communication systems. The scheme proposed in the present application can select LDPC codes with different puncturing column numbers according to the scene requirements.

[0244] It can be understood that the steps in the above figures are only exemplary and are not strictly limited. In addition, the size of the serial number of the above processes does not mean the order of execution. The execution order of the processes should be determined according to their functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0245] It can also be understood that some optional features in the embodiments of the present application can not depend on other features in some scenarios, or can be combined with other features in some scenarios, without limitation.

[0246] It can also be understood that the methods and operations implemented by the device (the sending end device or the receiving end device) in the above method embodiments can also be implemented by the components (such as chips or circuits) of the device, without limitation.

[0247] The method embodiments provided by the present application are described in detail above in combination with FIG. 1 to FIG. 8. The apparatus embodiments of the present application will be described below in combination with FIG. 9 and FIG. 10. It can be understood that, in order to implement the functions in the above embodiments, the apparatuses in FIG. 9 and FIG. 10 include the corresponding hardware structure and / or software module for performing each function. Those skilled in the art should easily realize that, in combination with the units and method steps of each example described in the embodiments disclosed in the present application, the present application can be implemented in the form of hardware or a combination of hardware and computer software. It can be understood that the technical features described in the above method embodiments are also applicable to the following apparatus embodiments.

[0248] FIG. 9 and FIG. 10 are structural schematic diagrams of possible apparatuses provided by the embodiments of the present application. The apparatuses can be used to implement the functions of the sending end device or the receiving end device in the above method embodiments, and thus can also achieve the beneficial effects possessed by the above method embodiments.

[0249] FIG. 9 is a schematic block diagram of a communication apparatus 1000 provided by the embodiments of the present application. As shown in FIG. 9, the apparatus 1000 can include a communication unit 1010 and a processing unit 1020. The communication unit 1010 can communicate with the outside, and the processing unit 1020 is configured to perform data processing. The communication unit 1010 can also be referred to as a communication interface or a transceiver unit.

[0250] In a possible design, the apparatus 1000 can implement the steps or processes performed by the sending end device in the above method embodiments, where the processing unit 1020 is configured to perform the processing-related operations of the sending end device in the above method embodiments, and the communication unit 1010 is configured to perform the sending-related operations of the sending end device in the above method embodiments.

[0251] In another possible design, the apparatus 1000 can implement the steps or processes performed by the receiving end device in the above method embodiments, where the communication unit 1010 is configured to perform the receiving-related operations of the receiving end device in the above method embodiments, and the processing unit 1020 is configured to perform the processing-related operations of the receiving end device in the above method embodiments.

[0252] It should be appreciated that the apparatus 1000 herein is embodied in the form of functional units. The term "unit" herein can refer to an application specific integrated circuit (ASIC), an electronic circuit, a processor (for example, a shared processor, a dedicated processor, or a group processor, etc.) and a memory for executing one or more software or firmware programs, a combination of logic circuitry and / or other suitable components that support the described functions. In an optional example, those skilled in the art can understand that the apparatus 1000 can be embodied in the form of the sending device in the above-described embodiments, and can be used to execute the respective processes and / or steps corresponding to the sending device in the above-described method embodiments, or the apparatus 1000 can be embodied in the form of the receiving device in the above-described embodiments, and can be used to execute the respective processes and / or steps corresponding to the receiving device in the above-described method embodiments. To avoid repetition, details are not described herein.

[0253] The apparatus 1000 of each of the above-described schemes has a function of implementing the respective steps performed by the sending device in the above-described methods, or the apparatus 1000 of each of the above-described schemes has a function of implementing the respective steps performed by the receiving device in the above-described methods. The function can be implemented by hardware, or can be implemented by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described functions; for example, the communication unit can be replaced by a transceiver (for example, the sending unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as the processing unit, can be replaced by a processor, which respectively performs the transceiving operations and related processing operations in each of the method embodiments.

[0254] In addition, the communication unit can also be a transceiving circuit (for example, can include a receiving circuit and a sending circuit), and the processing unit can be a processing circuit. In the embodiments of the present application, the apparatus in FIG. 9 can be the receiving device or the sending device in the above-described embodiments, or can be a chip or a chip system, for example, a system on chip (SoC). The communication unit can be an input / output circuit, a communication interface; and the processing unit can be a processor or a microprocessor integrated on the chip or an integrated circuit. Details are not limited herein.

[0255] FIG. 10 is a schematic block diagram of a communication apparatus 1100 provided by the embodiments of the present application. The apparatus 1100 includes a processor 1110 and a transceiver 1120. The processor 1110 and the transceiver 1120 communicate with each other through an internal connection path. The processor 1110 is configured to execute instructions to control the transceiver 1120 to send and / or receive signals.

[0256] Optionally, the apparatus 1100 further includes a memory 1130, which is in communication with the processor 1110 and the transceiver 1120 via the internal connection path. The memory 1130 is used to store instructions, which the processor 1110 can execute. In one possible implementation, the apparatus 1100 is configured to implement the procedures and steps corresponding to the transmitting end device in the above-described method embodiments. In another possible implementation, the apparatus 1100 is configured to implement the procedures and steps corresponding to the receiving end device in the above-described method embodiments.

[0257] Optionally, the memory 1130 can be integrated in the processor 1110.

[0258] In one possible scenario, the apparatus 1100 includes at least one processor integrated with a memory, and other memory in addition to the memory integrated in the processor.

[0259] It can be understood that the apparatus 1100 can be specifically the transmitting end device or the receiving end device in the above-described embodiments, or a chip or chip system. Correspondingly, the transceiver 1120 can be a transceiver circuit of the chip, which is not limited here. Specifically, the apparatus 1100 can be configured to execute the procedures and steps corresponding to the transmitting end device or the receiving end device in the above-described method embodiments.

[0260] Optionally, the memory 1130 can include a read-only memory and a random access memory, and provide instructions and data for the processor. The memory can include a non-volatile random access memory. For example, the memory can also store device type information. The processor 1110 can be configured to execute the instructions stored in the memory, and when the processor 1110 executes the instructions stored in the memory, the processor 1110 is configured to execute the procedures and steps of the above-described method embodiments corresponding to the transmitting end device or the receiving end device.

[0261] In the implementation process, the procedures of the above-described method can be completed by the integrated logic circuit of the hardware in the processor or the instructions in the form of software. The procedures of the method disclosed in the embodiments of the present application can be directly embodied as being completed by a hardware processor, or completed by a combination of hardware and software modules in the processor. The software modules can be located in the random access memory, the flash memory, the read-only memory, the programmable read-only memory, the electrically erasable programmable memory, the register, or other mature storage media in the field. The storage medium is located in the memory, and the processor reads the information in the memory and combines the hardware to complete the procedures of the above-described method. To avoid repetition, it will not be described in detail here.

[0262] It should be noted that the processor in the embodiments of the present application can be an integrated circuit chip with a signal processing capability. In the implementation process, the steps of the above method embodiments can be completed by the integrated logic circuit or the instruction in the form of software in the processor. The processor mentioned above can be a general processor, a digital signal processing (DSP), an ASIC, a field-programmable gate array (FPGA) or other programmable logic devices, a discrete gate or transistor logic device, a discrete hardware component. The processor in the embodiments of the present application can realize or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general processor can be a microprocessor or the processor can also be any conventional processor and the like. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or be executed by a combination of hardware and software modules in the code processor. The software module can be located in a random memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register or other mature storage medium in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and combines the hardware to complete the steps of the above method.

[0263] It is to be appreciated that the memory in the embodiments of the application can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Where the nonvolatile memory is a read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), or flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example, and not limitation, many forms of RAM are available, for example, static RAM (SRAM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), double-data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM). Note that the system and method described herein are intended to include all such memory types and any other suitable type of memory.

[0264] Optionally, the memory (e.g., 1130) in the embodiments of the application can be integrated in the processor (e.g., 1110).

[0265] In addition, the application also provides a computer readable storage medium, the computer readable storage medium stores computer instructions, when the computer instructions run on the computer, the operations and / or processes performed by the sending end device or the receiving end device in the method embodiments of the application are executed.

[0266] The application also provides a computer program product, the computer program product includes computer program codes or instructions, when the computer program codes or instructions run on the computer, the operations and / or processes performed by the sending end device or the receiving end device in the method embodiments of the application are executed.

[0267] Further, the application provides a chip including a processor. A memory for storing a computer program is arranged independently of the chip, and the processor is configured to execute the computer program stored in the memory, so that the operations and / or processes performed by the sending device or the receiving device in any one of the method embodiments are performed.

[0268] Further, the chip can further include a communication interface. The communication interface can be an input / output interface, an interface circuit, or the like. Further, the chip can further include a memory.

[0269] Further, the application provides a communication system including the sending device and the receiving device in the embodiments of the application.

[0270] It should be further noted that the memory described herein is intended to include, but not limited to, these and any other suitable type of memory.

[0271] Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solutions. Those skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the application. Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here. In several embodiments provided in the application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other form. The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., they can be located in one place, or distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiments. In addition, the functional units in each embodiment of the application can be integrated in one processing unit, or each unit can be physically present, or two or more units can be integrated in one unit.

[0272] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that contribute to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a ROM, a RAM, a magnetic disk or an optical disk, and various program code storage media.

[0273] It can be understood that the "embodiments" mentioned throughout the specification mean that the specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present application. Therefore, the various embodiments throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner.

[0274] It can also be understood that in the present application, "when", "if" and "if" all refer to the corresponding processing of the network element under certain objective conditions, not the time limit, and it is not required that the network element implementation must have a judgment action, nor does it mean that there are other limitations.

[0275] It can also be understood that in the various embodiments of the present application, "A corresponding B" means that B is associated with A, and B can be determined according to A. However, it can also be understood that determining B according to A does not mean that B is determined only according to A, but B can also be determined according to A and / or other information.

Claims

1. A communication method characterized by comprising: The method comprises: determining a first base matrix, wherein the first base matrix is one base matrix in a plurality of low-density parity-check (LDPC) base matrices, a puncturing column number P of the first base matrix is different from a puncturing column number of at least one base matrix remaining in the plurality of LDPC base matrices, 0≤P≤2, the P=A / B, A is a non-negative integer, and B is related to a first set of lifting values; obtaining a first information bit sequence corresponding to the first base matrix, the length of the first information bit sequence being K, wherein K is equal to the product of kb and Zc, kb is the column number of information columns contained in the first base matrix, and Zc is one lifting value contained in the first set of lifting values; processing the first information bit sequence based on a puncturing bit number L of the first base matrix to obtain a to-be-sent bit sequence, wherein the puncturing bit number L is determined based on the puncturing column number P of the first base matrix and the Zc.

2. A communication method, comprising: obtaining a received sequence; obtaining a to-be-decoded sequence based on a puncturing bit number L of a first base matrix and the received sequence, wherein the first base matrix is one base matrix in a plurality of low-density parity-check (LDPC) base matrices, a puncturing column number P of the first base matrix is different from a puncturing column number of at least one base matrix remaining in the plurality of LDPC base matrices, 0≤P≤2, the P=A / B, A is a non-negative integer, and B is related to a first set of lifting values; decoding the to-be-decoded sequence based on the first base matrix to obtain a first information bit sequence, the length of the first information bit sequence being K, wherein K is equal to the product of kb and Zc, kb is the column number of information columns contained in the first base matrix, and Zc is contained in the first set of lifting values.

3. The method according to claim 1 or 2, characterized in that, L = P * Zc+ P0, or, or, wherein the P0 is the number of fixed punctured bits, P0 is a non-negative integer.

4. The method according to any one of claims 1 to 3, wherein: Any of the multiple lifting values included in the first set of lifting values is equal to a*2 k , the B is equal to 2 k1 , the k1 is the k corresponding to any of the multiple lifting values, the multiple lifting values are integers greater than or equal to 2; or, Any one of the multiple lifting values included in the first set of lifting values is a*3 k , the B is equal to 3 k2 , the k2 is the k corresponding to any one of the multiple lifting values, the multiple lifting values are integers greater than or equal to 3.

5. The method of claim 4, wherein, the k1 is 1 or 2, and the k2 is 1 or 2.

6. The method according to any one of claims 1 to 5, characterized in that, The P is a value in a first set, the first set being {0, 0.25, 0.5, 0.75, 1, 1.25, 1.5, 1.75}, or {0, 0.5, 1, 1.5}, or {0, 1 / 3, 2 / 3, 1, 4 / 3, 5 / 3}, or {0, 2 / 3, 4 / 3}.

7. The method according to any one of claims 1 to 6, characterized in that, The plurality of LDPC matrices further comprises a second base matrix, a puncturing column number of the second base matrix being Q, a maximum code rate corresponding to the first base matrix is greater than a maximum code rate corresponding to the second base matrix, or, a maximum modulation order corresponding to the first base matrix is greater than a maximum modulation order corresponding to the second base matrix, or, a maximum coding and modulation scheme (MCS) level corresponding to the first base matrix is greater than a maximum MCS level corresponding to the second base matrix, or, a maximum transport block (TB) length corresponding to the first base matrix is greater than a maximum TB length corresponding to the second base matrix, or, a maximum number of coding blocks (CBs) corresponding to the first base matrix is greater than a maximum number of CBs corresponding to the second base matrix, or, The maximum number of multiple-input multiple-output (MIMO) streams corresponding to the first base matrix is greater than the maximum number of MIMO streams corresponding to the second base matrix, Or, The first base matrix corresponds to limited buffer rate matching (LBRM) enabled, and the second base matrix corresponds to LBRM disabled, Then P is less than Q.

8. The method of claim 7, wherein, The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 10. The method of claim 9, wherein, The P=0, and the Q=0.

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11. The method according to any one of claims 1 to 8, characterized in that, 9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 13. The method of claim 12, wherein, Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, 0 Or, 1 The P=0, and the Q=0.

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9. The method of any one of claims 1 to 8, wherein, The second puncturing column is a column in a third column set having the least common check node with the first puncturing column, the third column set including a column having the largest column weight in the first column set.

16. The method according to claim 14 or 15, characterized in that, The first puncturing column is an xth column of the first base matrix, the second puncturing column is a yth column of the first base matrix, the number of puncturing bits L includes Zc bits in the first information bit sequence corresponding to the first puncturing column and (P-1)*Zc bits corresponding to the second puncturing column, x < y, the to-be-transmitted bit sequence includes 0th bit to xZc-1th bit, xZc+Zcth bit to yZc-1th bit, yZc+(P-1)*Zcth bit to K-1th bit in the first information bit sequence, x > y, the to-be-transmitted bit sequence includes 0th bit to yZc-1th bit, yZc+(P-1)*Zcth bit to xZc-1th bit, xZc+Zcth bit to K-1th bit in the first information bit sequence.

17. A communications device, characterized by The communication device comprises a processor and an interface circuit, the interface circuit is used for receiving signals from other communication devices outside the communication device and transmitting the signals to the processor or sending signals from the processor to other communication devices outside the communication device, and the processor is used for implementing the method according to any one of claims 1 to 16 through a logic circuit or executing code instructions.

18. The communication apparatus according to claim 17, wherein The communication device is a chip or a chip system.

19. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions, and when the computer program or instructions are executed by the communication device, the method according to any one of claims 1 to 16 is implemented.

20. A computer program product, characterised in that, The computer program is used for implementing the method according to any one of claims 1 to 16 when the computer program is executed.

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