Storage apparatus, electronic device, and storage apparatus control method

Abstract

Provided in the embodiments of the present disclosure are a storage apparatus, an electronic device, and a storage apparatus control method. The storage apparatus comprises: an NVSRAM array, an SRAM operation circuit, a non-volatile storage operation circuit, an error detection and correction circuit, an input / output interface circuit and a column selection circuit, wherein the error detection and correction circuit is coupled to both the input / output interface circuit and the SRAM operation circuit, the SRAM operation circuit is coupled to the column selection circuit, the column selection circuit is coupled to the NVSRAM array, and the non-volatile storage operation circuit is coupled to the NVSRAM array; the error detection and correction circuit is configured to encode and decode data transmitted between the input / output interface circuit and the SRAM operation circuit, so as to determine whether an error is present in the data and perform error correction; and the column selection circuit is configured to isolate an operation of the SRAM operation circuit from an operation of the nonvolatile storage operation circuit, and isolate a data read / write operation from a data recovery operation. The storage apparatus can improve the reliability of data read / write, backup and recovery.

Description

Storage device, electronic device, and storage device control method

[0001] This application claims priority to Chinese Patent Application Nos. 202410475769.2, 202410476041.1, and 202410475909.6, filed on April 19, 2024, the contents of which are hereby incorporated by reference in their entirety as part of the present application. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to a storage device, an electronic device, and a storage device control method. BACKGROUND

[0003] With the rapid development of science and technology and economy, the application range of storage devices is becoming wider and wider. Basic storage devices can be divided into volatile memory and non-volatile memory according to the characteristics of storage media. Volatile memory refers to a storage device whose stored data will be lost after power off, and correspondingly, non-volatile memory refers to a storage device whose stored data will not be lost after power off. Generally, volatile memory has high operation speed, while non-volatile memory has long storage time.

[0004] SRAM (Static Random Access Memory) is a volatile memory, and the data stored therein will be lost when the power is off. Therefore, it is necessary to always provide power to maintain the programming state of the SRAM memory. This method consumes a lot of energy, which is not conducive to the low-power design of the storage device. SUMMARY

[0005] The at least one embodiment of the present disclosure provides a storage device, comprising: an NVSRAM array, an SRAM operation circuit, a non-volatile storage operation circuit, an error detection and correction circuit, an input / output interface circuit, and a column selection circuit. The error detection and correction circuit is coupled to the input / output interface circuit, the error detection and correction circuit is coupled to the SRAM operation circuit, the SRAM operation circuit is coupled to the column selection circuit, the column selection circuit is coupled to the NVSRAM array, and the non-volatile storage operation circuit is coupled to the NVSRAM array. The NVSRAM array comprises a plurality of NVSRAM units arranged in an array, and each NVSRAM unit comprises an SRAM storage subunit and a non-volatile storage subunit. The non-volatile storage subunit is configured to back up data stored in the SRAM storage subunit. The non-volatile storage operation circuit is configured to perform a data backup operation on the SRAM storage subunit data in the selected NVSRAM unit in the NVSRAM array. The column selection circuit is configured to select a target unit column in the NVSRAM array that needs to be operated, and perform a data recovery operation on the non-volatile storage subunit data in the target unit column. The SRAM operation circuit is configured to perform a data read / write operation on the SRAM storage subunit data in the target unit column. The input / output interface circuit is configured to provide received input data to the error detection and correction circuit and receive output data to be output from the error detection and correction circuit. The error detection and correction circuit is configured to encode and decode data transmitted between the input / output interface circuit and the SRAM operation circuit, determine whether the data has an error, and correct the error. The column selection circuit is further configured to isolate the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit, and isolate the data read / write operation and the data recovery operation.

[0006] The at least one embodiment of the present disclosure provides a control method of a storage device, applied to the storage device provided by any one of the embodiments of the present disclosure. The method comprises: controlling the error detection and correction circuit to encode and decode data transmitted between the input / output interface circuit and the SRAM operation circuit, determine whether the data has an error, and correct the error.

[0007] The at least one embodiment of the present disclosure provides a storage device, comprising: an NVSRAM array, an SRAM operation circuit, a non-volatile storage operation circuit, an error detection and correction circuit, an input / output interface circuit, and a column selection circuit. The error detection and correction circuit is coupled to the SRAM operation circuit, the SRAM operation circuit is coupled to the input / output interface circuit, the SRAM operation circuit is coupled to the column selection circuit, the column selection circuit is coupled to the NVSRAM array, and the non-volatile storage operation circuit is coupled to the NVSRAM array. The NVSRAM array comprises a plurality of NVSRAM units arranged in an array, and each NVSRAM unit comprises an SRAM storage subunit and a non-volatile storage subunit configured to back up data stored in the SRAM storage subunit. The non-volatile storage operation circuit is configured to perform a data backup operation on the SRAM storage subunit data in the selected NVSRAM unit in the NVSRAM array. The column selection circuit is configured to select a target unit column in the NVSRAM array that needs to be operated, and perform a data recovery operation on the non-volatile storage subunit data in the target unit column. The SRAM operation circuit is configured to perform a data read / write operation on the SRAM storage subunit data in the target unit column. The input / output interface circuit is configured to provide received input data to the SRAM operation circuit and receive output data to be output from the SRAM operation circuit. The error detection and correction circuit is configured to encode and decode target data, determine whether the target data has an error, and correct the error. The column selection circuit is further configured to isolate the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit, and isolate the data read / write operation and the data recovery operation.

[0008] The at least one embodiment of the present disclosure provides a control method of a storage device, applied to the storage device provided by any one of the embodiments of the present disclosure. The method comprises: controlling the error detection and correction circuit to encode and decode target data, determine whether the target data has an error, and correct the error.

[0009] The at least one embodiment of the present disclosure provides a storage device, comprising: an NVSRAM array, an SRAM operation circuit, a non-volatile storage operation circuit and a column selection circuit. The column selection circuit is coupled with the NVSRAM array, the SRAM operation circuit is coupled with the column selection circuit, and the non-volatile storage operation circuit is coupled with the NVSRAM array. The NVSRAM array comprises a plurality of NVSRAM units arranged in an array, and each NVSRAM unit comprises an SRAM storage subunit and a non-volatile storage subunit configured to back up data stored in the SRAM storage subunit. The non-volatile storage operation circuit is configured to perform a data backup operation on the SRAM storage subunit data in the selected NVSRAM unit in the NVSRAM array. The column selection circuit is configured to select a target unit column in the NVSRAM array that needs to be operated, and perform a data recovery operation on the non-volatile storage subunit data in the target unit column. The SRAM operation circuit is configured to perform a data read-write operation on the SRAM storage subunit data in the target unit column. The column selection circuit is further configured to isolate the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit, and isolate the data read-write operation and the data recovery operation.

[0010] The at least one embodiment of the present disclosure provides a control method of a storage device, applied to the storage device provided by any one of the embodiments of the present disclosure. The method comprises: in the case that the SRAM operation circuit performs the data read-write operation, disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, and controlling the column selection circuit to couple the SRAM operation circuit and the NVSRAM array; or in the case that the column selection circuit performs the data recovery operation, disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, and controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array; or in the case that the non-volatile storage operation circuit performs the data backup operation, coupling the non-volatile storage operation circuit and the NVSRAM array, and controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array.

[0011] The at least one embodiment of the present disclosure provides an electronic device comprising the storage device provided by any one of the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0012] FIG. 1 shows a combined schematic diagram of a volatile storage subunit and a non-volatile storage subunit;

[0013] FIG. 2 shows a schematic block diagram of a storage device according to at least one embodiment of the present disclosure;

[0014] FIG. 3A shows a schematic block diagram of another storage device according to at least one embodiment of the present disclosure;

[0015] FIG. 3B shows a schematic block diagram of another storage device according to at least one embodiment of the present disclosure;

[0016] FIG. 3C shows a schematic block diagram of another storage device according to at least one embodiment of the present disclosure;

[0017] FIG. 4 shows a flowchart of a control method of a storage device according to at least one embodiment of the present disclosure;

[0018] FIG. 5 shows a flowchart of a control method of another storage device according to at least one embodiment of the present disclosure;

[0019] FIG. 6 shows a flowchart of a control method of another storage device according to at least one embodiment of the present disclosure;

[0020] FIG. 7 shows a flowchart of a control method of another storage device according to at least one embodiment of the present disclosure;

[0021] FIG. 8 shows a flowchart of a data writing method of a storage device according to at least one embodiment of the present disclosure;

[0022] FIG. 9 shows a flowchart of a data reading method of a storage device according to at least one embodiment of the present disclosure;

[0023] FIG. 10 shows a flowchart of a data backup method of a storage device according to at least one embodiment of the present disclosure;

[0024] FIG. 11 shows a flowchart of a data recovery method of a storage device according to at least one embodiment of the present disclosure;

[0025] FIG. 12 shows a schematic block diagram of a storage device according to at least one embodiment of the present disclosure;

[0026] FIG. 13A shows a schematic block diagram of another storage device according to at least one embodiment of the present disclosure;

[0027] FIG. 13B shows a schematic block diagram of another storage device according to at least one embodiment of the present disclosure;

[0028] FIG. 13C shows a schematic block diagram of another storage device according to at least one embodiment of the present disclosure;

[0029] FIG. 13D shows a schematic block diagram of another storage device according to at least one embodiment of the present disclosure;

[0030] FIG. 14A shows a flowchart of a control method of a storage device according to at least one embodiment of the present disclosure;

[0031] FIG. 14B shows a flowchart of another control method of a storage device according to at least one embodiment of the present disclosure;

[0032] FIG. 15 shows a flowchart of another control method of a storage device according to at least one embodiment of the present disclosure;

[0033] FIG. 16 shows a flowchart of another control method of a storage device according to at least one embodiment of the present disclosure;

[0034] FIG. 17 shows a flowchart of another control method of a storage device according to at least one embodiment of the present disclosure;

[0035] FIG. 18 shows a flowchart of another control method of a storage device according to at least one embodiment of the present disclosure;

[0036] FIG. 19 shows a flowchart of another control method of a storage device according to at least one embodiment of the present disclosure;

[0037] FIG. 20 shows a flowchart of a data backup of a storage device according to at least one embodiment of the present disclosure;

[0038] FIG. 21 shows a flowchart of a data recovery of a storage device according to at least one embodiment of the present disclosure;

[0039] FIG. 22 shows a schematic block diagram of a storage device according to at least one embodiment of the present disclosure;

[0040] FIG. 23 shows a schematic block diagram of another storage device according to at least one embodiment of the present disclosure;

[0041] FIG. 24 shows a flowchart of a control method of a storage device according to at least one embodiment of the present disclosure;

[0042] FIG. 25 shows a flowchart of another control method of a storage device according to at least one embodiment of the present disclosure;

[0043] FIG. 26 shows a flowchart of another control method of a storage device according to at least one embodiment of the present disclosure;

[0044] FIG. 27 shows a flowchart of a working method of a storage device according to at least one embodiment of the present disclosure;

[0045] FIG. 28 shows a flow diagram of a storage device data backup method according to at least one embodiment of the present disclosure;

[0046] FIG. 29 shows a flow diagram of a storage device data recovery method according to at least one embodiment of the present disclosure; and

[0047] FIG. 30 shows a schematic block diagram of an electronic device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of the present disclosure.

[0049] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one", "a", or "the" and similar terms do not denote a quantity restriction, but mean that there is at least one. The terms "include", "comprise", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms do not mean a physical or mechanical connection, but can include an electrical connection, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0050] A static random access memory (SRAM) includes a memory cell array, a row / column address decoder, a sense amplifier, a control circuit, a buffer / drive circuit, and the like. The memory cell array includes a plurality of SRAM memory sub-units, word lines, bit lines, and the like. The memory sub-units are arranged in multiple rows and multiple columns, and are addressed in the row direction by the word lines and in the column direction by the bit lines. SRAM can perform well in situations requiring fast data access, such as cache or CPU cache. Due to its fast data access speed, SRAM can be used as temporary storage for some data that needs to be accessed quickly.

[0051] For example, SRAM can have multiple types, such as 6T-SRAM (i.e., six-transistor type SRAM), 7T-SRAM (i.e., seven-transistor type SRAM), 8T-SRAM (i.e., eight-transistor type SRAM), and the like, multi-transistor type SRAM, which will not be specifically described here.

[0052] However, the SRAM loses the data stored therein after power failure. SRAM does not have its own independent power supply and needs to obtain power from the outside to maintain the storage of data. Once the power is interrupted, the storage subunit will not be able to continue to maintain the charge state, resulting in data loss. Therefore, the operation of SRAM requires continuous power supply to maintain its data storage state.

[0053] NVM (Non-Volatile Memory) is a semiconductor memory that can maintain data storage after power failure. For example, the non-volatile memory can be RRAM (Resistive Random Access Memory), PRAM (Phase-Change Random Access Memory), Flash, etc. For example, RRAM and PRAM store data by changing resistance. For example, resistive random access memory uses thin film material to change resistance under the condition of applied voltage to achieve different resistance states, high resistance state (HRS) and low resistance state (LRS), to realize data storage. The different high and low resistance states represent logical "1" and logical "0", thereby realizing data storage and being able to maintain for a long time after power is cut off. The process of changing from high resistance state (HRS) to low resistance state (LRS) is called SET process, which can also be called setting process. The process of changing from low resistance state to high resistance state is called RESET process, which can also be called resetting process. The operating speed of non-volatile memory is usually slower and requires larger operating current or voltage.

[0054] Therefore, the NVM is combined with the SRAM to form the NVSRAM (Nonvolatile Static random Access Memory), which combines the advantages of the above two types of memories and can solve the problem of data loss after power failure of SRAM and the problem of operating speed, etc.

[0055] In the NVSRAM, the main memory area includes an array of NVSRAM cells formed by multiple rows and multiple columns, each NVSRAM cell includes an SRAM storage subunit and an NVM storage subunit corresponding to the SRAM storage subunit, and high-speed random access can be achieved. After power failure, the data in this area can still be stored for a long time. For example, the data in the SRAM storage subunit is backed up to the NVM storage subunit before power failure, and the data is restored from the NVM storage subunit to the SRAM storage subunit when power is restored. When writing data, the data is first stored in the SRAM storage subunit, and the data is also backed up to the NVM storage subunit to achieve non-volatile storage. In the read operation, the data is directly read from the SRAM storage subunit. The SRAM storage subunit provides fast read speed and low latency. When power failure occurs, the data in the SRAM storage subunit loses power supply, while the data in the NVM storage subunit remains, which enables the NVSRAM to maintain data integrity during power failure without the need for continuous power supply from an external power source. After power is restored, the data in the NVM storage subunit is restored to the SRAM storage subunit to restore the data state, so that the NVSRAM can provide data access after power is restored, realizing the combination of high-speed access and non-volatile storage.

[0056] However, the NVM storage subunit is susceptible to some factors during data backup and data recovery, resulting in a high error rate. For example, when the SRAM storage subunit performs data recovery, a large peak current may be generated, which reduces the stability of the NVSRAM, affects the success rate of data recovery, and ultimately results in a large error rate of the recovered data; errors may also occur when data is backed up to the NVM storage subunit, for example, incomplete charge injection or release may occur during data backup, or the NVM storage subunit is affected by voltage fluctuations, electromagnetic interference, etc. during data backup, and data bit errors occur when data is backed up to the NVM storage subunit, etc., all of which can result in a high error rate of the NVM storage subunit.

[0057] In addition, for example, in the case of an NVM storage subunit being an RRAM storage subunit, during a data backup process in the RRAM storage subunit or a data recovery process in the SRAM storage subunit, the RRAM storage subunit and the SRAM storage subunit can interfere with each other. For example, due to the different read-write mechanisms of the RRAM storage subunit and the SRAM storage subunit, if their operations are not properly coordinated, read-write conflicts can occur, causing mutual interference. Or, if the data synchronization between the RRAM storage subunit and the SRAM storage subunit is not properly handled, data loss can occur, affecting the system stability of the storage device, and so on.

[0058] To solve these problems, the characteristics and operation requirements of the RRAM storage subunit and the SRAM storage subunit need to be fully considered when designing the storage device, and appropriate measures need to be taken to coordinate their operations. For example, a reasonable read-write strategy can be developed to avoid read-write conflicts between the two; or the design of the storage device can be optimized to reduce the mutual influence between the two operations, such as improving circuit design, optimizing read-write timing, using different power supplies, etc. to reduce resource conflicts and interference, and error detection and correction techniques can also be used to detect and correct incorrect stored data.

[0059] To solve these problems, the characteristics and operation requirements of the RRAM storage subunit and the SRAM storage subunit need to be fully considered when designing the storage device, and appropriate measures need to be taken to coordinate their operations. For example, a reasonable read-write strategy can be developed to avoid read-write conflicts between the two; or the design of the storage device can be optimized to reduce the mutual influence between the two operations, such as improving circuit design, optimizing read-write timing, using different power supplies, etc. to reduce resource conflicts and interference, and error detection and correction techniques can also be used to detect and correct incorrect stored data.

[0060] FIG. 1 shows a combination of a volatile storage subunit and a non-volatile storage subunit.

[0061] As shown in FIG. 1, the illustrated NVSRAM combines a volatile storage subunit and a non-volatile storage subunit. In the example shown in FIG. 1, the volatile storage subunit is a 6T-SRAM (i.e., a six-transistor type SRAM), including transistors P0, P1, N0, N1, N2, N3, and bit line BL, bit line BLN, word line WL, power line CVDD, ground line VSS for operating the storage subunit, and further including storage node Q and storage node QN within the SRAM storage subunit. Bit line BL and bit line BLN are used for reading and writing data, word line WL is used for controlling the reading and writing operation, transistors P0 and N0 form an inverter, and transistors P1 and N1 form another inverter, and the two inverters are cross-connected to thereby provide storage node Q and storage node QN. The SRAM storage subunit has a bistable structure. When storage node Q is at a high level, storage node QN is at a low level, and at this time, the data stored can be selected as "1", and correspondingly, when storage node Q is at a low level, storage node QN is at a high level, and at this time, the data stored can be selected as "0"; transistors N2 and N3 are controlled by word line WL to turn on or turn off the storage subunit.

[0062] In the example shown in FIG. 1, the non-volatile storage subunit includes resistive random access memory (RRAM) R, RRAM RN, transistor N4, and transistor N5. The non-volatile storage subunit is connected to the volatile storage subunit in a differential manner, RRAM R is connected to storage node Q through transistor N4, RRAM RN is connected to storage node QN through transistor N5, the gates of transistors N4 and N5 are connected to control line CWLN, and the switching states of transistors N4 and N5 are controlled through control line CWLN. For example, the state in which the resistance of RRAM R is smaller than the resistance of RRAM RN is set as data "1", and vice versa.

[0063] In other forms, the volatile storage subunit can also be other forms of SRAM storage subunit; in addition to being connected to the volatile storage subunit in a differential manner, the non-volatile storage subunit can also be connected in a single-ended manner, for example, including only RRAM R and transistor N4. In addition, in addition to using RRAM subunits, PRAM subunits or the like can also be used in the non-volatile storage subunit.

[0064] Some embodiments of the present disclosure provide a storage device, an electronic device including the storage device, and a storage device control method.

[0065] The storage device includes an NVSRAM array, an SRAM operation circuit, a non-volatile storage operation circuit, an error detection and correction circuit, an input / output interface circuit, and a column selection circuit. The error detection and correction circuit is coupled to the input / output interface circuit, the error detection and correction circuit is coupled to the SRAM operation circuit, the SRAM operation circuit is coupled to the column selection circuit, the column selection circuit is coupled to the NVSRAM array, and the non-volatile storage operation circuit is coupled to the NVSRAM array.

[0066] The NVSRAM array includes a plurality of NVSRAM cells arranged in an array, and each NVSRAM cell includes an SRAM storage subunit and a non-volatile storage subunit, and the non-volatile storage subunit is configured to back up data stored in the SRAM storage subunit.

[0067] The non-volatile storage operation circuit is configured to perform a data backup operation on the SRAM storage subunit data in the selected NVSRAM cell in the NVSRAM array; the column selection circuit is configured to select a target cell column in the NVSRAM array that needs to be operated, and perform a data recovery operation on the non-volatile storage subunit data in the target cell column; the SRAM operation circuit is configured to perform a data read / write operation on the SRAM storage subunit data in the target cell column; the input / output interface circuit is configured to provide received input data to the error detection and correction circuit and receive output data to be output from the error detection and correction circuit; the error detection and correction circuit is configured to encode and decode data transmitted between the input / output interface circuit and the SRAM operation circuit, determine whether the data has an error and correct the error; and the column selection circuit is further configured to isolate the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit, and isolate the data read / write operation and the data recovery operation.

[0068] The storage device detects and corrects erroneous storage data by using the error detection and correction circuit, and isolates the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit by using the column selection circuit, thereby improving the reliability of data read / write, backup, and recovery.

[0069] FIG. 2 shows a schematic block diagram of a storage device according to at least one embodiment of the present disclosure.

[0070] As shown in FIG. 2, the storage device 1000 includes an NVSRAM array 120, an SRAM operation circuit 100, a non-volatile storage operation circuit 130, an error detection and correction circuit 160, an input / output interface circuit 150, and a column selection circuit 110.

[0071] The error correction circuit 160 is coupled with the input / output interface circuit 150, and is also coupled with the SRAM operation circuit 100. Therefore, the error correction circuit 160 is located between the input / output interface circuit 150 and the SRAM operation circuit 100 to transmit data. The SRAM operation circuit 100 is coupled with the column selection circuit 110, the column selection circuit 110 is coupled with the NVSRAM array 120, and the non-volatile storage operation circuit 130 is coupled with the NVSRAM array 120.

[0072] In the present disclosure, "coupled" is used to describe the signal connection between objects, and signal transmission can be performed after the coupling between the objects is established, and signal connection cannot be performed after the coupling between the objects is disconnected. The coupling can be achieved by, for example, electrical connection. For example, in the embodiments of the present disclosure, "coupled" can include two or more electronic elements or circuits connected together in some way, so that signals are transmitted between them. For example, two storage subunits can be directly connected, and information transmission can be achieved through signal or energy transmission, or two storage subunits are connected through other circuit elements, such as resistors, capacitors, switches, optoelectronic elements, or transmission line networks, to achieve signal transmission.

[0073] The NVSRAM array 120 includes a plurality of NVSRAM units 121 arranged in an array, and each NVSRAM unit 121 includes an SRAM storage subunit 122 and a non-volatile storage subunit 131 configured to back up data stored in the SRAM storage subunit 122. The array formed by the plurality of NVSRAM units 121 includes a plurality of rows and a plurality of columns. For example, the plurality of NVSRAM units 121 can form a storage array including M rows and N columns, where M and N are integers and 1≤M, 1≤N. The NVSRAM unit 121 may, for example, adopt the form shown in FIG. 1, but embodiments of the present disclosure are not limited to this specific form.

[0074] The NVSRAM unit 121 of the NVSRAM array 120 combines the characteristics of the SRAM storage subunit and the non-volatile storage subunit. The SRAM storage subunit 122 can be configured to store data and can quickly read and write data. The non-volatile storage subunit 131 is configured to back up data stored in the SRAM storage subunit 122 to prevent data loss in the SRAM storage subunit 122 in the event of power failure or system crash.

[0075] For example, the non-volatile storage subunit 131 can include RRAM, FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), PCM (Phase Change Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), PRAM, flash memory, and the like storage subunit, corresponding to different types of non-volatile storage subunit 131, the non-volatile storage operation circuit 130 in the embodiment of the present disclosure is adjusted accordingly, and the present disclosure does not limit this. For example, when the non-volatile storage subunit 131 includes an RRAM storage subunit, the non-volatile storage operation circuit 130 includes an RRAM operation circuit.

[0076] The non-volatile storage operation circuit 130 is configured to perform a data backup operation on the data in the SRAM storage subunit 122 in the selected NVSRAM cell 121 in the NVSRAM array 120.

[0077] In some embodiments, the non-volatile storage operation circuit 130 can communicate with a plurality of SRAM storage subunits 122. The non-volatile storage operation circuit 130 can perform a data backup operation on the SRAM storage subunit 122 data as needed, such as when the electronic device detects that an application program has failed or is abnormal, the non-volatile storage operation circuit 130 performs a data backup operation. For example, the non-volatile storage operation circuit 130 can also perform a data backup operation on the data in the SRAM storage subunit 122 in response to a backup instruction, or perform a periodic data backup operation on the SRAM storage subunit 122 based on a preset time, or perform a real-time data backup operation on the SRAM storage subunit 122.

[0078] To improve the efficiency of data backup, the non-volatile storage operation circuit 130 can use a parallel processing method to simultaneously perform a data backup operation on a plurality of selected SRAM storage subunit 122 data. For example, the non-volatile storage operation circuit 130 can simultaneously perform a data backup operation on the data in a plurality of SRAM storage subunits 122 in a selected row, or the non-volatile storage operation circuit 130 can simultaneously perform a data backup operation on a plurality of rows of SRAM storage subunit 122 data, or the non-volatile storage operation circuit 130 can simultaneously perform a data backup operation on a plurality of rows and columns of SRAM storage subunit 122 data.

[0079] To improve the reliability and stability of data backup, at least one embodiment of the present disclosure also adopts some safety designs to improve the redundancy of the non-volatile storage operation circuit 130.

[0080] For example, in at least one example, the non-volatile storage operation circuit 130 can adopt an ECC (Error Checking and Correcting) mechanism, which can add additional check bits when data is backed up to the non-volatile storage subunit 131, so as to detect and correct errors when the data is read. The ECC mechanism can improve the reliability of the data and reduce the risk of data loss due to hardware failure or data corruption.

[0081] For example, in at least one example, the non-volatile storage operation circuit 130 can also adopt a CRC (Cyclic Redundancy Check) mechanism to calculate the CRC value of the data before and after the data backup operation to ensure the integrity of the data. If the CRC values do not match, the non-volatile storage operation circuit 130 can take appropriate measures to recover the data or perform error handling. Other embodiments of the present disclosure can also adopt other data checking and error correction mechanisms, including but not limited to, parity check, SED (Single-bit Error Detection), SEC (Single-bit Error Correction), DED (Double-bit Error Detection), or FED (Fatal Error Detection), etc. Embodiments of the present disclosure are not limited thereto.

[0082] In some embodiments, the SRAM operation circuit 100 is configured to perform data read / write operations on the SRAM storage subunit 122 in the object cell column. Here, the "object cell column" is used to refer to the storage cell column that is the object of operation, which can be any column in the plurality of storage arrays.

[0083] For example, the SRAM operation circuit 100 performs data read / write operations on the selected SRAM storage subunit 122 by receiving the corresponding read / write command. For example, when the storage device 1000 needs to perform data read / write, the SRAM operation circuit 100 performs data read / write operations, the SRAM operation circuit 100 reads the data in the SRAM storage subunit 122 and inputs the data into the error detection and correction circuit 160, or the SRAM operation circuit 100 receives the data provided by the error detection and correction circuit 160 and writes the data into the SRAM storage subunit 122.

[0084] In some embodiments, the column selection circuit 110 is configured to select the object cell column in the NVSRAM array 120 that needs to be operated. For example, the column selection circuit 110 is responsive to the received address signal (here, the column selection signal) and converts it into an electrical signal to select the corresponding object cell column in the NVSRAM array 120. For example, the column selection circuit 110 can select the corresponding object cell column in the NVSRAM array 120 according to the data read / write operation required to be performed by the SRAM operation circuit 100.

[0085] Here, the address signal includes a row selection signal and a column selection signal, and the row selection signal is used by the word line driving circuit (to be described below) for addressing in the row direction, and the column selection signal is used by the column selection circuit for addressing in the column direction.

[0086] In some embodiments of the present disclosure, the column selection circuit 110 is configured to perform a data recovery operation on the non-volatile storage subcell data in the object cell column. Here, the “object cell column” is used to refer to the storage cell column that is the object of operation, which can be any column in the plurality of storage arrays.

[0087] For example, the column selection circuit 110 performs a data recovery operation on the selected non-volatile storage subcell 131 by receiving a corresponding data recovery operation command. When the data in the non-volatile storage subcell 131 needs to be recovered to the SRAM storage subcell 122, the column selection circuit 110 performs a data recovery operation, and the column selection circuit 110 controls the non-volatile storage subcell 131 to recover the stored data to the SRAM storage subcell 122.

[0088] As previously described, during the data backup operation performed by the non-volatile storage operation circuit 130, or during the data read / write operation performed by the SRAM operation circuit 100, or during the data recovery operation performed by the column selection circuit 110, the operations of the non-volatile storage operation circuit 130, the operations of the SRAM operation circuit 100, and the data recovery operation of the column selection circuit 110 can affect each other, thereby affecting the stability of the data backup operation, the data read / write operation, and the data recovery operation.

[0089] In at least some embodiments of the present disclosure, the column selection circuit 110 is further configured to isolate the operation of the SRAM operation circuit 100 and the operation of the non-volatile storage operation circuit 130, and to isolate the data read / write operation and the data recovery operation.

[0090] For example, independent column selection circuits 110 can be provided for the non-volatile storage operation circuit 130 and the SRAM operation circuit 100, respectively, to reduce the influence and interference between them. The independent column selection circuits 110 can have different circuit structures and elements to adapt to the characteristics and operation requirements of the non-volatile storage operation circuit 130 and the SRAM operation circuit 100.

[0091] In some embodiments, the non-volatile storage operation circuit 130 and the SRAM operation circuit 100 can also be power-isolated, such as being provided with independent power supplies respectively. For example, the non-volatile storage operation circuit 130 and the SRAM operation circuit 100 can also be provided with voltage stabilizers to improve the stability of the power supply of the circuits. For example, the operation of the non-volatile storage operation circuit 130 and the operation of the SRAM operation circuit 100 can also be controlled by logic design, such as allowing only the operation of the non-volatile storage operation circuit 130 or allowing only the operation of the SRAM operation circuit 100 in a specific situation, and prohibiting the simultaneous operation of both.

[0092] For example, the column selection circuit 110 can also not perform the data recovery operation in the case that the SRAM operation circuit 100 performs the data read / write operation or the non-volatile storage operation circuit 130 performs the data backup operation, so as to isolate the data read / write operation, the data backup operation and the data recovery operation.

[0093] In some embodiments, as shown in FIG. 2, the input / output interface circuit 150 is configured to provide the received input data to the error correction circuit 160 and receive the output data to be output from the error correction circuit 160. The error correction circuit 160 is configured to encode and decode the data transmitted between the input / output interface circuit 150 and the SRAM operation circuit 100, determine whether the data has an error and correct the error.

[0094] For example, the error correction circuit 160 can encode the data by using the parity code, can add an extra data check bit in the data to make the number of 1s in the entire byte even (even parity) or odd (odd parity), and can check the check bit when receiving the data to be checked. For example, the error correction circuit 160 can also encode the data by using the Hamming code, can divide the data into multiple groups and add a check bit in each group, so that the erroneous data in each group can be detected and corrected. For example, the error correction circuit 160 can also encode the data by using the cyclic redundancy check (CRC) method, can add a redundant check code in the data, can regard the data as a binary polynomial, and can use a generator polynomial to perform a modulo 2 division operation on the data to obtain the remainder as the CRC check code.

[0095] In at least some embodiments of the present disclosure, for example, the error correction circuit 160 can also include a data encoder and a data decoder. The data encoder can be configured to convert input data into a specific encoding format, increasing the redundancy information of the data, such as parity check code, Hamming code, cyclic redundancy check code, etc. The data decoder can be configured to decode the received encoded data into the original data, and at the same time, it will also perform error detection on the data, such as through parity check, CRC check, etc.

[0096] In at least some embodiments of the present disclosure, for example, the error correction circuit 160 can also include error detection and correction logic and control logic. The error detection and correction logic can perform error detection on the decoded data and determine whether the error can be corrected according to the encoding method. For example, if a parity check code is used, the logic will check the check bits and determine the error bits, and then correct the error bits. For some complex error conditions, multiple error corrections or degradation processes may be required. The control logic is used to control the entire process of data encoding, transmission, decoding and error correction, and can also be used to interact with other circuits, such as sending control signals to the column selection circuit 110 to control data transmission.

[0097] In at least some embodiments of the present disclosure, the error correction circuit 160 can also be configured to encode the data input from the input / output interface circuit 150 to the error correction circuit 160, write the encoded data to the SRAM operation circuit 100 for being written into the NVSRAM array 120 by the SRAM operation circuit 100; and the error correction circuit 160 can also be configured to determine whether the data read from the NVSRAM array 120 by the SRAM operation circuit 100 and input to the error correction circuit 160 has an error and correct the error.

[0098] For example, in the case of writing data into the storage device according to system instructions, after receiving the original data from the input / output interface circuit 150, the error detection and correction circuit 160 encodes the data. The encoding can be performed by adding extra check bits to increase the redundancy of the data, so that even if part of the data is damaged or lost after the data is written into the NVSRAM array 120, the error can be detected and corrected by the check bits. The encoded data will be written into the SRAM operation circuit 100 by the error detection and correction circuit 160. The SRAM operation circuit 100 receives the encoded data from the error detection and correction circuit 160 and writes it into the NVSRAM array 120. In the case of reading (previously stored) data from the storage device according to system instructions, after the SRAM operation circuit 100 reads the data from the NVSRAM array 120 and inputs it to the error detection and correction circuit 160, the error detection and correction circuit 160 can determine whether the read data has an error. For example, by comparing the read data with the expected data. If an error is found, the error detection and correction circuit 160 will use the check bits added in the encoding process to correct the error. For example, if one bit of the read data is incorrect, the error detection and correction circuit 160 can detect this error using the check bits and correct it using the correct value expected in the encoding process.

[0099] For example, the error detection and correction circuit 160 encodes the data including K-bit information code input from the input / output interface circuit 150 into the error detection and correction circuit 160 to obtain corresponding R-bit check code data. Then, the error detection and correction circuit 160 writes the encoded data including K-bit information code and R-bit check code into the SRAM operation circuit 100. The SRAM operation circuit 100 writes the data including K-bit information code and R-bit check code into the NVSRAM array 120 through the column selection circuit. In the case of data recovery operation by the column selection circuit, the error detection and correction circuit 160 decodes the data including K-bit information code and R-bit check code read from the NVSRAM array 120 by the SRAM operation circuit 100 and input into the error detection and correction circuit 160, and determines whether the decoding result has an error, and corrects the error if there is an error.

[0100] For example, in some embodiments, the storage device 1000 can perform error detection and correction operations when performing data read / write operations, and not perform error detection and correction operations when performing data backup operations or data recovery operations, which can improve the efficiency of data backup operations and data recovery operations.

[0101] The above describes a basic error correction and storage operation process of an embodiment of the present disclosure. In different embodiments, the error correction circuit 160 can use different encoding and decoding algorithms, such as using different check methods such as parity check, CRC check, etc., and the present embodiment of the present disclosure is not limited thereto. In addition, the data writing and reading process can also be different due to the specific hardware and interface design.

[0102] In some embodiments, when the SRAM operation circuit 100 performs data read / write operations, the column selection circuit 110 can be configured to couple the SRAM operation circuit 100 and the NVSRAM array 120, and accordingly, the non-volatile storage operation circuit 130 can be configured to decouple the coupling with the NVSRAM array.

[0103] In some embodiments, when the non-volatile storage operation circuit 130 performs data backup operations, the column selection circuit 110 can be configured to decouple the SRAM operation circuit 100 and the NVSRAM array 120, and the non-volatile storage operation circuit 130 can be configured to couple with the NVSRAM array 120.

[0104] In some embodiments, when the column selection circuit 110 performs data recovery operations, the column selection circuit 110 can be configured to decouple the SRAM operation circuit 100 and the NVSRAM array 120, and the non-volatile storage operation circuit 130 can be configured to decouple the coupling with the NVSRAM array 120.

[0105] For example, when the SRAM operation circuit 100 needs to perform data read / write operations, the column selection circuit 110 couples the SRAM operation circuit 100 and the NVSRAM array 120, and then the SRAM operation circuit 100 can perform data read / write operations on the SRAM storage subunit 122 in the NVSRAM array 120 to achieve fast data read / write transmission, and the column selection circuit 110 is configured to stop performing data recovery operations. At the same time, since the coupling between the non-volatile storage operation circuit 130 and the NVSRAM array 120 is disconnected, the column selection circuit 110 stops performing data recovery operations, and therefore will not affect the read / write operations of the SRAM operation circuit 100.

[0106] For example, when the non-volatile storage operation circuit 130 needs to perform data backup operations, the column selection circuit 110 disconnects the coupling between the SRAM operation circuit 100 and the NVSRAM array 120, and in addition, the column selection circuit 110 stops performing data recovery operations. However, the non-volatile storage operation circuit 130 is coupled with the NVSRAM array 120, and the non-volatile storage operation circuit 130 can perform data backup operations, and the SRAM operation circuit 100 and the column selection circuit 110 will not affect the data backup operation process.

[0107] For example, in the case of SRAM operation circuit 100 performing data read / write operation, non-volatile storage operation circuit 130 is configured to disconnect the coupling with NVSRAM array, stop the operation of non-volatile storage operation circuit 130, and column selection circuit 110 is configured to stop performing data recovery operation.

[0108] For example, in the case of non-volatile storage operation circuit 130 performing data backup operation, column selection circuit 110 is configured to disconnect the coupling of SRAM operation circuit with NVSRAM array, and stop the data recovery operation of column selection circuit 110.

[0109] For example, in the case of column selection circuit 110 performing data recovery operation, non-volatile storage operation circuit 130 can be configured to disconnect the coupling with NVSRAM array 120, stop data backup operation; column selection circuit 110 can also be configured to disconnect the coupling of SRAM operation circuit 100 with NVSRAM array 120, stop data read / write operation. To isolate data backup operation, data read / write operation and data recovery operation.

[0110] For example, in at least some embodiments of the present disclosure, column selection circuit 110 can further include a data recovery operation sub-circuit. FIG. 3A shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure. For example, as shown in FIG. 3A, column selection circuit 110 further includes data recovery operation sub-circuit 111.

[0111] For example, in some embodiments, data recovery operation sub-circuit 111 can be configured to perform data recovery operation on the data of non-volatile storage sub-unit 131 in the object unit column. For example, data recovery operation sub-circuit 111 can recover the data stored in the selected non-volatile storage sub-unit 131 to SRAM storage sub-unit 122 upon receiving the instruction to perform data recovery operation. For example, when performing data recovery operation, data recovery operation sub-circuit 111 needs to ensure isolation from the operation of SRAM operation circuit 100 and non-volatile storage operation circuit 130, to prevent conflicts between data read / write operation, data backup operation and data recovery operation, and to improve the integrity of the data and the stability of the system.

[0112] For example, in some embodiments, the column selection circuit 110 can further include a switch array (not shown in the figure) through which the column selection circuit 110 can control the coupling between the SRAM operation circuit 100 and the NVSRAM array 120. For example, in the case of data read / write operation of the SRAM operation circuit 100, the column selection circuit 110 can be configured to turn on the switch of the coupling between the column selection circuit 110 and the NVSRAM array 120. For example, in the case of data backup operation of the non-volatile storage operation circuit 130 or data recovery operation of the column selection circuit, the column selection circuit 110 can be further configured to turn off the switch of the coupling between the column selection circuit 110 and the NVSRAM array 120. For example, the switch array of the column selection circuit 110 can also be turned on or off according to the timing logic of controlling the operation of the non-volatile storage operation circuit 130, the operation of the column selection circuit 100 and the operation of the SRAM operation circuit 100, such as being turned on at a specific timing when only the SRAM operation circuit 100 is allowed to operate. For example, the switch array of the column selection circuit 110 is turned off when only the non-volatile storage operation circuit 130 is allowed to operate. For example, the switch array of the column selection circuit 110 is turned off at a specific timing when only the non-volatile storage operation circuit 130 is allowed to operate.

[0113] In some embodiments of the present disclosure, as shown in FIG. 2, the NVSRAM array 120 can also be configured to be coupled with the word line driving circuit 140 to control the operation of the word line in the NVSRAM array 120.

[0114] The word line driving circuit 140 for the NVSRAM array 120 is configured to control the circuit of the row (word line) where the storage unit is located in the NVSRAM array 120. In the NVSRAM array 120, for example, each storage unit is located at the intersection of the signal lines, that is, the horizontal signal line is the word line (Word Line), and the vertical signal line is the bit line (Bit Line). For example, the word line driving circuit 140 is responsible for controlling the switch connected to the word line to determine which row of storage units is selected for the required operation (correspondingly, the column selection circuit 110 is responsible for determining which column of storage units is selected for the required operation through the bit line).

[0115] For example, in some embodiments, the word line driving circuit 140 can include a decoder and a selector. The decoder is used to receive the address signal and decode it into the row address of the corresponding word line. The selector is responsible for selecting the corresponding word line to apply the driving signal according to the row address. In the case of data reading or writing of the selected storage unit, the word line driving circuit 140 can ensure the correct access to the selected storage unit while avoiding interference or misoperation to other unselected storage units.

[0116] FIG. 3B shows a schematic block diagram of another storage device according to at least one embodiment of the present disclosure.

[0117] As shown in FIG. 3B, in some embodiments of the present disclosure, the array width of the NVSRAM array 120 can be configured as N, i.e., having N columns of storage units (e.g., the number of corresponding bit lines is 2N), for example, each row in the NVSRAM array 120 can include N NVSRAM units. The array of the NVSRAM array 120 can also be configured to have M rows of storage units, for example, each column in the NVSRAM array 120 can include M NVSRAM units. The N columns of storage units of the NVSRAM array 120 can include data columns and redundancy columns, the data columns store information codes, and the redundancy columns store additional check codes as needed for encoding. The NVSRAM array 120 is configured in units of words, each row of the NVSRAM array 120 stores P words of data, and the stored data of each word can include K-bit information codes and R-bit check codes. For example, N = P*(K+R), where N, P, K, and R are positive integers, 1≤K<N, 1≤R<N, and 1≤P.

[0118] In this embodiment, the data columns and the redundancy columns can have various arrangements. For example, as shown in FIGS. 3B-3C, all data columns can be arranged adjacent to each other, and all redundancy columns can be arranged adjacent to each other; or the data columns can be grouped, the redundancy columns can be grouped, and then the data column groups and the redundancy column groups can be arranged alternately with each other. Embodiments of the present disclosure are not limited to the arrangement of the data columns and the redundancy columns.

[0119] In some embodiments of the present disclosure, the combined storage array of the NVSRAM shown in FIG. 1 can be arranged in the form shown in FIG. 3B or FIG. 3C, and can also be arranged in other forms, for example, the data columns are arranged adjacent to each other to form one partition, the redundancy columns are arranged adjacent to each other to form another partition, etc.

[0120] In some embodiments of the present disclosure, each row in the NVSRAM array 120 can include N memory cells, each of which has a corresponding address for locating and accessing the memory cell. For example, each row in the NVSRAM array 120 includes N memory cells, each of which is configured with X bit lines, then the number of bit lines of the NVSRAM memory array is X*N, in the case of transmission lines being bit lines or bit line pairs (e.g., bit lines BL and BLN as shown in FIG. 1), X can be configured as 2, then the number of bit lines of the NVSRAM memory array can be configured as 2N. For example, in at least one example, in the case of transmission lines being bit lines or bit line pairs (e.g., bit lines BL and BLN as shown in FIG. 1), the non-volatile storage operation circuit 130 can also be configured to couple with the NVSRAM array 120 through N or 2N bit lines. In some embodiments, for example, in the case of the column selection circuit 110 performing a data recovery operation, the column selection circuit 110 is also configured to set the voltage of the 2N bit lines to the same voltage value.

[0121] In some embodiments of the present disclosure, the non-volatile storage operation circuit 130 can be configured to couple with the NVSRAM array 120 through N groups of transmission lines. In the case of transmission lines being bit lines or bit line pairs, the non-volatile storage operation circuit 130 can also be configured to couple with the NVSRAM array 120 through N or 2N bit lines. The error correction circuit 160 can be configured to couple with the input / output interface circuit 150 through K groups of transmission lines. The error correction circuit 160 can also be configured to couple with the SRAM operation circuit 100 through K+R groups of transmission lines. The SRAM operation circuit 100 can be configured to couple with the column selection circuit 110 through K+R groups of transmission lines. The column selection circuit 110 couples with the NVSRAM array 120 through N groups of transmission lines. For example, in the case of transmission lines being bit lines or bit line pairs (e.g., bit lines BL and BLN as shown in FIG. 1), the column selection circuit 110 can also be configured to couple with the NVSRAM array 120 through N or 2N bit lines. For example, the error correction circuit 160 couples with the SRAM operation circuit 100 through K+R groups of transmission lines to write data including K-bit information code and R-bit check code after encoding into the SRAM operation circuit 100, or data including K-bit information code and R-bit check code read from the NVSRAM array 120 by the SRAM circuit is written into the error correction circuit 160 through K+R groups of transmission lines. The SRAM operation circuit 100 connects with the column selection circuit 110 through K+R groups of transmission lines for locating and accessing a specific memory cell in the NVSRAM array 120 according to the address provided by the column selection circuit 110, writing data including K-bit information code and R-bit check code into the NVSRAM array 120, and reading data including K-bit information code and R-bit check code from the NVSRAM array 120.

[0122] In the storage device 1000 of at least one embodiment of the present disclosure, by setting the error correction circuit 160 between the input / output interface circuit 150 and the SRAM operation circuit 100, the data error correction and other functions of the NVSRAM array 120 can be conveniently implemented. For example, the number and type of these transmission lines and other parameters can be flexibly adjusted according to the requirements and hardware conditions to optimize the performance and efficiency of the storage device 1000.

[0123] In some embodiments of the present disclosure, in the case of performing a data backup operation by the non-volatile storage operation circuit 130, the word line driving circuit 140 can also be configured to select the data of the SRAM storage sub-unit 122 in the I row of NVSRAM units 121 of the NVSRAM array 120 for the data backup operation, where I is an integer and M≥I≥1.

[0124] For example, the word line driving circuit 140 can select the SRAM storage sub-unit 122 in the I row of NVSRAM units 121 in the NVSRAM array 120 according to the received data backup operation instruction. For example, the word line driving circuit 140 can select the SRAM storage sub-unit 122 in the first I row of NVSRAM units 121, and the non-volatile storage operation circuit 130 can be configured to perform a parallel data backup operation on the data of the selected SRAM storage sub-unit 122 in the first I row of NVSRAM units 121, and backup all the data of the selected I row of SRAM storage sub-units 122 to the non-volatile storage sub-unit 131.

[0125] In some embodiments of the present disclosure, in the case of performing a data recovery operation by the column selection circuit 110, the word line driving circuit 140 can also be configured to select the data of the non-volatile storage sub-unit 131 in the J row of NVSRAM units 121 of the NVSRAM array 120 for the data recovery operation, where J is an integer and M≥J≥1.

[0126] For example, the word line driving circuit 140 can select the non-volatile storage sub-unit 131 in the J row of NVSRAM units 121 in the NVSRAM array 120 according to the received data recovery operation instruction. For example, the word line driving circuit 140 can select the non-volatile storage sub-unit 131 in the first J row of NVSRAM units 121, and the column selection circuit 110 can be configured to perform a parallel data recovery operation on the data of the selected non-volatile storage sub-unit 131 in the first J row of NVSRAM units 121, and recover all the data of the selected J row of non-volatile storage sub-units 131 to the SRAM storage sub-unit 122.

[0127] In some embodiments of the present disclosure, the SRAM operation circuit 100 is further configured to perform a data read / write operation on the data of the SRAM storage sub-cells 122 in the W NVSRAM cells 121 of the ith row of the selected NVSRAM array 120 in the case of performing the data read / write operation. Wherein, N≥W≥1, M≥i≥1, and W=K+R.

[0128] For example, the operation bit width of the data read / write operation of the SRAM operation circuit 100 is W. Illustratively, the SRAM operation circuit 100 can perform a data read / write operation on the data of the SRAM storage sub-cells 122 in the W NVSRAM cells 121 in a certain row (the ith row) of the selected NVSRAM array 120 according to the received data read / write operation instruction.

[0129] In some embodiments of the present disclosure, the non-volatile storage operation circuit 130 is further configured to perform a data backup operation on the data of the SRAM storage sub-cells 122 in the NVSRAM cells 121 of the E rows and / or the F columns of the selected NVSRAM array 120 in the case of performing the data backup operation. Wherein, E, F are integers and M≥E≥1, N≥F≥1.

[0130] For example, the operation bit width of the data backup operation of the non-volatile storage operation circuit 130 can be N*M.

[0131] For example, the non-volatile storage operation circuit 130 can perform a data backup operation on the data of the SRAM storage sub-cells 122 in the selected E rows or F columns of the NVSRAM cells 121 in the M rows and N columns of the NVSRAM array 120 according to the received data backup operation instruction. Alternatively, the non-volatile storage operation circuit 130 can perform a data backup operation on all the data of the SRAM storage sub-cells 122 in the F columns of the selected E rows of the NVSRAM cells 121 in the M rows and N columns of the NVSRAM array 120.

[0132] In some embodiments of the present disclosure, the column selection circuit 110 is further configured to perform a data recovery operation on the data of the non-volatile storage sub-cells 131 in the NVSRAM cells 121 of the G rows and / or the H columns of the selected NVSRAM array 120 in the case of performing the data recovery operation. Wherein, G, H are integers and M≥G≥1, N≥H≥1.

[0133] For example, the operation bit width of the data recovery operation of the column selection circuit 110 is N*M.

[0134] For example, the column selection circuit 110 can perform a data recovery operation on the data of the non-volatile storage sub-cells 131 in the selected G rows or H columns of the NVSRAM cells 121 in the M rows and N columns of the NVSRAM cells 121 in the NVSRAM array 120 according to the received data recovery operation instruction. Alternatively, the non-volatile storage operation circuit 130 can perform a data recovery operation on all the data of the non-volatile storage sub-cells 131 in the selected G rows of the NVSRAM cells 121 in the H columns of the NVSRAM cells 121 in the M rows and N columns of the NVSRAM cells 121 in the NVSRAM array 120.

[0135] FIG. 4 shows a flowchart of a control method of a storage device according to at least one embodiment of the present disclosure.

[0136] As shown in FIG. 4, in some embodiments of the present disclosure, the control method of the storage device can include steps S200-S210.

[0137] Step S200: Control the error detection and correction circuit to encode and decode the data transmitted between the input / output interface circuit and the SRAM operation circuit.

[0138] For step S200, for example, in the process of writing data into the storage device, the data is input into the error detection and correction circuit through the input / output interface circuit, the error detection and correction circuit encodes the data, and inputs the encoded data into the SRAM operation circuit for writing into the NVSRAM array for data storage and backup. For example, in the process of performing data read / write operation, the error detection and correction circuit decodes the data read from the NVSRAM array by the SRAM operation circuit and input into the error detection and correction circuit.

[0139] Step S210: Determine whether the data has an error and correct the error.

[0140] For step S210, the error detection and correction circuit determines the decoding result of the data, determines whether the decoding result has an error, and if there is an error, corrects the error. If there is no error, the data is output through the input / output interface circuit.

[0141] The method of encoding, decoding and correcting the data by the error detection and correction circuit can refer to the related description above, which will not be described here.

[0142] FIG. 5 shows a flowchart of another control method of a storage device according to at least one embodiment of the present disclosure.

[0143] As shown in FIG. 5, the method can include steps S300-S320.

[0144] Step S300: Determine that the SRAM operation circuit performs data read / write operation.

[0145] Step S310: disconnect the coupling between the non-volatile storage operation circuit and the NVSRAM array.

[0146] Step S320: control the column selection circuit to connect the coupling between the SRAM operation circuit and the NVSRAM array.

[0147] In the case of determining that the SRAM operation circuit performs data read / write operation, it is necessary to isolate the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit to avoid mutual influence and affect the reliability of data read / write. Therefore, it is necessary to disconnect the coupling between the non-volatile storage operation circuit and the NVSRAM array, and control the column selection circuit to connect the coupling between the SRAM operation circuit and the NVSRAM array, so as to isolate the operation of the non-volatile storage operation circuit and the SRAM operation circuit.

[0148] For step S310, in one example, for example, the non-volatile storage operation circuit stops the operation of the non-volatile storage operation circuit according to the received instruction that the SRAM operation circuit performs data read / write operation, and disconnects the coupling between the non-volatile storage operation circuit and the NVSRAM array.

[0149] For step S320, in one example, for example, in the case where the column selection circuit includes a switch array, step S320 further includes step S321 (not shown in the figure). Step S321: control the column selection circuit to turn on the switch array coupling the column selection circuit and the NVSRAM array. The method of isolating the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit can refer to the related description above, which will not be described here.

[0150] In some embodiments, the method shown in FIG. 5 can further include step S330 (not shown in the figure). Step S330: control the column selection circuit to stop data recovery operation.

[0151] In the case of determining that the SRAM operation circuit performs data read / write operation, it is necessary to isolate the data recovery operation of the column selection circuit and the operation of the SRAM operation circuit to avoid mutual influence and affect the reliability of data read / write. Therefore, it is necessary to control the column selection circuit to stop data recovery operation, so as to isolate the operation of the data recovery operation and the SRAM operation circuit.

[0152] FIG. 6 shows a flowchart of another control method of a storage device provided by at least one embodiment of the present disclosure. As shown in FIG. 6, the control method can include steps S350-S370.

[0153] Step S350: determine that the column selection circuit performs data recovery operation.

[0154] Step S360: disconnect the coupling between the non-volatile storage operation circuit and the NVSRAM array.

[0155] Step S370: control the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array.

[0156] In the case of determining that the column selection circuit performs the data recovery operation, the data recovery operation of the column selection circuit and the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit need to be isolated from each other to avoid affecting the reliability of data recovery. Therefore, the coupling between the non-volatile storage operation circuit and the NVSRAM array needs to be connected, and the column selection circuit needs to be controlled to disconnect the coupling between the SRAM operation circuit and the NVSRAM array, so as to isolate the column selection circuit, the non-volatile storage operation circuit and the SRAM operation circuit from each other.

[0157] FIG. 7 shows a flowchart of another control method of a storage device provided by at least one embodiment of the present disclosure.

[0158] As shown in FIG. 7, the control method can include steps S400-S420.

[0159] Step S400: determine that the non-volatile storage operation circuit performs the data backup operation.

[0160] Step S410: connect the coupling between the non-volatile storage operation circuit and the NVSRAM array.

[0161] Step S420: control the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array.

[0162] In the case of determining that the non-volatile storage operation circuit performs the data backup operation, the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit need to be isolated from each other to avoid affecting the reliability of data backup. Therefore, the coupling between the non-volatile storage operation circuit and the NVSRAM array needs to be connected, and the column selection circuit needs to be controlled to disconnect the coupling between the SRAM operation circuit and the NVSRAM array, so as to isolate the non-volatile storage operation circuit and the SRAM operation circuit from each other.

[0163] For step S420, in one example, for example, the column selection circuit stops the operation of the column selection circuit according to the received instruction that the non-volatile storage operation circuit performs the data backup operation. For another example, in the case that the column selection circuit further includes a switch array, step S420 further includes step S421 (not shown in the figure). Step S421: control the column selection circuit to disconnect the switch array that couples the column selection circuit and the NVSRAM array. The method of isolating the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit can refer to the related description above, which will not be described here again.

[0164] In some embodiments, the method shown in FIG. 7 can further include step S430 (not shown in the figure). Step S430: control the column selection circuit to stop the data recovery operation.

[0165] In the case of determining that the non-volatile storage operation circuit performs the data backup operation, the data recovery operation of the column selection circuit and the operation of the non-volatile storage operation circuit need to be isolated from each other to avoid affecting the reliability of the data backup. Therefore, it is necessary to control the column selection circuit to stop the data recovery operation, so as to isolate the data recovery operation and the operation of the non-volatile storage operation circuit.

[0166] FIG. 8 shows a flowchart of a data writing method of a storage device according to at least one embodiment of the present disclosure.

[0167] As shown in FIG. 8, in some embodiments of the present disclosure, the data writing method includes steps S500-S520 when data is written. The data writing method can be used in the storage device shown in FIG. 2 or FIG. 3A, for example.

[0168] Step S500: the error detection and correction circuit receives data input including K-bit information code.

[0169] For step S500, the input and output interface circuit receives data input including K-bit information code, which can be input from an external device or data generated internally in the electronic device. Then the input and output interface circuit inputs the data to the error detection and correction circuit. In some embodiments, the input and output interface circuit or the error detection and correction circuit can check the received data to ensure the integrity of the data.

[0170] Step S510: the error detection and correction circuit encodes the data including K-bit information code to obtain R-bit check code data.

[0171] For step S510, the error detection and correction circuit encodes the received K-bit information code data to generate R-bit check code data. The encoding method of the error detection and correction circuit can refer to the related description above, which will not be repeated here. For example, after encoding, the R-bit check code data can be appended to the K-bit information code data to form new data including K-bit information code and R-bit check code.

[0172] Step S520: the SRAM operation circuit writes the data including K-bit information code and R-bit check code into the NVSRAM array through the column selection circuit.

[0173] For step S520, in some embodiments, the error correction circuit will send corresponding control signals to the SRAM operation circuit to complete the write operation of the data. The column selection circuit is used to select a specific column in the NVSRAM array to write data to the designated storage unit. The error correction circuit writes the data including K-bit information code and R-bit check code into the NVSRAM array through the SRAM operation circuit and the column selection circuit. This step can reliably store the data in the NVSRAM array for subsequent reading, recovery and backup.

[0174] FIG. 9 shows a flowchart of a data reading method of a storage device according to at least one embodiment of the present disclosure.

[0175] As shown in FIG. 9, in some embodiments of the present disclosure, the data reading method includes steps S600-S650 when reading and writing data. The data reading method can be used in the storage device as shown in FIG. 2 or FIG. 3A, for example.

[0176] Step S600: The SRAM operation circuit reads target data from the NVSRAM array and inputs the target data into the error correction circuit.

[0177] For step S600, when data needs to be read from the NVSRAM array, the SRAM operation circuit receives a corresponding read request. For example, after a data recovery operation, the SRAM operation circuit reads out the data (i.e., target data) stored in a specific column of the NVSRAM array through the column selection circuit (i.e., target data), and the target data includes K-bit information code and R-bit check code. The target data read out by the SRAM operation circuit is input into the error correction circuit for subsequent decoding and error detection operations.

[0178] Step S610: The error correction circuit decodes the target data.

[0179] For step S610, the error correction circuit decodes the target data input from the SRAM operation circuit. In some embodiments, the decoding process can be the inverse operation of the encoding process, and the R-bit check code data is separated from the data according to a specific decoding algorithm, and the K-bit information code data is checked according to the check code. The encoding and decoding methods of the error correction circuit can refer to the related description above, which will not be repeated here.

[0180] Step S620: The error correction circuit determines whether the decoding result is correct. If the decoding result is incorrect, step S630 is performed, and if the decoding result is correct, step S640 is performed.

[0181] For step S620, the error correction and detection circuit judges the decoding result to determine whether there is an error in the data. If there is an error in the decoding result, error correction operation needs to be performed; if there is no error in the decoding result, the data including the K-bit information code in the target data can be output through the input and output interface circuit.

[0182] Step S630: The error correction and detection circuit performs error correction coding on the target data to obtain K-bit information code data after error correction.

[0183] For step S630, if the error correction and detection circuit judges that there is an error in the decoding result, the error correction coding is performed on the target data to obtain K-bit information code data after error correction. The error correction coding method of the error correction and detection circuit on the target data can refer to the related description in the foregoing, which will not be described here again.

[0184] Step S640: Output the K-bit information code data through the input and output interface circuit.

[0185] For step S640, the error correction and detection circuit outputs the data including the K-bit information code obtained after error correction through the input and output interface circuit.

[0186] FIG. 10 shows a flow diagram of a data backup method of a storage device provided in at least one embodiment of the present disclosure.

[0187] As shown in FIG. 10, the data backup method includes steps S700-S750. The data backup method can be used in the storage device as shown in FIG. 2 or FIG. 3A, for example.

[0188] Step S700: Perform data read and write.

[0189] For step S700, in some embodiments of the present disclosure, step S700 can include steps S500-S520 shown in FIG. 8 and steps S600-S650 shown in FIG. 9. In the case of data writing, the SRAM operation circuit writes data into the SRAM storage subunit in the NVSRAM unit, which can be the data including the K-bit information code and the R-bit check code obtained after the error correction and detection circuit encodes the received data in step S510. In the case of data reading, the SRAM operation circuit reads the data stored in the SRAM storage subunit and outputs after decoding without error by the error correction and detection circuit.

[0190] Step S710: Judge whether data backup operation needs to be performed.

[0191] For step S710, in some embodiments of the present disclosure, the storage device determines whether the data backup operation is needed according to the received instruction. If the data backup operation is needed, step S720 is performed; otherwise, step S700 is continued to continue the data read / write operation. The data can be the aforementioned data including K-bit information code and R-bit check code.

[0192] Step S720: selecting I rows of NVSRAM cells.

[0193] For step S720, in some embodiments of the present disclosure, in the case that the storage device determines to perform the data backup operation, the word line driving circuit determines I rows of data in the NVSRAM cells according to the address information. I is an integer and 0

[0194] Step S730: simultaneously backing up the data in the SRAM storage sub-cells in the selected I rows of storage cells to the RRAM storage sub-cells.

[0195] For step S730, the non-volatile storage operation circuit performs parallel operation to simultaneously backup the data in the determined I rows of SRAM storage sub-cells to the RRAM storage sub-cells.

[0196] Step S740: determining whether the data backup is completed.

[0197] For step S740, the non-volatile storage operation circuit determines whether the data backup is completed. If the backup is not completed, step S750 is performed; if it is determined that the data backup is completed, the data backup operation is ended.

[0198] Step S750: increasing the row address of the SRAM storage sub-cells by I again. Then the data backup operation of steps S720-S740 is continued.

[0199] For step S750, the word line driving circuit updates the row address of the SRAM storage sub-cells and increases the row address by I again to continue the next data backup operation. The non-volatile storage operation circuit backs up the determined I rows of data in the SRAM storage sub-cells to the RRAM storage sub-cells, and exemplarily, the (I+1)th row to the 2Ith row of NVSRAM cells can be selected. Then the data backup operation of steps S720-S740 is continued until all the data to be backed up is backed up to the RRAM storage sub-cells.

[0200] FIG. 11 shows a flowchart of a data recovery method of a storage device according to at least one embodiment of the present disclosure.

[0201] As shown in FIG. 11, the data recovery method includes steps S800-S850. The data recovery method can be used in the storage device as shown in FIG. 2 or FIG. 3A, for example.

[0202] Step S800: Determine whether to perform a data recovery operation.

[0203] For step S800, in some embodiments of the present disclosure, the storage device determines whether to perform a data recovery operation according to a received instruction or a preset instruction. If it is determined that a data recovery operation is needed, step S810 is performed; if it is determined that no data recovery operation is needed, step S840 is performed directly.

[0204] Step S810: Select I rows of NVSRAM cells.

[0205] For step S810, the word line driving circuit determines I rows of data in the NVSRAM cells according to the address information. I is an integer and 0

[0206] Step S820: Simultaneously restore the data of the selected I rows of RRAM storage sub-cells to the SRAM storage sub-cells.

[0207] For step S820, this step can be performed by the column selection circuit, for example. For example, the column selection circuit can perform a parallel operation to simultaneously restore the data in the determined I rows of RRAM storage sub-cells to the SRAM storage sub-cells. Then, step S830 is performed.

[0208] Step S830: Determine whether the data recovery operation is completed.

[0209] For step S830, if the data recovery operation is not completed, step S850 is performed; if the data recovery operation is completed, step S840 is performed.

[0210] Step S840: The SRAM operation circuit performs data read / write operations on the data in the SRAM storage sub-cells.

[0211] After the data recovery operation is completed, the SRAM operation circuit can read the data in the SRAM storage sub-cells, for example, and input the read data to the error detection and correction circuit for subsequent processing and use.

[0212] In some embodiments of the present disclosure, after step S840, steps S610-S650 as shown in FIG. 9 can be performed. For step S840, the SRAM operation circuit reading the data in the SRAM storage sub-cells is equivalent to the SRAM operation circuit reading the target data from the NVSRAM array and inputting the target data to the error detection and correction circuit in step S600.

[0213] Step S850: Increase the row address in the RRAM storage subunit by I rows, and then perform the operations of steps S810-S830.

[0214] For step S850, in the case where the data recovery operation is not completed, update the row address of the data in the RRAM storage subunit that needs to be recovered, and increase the row address by I rows, so as to continue the next step of data recovery operation. For example, the NVSRAM unit of the (I+1)th row to the 2Ith row can be selected. Then, the data recovery operation of steps S810-S830 will be continued until all the data that needs to be recovered is recovered into the SRAM storage subunit.

[0215] Some embodiments of the present disclosure also provide a storage device, an electronic device comprising the storage device, and a storage device control method.

[0216] The storage device comprises an NVSRAM array, an SRAM operation circuit, a non-volatile storage operation circuit, an error detection and correction circuit, an input / output interface circuit, and a column selection circuit. The error detection and correction circuit is coupled to the SRAM operation circuit, the SRAM operation circuit is coupled to the input / output interface circuit, the SRAM operation circuit is coupled to the column selection circuit, the column selection circuit is coupled to the NVSRAM array, and the non-volatile storage operation circuit is coupled to the NVSRAM array.

[0217] The NVSRAM array comprises a plurality of NVSRAM units arranged in an array, and each NVSRAM unit comprises an SRAM storage subunit and a non-volatile storage subunit, and the non-volatile storage subunit is configured to back up the data stored in the SRAM storage subunit.

[0218] The non-volatile storage operation circuit is configured to perform a data backup operation on the SRAM storage subunit data in the selected NVSRAM unit in the NVSRAM array; the column selection circuit is configured to select a target unit column in the NVSRAM array that needs to be operated, and perform a data recovery operation on the non-volatile storage subunit data in the target unit column; the SRAM operation circuit is configured to perform a data read / write operation on the SRAM storage subunit data in the target unit column; the input / output interface circuit is configured to provide the received input data to the SRAM operation circuit and receive the output data to be output from the SRAM operation circuit; the error detection and correction circuit is configured to encode and decode the target data and determine whether the target data has an error and correct the error; and the column selection circuit is further configured to isolate the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit, and isolate the data read / write operation and the data recovery operation.

[0219] The storage device can improve the reliability of data reading and writing, backup, and recovery by using a non-volatile storage subunit to backup the data of the SRAM storage subunit, using an error detection and correction circuit to detect and correct erroneous storage data, and using a column selection circuit to isolate the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit.

[0220] FIG. 12 shows a schematic block diagram of a storage device according to at least one embodiment of the present disclosure.

[0221] In some embodiments of the present disclosure, as shown in FIG. 12, the storage device 2000 includes an NVSRAM array 220, an SRAM operation circuit 200, a non-volatile storage operation circuit 230, an error detection and correction circuit 260, an input-output interface circuit 250, and a column selection circuit 210.

[0222] The error detection and correction circuit 260 is coupled to the SRAM operation circuit 200, the input-output interface circuit 250 is coupled to the SRAM operation circuit 200, and the SRAM operation circuit 200 is coupled to the column selection circuit 210, so that the SRAM operation circuit 200 is located between the input-output interface circuit 250 and the column selection circuit 210 to transmit data. The column selection circuit 210 is coupled to the NVSRAM array 220, and the non-volatile storage operation circuit 230 is coupled to the NVSRAM array 220.

[0223] In the present disclosure, “coupled” is used to describe the signal connection between objects, and when the coupling between the objects is established, signal transmission can be performed, and when the coupling between the objects is disconnected, signal connection cannot be performed. The coupling can be achieved by, for example, electrical connection. For example, in embodiments of the present disclosure, “coupled” can include two or more electronic elements or circuits connected together in some way, so that signals are transmitted between them. For example, two storage subunits can be directly connected, and information transmission can be achieved through signal or energy transmission, or two storage subunits can be connected through other circuit elements, such as resistors, capacitors, switches, optoelectronic elements, or transmission line networks, to achieve signal transmission.

[0224] The NVSRAM array 220 includes a plurality of NVSRAM units 221 arranged in an array, and each NVSRAM unit 221 includes an SRAM storage subunit 222 and a nonvolatile storage subunit 231 configured to back up data stored in the SRAM storage subunit 222. The plurality of NVSRAM units 221 form an array including a plurality of rows and a plurality of columns. For example, the plurality of NVSRAM units 221 can form a storage array including M rows and N columns, where M and N are integers and 1≤M, 1≤N. The NVSRAM unit 221 may, for example, take the form shown in FIG. 1, but embodiments of the present disclosure are not limited to this specific form.

[0225] The NVSRAM unit 221 of the NVSRAM array 220 combines the characteristics of the SRAM storage subunit and the nonvolatile storage subunit. The SRAM storage subunit 222 can be configured to store data and can quickly read and write data. The nonvolatile storage subunit 231 is configured to back up data stored in the SRAM storage subunit 222 to prevent data loss in the SRAM storage subunit 222 in the event of a power failure or system crash.

[0226] For example, the nonvolatile storage subunit 231 can include an RRAM, a FeRAM (Ferroelectric Random Access Memory), an MRAM (Magnetic Random Access Memory), a PCM (Phase Change Memory), an EEPROM (Electrically Erasable Programmable Read-Only Memory), a PRAM, a flash memory, or the like. Depending on the type of nonvolatile storage subunit 231, the nonvolatile storage operation circuit 230 in embodiments of the present disclosure is adjusted accordingly, and the present disclosure is not limited in this regard. For example, when the nonvolatile storage subunit 231 includes an RRAM storage subunit, the nonvolatile storage operation circuit 230 includes an RRAM operation circuit.

[0227] The nonvolatile storage operation circuit 230 is configured to perform a data backup operation on the SRAM storage subunit 222 in a selected NVSRAM unit 221 in the NVSRAM array 220.

[0228] In some embodiments, the non-volatile storage operation circuit 230 can communicate with a plurality of SRAM storage sub-units 222, and the non-volatile storage operation circuit 230 can perform data backup operation on the data of the SRAM storage sub-units 222 as needed, such as when the electronic device detects that an application program has a failure or an abnormality, the non-volatile storage operation circuit 230 performs a data backup operation. For example, the non-volatile storage operation circuit 230 can also perform a data backup operation on the data in the SRAM storage sub-units 222 in response to a backup instruction, or perform a periodic data backup operation on the SRAM storage sub-units 222 based on a preset time, or perform a real-time data backup operation on the SRAM storage sub-units 222.

[0229] To improve the efficiency of data backup, the non-volatile storage operation circuit 230 can use a parallel processing method to simultaneously perform data backup operations on the data of a plurality of selected SRAM storage sub-units 222. For example, the non-volatile storage operation circuit 230 can simultaneously perform data backup operations on the data in a plurality of SRAM storage sub-units 222 in a selected row, or the non-volatile storage operation circuit 230 can simultaneously perform data backup operations on the data of a plurality of selected rows of SRAM storage sub-units 222, or the non-volatile storage operation circuit 230 can simultaneously perform data backup operations on the data of a plurality of rows and columns of SRAM storage sub-units 222.

[0230] To improve the reliability and stability of data backup, at least one embodiment of the present disclosure also adopts some safety design to improve the redundancy of the non-volatile storage operation circuit 230.

[0231] For example, in at least one example, the non-volatile storage operation circuit 230 can use an ECC (Error Checking and Correcting) mechanism, which can add additional check bits when data is backed up to the non-volatile storage sub-unit 231, so as to detect and correct errors when the data is read. The ECC mechanism can improve the reliability of the data and reduce the risk of data loss due to hardware failure or data damage.

[0232] For example, in at least one example, the non-volatile storage operation circuit 230 can also employ a CRC (Cyclic Redundancy Check) mechanism to calculate the CRC value of the data before and after the data backup operation to ensure the integrity of the data. If the CRC values do not match, the non-volatile storage operation circuit 230 can take appropriate measures to recover the data or perform error handling. Other embodiments of the present disclosure can also employ other data check and error correction mechanisms, including but not limited to, parity check, SED (Single-bit Error Detection), SEC (Single-bit Error Correction), DED (Double-bit Error Detection), or FED (Fatal Error Detection), etc., and embodiments of the present disclosure are not limited thereto.

[0233] In some embodiments, the SRAM operation circuit 200 is configured to perform data read / write operations on the SRAM storage sub-cells 222 in the object cell column. Here, the "object cell column" is used to refer to the column of storage cells that is the object of the operation, which can be any column in the plurality of storage arrays.

[0234] For example, the SRAM operation circuit 200 performs data read / write operations on the selected SRAM storage sub-cells 222 by receiving the corresponding read / write command. For example, when the storage device 2000 needs to perform data read / write operations, the SRAM operation circuit 200 performs data read / write operations, the SRAM operation circuit 200 reads the data in the SRAM storage sub-cells 222 and inputs the data into the input / output interface circuit 250, or the SRAM operation circuit 200 receives the data provided by the input / output interface circuit 250 and writes the data into the SRAM storage sub-cells 222.

[0235] In some embodiments, the column selection circuit 210 is configured to select the object cell column in the NVSRAM array 220 that needs to be operated. For example, the column selection circuit 210 responds to the received address signal (here, the column selection signal) and converts it into an electrical signal, thereby selecting the corresponding object cell column in the NVSRAM array 220. For example, the column selection circuit 210 can select the corresponding object cell column in the NVSRAM array 220 according to the data recovery operation that needs to be performed or the data read / write operation that the SRAM operation circuit 200 needs to perform.

[0236] Here, the address signal includes a row selection signal and a column selection signal, and the row selection signal is used for addressing in the row direction by the word line driving circuit (to be described below), and the column selection signal is used for addressing in the column direction by the column selection circuit.

[0237] In some embodiments of the present disclosure, the column selection circuit 210 is configured to perform a data recovery operation on the non-volatile storage subcell data in the object cell column. Here, the "object cell column" is used to refer to the storage cell column that is the object of the operation, which can be any column in the plurality of storage arrays.

[0238] For example, the column selection circuit 210 performs a data recovery operation on the selected non-volatile storage subcell 231 by receiving a corresponding data recovery operation command. When the data in the non-volatile storage subcell 231 needs to be recovered to the SRAM storage subcell 222, the column selection circuit 210 performs a data recovery operation, and the column selection circuit 210 controls the non-volatile storage subcell 231 to recover the stored data to the SRAM storage subcell 222.

[0239] As previously described, during the data backup operation of the non-volatile storage operation circuit 230 or the data read / write operation of the SRAM operation circuit 200, or during the data recovery operation of the column selection circuit 210, the operations of the non-volatile storage operation circuit 230, the operations of the SRAM operation circuit 200, and the data recovery operation of the column selection circuit 210 can affect each other, thereby affecting the stability of the data backup operation, the data read / write operation, and the data recovery operation.

[0240] In at least some embodiments of the present disclosure, for example, the column selection circuit 210 is also configured to isolate the operation of the SRAM operation circuit 200 and the operation of the non-volatile storage operation circuit 230.

[0241] For example, independent column selection circuits 210 can be provided for the non-volatile storage operation circuit 230 and the SRAM operation circuit 200, respectively, to reduce the influence and interference between them. The independent column selection circuits 210 can have different circuit structures and elements to adapt to the characteristics and operation requirements of the non-volatile storage operation circuit 230 and the SRAM operation circuit 200.

[0242] In some embodiments, the non-volatile storage operation circuit 230 and the SRAM operation circuit 200 can also be power-isolated, such as being provided with independent power supplies, respectively. For example, the non-volatile storage operation circuit 230 and the SRAM operation circuit 200 can also be provided with voltage stabilizers to improve the stability of the power supply of the circuits. For example, the operation of the non-volatile storage operation circuit 230 and the operation of the SRAM operation circuit 200 can also be controlled by logic design, such as allowing only the operation of the non-volatile storage operation circuit 230 or only the operation of the SRAM operation circuit 200 in a specific case, and prohibiting the simultaneous operation of both.

[0243] In some embodiments, as shown in FIG. 12, the input-output interface circuit 250 is configured to provide the received input data to the SRAM operation circuit 200 and receive the output data to be output from the SRAM operation circuit 200; and the error detection and correction circuit 260 is configured to encode and decode the target data and determine whether an error occurs in the target data and correct the error.

[0244] For example, the column selection circuit 210 can also not perform the data recovery operation in the case that the SRAM operation circuit 200 performs the data read-write operation or the non-volatile storage operation circuit 230 performs the data backup operation, so as to isolate the data read-write operation, the data backup operation and the data recovery operation.

[0245] In at least some embodiments of the present disclosure, for example, the error detection and correction circuit 260 can encode the data by using the parity code, can add an extra data check bit in the data to make the number of 1s in the entire byte even (even parity) or odd (odd parity), and can check the check bit when receiving the data to be checked. For example, the error detection and correction circuit 260 can also encode the data by using the Hamming code, can divide the data into multiple groups and add a check bit in each group, so that the erroneous data in each group can be detected and corrected. For another example, the error detection and correction circuit 260 can also encode the data by using the cyclic redundancy check (CRC) method, can add a redundant check code in the data, and can regard the data as a binary polynomial, use a generator polynomial to perform a modulo 2 division operation on it, and the remainder obtained is the CRC check code.

[0246] In at least some embodiments of the present disclosure, for example, the error detection and correction circuit 260 can further include a data encoder and a data decoder. The data encoder can be configured to convert input data into a specific encoding format, and increase the redundancy information of the data, such as parity check code, Hamming code, cyclic redundancy check code, etc. The data decoder can be configured to decode the received encoded data into original data, and at the same time, it can also perform error detection on the data, such as through parity check, CRC check, etc.

[0247] In at least some embodiments of the present disclosure, for example, the error detection and correction circuit 260 can further include error detection and correction logic and control logic. The error detection and correction logic can perform error detection on the decoded data, and determine whether the error can be corrected according to the encoding method. For example, if parity check code is used, the logic will check the check bits and determine the error bits, and then correct the error bits. For some complex error conditions, multiple error corrections or degradation processes can be required. The control logic is used to control the entire process of data encoding, transmission, decoding and error correction, and can also be used to interact with other circuits, such as sending control signals to the column selection circuit 210 to control data transmission.

[0248] In at least some embodiments of the present disclosure, the error detection and correction circuit 260 can also be configured to encode the target data input from the SRAM operation circuit 200 to the error detection and correction circuit 260 in the case of data backup by the non-volatile storage operation circuit 230, and determine whether the target data read from the NVSRAM array 220 by the SRAM operation circuit 200 and input to the error detection and correction circuit 260 has an error and correct the error in the case of data recovery operation by the column selection circuit 210.

[0249] In one example of the present disclosure, for example, in the case of a data backup operation required according to system instructions, the SRAM operation circuit 200 reads data from the SRAM storage subunit 222 of the NVSRAM array and inputs the data to the error detection and correction circuit 260. After receiving the data from the SRAM operation circuit 200, the error detection and correction circuit 260 encodes the data. The encoding can be through the addition of additional check bits to increase the redundancy of the data, so that after the data is written to the NVSRAM array 220 again, even if part of the data is damaged or lost, the error can be detected and corrected through the check bits. The encoded data will be written to the SRAM operation circuit 200 by the error detection and correction circuit 260. The SRAM operation circuit 200 receives the encoded data from the error detection and correction circuit 260, and writes it to the NVSRAM array 220 through the column selection circuit.

[0250] Further, when encoding, the error detection and correction circuit 260 encodes the K-bit information code of the read target data to obtain an R-bit check code, and writes the R-bit check code into the SRAM storage sub-unit 222 of the NVSRAM array 220 through the SRAM operation circuit 200. Wherein, K and R are positive integers.

[0251] For example, when encoding, the error detection and correction circuit 260 obtains the K-bit information code of the target data, and then can process it through a specific encoding algorithm. The algorithm can generate an R-bit check code corresponding to the K-bit information code according to the content of the K-bit information code. The generated R-bit check code can be used to detect and correct errors that may occur in the data transmission or storage process. After generating the R-bit check code, the error detection and correction circuit 260 writes the data including the R-bit check code into the SRAM storage sub-unit 222 of the NVSRAM array 220 through the SRAM operation circuit 200. By storing the check code in the NVSRAM array 220, the data can be protected in the subsequent transmission or storage process. Even if data transmission errors or storage medium damage occur, the data can be recovered and corrected through the check code, thereby improving the reliability of the data and the stability of the system.

[0252] In one example of the present disclosure, for example, according to the system instruction, in the case where the storage device completes the data recovery operation, the column selection circuit can turn on the coupling between the SRAM operation circuit 200 and the NVSRAM array 220, and after the SRAM operation circuit 200 reads the already encoded data from the NVSRAM array 220 and inputs it to the error detection and correction circuit 260, the error detection and correction circuit 260 can determine whether the read data has errors and correct them. For example, the read data and the expected data can be compared. If an error is found, the error detection and correction circuit 260 will use the check bits added in the encoding process to correct the error. For example, if one bit of the read data is wrong, the error detection and correction circuit 260 can detect this error using the check bits, and correct it using the correct value expected in the encoding process.

[0253] Further, the error correction and detection circuit 260 decodes the target data read from the NVSRAM array 220 by the SRAM operation circuit 200. In the decoding process, the error correction and detection circuit 260 decodes and detects errors of the K-bit information code and the R-bit check code of the target data read, and performs error correction in response to the occurrence of errors. The K-bit error-corrected information code is written into the NVSRAM array 220 by the SRAM operation circuit 200. For example, in the decoding process, the SRAM operation circuit 200 reads the target data including the K-bit information code and the R-bit check code from the NVSRAM array 220 and delivers it to the error correction and detection circuit 260. Then, the error correction and detection circuit 260 decodes and detects errors of the read data by using a specific decoding algorithm. In this process, the error correction and detection circuit 260 can check the integrity of the data and detect whether there is an error by using the check code. If an error is found in the decoding process, the error correction and detection circuit 260 can start an error correction mechanism. The error correction and detection circuit 260 can then take corresponding error correction measures according to the type and degree of the error. For example, the error correction and detection circuit 260 can write the K-bit error-corrected information code into the SRAM storage subunit 222 of the NVSRAM array 220 by the SRAM operation circuit 200 to replace the original error data. For example, the error correction and detection circuit 260 can also output the K-bit error-corrected information code from the input and output interface circuit 250 by the SRAM operation circuit 200 for subsequent use. Not only the accuracy of the data can be improved, but also the security and reliability of the stored data can be improved.

[0254] In one example of the present disclosure, for example, in the case of the data backup operation performed by the non-volatile storage operation circuit 230, the error correction and detection circuit 260 encodes the data including the K-bit information code input from the SRAM operation circuit 200 into the error correction and detection circuit 260 to obtain the corresponding R-bit check code data. Then, the error correction and detection circuit 260 writes the encoded data including the R-bit check code into the SRAM operation circuit 200. The SRAM operation circuit 200 writes the data including the R-bit check code into the NVSRAM array 220 by the column selection circuit 210. In the case of the data recovery operation performed by the column selection circuit 210, the error correction and detection circuit 260 decodes the data including the K-bit information code and the R-bit check code read from the NVSRAM array 220 by the SRAM operation circuit 200 and input into the error correction and detection circuit 260, and determines whether the decoding result has errors. If there is an error, the error correction and detection circuit 260 performs error correction. Then, the error correction and detection circuit 260 can output the K-bit error-corrected information code from the input and output interface circuit 250 by the SRAM operation circuit 200 for subsequent use.

[0255] For example, in some embodiments of the present disclosure, the storage device 2000 can perform error correction operations when performing data backup operations or when performing data recovery operations, and can not perform error correction operations in the case of data read / write operations, which can improve the speed of data read / write.

[0256] The above describes a basic error correction and storage operation process of an embodiment of the present disclosure. In different embodiments, the error correction circuit 260 can use different encoding and decoding algorithms, such as using different check methods such as parity check, CRC check, etc., and the present disclosure is not limited thereto. In addition, the process of data writing and reading can also be different due to the specific hardware and interface design.

[0257] In at least some embodiments of the present disclosure, in the case of data read / write operations of the SRAM operation circuit 200, the column selection circuit 210 can be configured to couple the SRAM operation circuit 200 and the NVSRAM array 220, and accordingly, the non-volatile storage operation circuit 230 can be configured to disconnect the coupling with the NVSRAM array 220.

[0258] In some embodiments, in the case of data backup operations of the non-volatile storage operation circuit 230, the column selection circuit 210 can also be configured to disconnect the coupling of the SRAM operation circuit 200 and the NVSRAM array 220, and the non-volatile storage operation circuit 230 can also be configured to couple with the NVSRAM array 220.

[0259] In some embodiments, in the case of data recovery operations of the column selection circuit 210, the column selection circuit 210 can be configured to disconnect the coupling of the SRAM operation circuit 200 and the NVSRAM array 220, and the non-volatile storage operation circuit 230 can be configured to disconnect the coupling with the NVSRAM array 220.

[0260] For example, in the case where the SRAM operation circuit 200 needs to perform data read / write operations, the column selection circuit 210 couples the SRAM operation circuit 200 and the NVSRAM array 220, and the SRAM operation circuit 200 can perform data read / write operations on the SRAM storage subunit 222 in the NVSRAM array 220 to realize fast data read / write transmission, and the column selection circuit 210 is configured to stop performing data recovery operations. At the same time, since the coupling of the non-volatile storage operation circuit 230 and the NVSRAM array 220 is disconnected, the column selection circuit 210 stops performing data recovery operations, and therefore will not affect the read / write operations of the SRAM operation circuit 200.

[0261] For example, in the case that the non-volatile storage operation circuit 230 needs to perform a data backup operation, the column selection circuit 210 disconnects the coupling of the SRAM operation circuit 200 and the NVSRAM array 220, and in addition, the column selection circuit 210 stops performing a data recovery operation. While the non-volatile storage operation circuit 230 is coupled with the NVSRAM array 220, the non-volatile storage operation circuit 230 can perform a data backup operation, and the SRAM operation circuit 200 and the column selection circuit 210 do not affect the data backup operation.

[0262] For example, in the case that the SRAM operation circuit 200 performs a data read-write operation, the non-volatile storage operation circuit 230 is configured to disconnect the coupling with the NVSRAM array, stop the operation of the non-volatile storage operation circuit 230, and the column selection circuit 210 is configured to stop performing a data recovery operation.

[0263] For example, in the case that the non-volatile storage operation circuit 230 performs a data backup operation, the column selection circuit 210 is configured to disconnect the coupling of the SRAM operation circuit and the NVSRAM array, and stop the data recovery operation of the column selection circuit 210.

[0264] For example, in the case that the column selection circuit 210 performs a data recovery operation, the non-volatile storage operation circuit 230 can be configured to disconnect the coupling with the NVSRAM array 220 and stop the data backup operation; the column selection circuit 210 can also be configured to disconnect the coupling of the SRAM operation circuit 200 and the NVSRAM array 220 and stop the data read-write operation. In order to isolate the data backup operation, the data read-write operation and the data recovery operation.

[0265] For example, in at least some embodiments of the present disclosure, the column selection circuit 210 can further include a data recovery operation sub-circuit. FIG. 13A shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure. For example, as shown in FIG. 13A, the column selection circuit 210 further includes a data recovery operation sub-circuit 211.

[0266] For example, in some embodiments, the data recovery operation sub-circuit 211 can be configured to perform a data recovery operation on the non-volatile storage sub-unit 231 data in the object unit column. For example, the data recovery operation sub-circuit 211 can recover the data stored in the selected non-volatile storage sub-unit 231 to the SRAM storage sub-unit 222 upon receiving an instruction to perform a data recovery operation. For example, when performing a data recovery operation, the data recovery operation sub-circuit needs to ensure isolation from the operation of the SRAM operation circuit 200 and the non-volatile storage operation circuit 230, so as to prevent conflicts between the data read-write operation, the data backup operation and the data recovery operation, and improve the integrity of the data and the stability of the system.

[0267] For example, in some embodiments, the column selection circuit 210 can further include a switch array (not shown in the figure), through which the column selection circuit 210 can control the coupling between the SRAM operation circuit 200 and the NVSRAM array 220. For example, in the case of data read / write operation of the SRAM operation circuit 200, the column selection circuit 210 can be configured to turn on the switch coupling between the column selection circuit 210 and the NVSRAM array 220. For example, in the case of data backup operation of the non-volatile storage operation circuit 230 or data recovery operation of the column selection circuit, the column selection circuit 210 can also be configured to turn off the switch coupling between the column selection circuit 210 and the NVSRAM array 220. For example, the switch array of the column selection circuit 210 can also be turned on or off according to the timing logic controlling the operation of the non-volatile storage operation circuit 230, the operation of the column selection circuit 200 and the operation of the SRAM operation circuit 200, such as turning on the switch array of the column selection circuit 210 only when the SRAM operation circuit 200 is allowed to operate. Such as turning off the switch array of the column selection circuit 210 only when the non-volatile storage operation circuit 230 is allowed to operate.

[0268] In some embodiments of the present disclosure, as shown in FIG. 12, the NVSRAM array 220 can also be configured to be coupled with the word line driving circuit 240 to control the operation of the word line in the NVSRAM array 220.

[0269] The word line driving circuit 240 coupled with the NVSRAM array 220 is configured to control the circuit of the row (word line) where the storage unit is located in the NVSRAM array 220. In the NVSRAM array 220, for example, each storage unit is located at the intersection of the signal lines, that is, the horizontal signal line is the word line (Word Line), and the vertical signal line is the bit line (Bit Line). For example, the word line driving circuit 240 is responsible for controlling the switch connected with the word line to determine which row of storage units is selected for the required operation (correspondingly, the column selection circuit 210 is responsible for determining which column of storage units is selected for the required operation through the bit line).

[0270] For example, in some embodiments, the word line driving circuit 240 can include a decoder and a selector. The decoder is used to receive the address signal and decode it into the row address of the corresponding word line. The selector is responsible for selecting the corresponding word line to apply the driving signal according to the row address. When data is read or written to the selected storage unit, the word line driving circuit 240 can ensure the correct access to the selected storage unit while avoiding interference or misoperation to other unselected storage units.

[0271] As shown in FIG. 12, in some embodiments of the present disclosure, the array width of the NVSRAM array 220 can be configured as N, i.e., having N columns of storage units (e.g., the number of corresponding bit lines is 2N), for example, each row in the NVSRAM array 220 can include N NVSRAM units. The array of the NVSRAM array 220 can also be configured to have M rows of storage units, for example, each column in the NVSRAM array 220 can include M NVSRAM units. Each storage unit has a corresponding address for locating and accessing the storage unit. For example, each row in the NVSRAM array 220 includes N storage units, each storage unit is configured with X bit lines, then the number of bit lines of the NVSRAM storage array is X*N, in the case of transmission lines being bit line pairs, X can be configured as 2, then the number of bit lines of the NVSRAM storage array can be configured as 2N. For example, in at least one example, in the case of transmission lines being bit lines or bit line pairs (e.g., bit lines BL and BLN as shown in FIG. 1), the non-volatile storage operation circuit 230 can also be configured to be coupled with the NVSRAM array 220 through N or 2N bit lines. In some embodiments, for example, in the case of the column selection circuit 210 performing a data recovery operation, the column selection circuit 210 is also configured to set the voltage of the 2N bit lines to the same voltage value.

[0272] In some embodiments of the present disclosure, the N columns of storage units of the NVSRAM array 220 can include K columns of data columns and R columns of redundancy columns, the data columns store information codes, and the redundancy columns store additional check codes according to the encoding needs. The NVSRAM array 220 is configured in units of words (Word), each row of the NVSRAM array 220 stores P words of data, and the operation bit width of each word can be configured as W. The NVSRAM array 220 includes K columns of data columns to store information codes, and R columns of redundancy columns to store check codes. For example, the information codes can be configured in units of "words", and the check codes can be configured in units of "pages", and embodiments of the present disclosure are not limited thereto. For example, K=W*P, N, W, P, K, and R are positive integers, 1≤K

[0273] In embodiments of the present disclosure, the data columns and the redundancy columns can have various arrangements. For example, as shown in FIGS. 13B-13D, all the data columns can be arranged adjacent to each other, all the redundancy columns can be arranged adjacent to each other, or the data columns can be grouped and the redundancy columns can be grouped, and then the data column groups and the redundancy column groups can be arranged alternately, for example, K data columns and R redundancy columns can be arranged as a combination, and the NVSRAM array can include N columns of the combination; or the NVSRAM array can include multiple groups of K data columns and R data columns; or the NVSRAM array can include multiple groups of K data bits and R redundancy bits, for example, the K data bits can include multiple rows of information code data, and the R redundancy bits can include multiple rows of check code data. Embodiments of the present disclosure are not limited to the arrangement of the data columns and the redundancy columns.

[0274] In some embodiments of the present disclosure, for example, the error correction circuit 260 can be configured to be coupled to the SRAM operation circuit 200 through K+R groups of transmission lines. The SRAM operation circuit can be configured to be coupled to the input / output interface circuit 250 through W groups of transmission lines. The SRAM operation circuit 200 can also be configured to be coupled to the column selection circuit 210 through W groups of transmission lines. The column selection circuit 210 is coupled to the NVSRAM array 220 through N groups of transmission lines. The non-volatile storage operation circuit 230 can be configured to be coupled to the NVSRAM array 220 through N groups of transmission lines. For example, in the case of the transmission lines being bit lines or bit line pairs (for example, the bit lines BL and BLN as shown in FIG. 1), the column selection circuit 210 can also be configured to be coupled to the NVSRAM array 220 through N bit lines or 2N bit lines. For example, in some embodiments, the storage device 2000 can be configured as W≤K+R≤N*M.

[0275] The error correction circuit 260 is coupled to the SRAM operation circuit 200 through K+R groups of transmission lines, and the encoded data including R check code bits are written into the SRAM operation circuit 200, or the data including K information code bits and R check code bits read from the NVSRAM array 220 by the SRAM circuit are written into the error correction circuit 260 through K+R groups of transmission lines. The SRAM operation circuit 200 is connected to the column selection circuit 210 through W groups of transmission lines, for locating and accessing a specific storage unit in the NVSRAM array 220 according to the address provided by the column selection circuit 210, writing data including R check code bits into the NVSRAM array 220, and reading data including K information code bits and R check code bits from the NVSRAM array 220.

[0276] In the storage device 2000 of at least one embodiment of the present disclosure, in the case that the SRAM operation circuit 200 performs data read / write operation, the error correction circuit 260 does not perform error correction on the data, i.e. in the process that the SRAM operation circuit 200 reads the data input by the input / output interface circuit 250 and writes the data into the NVSRAM array 220 through the column selection circuit 210, the error correction circuit 260 does not perform error correction on the data. In the case that the column selection circuit 210 performs data recovery operation, the error correction circuit 260 performs error correction function, which can improve the speed of data read / write and the reliability of data backup and data recovery. For example, the number and type of these transmission lines and other parameters can be flexibly adjusted according to the requirements and hardware conditions to optimize the performance and efficiency of the storage device 2000.

[0277] In some embodiments of the present disclosure, in the case that the non-volatile storage operation circuit 230 performs data backup operation, the word line driving circuit 240 can also be configured to select the data of the SRAM storage sub-unit 222 in the I rows of NVSRAM units 221 of the NVSRAM array 220 for data backup operation, where I is an integer and M≥I≥1.

[0278] For example, the word line driving circuit 240 can select the SRAM storage sub-unit 222 in the I rows of NVSRAM units 221 of the NVSRAM array 220 according to the received data backup operation instruction. For example, the word line driving circuit 240 can select the SRAM storage sub-unit 222 in the 1st to Ith rows of NVSRAM units 221, and the non-volatile storage operation circuit 230 can be configured to perform parallel data backup operation on the data of the SRAM storage sub-unit 222 in the 1st to Ith rows of NVSRAM units 221 selected by the word line driving circuit 240, and backup all the data of the selected I rows of SRAM storage sub-units 222 into the non-volatile storage sub-unit 231.

[0279] In some embodiments of the present disclosure, in the case that the column selection circuit 210 performs data recovery operation, the word line driving circuit 240 can also be configured to select the data of the non-volatile storage sub-unit 231 in the J rows of NVSRAM units 221 of the NVSRAM array 220 for data recovery operation, where J is an integer and M≥J≥1.

[0280] For example, the word line driving circuit 240 can select the non-volatile storage sub-cells 231 in the J rows of the NVSRAM cells 221 in the NVSRAM array 220 according to the received data recovery operation instruction. Illustratively, the word line driving circuit 240 can select the non-volatile storage sub-cells 231 in the 1st row to the Jth row of the NVSRAM cells 221, and the column selection circuit 210 can be configured to perform a parallel data recovery operation on the data of the non-volatile storage sub-cells 231 in the 1st row to the Jth row of the NVSRAM cells 221 selected by the word line driving circuit 240, and recover all the data of the selected J rows of the non-volatile storage sub-cells 231 into the SRAM storage sub-cells 222.

[0281] In some embodiments of the present disclosure, the SRAM operation circuit 200 is further configured to perform a data read / write operation on the data of the SRAM storage sub-cells 222 in the W NVSRAM cells 221 in the ith row of the selected NVSRAM array 220 in the case of performing the data read / write operation. Wherein, N≥W≥1, M≥i≥1.

[0282] For example, the operation bit width of the data read / write operation of the SRAM operation circuit 200 is W. Illustratively, the SRAM operation circuit 200 can perform a data read / write operation on the data of the SRAM storage sub-cells 222 in the W NVSRAM cells 221 in a certain row (the ith row) of the selected NVSRAM array 220 according to the received data read / write operation instruction.

[0283] In some embodiments of the present disclosure, the non-volatile storage operation circuit 230 is further configured to perform a data backup operation on the data of the SRAM storage sub-cells 222 in the NVSRAM cells 221 in the E rows and / or the F columns of the selected NVSRAM array 220 in the case of performing the data backup operation. Wherein, E, F are integers and M≥E≥1, N≥F≥1.

[0284] For example, the operation bit width of the data backup operation of the non-volatile storage operation circuit 230 is N*M.

[0285] For example, the non-volatile storage operation circuit 230 can perform a data backup operation on the data of the SRAM storage sub-cells 222 in the selected E rows or F columns of the NVSRAM cells 221 in the M rows and N columns of the NVSRAM cells 221 in the NVSRAM array 220 according to the received data backup operation instruction. Or, the non-volatile storage operation circuit 230 can perform a data backup operation on all the data of the SRAM storage sub-cells 222 in the F columns of the selected E rows of the NVSRAM cells 221 in the M rows and N columns of the NVSRAM cells 221 in the NVSRAM array 220.

[0286] In some embodiments of the present disclosure, the column selection circuit 210 is further configured to perform a data recovery operation on the data of the non-volatile storage sub-cells 231 in the G rows and / or H columns of the NVSRAM cells 221 of the selected NVSRAM array 220 in the case of performing the data recovery operation. Wherein G, H are integers and M≥G≥1, N≥H≥1.

[0287] For example, the operation bit width of the data recovery operation of the column selection circuit 210 is N*M.

[0288] For example, the column selection circuit 210 can perform a data recovery operation on the data of the non-volatile storage sub-cells 231 in the selected G rows or H columns of the NVSRAM cells 221 in the M rows and N columns of the NVSRAM cells 221 of the NVSRAM array 220 according to the received data recovery operation instruction. Alternatively, the non-volatile storage operation circuit 230 can perform a data recovery operation on all the data of the non-volatile storage sub-cells 231 in the selected G rows of the NVSRAM cells 221 in the M rows and N columns of the NVSRAM cells 221 of the NVSRAM array 220.

[0289] The control method of the storage device provided by at least one embodiment of the present disclosure includes controlling the error detection and correction circuit to encode and decode the target data and determine whether an error occurs in the target data and correct the error. The control method can be used in the storage device shown in FIG. 12, for example.

[0290] For example, the error detection and correction circuit receives the target data read from the SRAM storage sub-cells of the NVSRAM array input by the SRAM operation circuit and encodes or decodes the target data according to the received control instruction. The error detection and correction circuit can further input the encoded target data to the SRAM operation circuit to write into the SRAM storage sub-cells of the NVSRAM array, or determine whether an error occurs and correct the error by judging the decoded target data.

[0291] FIG. 14A shows a flowchart of a control method of a storage device provided by at least one embodiment of the present disclosure.

[0292] As shown in FIG. 14A, in some embodiments of the present disclosure, the control method of the storage device includes steps S910-S911. The control method can be used in the storage device shown in FIG. 12, for example.

[0293] Step S910: Determine that the non-volatile storage operation circuit performs a data backup operation.

[0294] Step S911: Encode the target data input by the error detection and correction circuit from the SRAM operation circuit.

[0295] For example, the error correction circuit encodes the target data read from the SRAM storage subunit of the NVSRAM array and input to the error correction circuit in response to an instruction of the non-volatile storage operation circuit to perform a data backup operation. Alternatively, the non-volatile storage operation circuit to perform a data backup operation and the error correction circuit to encode the target data can be performed simultaneously, or the data backup can be performed first, or the target data can be encoded first, or the encoded target data can be backed up first, and the present disclosure is not limited in this regard.

[0296] FIG. 14B shows a flowchart of another method of controlling a storage device according to at least one embodiment of the present disclosure.

[0297] As shown in FIG. 14B, in some embodiments of the present disclosure, the method of controlling a storage device includes steps S920-S921. The method of controlling a storage device can be used in the storage device shown in FIG. 12, for example.

[0298] Step S920: Determine whether the column selection circuit completes the data recovery operation.

[0299] Step S921: Determine whether the target data read from the SRAM storage subunit of the NVSRAM array by the SRAM operation circuit and input to the error correction circuit is erroneous and corrected.

[0300] For example, the error correction circuit decodes the target data read from the SRAM storage subunit of the NVSRAM array by the SRAM operation circuit and input to the error correction circuit in response to an instruction of the column selection circuit to complete the data recovery operation, and determines whether the decoded result is erroneous, and corrects the error if any.

[0301] The method of encoding, decoding and correcting data by the error correction circuit can refer to the related description above, which will not be repeated here.

[0302] FIG. 15 shows a flowchart of another method of controlling a storage device according to at least one embodiment of the present disclosure.

[0303] In some embodiments of the present disclosure, step S911 of the method of controlling a storage device shown in FIG. 14A can further include steps S1010-S1011 shown in FIG. 15.

[0304] Step S1010: When encoding, encode the K-bit information code of the read target data to obtain an R-bit check code.

[0305] For step S1010, the error detection and correction circuit encodes the K-bit information code data of the target data received to generate R-bit check code data. The encoding method of the error detection and correction circuit can refer to the related description above, which will not be repeated here. For example, after encoding, the R-bit check code data can be appended to the K-bit information code data to form data including K-bit information code and R-bit check code.

[0306] Step S1011: write the R-bit check code into the NVSRAM array through the SRAM operation circuit.

[0307] For step S1011, for example, the error detection and correction circuit sends a corresponding control signal to the SRAM operation circuit, and the SRAM operation circuit can write the data including the R-bit check code into the SRAM storage subunit of the NVSRAM array through the column selection circuit. The column selection circuit can be used to select a specific column in the NVSRAM array to write data into the designated storage unit. This step can reliably store data in the SRAM storage subunit of the NVSRAM array for subsequent recovery or backup operations.

[0308] FIG. 16 shows a flowchart of another control method of a storage device provided by at least one embodiment of the present disclosure.

[0309] In some embodiments of the present disclosure, step S921 in the control method of the storage device shown in FIG. 14B can further include steps S1020-S1022 shown in FIG. 16.

[0310] Step S1020: when decoding, decode and detect errors of the K-bit information code and the R-bit check code of the target data read.

[0311] Step S1021: determine whether the decoding result has an error.

[0312] Step S1022: in response to an error, perform error correction, and write the K-bit error-corrected information code into the NVSRAM array through the SRAM operation circuit. Wherein K and R are positive integers.

[0313] For step S1020, for example, in response to the instruction of the data recovery operation of the column selection circuit, the SRAM operation circuit selects the data (i.e. target data) stored in a specific column of the SRAM storage subunit of the NVSRAM array through the column selection circuit, and the SRAM operation circuit reads out the target data from the NVSRAM array. The read-out target data is input to the error correction circuit by the SRAM operation circuit, so as to perform subsequent decoding and error detection operations. The error correction circuit decodes the target data including K-bit information code and R-bit check code read from the SRAM storage subunit of the NVSRAM array input by the SRAM operation circuit. In some embodiments, the decoding process can be the inverse operation of the encoding process, and the R-bit check code data is separated from the data according to a specific decoding algorithm, and the K-bit information code data is checked according to the check code. Subsequently, the error correction circuit performs step S1021 to determine whether the decoding result has an error, and if there is an error, step S1022 is started to correct the error, and the K-bit corrected information code is written into the SRAM storage subunit of the NVSRAM array through the SRAM operation circuit to replace the error data. Alternatively, the K-bit corrected information code can also be output from the input / output interface circuit through the SRAM operation circuit for subsequent use. If there is no error, the target data is input to the input / output interface circuit through the SRAM operation circuit for data output. The input / output interface circuit can send the target data to the corresponding external device or other circuit in the electronic device for subsequent operation. The method of encoding, decoding and error correction of the error correction circuit can refer to the related description above, which will not be repeated here.

[0314] FIG. 17 shows a flowchart of another control method of a storage device according to at least one embodiment of the present disclosure.

[0315] As shown in FIG. 17, the method can include steps S1100-S1120.

[0316] Step S1100: determining that the SRAM operation circuit performs data read / write operation.

[0317] Step S1110: disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array.

[0318] Step S1120: controlling the column selection circuit to couple the SRAM operation circuit and the NVSRAM array.

[0319] In the case of determining that the SRAM operation circuit performs the data read / write operation, the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit need to be isolated from each other to avoid affecting the reliability of the data read / write operation. Therefore, the coupling between the non-volatile storage operation circuit and the NVSRAM array needs to be disconnected, and the coupling between the SRAM operation circuit and the NVSRAM array needs to be connected by the column selection circuit to isolate the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit.

[0320] For step S1110, in one example, for example, the non-volatile storage operation circuit stops the operation of the non-volatile storage operation circuit according to the received instruction that the SRAM operation circuit performs the data read / write operation, and disconnects the coupling between the non-volatile storage operation circuit and the NVSRAM array.

[0321] For step S1120, in one example, for example, in the case where the column selection circuit includes a switch array, step S1120 further includes step S1121 (not shown in the figure). Step S1021: control the column selection circuit to turn on the switch array coupled between the column selection circuit and the NVSRAM array. The method of isolating the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit can refer to the related description above, which will not be described here.

[0322] In some embodiments, the method shown in FIG. 17 can further include step S1130 (not shown in the figure). Step S1130: control the column selection circuit to stop the data recovery operation.

[0323] In the case of determining that the SRAM operation circuit performs the data read / write operation, the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit need to be isolated from each other to avoid affecting the reliability of the data read / write operation. Therefore, the coupling between the non-volatile storage operation circuit and the NVSRAM array needs to be disconnected, and the coupling between the SRAM operation circuit and the NVSRAM array needs to be connected by the column selection circuit to isolate the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit.

[0324] FIG. 18 shows a flowchart of another control method of a storage device provided by at least one embodiment of the present disclosure. As shown in FIG. 18, the control method can include steps S1150-S1170.

[0325] Step S1150: determine that the column selection circuit performs the data recovery operation.

[0326] Step S1160: disconnect the coupling between the non-volatile storage operation circuit and the NVSRAM array.

[0327] Step S1170: control the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array.

[0328] In the case of determining the data recovery operation of the column selection circuit, the data recovery operation of the column selection circuit and the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit are required to be isolated from each other so as not to affect the reliability of the data recovery. Therefore, the coupling between the non-volatile storage operation circuit and the NVSRAM array needs to be disconnected, and the column selection circuit needs to be controlled to disconnect the coupling between the SRAM operation circuit and the NVSRAM array, so as to isolate the column selection circuit, the non-volatile storage operation circuit and the SRAM operation circuit from each other.

[0329] FIG. 19 shows a flowchart of another control method of a storage device according to at least one embodiment of the present disclosure.

[0330] As shown in FIG. 19, the control method can include steps S1200-S1220.

[0331] Step S1200: determining that the non-volatile storage operation circuit performs data backup.

[0332] Step S1210: connecting the coupling between the non-volatile storage operation circuit and the NVSRAM array.

[0333] Step S1220: controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array.

[0334] In the case of determining that the non-volatile storage operation circuit performs data backup, the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit need to be isolated from each other so as not to affect the reliability of the data backup. Therefore, the coupling between the non-volatile storage operation circuit and the NVSRAM array needs to be connected, and the column selection circuit needs to be controlled to disconnect the coupling between the SRAM operation circuit and the NVSRAM array, so as to isolate the non-volatile storage operation circuit and the SRAM operation circuit from each other.

[0335] For step S1220, in one example, for example, the column selection circuit stops the operation of the column selection circuit according to the received instruction that the non-volatile storage operation circuit performs data backup. For another example, in the case that the column selection circuit further includes a switch array, step S1220 further includes step S1221 (not shown in the figure). Step S1221: controlling the column selection to disconnect the switch array coupling the column selection circuit and the NVSRAM array. The method of isolating the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit can refer to the related description above, which will not be described here again.

[0336] In some embodiments, the method shown in FIG. 19 can further include step S1230 (not shown in the figure). Step S1230: controlling the column selection circuit to stop the data recovery operation.

[0337] In the case of determining the data backup operation of the non-volatile storage operation circuit, the data recovery operation of the column selection circuit and the operation of the non-volatile storage operation circuit need to be isolated from each other to avoid affecting the reliability of the data backup. Therefore, the data recovery operation of the column selection circuit needs to be stopped to isolate the data recovery operation and the operation of the non-volatile storage operation circuit.

[0338] FIG. 20 shows a flowchart of a data backup method of a storage device according to at least one embodiment of the present disclosure.

[0339] As shown in FIG. 20, the data backup method includes steps S1300-S1391. The data backup method can be used in the storage device shown in FIG. 12 or FIG. 13A, for example.

[0340] Step S1300: data read / write is performed.

[0341] For step S1300, the SRAM operation circuit writes data into the NVSRAM array. The data can be received by the SRAM operation circuit from the input / output interface circuit, and the SRAM operation circuit writes the data into the SRAM storage subunit in the NVSRAM array through the column selection circuit.

[0342] Step S1310: it is determined whether a data backup operation is needed.

[0343] For step S1310, in some embodiments of the present disclosure, the storage device determines whether a data backup operation is needed according to the received instruction. If the data backup operation is needed, step S1320 is performed; otherwise, step S1300 is continued to write data into the SRAM storage subunit in the NVSRAM unit.

[0344] Step S1320: reading the i-th row data K-bit information code.

[0345] For step S1320, the SRAM operation circuit reads the i-th row data of the SRAM storage subunit in the NVSRAM array through the column selection circuit, the data including the K-bit information code, and inputs the data into the error correction circuit. I and K are integers and 0

[0346] Step S1330: encoding the K-bit information code data of the i-th row to obtain the R-bit check code.

[0347] For step S1330, the error correction circuit encodes the received K-bit information code of the i-th row data to obtain the R-bit check code.

[0348] Step S1340: writing the R-bit check code of the i-th row.

[0349] For step S1340, the ECC circuit writes the R-bit check code into the i-th row of data of the SRAM storage sub-unit of the NVSRAM array through the SRAM operation circuit, for the subsequent data backup operation. For example, in some embodiments, steps S1330-S1340 can correspond to steps S1010-S1011 shown in FIG. 15. The method of encoding data by the ECC circuit can refer to the related description above, which will not be repeated here. Then step S1350 is performed.

[0350] Step S1350: determining whether the encoding is completed.

[0351] For step S1350, it is determined whether the data to be backed up in the NVSRAM array is all encoded. If not, step S1391 is performed. If yes, step S1360 is performed.

[0352] Step S1391: increasing the row address by 1.

[0353] For step S1391, in the case that the data encoding operation is not completed, the row address of the data to be encoded in the SRAM storage sub-unit is updated, and the row address is increased by 1 row. Then the data encoding operation of steps S1320-S1350 will be continued until all the data to be encoded is encoded and written into the SRAM storage sub-unit.

[0354] Step S1360: selecting J rows of NVSRAM cells.

[0355] For step S1360, after the data is encoded by the ECC circuit, the data backup operation is performed. For example, the word line driving circuit determines the J rows of data in the NVSRAM cells according to the address information. J is an integer and 0

[0356] Step S1370: simultaneously performing data backup on all data (including data bits and check bits) in the SRAM storage sub-unit of the J rows of storage cells.

[0357] For step S1370, the non-volatile storage operation circuit performs parallel operation, and simultaneously performs backup operation on the data including K-bit information code and R-bit check code in all storage sub-units of the J rows of SRAM storage sub-units, and backs up the data to the RRAM storage sub-unit.

[0358] Step S1380: determining whether the data backup is completed.

[0359] For step S1380, the nonvolatile storage operation circuit determines whether the data backup is completed. If the backup is not completed, step S1390 is performed; if it is determined that the data backup is completed, the data backup operation is ended.

[0360] Step S1390: the row address is increased by J.

[0361] For step S1390, the word line driving circuit updates the row address of the SRAM storage subunit, and the row address is increased by J, so as to continue the next step of the data backup operation. For example, the nonvolatile storage operation circuit determines to backup the data of the (J+1)th row to the 2Jth row in the SRAM storage subunit to the RRAM storage subunit. Then, the data backup operation of steps S1360-S1380 is continued until all the data to be backed up is backed up to the RRAM storage subunit.

[0362] FIG. 21 shows a flowchart of a data recovery method of a storage device according to at least one embodiment of the present disclosure.

[0363] As shown in FIG. 21, the data recovery method includes steps S1400-S1493. The data recovery method can be used in the storage device shown in FIG. 12 or FIG. 13A, for example.

[0364] Step S1400: whether to perform data recovery.

[0365] For step S1400, it is determined whether the storage device performs data recovery. The determination of whether the storage device performs data recovery can be made according to actual needs, or an instruction to perform data recovery is received to determine to perform the data recovery operation. If it is determined to perform the data recovery operation, step S1410 is performed; if it is determined not to perform the data recovery operation, step S1491 is directly performed.

[0366] Step S1410: selecting I rows of NVSRAM units.

[0367] For step S1410, the word line driving circuit determines the I rows of data in the NVSRAM unit according to the address information. I is an integer and 0<I. For example, the first row to the Ith row of NVSRAM units are selected.

[0368] Step S1420: simultaneously performing data recovery on all storage units in the I rows.

[0369] For step S1420, this step can be performed by the column selection circuit, for example. For example, the column selection circuit performs parallel operation to simultaneously restore the I rows of data in the determined RRAM storage subunit to the SRAM storage subunit. Then, step S1430 is performed.

[0370] Step S1430: whether data recovery is completed.

[0371] For step S1430, it is determined whether the data recovery operation is completed, if yes, step S1440 is performed, if not, step S1493 is performed.

[0372] Step S1493: the row address is increased by I.

[0373] For step S1493, in the case that the data recovery operation is not completed, the row address of the data to be recovered in the RRAM storage subunit is increased by I again. For example, the word line driving circuit can determine the data of the (I+1)th row to the 2Ith row in the RRAM storage subunit according to the address information. Then, steps S1410-S1430 are continuously performed until all the data to be recovered is recovered.

[0374] Step S1440: reading the data of the jth row including K-bit information code and R-bit check code.

[0375] For step S1440, when the data recovery operation is completed, the SRAM operation circuit reads the data of the jth row including K-bit information code and R-bit check code in the SRAM storage subunit, and inputs the read data into the error correction circuit for subsequent processing and use. j is an integer and 0

[0376] Step S1450: decoding and error checking the read data of the jth row including K-bit information code and R-bit check code.

[0377] For step S1450, the error correction circuit decodes and error checks the data of the jth row including K-bit information code and R-bit check code input from the SRAM operation circuit. In some embodiments, the decoding process can be the inverse operation of the encoding process, and the R-bit check code data is separated from the data according to a specific decoding algorithm, and the K-bit information code data is checked according to the check code. The decoding method of the error correction circuit for data can refer to the related description in the foregoing, which will not be described here.

[0378] Step S1460: determining whether there is an error.

[0379] For step S1460, the error correction circuit determines the decoding result to determine whether there is an error in the data. If there is an error in the decoding result, an error correction operation needs to be performed, and step S1470 is performed; if there is no error in the decoding result, step S1490 is performed.

[0380] Step S1470: correcting the jth row data to obtain K-bit error-corrected information code.

[0381] For step S1470, if the error correction circuit judges that the decoding result has an error, the data is error correction coded. The error correction circuit corrects the data of the jth row to obtain K-bit error correction information code. The error correction coding method of the error correction circuit on the data can refer to the related description in the foregoing, which will not be described here.

[0382] Step S1480: the jth row writes the K-bit error correction information code.

[0383] For step S1480, the error correction circuit writes the K-bit error correction information code data into the SRAM storage subunit of the NVSRAM array through the SRAM operation circuit to replace the original error data.

[0384] Step S1490: judging whether the error correction is completed.

[0385] For step S1490, it is judged whether the error correction circuit completes the error correction operation, if yes, step S1491 is performed, if not, step S1492 is performed.

[0386] Step S1491: data reading and writing.

[0387] For step S1491, after the error correction circuit completes the error correction operation, the SRAM operation circuit reads the data after the error correction in the NVSRAM array through the column selection circuit, and inputs the data to the input and output interface circuit for subsequent processing.

[0388] Step S1492: the row address is increased by 1.

[0389] For step S1492, in the case where the error correction operation is not completed, the row address of the data in the SRAM storage subunit which needs to be error correction is updated, and the row address is increased by 1, then the SRAM operation circuit can read the data including K-bit information code and R-bit check code in the j+1th row in the SRAM storage subunit, and input the read data to the error correction circuit. Then continue to perform steps S1440-S1490 until all the data to be error correction is completed.

[0390] Some embodiments of the present disclosure also provide a storage device, an electronic device comprising the storage device, and a storage device control method.

[0391] The storage device comprises an NVSRAM array, an SRAM operation circuit, a non-volatile storage operation circuit, and a column selection circuit. The column selection circuit is coupled with the NVSRAM array, the SRAM operation circuit is coupled with the column selection circuit, and the non-volatile storage operation circuit is coupled with the NVSRAM array.

[0392] The NVSRAM array includes a plurality of NVSRAM units arranged in an array, and each NVSRAM unit includes an SRAM storage subunit and a nonvolatile storage subunit configured to back up data stored in the SRAM storage subunit.

[0393] The nonvolatile storage operation circuit is configured to perform a data backup operation on the SRAM storage subunit data in the selected NVSRAM unit in the NVSRAM array; the column selection circuit is configured to select a column of target units in the NVSRAM array that needs to be operated and perform a data recovery operation on the nonvolatile storage subunit data in the column of target units; the SRAM operation circuit is configured to perform a data read / write operation on the SRAM storage subunit in the column of target units; and the column selection circuit is further configured to isolate the operation of the SRAM operation circuit and the operation of the nonvolatile storage operation circuit, and to isolate the data read / write operation and the data recovery operation.

[0394] The storage device backs up the data of the SRAM storage subunit using the nonvolatile storage subunit, isolates the operation of the SRAM operation circuit and the operation of the nonvolatile storage operation circuit using the column selection circuit, and isolates the data read / write operation and the data recovery operation, thereby improving the reliability of data read / write, backup, and recovery.

[0395] FIG. 22 shows a schematic block diagram of a storage device according to at least one embodiment of the present disclosure.

[0396] In some embodiments of the present disclosure, as shown in FIG. 22, the storage device 3000 includes an NVSRAM array 320, an SRAM operation circuit 300, a nonvolatile storage operation circuit 330, and a column selection circuit 310.

[0397] The SRAM operation circuit 300 is coupled to the column selection circuit 310, the column selection circuit 310 is coupled to the NVSRAM array 320, and the nonvolatile storage operation circuit 330 is coupled to the NVSRAM array 320.

[0398] In the present disclosure, “coupled” is used to describe the signal connection between objects, and when the coupling between the described objects is established, signal transmission can be performed, and when the coupling between the described objects is disconnected, signal connection cannot be performed. The coupling can be achieved by, for example, electrical connection. For example, in embodiments of the present disclosure, “coupled” can include two or more electronic elements or circuits connected together in some way, so that signals are transmitted between them. For example, two storage subunits can be directly connected, and information transmission can be achieved through signal or energy transmission, or two storage subunits can be connected through other circuit elements, such as resistors, capacitors, switches, optoelectronic elements, etc., or transmission line networks, etc., to achieve signal transmission.

[0399] The NVSRAM array 320 includes a plurality of NVSRAM cells 321 arranged in an array, and each NVSRAM cell 321 includes an SRAM storage sub-cell 322 and a non-volatile storage sub-cell 331. The non-volatile storage sub-cell 331 is configured to back up data stored in the SRAM storage sub-cell 322. The array formed by the plurality of NVSRAM cells 321 includes multiple rows and multiple columns. For example, the plurality of NVSRAM cells 321 can form a storage array including M rows and N columns, where M and N are integers and 1≤M and 1≤N. The NVSRAM cells 321 can, for example, take the form shown in FIG. 1 , but the embodiments of the present disclosure are not limited to this specific form.

[0400] NVSRAM cells 321 of NVSRAM array 320 combine the characteristics of SRAM storage subcells and non-volatile storage subcells. SRAM storage subcells 322 can be configured to store data and quickly read and write data. Non-volatile storage subcells 331 are configured to back up the data stored in SRAM storage subcells 322 to prevent data loss in the SRAM storage subcells 322 in the event of a power outage or system crash.

[0401] For example, the non-volatile storage subunit 331 may include RRAM, FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), PCM (Phase Change Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), PRAM, flash memory, and other storage subunits. Corresponding to different types of non-volatile storage subunits 331, the non-volatile storage operation circuit 330 in the embodiment of the present disclosure is adjusted accordingly, and the present disclosure is not limited to this. For example, when the non-volatile storage subunit 331 includes an RRAM storage subunit, the non-volatile storage operation circuit 330 includes an RRAM operation circuit.

[0402] The nonvolatile storage operation circuit 330 is configured to perform a data backup operation on the data of the SRAM storage sub-cell 322 in the selected NVSRAM cell 321 in the NVSRAM array 320 .

[0403] In some embodiments, the non-volatile storage operation circuit 330 can communicate with multiple SRAM storage subunits 322. The non-volatile storage operation circuit 330 can perform data backup operations on the data in the SRAM storage subunits 322 as needed. For example, when the electronic device detects a failure or anomaly in an application, the non-volatile storage operation circuit 330 performs a data backup operation. For another example, the non-volatile storage operation circuit 330 can also perform a data backup operation on the data in the SRAM storage subunits 322 in response to a backup instruction, perform a periodic data backup operation on the SRAM storage subunits 322 based on a preset time, or perform a real-time data backup operation on the SRAM storage subunits 322.

[0404] To improve data backup efficiency, the non-volatile storage operation circuit 330 can employ a parallel processing method to simultaneously perform data backup operations on data in multiple selected SRAM storage subunits 322. For example, the non-volatile storage operation circuit 330 can simultaneously perform data backup operations on data in multiple SRAM storage subunits 322 in a selected row, or the non-volatile storage operation circuit 330 can simultaneously perform data backup operations on data in multiple selected rows of SRAM storage subunits 322, or the non-volatile storage operation circuit 330 can be selected to simultaneously perform data backup operations on data in multiple rows and columns of SRAM storage subunits 322.

[0405] In some embodiments of the present disclosure, the SRAM operation circuit 300 is configured to perform data read and write operations on the SRAM storage sub-unit 322 in the object cell column. Here, "object cell column" is used to refer to the storage cell column that is the object of operation, which can be any column in a plurality of storage arrays. For example, the SRAM operation circuit 300 performs data read and write operations on the selected SRAM storage sub-unit 322 by receiving corresponding read and write commands. Exemplarily, when the storage device 3000 needs to read and write data, the SRAM operation circuit 300 performs data read and write operations, the SRAM operation circuit 300 reads the data in the SRAM storage sub-unit 322, and inputs the data into the input-output interface circuit 350, or the SRAM operation circuit 300 receives data provided by the input-output interface circuit 350 and writes the data into the SRAM storage sub-unit 322.

[0406] In some embodiments, the column selection circuit 310 is configured to select a target cell column to be operated on in the NVSRAM array 320. For example, the column selection circuit 310 responds to a received address signal and converts it into an electrical signal, thereby selecting a corresponding target cell column in the NVSRAM array 320. For example, the column selection circuit 310 can select a corresponding target cell column in the NVSRAM array 320 based on the data read and write operations required by the SRAM operation circuit 300.

[0407] Here, the address signal includes a row selection signal and a column selection signal. The word line driver circuit (described below) uses the row selection signal to perform addressing in the row direction, and the column selection circuit uses the column selection signal to perform addressing in the column direction.

[0408] In some embodiments of the present disclosure, the column selection circuit 310 is configured to perform a data recovery operation on the non-volatile storage sub-cell data in the target cell column. Here, "target cell column" is used to refer to the storage cell column that is the target of the operation, which can be any column in multiple storage arrays.

[0409] For example, upon receiving a corresponding data recovery operation command, the column selection circuit 310 performs a data recovery operation on the selected non-volatile storage sub-unit 331. When the data in the non-volatile storage sub-unit 331 needs to be recovered to the SRAM storage sub-unit 322, the column selection circuit 310 performs the data recovery operation and controls the non-volatile storage sub-unit 331 to recover the stored data to the SRAM storage sub-unit 322.

[0410] As mentioned above, during the process of performing a data backup operation in the non-volatile storage operation circuit 330, or performing a data read / write operation in the SRAM operation circuit 300, or performing a data recovery operation in the column selection circuit 310, the operation of the non-volatile storage operation circuit 330, the operation of the SRAM operation circuit 300, and the data recovery operation of the column selection circuit 310 may affect each other, thereby affecting the stability of the data backup operation, the data read / write operation, and the data recovery operation.

[0411] In at least some embodiments of the present disclosure, for example, the column select circuit 310 is further configured to isolate the operation of the SRAM operation circuit 300 and the operation of the nonvolatile memory operation circuit 330 , and to isolate data read and write operations and data recovery operations.

[0412] For example, independent column selection circuits 310 may be provided for the non-volatile storage operation circuit 330 and the SRAM operation circuit 300 respectively to reduce interference between the two. The independent column selection circuits 310 may have different circuit structures and components to adapt to the characteristics and operation requirements of the non-volatile storage operation circuit 330 and the SRAM operation circuit 300.

[0413] In some embodiments, power supply isolation can be implemented for the non-volatile memory operation circuit 330 and the SRAM operation circuit 300. For example, independent power supplies can be provided for the non-volatile memory operation circuit 330 and the SRAM operation circuit 300. For example, voltage regulators can be added to the non-volatile memory operation circuit 330 and the SRAM operation circuit 300 to improve the stability of the circuit power supply. For example, logic design can be used to control the operation of the non-volatile memory operation circuit 330 and the operation of the SRAM operation circuit 300. For example, in specific circumstances, only the non-volatile memory operation circuit 330 or only the SRAM operation circuit 300 can be allowed to operate, and simultaneous operation of the two can be prohibited.

[0414] For example, the column selection circuit 310 may not perform a data recovery operation when the SRAM operation circuit 300 performs a data read / write operation or the non-volatile storage operation circuit 330 performs a data backup operation, thereby isolating the data read / write operation, the data backup operation, and the data recovery operation.

[0415] In some embodiments, when the SRAM operation circuit 300 performs data read and write operations, the column selection circuit 310 can be configured to connect the SRAM operation circuit 300 and the NVSRAM array 320, and accordingly, the non-volatile storage operation circuit 330 can be configured to disconnect the coupling with the NVSRAM array 320.

[0416] In some embodiments, when the non-volatile storage operation circuit 330 performs a data backup operation, the column selection circuit 310 can be configured to disconnect the SRAM operation circuit 300 from the NVSRAM array 320, and the non-volatile storage operation circuit 330 can be configured to connect the coupling with the NVSRAM array 320.

[0417] In some embodiments, when the column selection circuit 310 performs a data recovery operation, the column selection circuit 310 can be configured to disconnect the SRAM operation circuit 300 from the NVSRAM array 320 , and the non-volatile storage operation circuit 330 can be configured to disconnect from the NVSRAM array 320 .

[0418] For example, in the case that the SRAM operation circuit 300 needs to perform data read / write operation, the column selection circuit 310 couples the SRAM operation circuit 300 and the NVSRAM array 320, and then the SRAM operation circuit 300 can perform data read / write operation on the SRAM storage subunit 322 in the NVSRAM array 320 to realize fast data read / write transmission, and the column selection circuit 310 is configured to stop the data recovery operation. At the same time, since the coupling between the non-volatile storage operation circuit 330 and the NVSRAM array 320 is disconnected, the column selection circuit 310 stops the data recovery operation, and thus the read / write operation of the SRAM operation circuit 300 is not affected.

[0419] For example, in the case that the non-volatile storage operation circuit 330 needs to perform data backup operation, the column selection circuit 310 disconnects the coupling between the SRAM operation circuit 300 and the NVSRAM array 320, and in addition, the column selection circuit 310 stops the data recovery operation. While the non-volatile storage operation circuit 330 is coupled with the NVSRAM array 320, the non-volatile storage operation circuit 330 can perform data backup operation, and the SRAM operation circuit 300 and the column selection circuit 310 do not affect the data backup operation process.

[0420] For example, in the case that the SRAM operation circuit 300 performs data read / write operation, the non-volatile storage operation circuit 330 is configured to disconnect the coupling with the NVSRAM array and stop the operation of the non-volatile storage operation circuit 330, and the column selection circuit 310 is configured to stop the data recovery operation.

[0421] For example, in the case that the non-volatile storage operation circuit 330 performs data backup, the column selection circuit 310 can also be configured to disconnect the coupling between the SRAM operation circuit and the NVSRAM array and stop the data recovery operation of the column selection circuit 310.

[0422] For example, in the case that the column selection circuit 310 performs data recovery operation, the non-volatile storage operation circuit 330 can be configured to disconnect the coupling with the NVSRAM array 320 and stop the data backup operation; and the column selection circuit 310 can also be configured to disconnect the coupling between the SRAM operation circuit 300 and the NVSRAM array 320 and stop the data read / write operation. In order to isolate the data backup operation, the data read / write operation and the data recovery operation.

[0423] For example, in at least some embodiments of the present disclosure, the column selection circuit 310 can further include a data recovery operation sub-circuit. FIG. 23 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure. For example, as shown in FIG. 23, the column selection circuit 310 further includes a data recovery operation sub-circuit 311.

[0424] For example, in some embodiments, the data recovery operation sub-circuit 311 can be configured to perform a data recovery operation on the non-volatile storage sub-cells 331 data in the object unit column. For example, the data recovery operation sub-circuit 311 can recover the data stored in the selected non-volatile storage sub-cells 331 to the SRAM storage sub-cells 322 upon receiving an instruction to perform a data recovery operation. For example, when performing a data recovery operation, the data recovery operation sub-circuit 311 needs to ensure that the operation of the SRAM operation circuit 300 and the non-volatile storage operation circuit 330 is isolated to prevent conflicts between data read-write operations, data backup operations, and data recovery operations, thereby improving the integrity of the data and the stability of the system.

[0425] For example, in some embodiments, the column selection circuit 310 can further include a switch array (not shown in the figure), and the column selection circuit 310 can control the coupling between the SRAM operation circuit 300 and the NVSRAM array 320 through the switch array. For example, when the SRAM operation circuit 300 performs a data read-write operation, the column selection circuit 310 can be configured to turn on the switch that couples the column selection circuit 310 and the NVSRAM array 320. For example, when the non-volatile storage operation circuit 330 performs a data backup operation or the column selection circuit performs a data recovery operation, the column selection circuit 310 can be further configured to turn off the switch that couples the column selection circuit 310 and the NVSRAM array 320. For example, the switch array of the column selection circuit 310 can also be turned on or off according to the timing logic that controls the operation of the non-volatile storage operation circuit 330, the operation of the column selection circuit 300, and the operation of the SRAM operation circuit 300. For example, under a specific timing, the switch array of the column selection circuit 310 is turned on only when the SRAM operation circuit 300 is allowed to operate. For example, under a specific timing, the switch array of the column selection circuit 310 is turned off only when the non-volatile storage operation circuit 330 is allowed to operate.

[0426] In some embodiments of the present disclosure, as shown in FIG. 22, the NVSRAM array 320 can be further configured to be coupled with the word line driving circuit 340 to control the operation of the word line in the NVSRAM array 320.

[0427] The word line driver circuit 340 for the NVSRAM array 320 is configured to control the circuitry of the row (word line) in which the memory cells are located in the NVSRAM array 320. In the NVSRAM array 320, for example, each memory cell is located at the intersection of signal lines, i.e., the horizontal signal lines are word lines and the vertical signal lines are bit lines. For example, the word line driver circuit 340 is responsible for controlling the switches connected to the word lines to determine which row of memory cells is selected for the desired operation (correspondingly, the column selection circuit 310 is responsible for determining which column of memory cells is selected for the desired operation through the bit lines).

[0428] For example, in some embodiments, the word line driver circuit 340 can include a decoder and a selector. The decoder is configured to receive the address signal and decode it into the row address of the corresponding word line. The selector is responsible for selecting the corresponding word line according to the row address to apply the driving signal. When data is read or written to the selected memory cell, the word line driver circuit 340 can ensure the correct access to the selected memory cell while avoiding interference or misoperation to other unselected memory cells.

[0429] As described above, as shown in FIG. 22, in some embodiments of the present disclosure, the array width of the NVSRAM array 320 can be configured to N, i.e., having N columns of memory cells (or the number of bit lines is 2N), for example, each row in the NVSRAM array 320 can include N NVSRAM cells. The array of the NVSRAM array 320 can also be configured to have M rows of memory cells, for example, each column in the NVSRAM array 320 can include M NVSRAM cells. Each memory cell has a corresponding address for locating and accessing the memory cell. For example, each row in the NVSRAM array 320 includes N memory cells, each memory cell is configured with X bit lines, then the number of bit lines of the NVSRAM memory array is X*N, in the case of transmission lines being bit line pairs, X can be configured to 2, then the number of bit lines of the NVSRAM memory array can be configured to 2N.

[0430] In some embodiments, for example, the NVSRAM array 320 can be configured in units of words. The non-volatile storage operation circuit 330 can be configured to be coupled with the NVSRAM array 320 through N groups of transmission lines. For example, in at least one example, in the case that the transmission lines are bit lines or bit line pairs (for example, the bit lines BL and BLN as shown in FIG. 1), the non-volatile storage operation circuit 330 can also be configured to be coupled with the NVSRAM array 320 through N or 2N bit lines. In some embodiments, for example, in the case that the column selection circuit 310 performs a data recovery operation, the column selection circuit 310 is also configured to set the voltages of the 2N bit lines to the same voltage value.

[0431] In some embodiments, for example, the SRAM operation circuit 300 can be configured to be coupled with the column selection circuit 310 through W groups of transmission lines. The SRAM operation circuit 300 can also be configured to be coupled with the input / output interface circuit 350 through the W groups of transmission lines. The column selection circuit 310 is coupled with the NVSRAM array 320 through N groups of transmission lines. For example, in the case that the transmission lines are bit lines or bit line pairs (for example, the bit lines BL and BLN as shown in FIG. 1), the SRAM operation circuit 300 can be configured to be coupled with the column selection circuit 310 through W or 2W bit lines, and the column selection circuit 310 can be configured to be coupled with the NVSRAM array 320 through N or 2N bit lines. W and N are integers and N≥W≥1.

[0432] The SRAM operation circuit 300 is connected with the column selection circuit 310 through W groups of transmission lines, for locating and accessing a specific storage unit in the NVSRAM array 320 according to an address provided by the column selection circuit 310, writing data into the NVSRAM array 320, and reading data from the NVSRAM array 320.

[0433] In the storage device 3000 of at least one embodiment of the present disclosure, the number and type of these transmission lines and other parameters can be flexibly adjusted according to needs and hardware conditions, to optimize the performance and efficiency of the storage device 3000.

[0434] In some embodiments of the present disclosure, in the case that the non-volatile storage operation circuit 330 performs a data backup operation, the word line driving circuit 340 can also be configured to select the SRAM storage sub-unit 322 data in the I rows of NVSRAM units 321 of the NVSRAM array 320 for the data backup operation, where I is an integer and M≥I≥1.

[0435] For example, the word line driving circuit 340 can select the SRAM storage sub- units 322 in the I rows of NVSRAM units 321 in the NVSRAM array 320 according to the received data backup operation instruction. Illustratively, the word line driving circuit 340 can select the SRAM storage sub-units 322 in the 1st row to the Ith row of NVSRAM units 321, and the non-volatile storage operation circuit 330 can be configured to perform a parallel data backup operation on the data of the selected SRAM storage sub-units 322 in the 1st row to the Ith row of NVSRAM units 321 selected by the word line driving circuit 340, and backup all the data of the selected I rows of SRAM storage sub-units 322 to the non-volatile storage sub-units 331.

[0436] In some embodiments of the present disclosure, in the case of performing a data recovery operation by the column selection circuit 310, the word line driving circuit 340 can also be configured to select the data of the non-volatile storage sub-units 331 in the J rows of NVSRAM units 321 of the NVSRAM array 320 for the data recovery operation, where J is an integer and M≥J≥1.

[0437] For example, the word line driving circuit 340 can select the non-volatile storage sub-units 331 in the J rows of NVSRAM units 321 in the NVSRAM array 320 according to the received data recovery operation instruction. Illustratively, the word line driving circuit 340 can select the non-volatile storage sub-units 331 in the 1st row to the Jth row of NVSRAM units 321, and the column selection circuit 310 can be configured to perform a parallel data recovery operation on the data of the selected non-volatile storage sub-units 331 in the 1st row to the Jth row of NVSRAM units 321 selected by the word line driving circuit 340, and recover all the data of the selected J rows of non-volatile storage sub-units 331 to the SRAM storage sub-units 322.

[0438] In some embodiments of the present disclosure, the SRAM operation circuit 300 is also configured to perform a data read / write operation on the data of the selected SRAM storage sub-units 322 in the W NVSRAM units 321 in the ith row of the NVSRAM array 320 in the case of performing a data read / write operation. Wherein N≥W≥1, M≥i≥1.

[0439] For example, the operation bit width of the data read / write operation of the SRAM operation circuit 300 is W. Illustratively, the SRAM operation circuit 300 can perform a data read / write operation on the data of the SRAM storage sub-units 322 in the W NVSRAM units 321 in a certain row (the ith row) of the NVSRAM array 320 according to the received data read / write operation instruction.

[0440] In some embodiments of the present disclosure, the non-volatile storage operation circuit 330 is further configured to perform a data backup operation on the data of the SRAM storage sub-unit 322 in the NVSRAM cell 321 of the selected E row and / or F column of the NVSRAM array 320 in the case of performing the data backup operation. Wherein E, F are integers and M≥E≥1, N≥F≥1.

[0441] For example, the operation bit width of the data backup operation of the non-volatile storage operation circuit 330 is N*M.

[0442] For example, the non-volatile storage operation circuit 330 can perform a data backup operation on the data of the SRAM storage sub-unit 322 in the NVSRAM cell 321 of the selected E row or F column in the NVSRAM cell 321 including M rows and N columns in the NVSRAM array 320 according to the received data backup operation instruction. Or, the non-volatile storage operation circuit 330 can perform a data backup operation on all the data of the SRAM storage sub-unit 322 in the F column in the NVSRAM cell 321 of the selected E row in the NVSRAM array 320 including M rows and N columns of NVSRAM cells 321.

[0443] In some embodiments of the present disclosure, the column selection circuit 310 is further configured to perform a data recovery operation on the data of the non-volatile storage sub-unit 331 in the NVSRAM cell 321 of the selected G row and / or H column of the NVSRAM array 320 in the case of performing the data recovery operation. Wherein G, H are integers and M≥G≥1, N≥H≥1.

[0444] For example, the operation bit width of the data recovery operation of the column selection circuit 310 is N*M.

[0445] For example, the column selection circuit 310 can perform a data recovery operation on the data of the non-volatile storage sub-unit 331 in the NVSRAM cell 321 of the selected G row or H column in the NVSRAM array 320 including M rows and N columns according to the received data recovery operation instruction. Or, the non-volatile storage operation circuit 330 can perform a data recovery operation on all the data of the non-volatile storage sub-unit 331 in the H column in the NVSRAM cell 321 of the selected G row in the NVSRAM array 320 including M rows and N columns of NVSRAM cells 321.

[0446] In some embodiments of the present disclosure, for example, as shown in FIG. 22, the storage device further comprises an input-output interface circuit 350, the input-output interface 350 is coupled with the SRAM operation circuit 300, and the input-output interface 350 is configured to provide the received input data to the SRAM operation circuit 300 and receive the output data to be output from the SRAM operation circuit 300.

[0447] FIG. 24 shows a flowchart of a control method of a storage device according to at least one embodiment of the present disclosure. As shown in FIG. 24, the method can include steps S1500-S1520.

[0448] Step S1500: determining that the SRAM operation circuit performs data read-write operation.

[0449] Step S1510: disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array.

[0450] Step S1520: controlling the column selection circuit to couple the SRAM operation circuit and the NVSRAM array.

[0451] In the case of determining that the SRAM operation circuit performs data read-write operation, it is necessary to isolate the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit to avoid mutual influence and affect the reliability of data read-write. Therefore, it is necessary to disconnect the coupling between the non-volatile storage operation circuit and the NVSRAM array, and control the column selection circuit to couple the SRAM operation circuit and the NVSRAM array, so as to isolate the operation of the non-volatile storage operation circuit and the SRAM operation circuit.

[0452] For step S1510, in one example, for example, the non-volatile storage operation circuit stops the operation of the non-volatile storage operation circuit according to the received instruction that the SRAM operation circuit performs data read-write operation, and disconnects the coupling between the non-volatile storage operation circuit and the NVSRAM array.

[0453] For step S1520, in one example, for example, in the case where the column selection circuit includes a switch array, step S1520 further includes step S1521 (not shown in the figure). Step S1521: controlling the column selection circuit to turn on the switch array coupling the column selection circuit and the NVSRAM array. The method of isolating the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit can refer to the related description above, which will not be described here.

[0454] In some embodiments, the method shown in FIG. 24 can further include step S1530 (not shown in the figure). Step S1530: controlling the column selection circuit to stop data recovery operation.

[0455] In the case of determining that the SRAM operation circuit performs the data read / write operation, the data recovery operation of the column selection circuit and the operation of the SRAM operation circuit need to be isolated from each other to avoid affecting the reliability of the data read / write. Therefore, the data recovery operation of the column selection circuit needs to be stopped to isolate the data recovery operation and the operation of the SRAM operation circuit.

[0456] FIG. 25 shows a flowchart of another control method of a storage device according to at least one embodiment of the present disclosure. As shown in FIG. 25, the control method can include steps S1550-S1570.

[0457] Step S1550: determining that the column selection circuit performs the data recovery operation.

[0458] Step S1560: disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array.

[0459] Step S1570: controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array.

[0460] In the case of determining that the column selection circuit performs the data recovery operation, the data recovery operation of the column selection circuit, the operation of the SRAM operation circuit, and the operation of the non-volatile storage operation circuit need to be isolated from each other to avoid affecting the reliability of the data recovery. Therefore, the coupling between the non-volatile storage operation circuit and the NVSRAM array needs to be disconnected, and the column selection circuit needs to be controlled to disconnect the coupling between the SRAM operation circuit and the NVSRAM array to isolate the column selection circuit, the non-volatile storage operation circuit, and the SRAM operation circuit.

[0461] FIG. 26 shows a flowchart of another control method of a storage device according to at least one embodiment of the present disclosure. As shown in FIG. 26, the control method can include steps S1600-S1620.

[0462] Step S1600: determining that the non-volatile storage operation circuit performs the data backup operation.

[0463] Step S1610: connecting the coupling between the non-volatile storage operation circuit and the NVSRAM array.

[0464] Step S1620: controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array.

[0465] In the case of determining that the non-volatile storage operation circuit performs the data backup operation, the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit need to be isolated from each other to avoid affecting the reliability of the data backup. Therefore, the coupling between the non-volatile storage operation circuit and the NVSRAM array needs to be connected, and the coupling between the SRAM operation circuit and the NVSRAM array needs to be disconnected by the column selection circuit to isolate the operation of the non-volatile storage operation circuit and the SRAM operation circuit.

[0466] For step S1620, in one example, for example, the column selection circuit stops the operation of the column selection circuit according to the received instruction that the non-volatile storage operation circuit performs the data backup operation. For another example, in the case where the column selection circuit further includes a switch array, step S1620 further includes step S1621 (not shown in the figure). Step S1621: control the column selection circuit to disconnect the switch array coupled between the column selection circuit and the NVSRAM array. The method of isolating the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit can refer to the related description above, which will not be repeated here.

[0467] In some embodiments, the method shown in FIG. 26 can further include step S1630 (not shown in the figure). Step S1630: control the column selection circuit to stop the data recovery operation.

[0468] In the case of determining that the non-volatile storage operation circuit performs the data backup operation, the data recovery operation of the column selection circuit and the operation of the non-volatile storage operation circuit need to be isolated from each other to avoid affecting the reliability of the data backup. Therefore, the data recovery operation of the column selection circuit needs to be stopped to isolate the operation of the data recovery operation and the operation of the non-volatile storage operation circuit. For example, in the case where the column selection circuit includes a data recovery operation sub-circuit, the data recovery operation sub-circuit can also be controlled to stop performing the data recovery operation.

[0469] FIG. 27 shows a flowchart of a working method of a storage device according to at least one embodiment of the present disclosure. As shown in FIG. 27, in some embodiments of the present disclosure, the working method flow of the storage device includes steps S1700-S1760. The working method can be used in the storage device shown in FIG. 22 or FIG. 23, for example.

[0470] Step S1700: power on the storage device.

[0471] For step S1700, the storage device starts to power on, that is, the storage device is connected to the power supply and starts to work. The process can be controlled by a power supply circuit, which can provide the required voltage and current to the storage device to ensure its normal operation.

[0472] Step S1710: determine whether to perform data recovery.

[0473] For step S1710, the storage device can determine whether a data recovery operation is needed according to the received instruction or the state of the electronic device. If a data recovery is needed, step S1720 is performed; otherwise, step S1730 is performed.

[0474] Step S1720: Perform data recovery.

[0475] For step S1720, data previously backed up into the RRAM storage subunit is restored into the SRAM storage subunit, for example. This step can be controlled by the column selection circuit, for example. The column selection circuit can restore data in the selected RRAM storage subunit into the SRAM storage subunit in conjunction with the selection operation of the word line driving circuit, for example. In some embodiments, step S1720 further includes steps S1900-S1950 shown in FIG. 29 (to be described below), for example.

[0476] Step S1730: Perform data read / write.

[0477] For step S1730, this step can be controlled by the SRAM operation circuit. The SRAM operation circuit can read data in the SRAM storage subunit of the NVSRAM array in conjunction with the selection operation of the word line driving circuit, for example.

[0478] Step S1740: Determine whether to perform data backup.

[0479] For step S1740, the storage device determines whether a data backup operation is needed. If a data backup is needed, step S1750 is performed; otherwise, step S1760 is performed.

[0480] Step S1750: Perform data backup.

[0481] For step S1750, the storage device performs a data backup operation to backup data in the SRAM storage subunit into the RRAM storage subunit. This step can be controlled by the non-volatile storage operation circuit. The non-volatile storage operation circuit can backup data in the selected SRAM storage subunit into the RRAM storage subunit in conjunction with the selection operation of the word line driving circuit, for example. In some embodiments, step S1750 further includes steps S1800-S1850 shown in FIG. 28 (to be described below), for example.

[0482] Step S1760: Determine whether a power failure occurs.

[0483] For step S1760, the electronic device determines whether a power failure occurs in the storage device. If a power failure occurs, the operation of the storage device will be ended; otherwise, the process will return to step S1710 to continue determining whether the data recovery operation is needed. This process ensures that the storage device can continuously operate in a normal working state and protect the integrity of the data in the case of a power failure.

[0484] FIG. 28 shows a flowchart of a data backup method of a storage device according to at least one embodiment of the present disclosure.

[0485] As shown in FIG. 28, the data backup method includes steps S1800-S1850. The data backup method can be used in the storage device shown in FIG. 22 or FIG. 23, for example.

[0486] Step S1800: data read / write is performed.

[0487] For step S1800, in the case of data writing, the SRAM operation circuit writes data into the SRAM storage subunit in the NVSRAM unit. In the case of data reading, the SRAM operation circuit reads the data stored in the SRAM storage subunit (in combination with the selection operation of the word line driving circuit) and outputs it through the input / output interface circuit.

[0488] Step S1810: determine whether the data backup operation is needed.

[0489] For step S1810, for example, the storage device determines whether the data backup operation is needed according to the received instruction. If the data backup operation is needed, step S1820 is performed; otherwise, step S1800 is continued to continue the data read / write operation.

[0490] Step S1820: select I rows of NVSRAM units.

[0491] For step S1820, in some embodiments of the present disclosure, in the case where the storage device determines to perform the data backup operation, the word line driving circuit determines the data in I rows of NVSRAM units according to the address information. I is an integer and 0

[0492] Step S1830: simultaneously backup the data in the SRAM storage subunit in the selected I rows of storage units to the RRAM storage subunit.

[0493] In step S1830, the non-volatile storage operation circuit performs a parallel operation to simultaneously back up the data in the determined row 1 of the SRAM storage sub-cells to the RRAM storage sub-cells. Exemplarily, the non-volatile storage operation circuit backs up the data in the selected rows 1 to 1 of the SRAM storage sub-cells to the RRAM storage sub-cells.

[0494] Step S1840: Determine whether the data backup is completed.

[0495] In step S1840, the nonvolatile storage operation circuit determines whether the data backup is completed. If the backup is not completed, step S1850 is performed; if it is determined that the data backup is completed, the data backup operation is terminated.

[0496] Step S1850: Increase the row address of the SRAM storage subunit by 1. Then continue with the data backup operation of steps S1820-S1840.

[0497] In step S1850, the word line driver circuit updates the row address of the SRAM storage subunit, increasing the row address by one, so as to proceed to the next data backup operation. Exemplarily, the non-volatile storage operation circuit backs up the data in the determined SRAM storage subunits in rows (I+1) through (2I) to the RRAM storage subunit. The data backup operation of steps S1820-S1840 is then continued until all data to be backed up has been backed up to the RRAM storage subunit.

[0498] Figure 28 shows a flow chart of a method for recovering data from a storage device according to at least one embodiment of the present disclosure. As shown in Figure 28 , the method includes steps S1900 to S1950. The method can be used, for example, for a storage device such as that shown in Figure 22 or Figure 23 .

[0499] Step S1900: Determine whether to perform a data recovery operation.

[0500] Regarding step S1900, in some embodiments of the present disclosure, the storage device determines whether to perform a data recovery operation based on a received instruction or a preset instruction. If it is determined that a data recovery operation is required, step S1910 is performed; if it is determined that a data recovery operation is not required, step S1940 is directly performed.

[0501] Step S1910: Select I row of NVSRAM cells.

[0502] In step S1910, the word line driving circuit determines the data in row I of NVSRAM cells according to the address information. I is an integer and 0<I. Exemplarily, the word line driving circuit determines the data in rows 1 to 1 of NVSRAM cells according to the address information.

[0503] Step S1920: data in the selected I rows of RRAM storage sub-units are simultaneously recovered to the SRAM storage sub-units.

[0504] For step S1920, the column selection circuit operates in parallel to recover the data in the determined I rows of RRAM storage sub-units to the SRAM storage sub-units. Then, step S1930 is performed.

[0505] Step S1930: it is determined whether the data recovery operation is completed.

[0506] For step S1930, if the data recovery operation is not completed, step S1950 is performed; if the data recovery operation is completed, step S1940 is performed.

[0507] Step S1940: the SRAM operation circuit performs read and write operations on the data in the SRAM storage sub-units.

[0508] For step S1940, for example, after the data recovery operation is completed, the SRAM operation circuit can read the data in the SRAM storage sub-units and input the read data to the input and output interface circuit for subsequent processing and use.

[0509] Step S1950: the row address is increased by I rows.

[0510] For step S1950, in the case where the data recovery operation is not completed, the row address of the data in the RRAM storage sub-units that need to be recovered is updated, and the row address is increased by I rows, so as to continue the next data recovery operation. For example, the column selection circuit recovers the data in the determined (I+1) th row to the 2I th row of RRAM storage sub-units to the SRAM storage sub-units. Then, the data recovery operation of steps S1910-S1930 is continued until all the data that need to be recovered are recovered to the SRAM storage sub-units.

[0511] At least one embodiment of the present disclosure also provides an electronic device including the storage device described above. The electronic device can improve the reliability of data reading and writing, backup, and storage.

[0512] FIG. 30 shows a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure. As shown in FIG. 30, the electronic device 4000 includes a storage device, which can include the storage device 1000, the storage device 2000, or the storage device 3000 provided by the foregoing embodiments.

[0513] The electronic device 4000 in the embodiments of the present disclosure can include, but is not limited to, a mobile terminal such as a mobile phone, a notebook computer, a digital broadcast receiver, a PDA (Personal Digital Assistant), a PAD (Tablet Personal Computer), a PMP (Portable Multimedia Player), a car terminal (for example, a car navigation terminal), and the like, and a stationary terminal such as a digital TV, a desktop computer, and the like.

[0514] The specific functions and technical effects of the electronic device 4000 in the above embodiments of the present disclosure can refer to the description of the storage device 1000, the storage device 2000, and the storage device 3000 above, which will not be repeated here.

[0515] The following points need to be explained:

[0516] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the usual design.

[0517] (2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0518] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A storage device, comprising: The NVSRAM array, the SRAM operation circuit, the non-volatile storage operation circuit, the error detection and correction circuit, the input / output interface circuit, the column selection circuit, The error detection and correction circuit is coupled with the input / output interface circuit, the error detection and correction circuit is coupled with the SRAM operation circuit, the SRAM operation circuit is coupled with the column selection circuit, the column selection circuit is coupled with the NVSRAM array, and the non-volatile storage operation circuit is coupled with the NVSRAM array. The NVSRAM array includes a plurality of NVSRAM units arranged in an array, and each NVSRAM unit includes an SRAM storage subunit and a non-volatile storage subunit, and the non-volatile storage subunit is configured to back up data stored in the SRAM storage subunit. The non-volatile storage operation circuit is configured to perform data backup operation on the SRAM storage subunit data in the selected NVSRAM unit in the NVSRAM array. The column selection circuit is configured to select the object unit column in the NVSRAM array that needs to be operated, and perform data recovery operation on the non-volatile storage subunit data in the object unit column. The SRAM operation circuit is configured to perform data read / write operation on the SRAM storage subunit data in the object unit column. The input / output interface circuit is configured to provide received input data to the error detection and correction circuit and receive output data to be output from the error detection and correction circuit. The error detection and correction circuit is configured to encode and decode data transmitted between the input / output interface circuit and the SRAM operation circuit, determine whether the data has an error and correct the error; and The column selection circuit is further configured to isolate the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit, and isolate the data read / write operation and the data recovery operation.

2. The memory device of claim 1, wherein, The error detection and correction circuit is further configured to encode data input from the input / output interface circuit into the error detection and correction circuit, and write the encoded data into the SRAM operation circuit for being written into the NVSRAM array; And The error detection and correction circuit is further configured to determine whether the data read by the SRAM operation circuit from the NVSRAM array and input into the error detection and correction circuit has an error and correct the error.

3. The memory device of claim 1, wherein, The non-volatile storage operation circuit is further configured to disconnect the coupling with the NVSRAM array in the case that the SRAM operation circuit performs the data read / write operation or the column selection circuit performs the data recovery operation; The column selection circuit is further configured to connect the coupling of the SRAM operation circuit and the NVSRAM array in the case that the SRAM operation circuit performs the data read / write operation; The column selection circuit is further configured to disconnect the coupling of the SRAM operation circuit and the NVSRAM array in the case that the data recovery operation is performed.

4. The memory device of claim 3, wherein, The non-volatile storage operation circuit is further configured to, in a case where the non-volatile storage operation circuit performs the data backup operation, connect the NVSRAM array; The column selection circuit is further configured to, in a case where the non-volatile storage operation circuit performs the data backup operation, disconnect the coupling between the SRAM operation circuit and the NVSRAM array.

5. The memory device of claim 3, wherein, The column selection circuit comprises a data recovery operation sub-circuit; The data recovery operation sub-circuit is configured to perform the data recovery operation on the non-volatile storage sub-cell data in the object cell column.

6. The memory device of any one of claims 1-5, wherein, The array width of the NVSRAM array is N; The NVSRAM array comprises M rows of the NVSRAM cells; The non-volatile storage operation circuit is coupled to the NVSRAM array through N groups of transmission lines; The error correction circuit is coupled to the input / output interface circuit through K groups of transmission lines; The error correction circuit is coupled to the SRAM operation circuit through K+R groups of transmission lines; The SRAM operation circuit is coupled to the column selection circuit through K+R groups of transmission lines; The column selection circuit is coupled to the NVSRAM array through N groups of transmission lines, wherein K, R, M and N are integers and 1≤K 7. The storage device of claim 6, further comprising: a word line driving circuit configured to be coupled to the NVSRAM array to control the operation of word lines in the NVSRAM array; wherein, in a case where the non-volatile storage operation circuit performs the data backup operation, the word line driving circuit is further configured to select the SRAM storage sub-cell data in I rows of NVSRAM cells of the NVSRAM array to perform the data backup operation; or, in a case where the column selection circuit performs the data recovery operation, the word line driving circuit is further configured to select the non-volatile storage sub-cell data in J rows of NVSRAM cells of the NVSRAM array to perform the data recovery operation, wherein I and J are integers and M≥I≥1 and M≥J≥1.

8. The memory device of claim 6, wherein, The SRAM operation circuit is further configured to, in a case where the data read / write operation is performed, perform the data read / write operation on the data of the SRAM storage sub-cell in the i-th row of the selected W NVSRAM cells of the NVSRAM array; The non-volatile storage operation circuit is further configured to, in a case where the data backup operation is performed, perform the data backup operation on the data of the SRAM storage sub-cell in the NVSRAM cells of the E rows and / or F columns of the selected NVSRAM array; The column selection circuit is further configured to, in a case where the data recovery operation is performed, perform the data recovery operation on the data of the non-volatile storage sub-cell in the NVSRAM cells of the G rows and / or H columns of the selected NVSRAM array, wherein i, E, F, G, H, W are integers and N≥W≥1, M≥E≥1, M≥G≥1, N≥F≥1, N≥H≥1, M≥i≥1, and W=K+R.

9. A control method for the memory device of any one of claims 1-8, comprising: controlling the error detection and correction circuit to encode and decode data transmitted between the input / output interface circuit and the SRAM operation circuit, to determine whether the data has errors and to correct the errors.

10. The control method of claim 9, further comprising: in a case where it is determined that the SRAM operation circuit performs the data read / write operation, disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, and controlling the column selection circuit to connect the coupling between the SRAM operation circuit and the NVSRAM array; or, in a case where it is determined that the column selection circuit performs the data recovery operation, disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, and controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array; or, in a case where it is determined that the non-volatile storage operation circuit performs the data backup operation, connecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, and controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array.

11. A storage device comprising: an NVSRAM array, an SRAM operation circuit, a non-volatile storage operation circuit, an error detection and correction circuit, an input / output interface circuit, a column selection circuit, wherein the error detection and correction circuit is coupled to the SRAM operation circuit, the SRAM operation circuit is coupled to the input / output interface circuit, the SRAM operation circuit is coupled to the column selection circuit, the column selection circuit is coupled to the NVSRAM array, and the non-volatile storage operation circuit is coupled to the NVSRAM array; the NVSRAM array includes a plurality of NVSRAM cells arranged in an array, and each NVSRAM cell includes an SRAM storage sub-cell and a non-volatile storage sub-cell, the non-volatile storage sub-cell is configured to perform a data backup operation on data stored in the SRAM storage sub-cell; the non-volatile storage operation circuit is configured to perform a data backup operation on SRAM storage sub-cell data in a selected NVSRAM cell in the NVSRAM array; the column selection circuit is configured to select a target cell column in the NVSRAM array that needs to be operated, and to perform a data recovery operation on non-volatile storage sub-cell data in the target cell column; the SRAM operation circuit is configured to perform a data read / write operation on SRAM storage sub-cell data in the target cell column; the input / output interface circuit is configured to provide received input data to the SRAM operation circuit and to receive output data to be output from the SRAM operation circuit; the error detection and correction circuit is configured to encode and decode target data and to determine whether the target data has errors and to correct the errors; and the column selection circuit is further configured to isolate the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit, and to isolate the data read / write operation and the data recovery operation.

12. The memory device of claim 11, wherein, The error correction circuit is further configured to encode target data input from the SRAM operation circuit into the error correction circuit in the case that the non-volatile storage operation circuit performs the data backup operation. And The error correction circuit is further configured to determine whether the target data read by the SRAM operation circuit from the NVSRAM array and input into the error correction circuit has an error and correct the error in the case that the column selection circuit completes the data recovery operation.

13. The memory device of claim 12, wherein, The error correction circuit is further configured to encode the K-bit information code of the target data read to obtain an R-bit check code when encoding, and write the R-bit check code into the NVSRAM array through the SRAM operation circuit; and, The error correction circuit is further configured to decode and detect errors of the K-bit information code and the R-bit check code of the target data read when decoding, and correct the error in response to an error, and write the K-bit corrected information code into the NVSRAM array through the SRAM operation circuit, wherein K and R are positive integers.

14. The memory device of claim 11, wherein, The non-volatile storage operation circuit is further configured to disconnect the coupling with the NVSRAM array in the case that the SRAM operation circuit performs the data read / write operation or the column selection circuit performs the data recovery operation. The column selection circuit is further configured to connect the coupling between the SRAM operation circuit and the NVSRAM array in the case that the SRAM operation circuit performs the data read / write operation. The column selection circuit is further configured to disconnect the coupling between the SRAM operation circuit and the NVSRAM array in the case that the data recovery operation is performed.

15. The memory device of claim 14, wherein, The non-volatile storage operation circuit is further configured to connect the coupling between the non-volatile storage operation circuit and the NVSRAM array in the case that the non-volatile storage operation circuit performs the data backup operation. The column selection circuit is further configured to disconnect the coupling between the SRAM operation circuit and the NVSRAM array in the case that the non-volatile storage operation circuit performs the data backup operation.

16. The memory device of claim 14, wherein, The column selection circuit comprises a data recovery operation sub-circuit. The data recovery operation sub-circuit is configured to perform the data recovery operation on the non-volatile storage sub-unit data in the object unit column.

17. The storage device of any of claims 11-16, wherein, The array width of the NVSRAM array is N; The NVSRAM array comprises M rows of NVSRAM units; The error correction circuit is coupled with the SRAM operation circuit through a transmission line; The SRAM operation circuit is coupled with the input / output interface circuit through W groups of transmission lines; The SRAM operation circuit is coupled with the column selection circuit through W groups of transmission lines; The column selection circuit is coupled with the NVSRAM array through N groups of transmission lines; The non-volatile storage operation circuit is coupled with the NVSRAM array through N transmission lines, wherein M, N and W are integers and 1≤N, 1≤M, and 1≤W≤N.

18. The storage device of claim 17, further comprising: a word line driving circuit configured to be coupled with the NVSRAM array to control operation of word lines in the NVSRAM array; wherein, in the case that the non-volatile storage operation circuit performs the data backup operation, the word line driving circuit is further configured to select SRAM storage sub-cell data in I rows of NVSRAM cells of the NVSRAM array to perform the data backup operation; or, in the case that the column selection circuit performs the data recovery operation, the word line driving circuit is further configured to select non-volatile storage sub-cell data in J rows of NVSRAM cells of the NVSRAM array to perform the data recovery operation, wherein I and J are integers, and M≥I≥1, M≥J≥1.

19. The memory device of claim 17, wherein, the SRAM operation circuit is further configured to, in the case that the data read / write operation is performed, perform the data read / write operation on data of the SRAM storage sub-cells in the selected i-th row of W NVSRAM cells of the NVSRAM array; the non-volatile storage operation circuit is further configured to, in the case that the data backup operation is performed, perform the data backup operation on data of the SRAM storage sub-cells in the selected E rows and / or F columns of NVSRAM cells of the NVSRAM array; the column selection circuit is further configured to, in the case that the data recovery operation is performed, perform the data recovery operation on data of the non-volatile storage sub-cells in the selected G rows and / or H columns of NVSRAM cells of the NVSRAM array, wherein i, E, F, G, H, W are integers and N≥W≥1, M≥E≥1, M≥G≥1, N≥F≥1, N≥H≥1, M≥i≥1.

20. A control method for the storage device of any one of claims 11-19, comprising: controlling the error detection and correction circuit to encode and decode the target data and determine whether the target data has an error and correct the error.

21. The control method according to claim 20, wherein the control of the error detection and correction circuit to encode and decode the target data and determine whether the target data has an error and correct the error, comprising: in the case that the non-volatile storage operation circuit performs the data backup operation, encoding target data input from the SRAM operation circuit to the error detection and correction circuit; and in the case that the column selection circuit completes the data recovery operation, determining whether target data read from the NVSRAM array by the SRAM operation circuit and input to the error detection and correction circuit has an error and corrects the error.

22. The control method according to claim 20, wherein in the encoding, encoding K-bit information code of the read target data to obtain R-bit check code, and writing the R-bit check code into the NVSRAM array through the SRAM operation circuit; in the decoding, decoding and detecting errors of K-bit information code and R-bit check code of the read target data, and in response to an error, performing error correction, and writing K-bit error-corrected information code into the NVSRAM array through the SRAM operation circuit, wherein K and R are positive integers.

23. The control method of claim 20 or 21, further comprising: in a case where it is determined that the SRAM operation circuit performs the data read-write operation, disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, and controlling the column selection circuit to connect the coupling between the SRAM operation circuit and the NVSRAM array; or, in a case where it is determined that the column selection circuit performs the data recovery operation, disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, and controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array; or, in a case where it is determined that the non-volatile storage operation circuit performs the data backup operation, connecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, and controlling the column selection circuit to disconnect the coupling between the SRAM and the NVSRAM array.

24. A storage device comprising: an NVSRAM array, an SRAM operation circuit, a non-volatile storage operation circuit, and a column selection circuit, wherein the column selection circuit is coupled with the NVSRAM array, the SRAM operation circuit is coupled with the column selection circuit, and the non-volatile storage operation circuit is coupled with the NVSRAM array; the NVSRAM array includes a plurality of NVSRAM cells arranged in an array, and each NVSRAM cell includes an SRAM storage sub-cell and a non-volatile storage sub-cell, the non-volatile storage sub-cell being configured to perform a data backup operation on data stored in the SRAM storage sub-cell; the non-volatile storage operation circuit is configured to perform a data backup operation on the SRAM storage sub-cell data in a selected NVSRAM cell in the NVSRAM array; the column selection circuit is configured to select a target cell column in the NVSRAM array that needs to be operated, and perform a data recovery operation on the non-volatile storage sub-cell data in the target cell column; the SRAM operation circuit is configured to perform a data read-write operation on the SRAM storage sub-cell data in the target cell column; and the column selection circuit is further configured to isolate the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit, and isolate the data read-write operation and the data recovery operation.

25. The memory device of claim 24, wherein, the non-volatile storage operation circuit is further configured to disconnect the coupling with the NVSRAM array in a case where the SRAM operation circuit performs the data read-write operation or the column selection circuit performs the data recovery operation; the column selection circuit is further configured to connect the coupling between the SRAM operation circuit and the NVSRAM array in a case where the SRAM operation circuit performs the data read-write operation; the column selection circuit is further configured to disconnect the coupling between the SRAM operation circuit and the NVSRAM array in a case where the data recovery operation is performed.

26. The storage device of claim 25, wherein, the non-volatile storage operation circuit is further configured to connect the coupling with the NVSRAM array in a case where the non-volatile storage operation circuit performs the data backup operation; The column selection circuit is further configured to, in the case that the non-volatile storage operation circuit performs the data backup operation, disconnect the coupling between the SRAM operation circuit and the NVSRAM array.

27. The memory device of claim 25 or 26, wherein, The column selection circuit comprises a data recovery operation sub-circuit; The data recovery operation sub-circuit is configured to perform the data recovery operation on the non-volatile storage sub-cell data in the object cell column.

28. The storage device of any of claims 24-27, wherein, The array width of the NVSRAM array is N; The NVSRAM array comprises M rows of the NVSRAM cells; The non-volatile storage operation circuit is coupled to the NVSRAM array through N groups of transmission lines; The SRAM operation circuit is coupled to the column selection circuit through W groups of transmission lines; The column selection circuit is coupled to the NVSRAM array through N groups of transmission lines, wherein W, M and N are integers and N≥W≥1, M≥1.

29. The storage device of claim 28, further comprising: a word line driving circuit configured to be coupled to the NVSRAM array to control the operation of word lines in the NVSRAM array; wherein, in the case that the non-volatile storage operation circuit performs the data backup operation, the word line driving circuit is further configured to select the SRAM storage sub-cell data in I rows of NVSRAM cells of the NVSRAM array to perform the data backup operation; or, in the case that the column selection circuit performs the data recovery operation, the word line driving circuit is further configured to select the non-volatile storage sub-cell data in J rows of NVSRAM cells of the NVSRAM array to perform the data recovery operation, wherein I and J are integers and M≥I≥1, M≥J≥1.

30. The memory device of claim 28, wherein, The SRAM operation circuit is further configured to, in the case that the data read-write operation is performed, perform the data read-write operation on the data of the SRAM storage sub-cell in the selected i-th row of W NVSRAM cells of the NVSRAM array; The non-volatile storage operation circuit is further configured to, in the case that the data backup operation is performed, perform the data backup operation on the data of the SRAM storage sub-cell in the selected E rows and / or F columns of NVSRAM cells of the NVSRAM array; The column selection circuit is further configured to, in the case that the data recovery operation is performed, perform the data recovery operation on the data of the non-volatile storage sub-cell in the selected G rows and / or H columns of NVSRAM cells of the NVSRAM array, wherein i, E, F, G, H, W are integers and N≥W≥1, M≥E≥1, M≥G≥1, N≥F≥1, N≥H≥1, M≥i≥1.

31. The storage device of any one of claims 24-30, further comprising: an input-output interface circuit configured to be coupled to the SRAM operation circuit to provide received input data to the SRAM operation circuit and receive output data to be output from the SRAM operation circuit.

32. A control method for the storage device of any one of claims 24-31, comprising: In a case where it is determined that the SRAM operation circuit performs the data read / write operation, the coupling between the non-volatile storage operation circuit and the NVSRAM array is disconnected, and the column selection circuit is controlled to couple the SRAM operation circuit and the NVSRAM array; or, In a case where it is determined that the column selection circuit performs the data recovery operation, the coupling between the non-volatile storage operation circuit and the NVSRAM array is disconnected, and the column selection circuit is controlled to disconnect the coupling between the SRAM operation circuit and the NVSRAM array; or, In a case where it is determined that the non-volatile storage operation circuit performs the data backup operation, the coupling between the non-volatile storage operation circuit and the NVSRAM array is coupled, and the column selection circuit is controlled to disconnect the coupling between the SRAM operation circuit and the NVSRAM array.

33. The storage device of any one of claims 1-8, 11-19, 24-31, wherein, The non-volatile storage subunit includes an RRAM storage subunit, an MRAM storage subunit, or a PRAM storage subunit.

34. An electronic device, comprising: The storage device of any one of claims 1-8 and / or 11-19 and / or 24-31. The storage device of any one of claims 1-8 and / or 11-19 and / or 24-31.

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