Storage apparatus, electronic device, and storage apparatus control method

Abstract

A storage apparatus, an electronic device, and a storage apparatus control method. A column selection circuit in the storage apparatus is coupled with an NVSRAM array; a first input / output interface circuit is coupled with an SRAM operating circuit; the SRAM operating circuit is coupled with the column selection circuit; and a nonvolatile storage operating circuit is coupled with the NVSRAM array. The nonvolatile storage operating circuit is configured to perform data backup operation on SRAM storage subunit data; and the SRAM operating circuit is configured to perform a first data read-write operation on the SRAM storage subunit data. The column selection circuit is configured to perform a data recovery operation on the nonvolatile storage subunit data, isolate operations of the SRAM operating circuit and operations of the nonvolatile storage operating circuit, and isolate the first data read-write operation, a second data read-write operation and the data recovery operation. A second input / output interface circuit is coupled with the NVSRAM array, and is configured to perform the second data read-write operation on the NVSRAM array. The storage apparatus can improve the reliability and flexibility of data read-write, backup and recovery.

Description

Storage device, electronic device, and control method of storage device

[0001] This application claims priority to Chinese Patent Application Nos. 202410476134.4 and 202410479895.5, filed on April 19, 2024, the contents of which are hereby incorporated by reference in their entirety as part of the present application. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to a storage device, an electronic device, and a control method of the storage device. BACKGROUND

[0003] With the rapid development of science and technology and economy, the application range of memory is becoming wider and wider. Basic memory can be divided into volatile memory and non-volatile memory according to the characteristics of the storage medium. Volatile memory refers to the memory whose stored data will be lost after power off, and accordingly, non-volatile memory refers to the memory whose stored data will not be lost after power off. Generally, volatile memory has fast operation speed, while non-volatile memory has long storage time.

[0004] SRAM (Static Random Access Memory) is a volatile memory, and the data stored therein will be lost when the power is disconnected, so it is necessary to always provide power to maintain the programming state of the SRAM memory. This method consumes a lot of energy, which is not conducive to the low-power design of the storage device. SUMMARY

[0005] The at least one embodiment of the present disclosure provides a storage device, comprising: an NVSRAM array, an SRAM operation circuit, a non-volatile storage operation circuit, a first input / output interface circuit, a column selection circuit, and a second input / output interface circuit, wherein the column selection circuit is coupled with the NVSRAM array, the SRAM operation circuit is coupled with the column selection circuit, and the non-volatile storage operation circuit is coupled with the NVSRAM array; the NVSRAM array comprises a plurality of NVSRAM units arranged in an array, and each NVSRAM unit comprises an SRAM storage subunit and a non-volatile storage subunit, the non-volatile storage subunit is configured to back up data stored in the SRAM storage subunit; the non-volatile storage operation circuit is configured to perform a data backup operation on the SRAM storage subunit data in a selected NVSRAM unit in the NVSRAM array; the SRAM operation circuit is configured to perform a first data read / write operation on the SRAM storage subunit data; the column selection circuit is configured to perform a data recovery operation on the non-volatile storage subunit data; the column selection circuit is further configured to select a target unit column in the NVSRAM array to be operated in the case of performing the data recovery operation or in the case of the SRAM operation circuit performing the first data read / write operation; the first input / output interface circuit is coupled with the SRAM operation circuit and is configured to provide received first input data to the SRAM operation circuit and receive first output data to be output from the SRAM operation circuit; the column selection circuit is further configured to isolate the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit, and to isolate the first data read / write operation, the second data read / write operation, and the data recovery operation; and the second input / output interface circuit is coupled with the NVSRAM array and is configured to perform a second data read / write operation on the NVSRAM array.

[0006] The control method of the storage device includes: in a case where it is determined that the SRAM operation circuit performs the first data read / write operation, disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, controlling the column selection circuit to couple the SRAM operation circuit and the NVSRAM array, and controlling the second input / output circuit to disconnect the coupling with the NVSRAM array; or in a case where it is determined that the second input / output interface circuit performs the second data read / write operation, disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, coupling the second input / output interface circuit and the NVSRAM array, and controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array; or in a case where it is determined that the non-volatile storage operation circuit performs the data backup operation, coupling the non-volatile storage operation circuit and the NVSRAM array, controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array, and controlling the second input / output circuit to disconnect the coupling with the NVSRAM array; or in a case where it is determined that the column selection circuit performs the data recovery operation, disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array, and controlling the second input / output interface circuit to disconnect the coupling with the NVSRAM array.

[0007] The at least one embodiment of the present disclosure provides a storage device, comprising: an NVSRAM array, an SRAM operation circuit, a non-volatile storage operation circuit, an error detection and correction circuit, a first input / output interface circuit, a column selection circuit, a second input / output interface circuit, wherein the error detection and correction circuit is coupled with the SRAM operation circuit, the SRAM operation circuit is coupled with the column selection circuit, the column selection circuit is coupled with the NVSRAM array, and the non-volatile storage operation circuit is coupled with the NVSRAM array; the NVSRAM array comprises a plurality of NVSRAM units arranged in an array, and each NVSRAM unit comprises an SRAM storage subunit and a non-volatile storage subunit, the non-volatile storage subunit is configured to back up data stored in the SRAM storage subunit; the non-volatile storage operation circuit is configured to perform a data backup operation on the SRAM storage subunit data in the selected NVSRAM unit in the NVSRAM array; the SRAM operation circuit is configured to perform a first data read / write operation on the SRAM storage subunit data; the column selection circuit is configured to perform a data recovery operation on the non-volatile storage subunit data; the column selection circuit is further configured to select a target unit column in the NVSRAM array that needs to be operated in the case of performing the data recovery operation or in the case of the SRAM operation circuit performing the first data read / write operation; the first input / output interface circuit is coupled with the SRAM operation circuit and is configured to provide received first input data to the SRAM operation circuit and receive first output data to be output from the SRAM operation circuit; the error detection and correction circuit is configured to encode and decode target data, determine whether the target data has an error, and correct the error; the column selection circuit is further configured to isolate the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit, and isolate the first data read / write operation, the second data read / write operation, and the data recovery operation; and the second input / output interface circuit is coupled with the NVSRAM array and is configured to perform a second data read / write operation on the NVSRAM array.

[0008] The at least one embodiment of the present disclosure provides a control method of a storage device, for the storage device provided in any embodiment of the present disclosure. The control method comprises: controlling the error detection and correction circuit to encode and decode target data, determine whether the target data has an error, and correct the error.

[0009] The at least one embodiment of the present disclosure provides an electronic device comprising the storage device provided in any embodiment of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure and not limit the present disclosure.

[0011] FIG. 1 shows a schematic diagram of a combination of a volatile storage subunit and a non-volatile storage subunit;

[0012] FIG. 2 shows a schematic block diagram of a storage device provided by at least one embodiment of the present disclosure;

[0013] FIG. 3 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure;

[0014] FIG. 4 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure;

[0015] FIG. 5 shows a flowchart of a control method of a storage device provided by at least one embodiment of the present disclosure;

[0016] FIG. 6 shows a flowchart of another control method of a storage device provided by at least one embodiment of the present disclosure;

[0017] FIG. 7 shows a flowchart of another control method of a storage device provided by at least one embodiment of the present disclosure;

[0018] FIG. 8 shows a flowchart of another control method of a storage device provided by at least one embodiment of the present disclosure;

[0019] FIG. 9 shows a flowchart of a working method of a storage device provided by at least one embodiment of the present disclosure;

[0020] FIG. 10 shows a flowchart of a data backup method of a storage device provided by at least one embodiment of the present disclosure;

[0021] FIG. 11 shows a flowchart of a data recovery method of a storage device provided by at least one embodiment of the present disclosure;

[0022] FIG. 12 shows a schematic block diagram of a storage device provided by at least one embodiment of the present disclosure;

[0023] FIG. 13 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure;

[0024] FIG. 14 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure;

[0025] FIG. 15 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure;

[0026] FIG. 16A shows a schematic block diagram of another storage device according to at least one embodiment of the present disclosure;

[0027] FIG. 16B shows a schematic block diagram of another storage device according to at least one embodiment of the present disclosure;

[0028] FIG. 17 shows a flow diagram of a control method of a storage device according to at least one embodiment of the present disclosure;

[0029] FIG. 18 shows a flow diagram of a control method of another storage device according to at least one embodiment of the present disclosure;

[0030] FIG. 19 shows a flow diagram of a control method of another storage device according to at least one embodiment of the present disclosure;

[0031] FIG. 20 shows a flow diagram of a control method of another storage device according to at least one embodiment of the present disclosure;

[0032] FIG. 21 shows a flow diagram of a control method of another storage device according to at least one embodiment of the present disclosure;

[0033] FIG. 22 shows a flow diagram of a control method of another storage device according to at least one embodiment of the present disclosure;

[0034] FIG. 23 shows a flow diagram of a control method of another storage device according to at least one embodiment of the present disclosure;

[0035] FIG. 24 shows a flow diagram of a control method of another storage device according to at least one embodiment of the present disclosure;

[0036] FIG. 25 shows a flow diagram of a data backup of a storage device according to at least one embodiment of the present disclosure;

[0037] FIG. 26 shows a flow diagram of a data recovery of a storage device according to at least one embodiment of the present disclosure; and

[0038] FIG. 27 shows a schematic block diagram of an electronic device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0040] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The technical terms used in the present disclosure are not limited to the generally accepted meanings of the terms. The technical terms used in the present disclosure should be understood as follows. The terms "first", "second", and the like, do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one", "a", or "the" do not denote a quantity restriction, but mean that there is at least one. The terms "include" or "contain" and the like mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connected" or "connected" and the like are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "up", "down", "left", "right", and the like are used only to represent relative positional relationships, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0041] Static random access memory (SRAM) includes a memory cell array, a row / column address decoder, a sense amplifier, a control circuit, a buffer / driver circuit, and the like. The memory cell array includes a plurality of SRAM memory sub-units, word lines, bit lines, and the like. The memory sub-units are arranged in multiple rows and multiple columns, and are addressed in the row direction by the word lines and in the column direction by the bit lines. SRAM can perform well in situations requiring fast data access, such as cache or CPU cache, etc. Due to its fast data access speed, SRAM can be used as a storage for some data that requires fast access.

[0042] For example, SRAM can have multiple types, such as 6T-SRAM (i.e., six-transistor type SRAM), 7T-SRAM (i.e., seven-transistor type SRAM), 8T-SRAM (i.e., eight-transistor type SRAM), and the like. Multiple transistor type SRAMs are not specifically described here.

[0043] However, the data stored in SRAM will be lost after power failure. SRAM does not have its own independent power supply and needs to obtain power from the outside to maintain data storage. Once the power is interrupted, the memory sub-units will not be able to continue to maintain the charge state, resulting in data loss. Therefore, the operation of SRAM requires continuous power supply to maintain its data storage state.

[0044] NVM (Non-Volatile Memory) is a kind of semiconductor memory that can keep data storage after power off. For example, the non-volatile memory can be RRAM (Resistive Random Access Memory), PRAM (Phase-Change Random Access Memory), Flash, etc. For example, RRAM and PRAM can store data by changing resistance. For example, the resistive random access memory can use the resistance of the thin film material under the condition of the applied voltage to realize data storage in different resistance states, i.e. high resistance state (HRS) and low resistance state (LRS). The different high and low resistance states represent logical "1" and logical "0", thereby realizing data storage and being able to keep for a long time after power off. The process of transition from high resistance state (HRS) to low resistance state (LRS) can be called SET process, also called setting process. The process of transition from low resistance state to high resistance state can be called RESET process, also called resetting process. The non-volatile memory has a relatively slow operation speed and needs a large operation current or voltage.

[0045] Therefore, the NVM is combined with the SRAM to form NVSRAM (Nonvolatile Static random Access Memory), which combines the advantages of the above two types of memories, and can solve the problem of data loss after power off of the SRAM and the problem of operation speed, etc.

[0046] In the NVSRAM, the main memory area includes an array of NVSRAM cells formed by multiple rows and multiple columns, each NVSRAM cell includes an SRAM storage subunit and an NVM storage subunit corresponding to the SRAM storage subunit, and high-speed random access can be achieved. After power failure, the data in this area can still be stored for a long time. For example, the data in the SRAM storage subunit can be backed up to the NVM storage subunit before power failure, and the data can be restored from the NVM storage subunit to the SRAM storage subunit when power is restored. When data is written, the data is first stored in the SRAM storage subunit, and the data is also backed up to the NVM storage subunit to achieve non-volatile storage. In the read operation, the data is directly read from the SRAM storage subunit. The SRAM storage subunit provides fast read speed and low latency. When power failure occurs, the data in the SRAM storage subunit loses power supply, but the data in the NVM storage subunit can still be maintained, which enables the NVSRAM to maintain the integrity of the data during power failure without the need for continuous power supply from an external power source. After power is restored, the data in the NVM storage subunit is restored to the SRAM storage subunit to restore the data state, so that the NVSRAM can provide data access after power is restored, realizing the combination of high-speed access and non-volatile storage.

[0047] However, the NVM storage subunit is susceptible to some factors during data backup and data recovery, resulting in a high error rate. For example, when the SRAM storage subunit performs data recovery, a large peak current may be generated, which can reduce the stability of the NVSRAM, affect the success rate of data recovery, and ultimately result in a large error rate of the recovered data; errors can also occur when data is backed up to the NVM storage subunit, for example, incomplete charge injection or release can occur during data backup, or the NVM storage subunit can be affected by voltage fluctuations, electromagnetic interference, etc. during data backup, and data bit errors can occur when data is backed up to the NVM storage subunit, all of which can result in a high error rate of the NVM storage subunit.

[0048] In addition, for example, in the case of an NVM storage subunit being an RRAM storage subunit, during the data backup by the RRAM storage subunit or the data recovery by the SRAM storage subunit, the RRAM storage subunit and the SRAM storage subunit can interfere with each other. For example, due to the different read-write mechanisms of the RRAM storage subunit and the SRAM storage subunit, if their operations are not properly coordinated, read-write conflicts can occur, causing mutual interference; or if the data synchronization between the RRAM storage subunit and the SRAM storage subunit is not properly handled, data loss can occur, affecting the system stability of the storage device, and so on.

[0049] The inventors of the present disclosure have noticed that, in order to solve these problems, the characteristics and operation requirements of the RRAM storage subunit and the SRAM storage subunit need to be fully considered when designing the storage device, and corresponding measures need to be taken to coordinate their operations. For example, read-write conflicts can be avoided by formulating reasonable read-write strategies; or the mutual influence between the two operations can be reduced by optimizing the design of the storage device, such as reducing resource conflicts and interference by improving circuit design, optimizing read-write timing, using different power supplies, and so on.

[0050] The inventors of the present disclosure have noticed that, in order to solve these problems, the characteristics and operation requirements of the RRAM storage subunit and the SRAM storage subunit need to be fully considered when designing the storage device, and corresponding measures need to be taken to coordinate their operations. For example, read-write conflicts can be avoided by formulating reasonable read-write strategies; or the mutual influence between the two operations can be reduced by optimizing the design of the storage device, such as reducing resource conflicts and interference by improving circuit design, optimizing read-write timing, using different power supplies, and so on.

[0051] FIG. 1 shows a combination of a volatile storage subunit and a non-volatile storage subunit.

[0052] As shown in FIG. 1, the illustrated NVSRAM combines a volatile storage subunit and a non-volatile storage subunit. In the example shown in FIG. 1, the volatile storage subunit is a 6T-SRAM (i.e., a six-transistor type SRAM), including transistors P0, P1, N0, N1, N2, N3, and bit line BL, bit line BLN, word line WL, power line CVDD, ground line VSS for operating the storage subunit, and further including storage node Q and storage node QN within the SRAM storage subunit. Bit line BL and bit line BLN are used for reading and writing data, word line WL is used for controlling the reading and writing operation, transistors P0 and N0 form an inverter, and transistors P1 and N1 form another inverter, and the two inverters are cross-connected to thereby provide storage node Q and storage node QN. The SRAM storage subunit has a bistable structure. When storage node Q is at a high level, storage node QN is at a low level, and at this time, the data stored can be selected as "1", and correspondingly, when storage node Q is at a low level, storage node QN is at a high level, and at this time, the data stored can be selected as "0"; transistors N2 and N3 are controlled by word line WL to turn on or turn off the storage subunit.

[0053] In the example shown in FIG. 1, the non-volatile storage subunit can include resistive random storage subunit (RRAM) R, resistive random storage subunit RN, transistor N4, and transistor N5. The non-volatile storage subunit is connected to the volatile storage subunit in a differential manner, resistive random storage subunit R is connected to storage node Q through transistor N4, resistive random storage subunit RN is connected to storage node QN through transistor N5, the gates of transistors N4 and N5 are connected to control line CWLN, and the switching states of transistors N4 and N5 are controlled through control line CWLN. For example, the state in which the resistance of resistive random storage subunit R is greater than the resistance of resistive random storage subunit RN is set as data "1", and vice versa.

[0054] In other forms, the volatile storage subunit can also be other forms of SRAM subunits; in addition to being connected to the volatile storage subunit in the differential manner as described above, the non-volatile storage subunit can also be connected in a single-ended manner, for example, including only resistive random storage subunit R and transistor N4. In addition, in addition to using RRAM subunits, the non-volatile storage subunit can also use PRAM subunits, etc.

[0055] Some embodiments of the present disclosure provide a storage device, an electronic device including the storage device, and a storage device control method.

[0056] The storage device includes an NVSRAM array, an SRAM operation circuit, a non-volatile storage operation circuit, a column selection circuit, a first input / output interface circuit, and a second input / output interface circuit. The column selection circuit is coupled to the NVSRAM array, the SRAM operation circuit is coupled to the column selection circuit, and the non-volatile storage operation circuit is coupled to the NVSRAM array.

[0057] The NVSRAM array includes a plurality of NVSRAM cells arranged in an array, and each NVSRAM cell includes an SRAM storage subunit and a non-volatile storage subunit configured to back up data stored in the SRAM storage subunit.

[0058] The non-volatile storage operation circuit is configured to perform a data backup operation on the SRAM storage subunit data in a selected NVSRAM cell in the NVSRAM array, the SRAM operation circuit is configured to perform a first data read / write operation on the SRAM storage subunit data, the column selection circuit is configured to perform a data recovery operation on the non-volatile storage subunit data, and the column selection circuit is further configured to select a column of cells in the NVSRAM array to be operated on during the data recovery operation or when the SRAM operation circuit performs the first data read / write operation. The column selection circuit is further configured to isolate the operations of the SRAM operation circuit and the non-volatile storage operation circuit, and to isolate the first data read / write operation, the second data read / write operation, and the data recovery operation. The first input / output interface circuit is coupled to the SRAM operation circuit and configured to provide received first input data to the SRAM operation circuit and receive first output data to be output from the SRAM operation circuit. The second input / output interface circuit is coupled to the NVSRAM array and configured to perform a second data read / write operation on the NVSRAM array.

[0059] The storage device backs up data of the SRAM storage subunit using the non-volatile storage subunit, isolates the operations of the SRAM operation circuit and the non-volatile storage operation circuit using the column selection circuit, and isolates the first data read / write operation, the second data read / write operation, and the data recovery operation. The storage device also transmits input or output data of the storage device through the first input / output interface circuit or the second input / output interface circuit, thereby improving the reliability and flexibility of data read / write, backup, and recovery.

[0060] FIG. 2 shows a schematic block diagram of a storage device according to at least one embodiment of the present disclosure.

[0061] In some embodiments of the present disclosure, as shown in FIG. 2, the storage device 1000 includes an NVSRAM array 120, an SRAM operation circuit 100, a non-volatile storage operation circuit 130, a column selection circuit 110, a first input / output interface circuit 150, and a second input / output interface circuit 160.

[0062] The SRAM operation circuit 100 is coupled with the column selection circuit 110, the column selection circuit 110 is coupled with the NVSRAM array 120, the non-volatile storage operation circuit 130 is coupled with the NVSRAM array 120, the first input / output interface circuit 150 is coupled with the SRAM operation circuit 100, and the second input / output interface circuit 160 is coupled with the NVSRAM array 120.

[0063] In the present disclosure, "coupled" is used to describe the signal connection between the described objects, and the signal connection can be performed after the coupling between the described objects is established, and the signal connection cannot be performed after the coupling between the described objects is disconnected. The coupling can be achieved by, for example, electrical connection. For example, in the embodiments of the present disclosure, "coupled" can include two or more electronic elements or circuits connected together in some way, so that the signals between them are transmitted to each other. For example, two storage subunits can be directly connected, and the transmission of information can be achieved through the transmission of signals or energy, or two storage subunits are connected through other circuit elements, such as through resistors, capacitors, switches, optoelectronic elements, or transmission line networks, etc., to achieve signal transmission.

[0064] The NVSRAM array 120 includes a plurality of NVSRAM units 121 arranged in an array, and each NVSRAM unit 121 includes an SRAM storage subunit 122 and a non-volatile storage subunit 131, and the non-volatile storage subunit 131 is configured to back up the data stored in the SRAM storage subunit 122. The array formed by the plurality of NVSRAM units 121 includes a plurality of rows and a plurality of columns. For example, the plurality of NVSRAM units 121 can form a storage array including M rows and N columns, where M and N are integers and 1≤M, 1≤N. The NVSRAM unit 121 may, for example, adopt the form shown in FIG. 1, but the embodiments of the present disclosure are not limited to this specific form.

[0065] The NVSRAM unit 121 of the NVSRAM array 120 combines the characteristics of the SRAM storage subunit and the non-volatile storage subunit. The SRAM storage subunit 122 can be configured to store data and can quickly read and write data. The non-volatile storage subunit 131 is configured to back up the data stored in the SRAM storage subunit 122, so as to prevent the data stored in the SRAM storage subunit 122 from being lost in the event of power off or system crash.

[0066] For example, the non-volatile storage subunit 131 can include RRAM, FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), PCM (Phase Change Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), PRAM, flash memory, and the like. Corresponding to different types of non-volatile storage subunits 131, the non-volatile storage operation circuit 130 in the embodiments of the present disclosure is adjusted accordingly, and the present disclosure is not limited thereto. For example, when the non-volatile storage subunit 131 includes an RRAM storage subunit, the non-volatile storage operation circuit 130 can include an RRAM operation circuit.

[0067] The non-volatile storage operation circuit 130 is configured to perform a data backup operation on the SRAM storage subunit 122 data in the selected NVSRAM cell 121 in the NVSRAM array 120.

[0068] In some embodiments, the non-volatile storage operation circuit 130 can communicate with a plurality of SRAM storage subunits 122, and the non-volatile storage operation circuit 130 can perform a data backup operation on the SRAM storage subunit 122 data as needed, such as when the electronic device detects that an application program has failed or abnormally, the non-volatile storage operation circuit 130 performs a backup operation. For example, the non-volatile storage operation circuit 130 can also perform a data backup operation on the data in the SRAM storage subunit 122 in response to a backup instruction, or perform a periodic data backup operation on the SRAM storage subunit 122 based on a preset time, or perform a real-time data backup operation on the SRAM storage subunit 122.

[0069] To improve the efficiency of data backup, the non-volatile storage operation circuit 130 can use a parallel processing method to simultaneously perform a data backup operation on a plurality of selected SRAM storage subunit 122 data. For example, the non-volatile storage operation circuit 130 can simultaneously perform a data backup operation on the data in a row of SRAM storage subunits 122, or the non-volatile storage operation circuit 130 can simultaneously perform a data backup operation on a plurality of rows of SRAM storage subunit 122 data.

[0070] In some embodiments of the present disclosure, the first input / output interface circuit 150 is configured to provide the received first input data to the SRAM operation circuit 100 and receive the first output data to be output from the SRAM operation circuit 100. The SRAM operation circuit 100 is configured to perform the first data read / write operation on the SRAM storage subunit 122. The column selection circuit 110 is configured to perform the data recovery operation on the nonvolatile storage subunit data. The second input / output interface circuit 160 is configured to perform the second data read / write operation on the NVSRAM array 120.

[0071] Here, the "first data read / write operation" refers to the data read / write operation performed by the SRAM operation circuit 100 on the SRAM storage subunit 122. The "second data read / write operation" refers to the data read / write operation performed by the second input / output interface circuit 160 on the SRAM storage subunit 122. For example, the first input / output interface circuit 150 can be configured to receive the first input data of the storage device 1000 and provide the first input data to the SRAM operation circuit 100. When the SRAM operation circuit 100 needs to perform data output, the first input / output interface circuit 150 can be configured to receive the first output data to be output from the SRAM operation circuit 100.

[0072] For example, the storage device 1000 can determine whether the data input into the storage device 1000 is input from the first input / output interface circuit 150 or from the second input / output interface circuit 160 according to the received control instruction, the data bit width or data type input into the storage device 1000, the working condition of each circuit in the storage device 1000, etc. For example, when the column selection circuit 110 performs the data recovery operation, the data input into the storage device 1000 can be input from the second data input / output interface circuit 160. For example, when the second input / output interface circuit 160 performs the second data read / write operation, the data input into the storage device 1000 can be input from the second input / output interface circuit 160. For example, the bit width of the data input or output by the first input / output interface circuit 150 and the second input / output interface circuit 160 can be preset, for example, the data bit width input or output by the first input / output interface circuit 150 can be greater than that of the second input / output interface circuit 160; for example, the data bit width input or output by the first input / output interface circuit 150 is 32 bits, and the data bit width input or output by the second input / output interface circuit 160 is 512 bits, and when the data bit width input into the storage device 1000 is 32 bits, the data can be input from the first input / output interface circuit 150, and the embodiments of the present disclosure are not limited thereto.

[0073] For example, the first data read / write operation on the selected SRAM storage subunit 122 by the SRAM operation circuit 100, or the second data read / write operation on the selected SRAM storage subunit 122 by the second input / output interface circuit 150, can be determined by the received read / write instruction, the data bit width or data type, the working condition of each circuit in the storage device 1000, and the like.

[0074] In some embodiments, the column selection circuit 110 is configured to select the object cell column in the NVSRAM array 120 that needs to be operated in the data recovery operation, or in the case that the SRAM operation circuit 100 performs the first data read / write operation. For example, in the case that the SRAM operation circuit 100 performs the first data read / write operation or the column selection circuit 110 performs the data recovery operation, the column selection circuit 110 responds to the received address signal and converts it into an electrical signal, thereby selecting the corresponding object cell column in the NVSRAM array 120; for example, the column selection circuit 110 can select the corresponding object cell column in the NVSRAM array 120 according to the instruction that the SRAM operation circuit 100 needs to perform the first data read / write operation or the column selection circuit 110 needs to perform the data recovery operation.

[0075] Here, the "object cell column" is used to refer to the storage column that is the object of operation, which can be any column in the plurality of storage arrays. The "address signal" includes a row selection signal and a column selection signal, and the row selection signal is used for row addressing by the word line driving circuit (to be described below), and the column selection signal is used for column addressing by the column selection circuit.

[0076] As described above, in the process of the non-volatile storage operation circuit 130 performing the data backup operation, or in the process of the SRAM operation circuit 100 performing the first data read / write operation, or in the process of the column selection circuit 110 performing the data recovery operation, or in the process of the second input / output interface circuit 160 performing the second data read / write operation, the operation of the non-volatile storage operation circuit 130, the operation of the SRAM operation circuit 100, the operation of the second input / output interface circuit 160, and the data recovery operation of the column selection circuit 110 can affect each other, thereby affecting the stability of data backup and data recovery.

[0077] In at least some embodiments of the present disclosure, the column selection circuit 110 can also be configured to isolate the operation of the SRAM operation circuit 100 and the operation of the non-volatile storage operation circuit 130. For example, the second input / output interface circuit 160 can also be configured to isolate the operation of the second input / output interface circuit 160 and the operation of the non-volatile storage operation circuit 130.

[0078] For example, the non-volatile storage operation circuit 130 and the SRAM operation circuit 100 can be respectively provided with independent column selection circuits 110 to reduce the interference between them, and the independent column selection circuits 110 can have different circuit structures and elements to adapt to the characteristics and operation requirements of the non-volatile storage operation circuit 130 and the SRAM operation circuit 100.

[0079] For example, the column selection circuit 110 can also not perform the data recovery operation in the case that the SRAM operation circuit 100 performs the first data read-write operation, the second input-output interface circuit 170 performs the second data read-write operation, or the non-volatile storage operation circuit 130 performs the data backup operation, so as to isolate the first data read-write operation, the second data read-write operation, the data backup operation and the data recovery operation.

[0080] In some embodiments, the non-volatile storage operation circuit 130, the SRAM operation circuit 100 or the second input-output interface circuit 160 can also be power-isolated, for example, the non-volatile storage operation circuit 130, the SRAM operation circuit 100 or the second input-output interface circuit 160 can be respectively provided with independent power supplies or power supply lines. For example, the power supply stability of the circuit can also be improved by adding a voltage stabilizer in the non-volatile storage operation circuit 130, the SRAM operation circuit 100 or the second input-output interface circuit 160. For example, the data of the non-volatile storage operation circuit 130, the SRAM operation circuit 100 or the second input-output interface circuit 160 can also be transmitted by optical signals through an optical coupler. For example, the operation of the non-volatile storage operation circuit 130, the operation of the SRAM operation circuit 100 or the operation of the second input-output interface circuit 160 can also be controlled by logic design, for example, in a specific situation, only the operation of the non-volatile storage operation circuit 130 can be allowed, or only the operation of the SRAM operation circuit 100 can be allowed, or only the operation of the second input-output interface circuit 160 can be allowed, and the non-volatile storage operation circuit 130 and the SRAM operation circuit 100 or the second input-output interface circuit 160 are prohibited from operating at the same time.

[0081] FIG. 3 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure.

[0082] As shown in FIG. 3, in some embodiments of the present disclosure, the second input-output interface circuit 160 includes a shift register operation circuit 161, an input interface circuit 162, and an output interface circuit 163. The shift register operation circuit 161 is coupled with the NVSRAM array 120 and configured to perform a second data read-write operation on the NVSRAM array 120; the input interface circuit 162 is coupled with the shift register operation circuit 161 and configured to receive second input data and provide the received second input data to the shift register operation circuit 161; and the output interface circuit 163 is coupled with the shift register operation circuit 161 and configured to receive second output data to be output from the shift register operation circuit 161.

[0083] Here, the "second input data" refers to data input to the storage device 1000 through the input interface circuit 162 in the second input-output interface circuit 160. The "second output data" refers to data output from the storage device 1000 through the output interface circuit 163 in the second input-output interface circuit 160, and embodiments of the present disclosure do not limit the content and form of the data, etc.

[0084] For example, the shift register operation circuit 161 can input the received second input data into the SRAM storage sub-unit 122 of the NVSRAM array 120, or the shift register operation circuit 161 can read the second output data from the SRAM storage sub-unit 122 of the NVSRAM array 120 and output the data from the storage device 1000 through the output interface circuit 163.

[0085] For example, the shift register operation circuit 161 can temporarily store the received second input data, and then input the second input data into the SRAM storage sub-unit 122 in the NVSRAM array 120.

[0086] For example, the shift register operation circuit 161 can also convert the received second input data. For example, the shift register operation circuit 161 can convert the serially received second input data into parallel input into the SRAM storage sub-unit 122 in the NVSRAM array 120.

[0087] In some embodiments of the present disclosure, as shown in FIG. 2 or FIG. 3, the NVSRAM array 120 can also be configured to be coupled with the word line driving circuit 140. The word line driving circuit 140 is configured to select the object unit row to be operated in the NVSRAM array 120 in the case of performing the first data read-write operation by the SRAM operation circuit 100, or in the case of performing the second data read-write operation by the second input-output interface circuit 160, or in the case of performing the data recovery operation by the column selection circuit, or in the case of performing the data backup operation by the non-volatile storage operation circuit.

[0088] Here, the “object cell row” is used to refer to a storage cell row that is an operation object, which may be any row in a plurality of storage arrays.

[0089] The word line driver circuit 140 (Word Line Driver) for the NVSRAM array 120 is configured to control the rows (word lines) of memory cells in the NVSRAM array 120. In the NVSRAM array 120, for example, each memory cell is located at the intersection of signal lines, i.e., the horizontal signal lines are word lines, and the vertical signal lines are bit lines. For example, the word line driver circuit 140 is responsible for controlling the switches connected to the word lines to determine which row of memory cells is selected for the desired operation (correspondingly, the column select circuit 110 is responsible for determining which column of memory cells is selected for the desired operation via the bit lines).

[0090] For example, in some embodiments, word line driver circuit 140 may include a decoder and a selector. The decoder receives an address signal and decodes it into a row address for the corresponding word line. The selector selects the corresponding word line based on the row address and applies a drive signal. When reading or writing data from or into a selected memory cell, word line driver circuit 140 ensures correct access to the selected memory cell while avoiding interference or malfunction in other unselected memory cells.

[0091] For example, in some embodiments, when the second input / output interface circuit 160 performs a second data read / write operation, the word line driver circuit 140 may be configured to select a row of memory cells in the NVSRAM array 120 to be selected for the second data read / write operation. When performing a data read operation, the second input / output interface circuit 160 may read data from the selected row; when performing a data write operation, the second input / output interface circuit 160 may write data to the selected row of memory cells.

[0092] For example, in some embodiments, when the second input-output interface circuit 160 performs a second data read and write operation, the column selection circuit can be used to determine which column of storage cells is selected for the second data read and write operation, or the second data read and write operation can be performed on all columns of storage cells in the NVSRAM array 120. The embodiments of the present disclosure are not limited to this.

[0093] For example, in some embodiments, when the SRAM operating circuit 100 performs a first data read / write operation, the word line driver circuit 140 may be configured to select a row of memory cells in the NVSRAM array 120 to be selected for the first data read / write operation. Exemplarily, when the SRAM operating circuit 100 performs the first data read / write operation, the SRAM operating circuit 100 may read the selected row of data during a data read operation; and may write data to the selected row of memory cells during a data write operation.

[0094] For example, in some embodiments, when the non-volatile storage operation circuit 130 performs a data backup operation, the word line driver circuit 140 may be configured to select a row of memory cells in the NVSRAM array 120 to be selected for the data backup operation. For example, when performing the data backup operation, the non-volatile storage operation circuit 130 may read the data of the selected row in the SRAM storage sub-unit 122 and back up the data of the selected row in the SRAM storage sub-unit 122 to the non-volatile storage sub-unit 131.

[0095] For example, in some embodiments, when the column selection circuit 110 performs a data recovery operation, the word line driver circuit 140 may be configured to select a row of memory cells in the NVSRAM array 120 to be selected for the data recovery operation. For example, when performing the data recovery operation, the column selection circuit 110 may restore the data of the selected row in the nonvolatile memory sub-cell 131 to the SRAM memory sub-cell 122.

[0096] FIG4 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure.

[0097] As shown in FIG4 , in some embodiments of the present disclosure, the second input / output interface circuit 160 may further include an isolation sub-circuit 164. The isolation sub-circuit 164 is coupled between the NVSRAM array 120 and the shift register operation circuit 161. The isolation sub-circuit 164 may be configured to turn on a switch coupling the shift register operation circuit 161 to the NVSRAM array 120 when the shift register operation circuit 161 performs a second data read / write operation. Alternatively, the isolation sub-circuit 164 may be configured to turn off the switch coupling the shift register operation circuit 161 to the NVSRAM array 120 when the non-volatile storage operation circuit 130 performs a data backup operation.

[0098] For example, in at least some embodiments of the present disclosure, when the shift register operation circuit 161 performs a second data read / write operation, the isolation sub-circuit 164 can couple the shift register operation circuit 161 and the NVSRAM array 120. The shift register operation circuit 161 can then perform the second data read / write operation on the SRAM storage sub-units 122 in the NVSRAM array 120, thereby achieving fast data read / write transmission. At the same time, since the non-volatile storage operation circuit 130 is disconnected from the NVSRAM array 120, the read / write operation of the shift register operation circuit 161 is not affected.

[0099] When the non-volatile storage operation circuit 130 needs to perform a data backup operation, the isolation sub-circuit 164 can disconnect the shift register operation circuit 161 from the NVSRAM array 120, while the non-volatile storage operation circuit 130 is coupled to the NVSRAM array 120. The non-volatile storage operation circuit 130 can perform a data backup operation, and the shift register operation circuit 161 will not affect the data backup operation of the non-volatile storage operation circuit 130.

[0100] In some embodiments of the present disclosure, when the SRAM operation circuit 100 performs a first data read and write operation, the column selection circuit 110 can also be configured to connect the coupling between the SRAM operation circuit 100 and the NVSRAM array 120, the non-volatile storage operation circuit 130 can be configured to disconnect the coupling with the NVSRAM array 120, and the second input-output interface circuit 160 can be configured to disconnect the coupling with the NVSRAM array 120.

[0101] In some embodiments of the present disclosure, when the non-volatile storage operation circuit 130 performs data backup, the column selection circuit 110 can also be configured to disconnect the SRAM operation circuit 100 and the NVSRAM array 120, the non-volatile storage operation circuit 130 can also be configured to connect the coupling with the NVSRAM array 120, and the second input-output interface circuit 160 can be configured to disconnect the coupling with the NVSRAM array 120.

[0102] In some embodiments of the present disclosure, when the column selection circuit 110 performs a data recovery operation, the column selection circuit can also be configured to disconnect the SRAM operation circuit 100 and the NVSRAM array 120, the non-volatile storage operation circuit 130 can be configured to disconnect the NVSRAM array 120, and the second input-output interface circuit 160 can be configured to disconnect the NVSRAM array 120.

[0103] In some embodiments of the present disclosure, when the second input-output interface circuit 160 performs a second data read and write operation, the column selection circuit 110 can also be configured to disconnect the SRAM operation circuit 100 and the NVSRAM array 120, and the non-volatile storage operation circuit 130 can also be configured to disconnect the NVSRAM array 120.

[0104] For example, in at least some embodiments of the present disclosure, when the SRAM operating circuit 100 needs to perform a first data read / write operation, the column selection circuit 110 couples the SRAM operating circuit 100 and the NVSRAM array 120. The SRAM operating circuit 100 can then perform read / write operations on the SRAM storage subunits 122 in the NVSRAM array 120, thereby achieving fast data read / write transmission. Simultaneously, since the non-volatile storage operating circuit 130 is disconnected from the NVSRAM array 120 and the second input / output interface circuit 160 is disconnected from the NVSRAM array 120, the read / write operations of the SRAM operating circuit 100 are not affected.

[0105] For example, when the non-volatile storage operation circuit 130 needs to perform data backup, the second input / output interface circuit 160 is disconnected from the NVSRAM array 120, and the column selection circuit 110 disconnects the SRAM operation circuit 100 from the NVSRAM array 120, while the non-volatile storage operation circuit 130 is coupled to the NVSRAM array 120. The non-volatile storage operation circuit 130 can perform the backup operation, and the SRAM operation circuit 100 will not affect the data backup process.

[0106] For example, when the column selection circuit 110 needs to perform a data recovery operation, the second input / output interface circuit 160 is disconnected from the NVSRAM array 120, the column selection circuit 110 disconnects the SRAM operation circuit 100 from the NVSRAM array 120, and the non-volatile storage operation circuit 130 is also disconnected from the NVSRAM array 120. Therefore, the SRAM operation circuit 100, the non-volatile storage operation circuit 130, and the second input / output interface circuit 160 will not affect the data recovery operation process of the column selection circuit 110.

[0107] For example, when the second input / output interface circuit 160 needs to perform a second data read / write operation, the non-volatile storage operation circuit 130 is disconnected from the NVSRAM array 120, and the column selection circuit 110 disconnects the SRAM operation circuit 100 from the NVSRAM array 120. Therefore, the operations of the SRAM operation circuit 100 and the non-volatile storage operation circuit 130 will not affect the second data read / write operation process of the second input / output interface circuit 160.

[0108] In some embodiments of the present disclosure, as shown in FIG. 4 , the column selection circuit 110 further includes a data recovery operation sub-circuit 111 .

[0109] For example, in some embodiments, the data recovery operation sub-circuit 111 can be configured to perform a data recovery operation on the data in the non-volatile storage sub-unit 131 in the target unit column. For example, upon receiving a data recovery operation instruction, the data recovery operation sub-circuit 111 can restore the data stored in the selected non-volatile storage sub-unit 131 to the SRAM storage sub-unit 122. For example, when performing a data recovery operation, the data recovery operation sub-circuit must ensure isolation from the operations of the SRAM operation circuit 100, the second input / output interface circuit 160, and the non-volatile storage operation circuit 130 to prevent conflicts between the first data read / write operation, the second data read / write operation, the data backup operation, and the data recovery operation, thereby improving data integrity and system stability.

[0110] For example, in some embodiments, the column selection circuit 110 or the isolation sub-circuit 164 may further include a switch array (not shown). For example, the column selection circuit 110 may control the coupling between the SRAM operation circuit 100 and the NVSRAM array 120 through the switch array. For example, the shift register operation circuit 161 may be coupled to the NVSRAM array 120 through the switch array of the isolation sub-circuit 164.

[0111] For example, when the SRAM operation circuit 100 performs a first data read / write operation, the column selection circuit 110 may be configured to turn on the switch array coupling the column selection circuit 110 to the NVSRAM array 120. For example, when the non-volatile memory operation circuit 130 performs a data backup operation, the column selection circuit 110 may also be configured to turn off the switch array coupling the column selection circuit 110 to the NVSRAM array 120.

[0112] For example, the switch array of the column selection circuit 110 or the isolation sub-circuit 164 can be turned on or off according to the timing logic that controls the operation of the non-volatile memory operation circuit 130, the operation of the SRAM operation circuit 100, or the operation of the shift register operation circuit 161. For example, at a specific timing, when only the SRAM operation circuit 100 is allowed to operate, the switch array of the column selection circuit 110 is turned on. For example, at a specific timing, when only the non-volatile memory operation circuit 130 is allowed to operate, the switch array of the column selection circuit 110 is turned off.

[0113] As described above, as shown in FIG3 , in some embodiments of the present disclosure, the array width of the NVSRAM array 120 can be configured as N, i.e., having N columns of memory cells (or 2N bit lines). For example, each row in the NVSRAM array 120 may include N NVSRAM cells. The NVSRAM array 120 can also be configured to have M rows of memory cells. For example, each column in the NVSRAM array 120 may include M NVSRAM cells. Each memory cell has a corresponding address for locating and accessing the memory cell. The NVSRAM array 120 can also be configured to have M rows of memory cells. For example, each row in the NVSRAM array 120 includes N memory cells, and each memory cell is configured with X bit lines (X is greater than or equal to 1). The number of bit lines in the NVSRAM memory array is X*N. If the transmission lines are bit line pairs, X can be configured as 2, and the number of bit lines in the NVSRAM memory array can be configured as 2N. In some embodiments, for example, the NVSRAM array 120 can be configured in units of words. The nonvolatile memory operation circuit 130 can be configured to be coupled to the NVSRAM array 120 through N groups of transmission lines. For example, in at least one example, when the transmission lines are bit lines or bit line pairs (e.g., bit lines BL and BLN as shown in FIG. 1 ), the nonvolatile memory operation circuit 130 can also be configured to be coupled to the NVSRAM array 120 through N or 2N bit lines.

[0114] In some embodiments of the present disclosure, as shown in FIG3 , the SRAM operation circuit 100 can be configured to be coupled to the column selection circuit 110 via the W1 group of transmission lines. The SRAM operation circuit 100 can also be configured to be coupled to the first input / output interface circuit 150 via the W1 group of transmission lines. The non-volatile storage operation circuit 130 is coupled to the NVSRAM array 120 via N groups of transmission lines. The column selection circuit 110 is coupled to the NVSRAM array 120 via N groups of transmission lines. For example, when the transmission lines are bit lines or bit line pairs (e.g., bit lines BL and BLN as shown in FIG1 ), the column selection circuit 110 can also be configured to be coupled to the NVSRAM array 120 via N or 2N bit lines. W1 and N are integers and N≥W1>1. In some embodiments, for example, when the column selection circuit 110 performs a data recovery operation, the column selection circuit 110 can also be configured to set the voltages of the 2N bit lines to the same voltage value.

[0115] The SRAM operation circuit 100 is connected to the column selection circuit 110 through the W1 group of transmission lines, and is used to locate and access specific storage cells in the NVSRAM array 120 according to the address provided by the column selection circuit 110, write data into the NVSRAM array 120, and read data from the NVSRAM array 120.

[0116] In some embodiments of the present disclosure, the shift register operation circuit 161 can be coupled to the NVSRAM array 120 through N groups of transmission lines, the input interface circuit 162 can be coupled to the shift register operation circuit 161 through W2 groups of transmission lines, and the output interface circuit 163 can be coupled to the shift register operation circuit 161 through W2 groups of transmission lines, where W2 and N are integers and N≥W2>1.

[0117] When the transmission lines are bit lines, the shift register operation circuit 161 is connected to the NVSRAM array 120 through N groups of transmission lines. When the transmission lines are bit line pairs (for example, the bit lines BL and BLN shown in Figure 1), the shift register operation circuit 161 can also be connected to the NVSRAM array 120 through 2N bit lines.

[0118] In some embodiments of the present disclosure, W1 and W2 can be used to represent the operating bit width of each word in the transmitted data. For example, when W1 and W2 are the same, the storage device 1000 can select any first input-output interface circuit 150 or input interface circuit 162 to receive data input to the storage device 1000, or select any first input-output interface circuit 150 or output interface circuit 163 to output data. For example, when W1 is greater than W2 and is the same, the input interface of the data can be determined based on the data bit width of the input storage device 1000; illustratively, W1 can be 512 bits and W2 can be 32 bits. When the data input or output of the storage device 1000 is 512 bits, the first input-output interface circuit 150 is selected to receive or output the data.

[0119] In some embodiments of the present disclosure, when the non-volatile storage operation circuit 130 performs a data backup operation, the word line driving circuit 140 can also be configured to select the SRAM storage sub-unit 122 data in I row NVSRAM cells 121 of the NVSRAM array 120 to perform a data backup operation, where I is an integer and M≥I≥1.

[0120] For example, the word line driver circuit 140 may select the SRAM storage sub-units 122 in the NVSRAM cells 121 in row 1 of the NVSRAM array 120 according to the received data backup operation instruction. Exemplarily, the word line driver circuit 140 may select the SRAM storage sub-units 122 in the NVSRAM cells 121 in rows 1 to 1, and the non-volatile storage operation circuit 130 may be configured to perform a parallel data backup operation on the data of the SRAM storage sub-units 122 in the NVSRAM cells 121 in rows 1 to 1 selected by the word line driver circuit 140, and back up all the data of the selected SRAM storage sub-units 122 in the row 1 to 1 to the non-volatile storage sub-unit 131.

[0121] In some embodiments of the present disclosure, when the column selection circuit 110 performs a data recovery operation, the word line driving circuit 140 can also be configured to select the non-volatile storage sub-unit 131 data in the J-row NVSRAM unit 121 of the NVSRM array 120 to perform a data recovery operation, where J is an integer and M≥J≥1.

[0122] For example, the word line driver circuit 140 may select the non-volatile storage sub-cells 131 in the Jth row of NVSRAM cells 121 in the NVSRAM array 120 according to the received data recovery operation instruction. Exemplarily, the word line driver circuit 140 may select the non-volatile storage sub-cells 131 in the 1st to the Jth rows of NVSRAM cells 121, and the column selection circuit 110 may be configured to perform a parallel data recovery operation on the data of the non-volatile storage sub-cells 131 in the 1st to the Jth rows of NVSRAM cells 121 selected by the word line driver circuit 140, thereby restoring all the data of the non-volatile storage sub-cells 131 in the selected Jth row to the SRAM storage sub-cells 122.

[0123] In some embodiments of the present disclosure, the SRAM operation circuit 100 is further configured to, when performing the first data read / write operation, perform the first data read / write operation on the data of the SRAM storage sub-units 122 in the W1 NVSRAM cells 121 in the i-th row of the selected NVSRAM array 120, where N≥W1≥1 and M≥i≥1.

[0124] For example, the operation bit width of the first data read / write operation of the SRAM operation circuit 100 is W1. Exemplarily, the SRAM operation circuit 100 may perform the first data read / write operation on the data of the SRAM storage sub-units 122 in W1 NVSRAM cells 121 in a row (i-th row) of the selected NVSRAM array 120 according to the received first data read / write operation instruction.

[0125] In some embodiments of the present disclosure, the second input / output interface circuit 170 is further configured to perform the second data read / write operation on the data of the SRAM storage sub-units 122 in the W2 NVSRAM cells 121 in the i-th row of the selected NVSRAM array 120, when performing the second data read / write operation. Where N ≥ W2 ≥ 1, and M ≥ i ≥ 1.

[0126] For example, the operation bit width of the second data read-write operation of the second input-output interface circuit 170 is W2. For example, the SRAM operation circuit 100 can perform a second data read-write operation on the data of the SRAM storage sub-cells 122 in the W2 NVSRAM cells 121 in a selected row (i-th row) of the NVSRAM array 120 according to a received second data read-write operation instruction.

[0127] In some embodiments of the present disclosure, the non-volatile storage operation circuit 130 is further configured to perform a data backup operation on the data of the SRAM storage sub-cells 122 in the NVSRAM cells 121 in the E rows and / or the F columns of the selected NVSRAM array 120 in the case of performing the data backup operation. Wherein E, F are integers and M≥E≥1, N≥F≥1.

[0128] For example, the operation bit width of the data backup operation of the non-volatile storage operation circuit 130 is N*M.

[0129] For example, the non-volatile storage operation circuit 130 can perform a data backup operation on the data of the SRAM storage sub-cells 122 in the selected E rows or F columns of the NVSRAM cells 121 in the M rows and N columns of the NVSRAM array 120 according to a received data backup operation instruction. Alternatively, the non-volatile storage operation circuit 130 can perform a data backup operation on all the data of the SRAM storage sub-cells 122 in the F columns of the NVSRAM cells 121 in the selected E rows of the NVSRAM array 120 in the M rows and N columns of the NVSRAM array 120.

[0130] In some embodiments of the present disclosure, the column selection circuit 110 is further configured to perform a data recovery operation on the data of the non-volatile storage sub-cells 131 in the NVSRAM cells 121 in the G rows and / or the H columns of the selected NVSRAM array 120 in the case of performing the data recovery operation. Wherein G, H are integers and M≥G≥1, N≥H≥1.

[0131] For example, the operation bit width of the data recovery operation of the column selection circuit 110 is N*M.

[0132] For example, the column selection circuit 110 can perform a data recovery operation on the data of the nonvolatile storage sub-cells 131 in the selected G rows or H columns of the NVSRAM cells 121 in the M rows and N columns of the NVSRAM cells 121 in the NVSRAM array 120 according to the received data recovery operation instruction. Alternatively, the nonvolatile storage operation circuit 130 can perform a data recovery operation on all the data of the nonvolatile storage sub-cells 131 in the selected G rows of the NVSRAM cells 121 in the H columns of the NVSRAM cells 121 in the M rows and N columns of the NVSRAM cells 121 in the NVSRAM array 120.

[0133] In the storage device 1000 of at least one embodiment of the present disclosure, the number and type of these transmission lines and other parameters can be flexibly adjusted according to requirements and hardware conditions to optimize the performance and efficiency of the storage device 1000.

[0134] In some embodiments of the present disclosure, the storage device 1000 can further include a control circuit 170 (not shown in the figure), which can be coupled with the SRAM operation circuit 100, the nonvolatile storage operation circuit 130, the first input / output interface circuit 150, the column selection circuit 110, and the second input / output interface circuit 160.

[0135] The control circuit 170 can be configured to provide corresponding control signals to the SRAM operation circuit 100, the nonvolatile storage operation circuit 130, the first input / output interface circuit 150, the column selection circuit 110, and the second input / output interface circuit 160 according to the selected working mode.

[0136] For example, the control circuit 170 in the storage device 1000 can generate corresponding control signals according to the working mode of the storage device 1000 or specific requirements, and provide the generated control signals to the corresponding operation circuits.

[0137] For example, in the case where the storage device 1000 needs to perform data reading or data writing, the control circuit 170 can provide the SRAM operation circuit 100 with a control signal for performing a first data read / write operation or provide the second input / output interface circuit 160 with a control signal for performing a second data read / write operation according to the preset conditions.

[0138] For example, in the case where the storage device 1000 needs to perform a data backup operation, the control circuit 170 can provide the nonvolatile storage operation circuit 130 with a control signal for performing a data backup operation, and the nonvolatile storage operation circuit 130 can perform a data backup operation on the data in the selected SRAM storage sub-cells 122 according to the received data backup operation control signal.

[0139] For example, in the case that the storage device 1000 needs to perform a data recovery operation, the control circuit 170 can provide a control signal for performing the data recovery operation to the column selection circuit 110, and the column selection circuit 110 can perform the data recovery operation on the data in the selected non-volatile storage subunit 131 according to the received data recovery operation control signal.

[0140] For example, the control circuit 170 can also monitor the working state or health state of the storage device 1000, such as in the case that the first input / output interface circuit 150 fails, the control circuit 170 can provide a second data read / write operation control signal to the second input / output interface circuit 160 when the storage device 1000 needs to perform a data read / write operation. The control circuit 170 can also take appropriate measures to repair the failed circuit or report error information, so as to improve the reliability and stability of the storage device 1000.

[0141] In at least one embodiment of the present disclosure, the control circuit 170 can improve the operating efficiency of the storage device 1000 in different working modes through connection or interaction with other circuits, components of the storage device 1000. The control circuit 170 can also adjust the working state and parameters of each circuit, component as needed to achieve flexible control and management of the storage device 1000.

[0142] FIG. 5 shows a flowchart of a control method of a storage device according to at least one embodiment of the present disclosure. As shown in FIG. 5, the method can include steps S310-S313.

[0143] Step S310: Determine that the SRAM operation circuit performs a first data read / write operation.

[0144] Step S311: Disconnect the coupling between the non-volatile storage operation circuit and the NVSRAM array.

[0145] Step S312: Control the column selection circuit to connect the coupling between the SRAM operation circuit and the NVSRAM array.

[0146] Step S313: Control the second input / output interface circuit to disconnect the coupling with the NVSRAM array.

[0147] In the case that the SRAM operation circuit performs a first data read / write operation, it is necessary to isolate the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit to prevent mutual influence and affect the reliability of the first data read / write operation. Therefore, it is necessary to disconnect the coupling between the non-volatile storage operation circuit and the NVSRAM array, and control the column selection circuit to connect the coupling between the SRAM operation circuit and the NVSRAM array, so as to isolate the non-volatile storage operation circuit and the SRAM operation circuit.

[0148] For step S311, in one example, for example, the non-volatile storage operation circuit stops operation of the non-volatile storage operation circuit according to the received instruction of the SRAM operation circuit performing the first data read-write operation.

[0149] For step S312, in one example, for example, in the case where the column selection circuit includes a switch array, step S312 further includes step S3121 (not shown in the figure).

[0150] Step S3121: control the column selection circuit to turn on the switch array coupled with the NVSRAM array. The method of isolating the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit can refer to the related description above, which will not be repeated here.

[0151] For step S313, in one example, for example, the second input-output interface circuit stops performing the second data read-write operation according to the received instruction of the SRAM operation circuit performing the first data read-write operation, and controls the second input-output interface circuit to disconnect the coupling with the NVSRAM array to avoid affecting the operation of the SRAM operation circuit.

[0152] In some embodiments, the method shown in FIG. 5 can further include step S314 (not shown in the figure). Step S314: control the column selection circuit to stop the data recovery operation.

[0153] In the case of determining that the SRAM operation circuit performs the first data read-write operation, it is necessary to isolate the data recovery operation of the column selection circuit and the operation of the SRAM operation circuit to avoid mutual influence and affect the reliability of data read-write. Therefore, it is necessary to control the column selection circuit to stop the data recovery operation, so as to isolate the data recovery operation of the column selection circuit and the first data read-write operation of the SRAM operation circuit.

[0154] FIG. 6 shows a flowchart of a control method of a storage device according to at least one embodiment of the present disclosure. As shown in FIG. 6, the method can include steps S320-S323.

[0155] Step S320: determine that the second input-output interface circuit performs the second data read-write operation.

[0156] Step S321: disconnect the coupling between the non-volatile storage operation circuit and the NVSRAM array.

[0157] Step S322: connect the coupling between the second input-output interface circuit and the NVSRAM array.

[0158] Step S323: control the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array.

[0159] In the case of determining that the second input / output interface circuit performs the second data read / write operation, the operation of the non-volatile storage operation circuit and the operation of the second input / output interface circuit need to be isolated from each other to avoid affecting the reliability of the second data read / write operation. Therefore, the coupling between the non-volatile storage operation circuit and the NVSRAM array needs to be disconnected, and the coupling between the second input / output interface circuit and the NVSRAM array needs to be connected, so as to isolate the operation of the non-volatile storage operation circuit and the second input / output interface circuit.

[0160] For step S321, in one example, for example, the non-volatile storage operation circuit can stop the operation of the non-volatile storage operation circuit according to the received instruction of the second input / output interface circuit performing the second data read / write operation.

[0161] For step S322, in one example, for example, in the case where the second input / output interface circuit includes an isolation sub-circuit, step S322 further includes step S3221 (not shown in the figure).

[0162] Step S3221: control the isolation sub-circuit to turn on the coupling between the second input / output interface circuit and the NVSRAM array. The method of isolating the operation of the non-volatile storage operation circuit and the operation of the second input / output interface circuit can refer to the related description above, which will not be repeated here.

[0163] For step S323, in one example, for example, the column selection circuit disconnects the coupling between the SRAM operation circuit and the NVSRAM array according to the received instruction of the second input / output interface circuit performing the second data read / write operation, so as to avoid affecting the second data read / write operation of the second input / output interface circuit.

[0164] In some embodiments, the method shown in FIG. 6 can further include step S234 (not shown in the figure). Step S234: control the column selection circuit to stop the data recovery operation.

[0165] In the case of determining that the second input / output interface circuit performs the second data read / write operation, the data recovery operation of the column selection circuit and the operation of the second input / output interface circuit need to be isolated from each other to avoid affecting the reliability of the data read / write. Therefore, the column selection circuit needs to be controlled to stop the data recovery operation, so as to isolate the data recovery operation of the column selection circuit and the second data read / write operation of the second input / output interface circuit.

[0166] FIG. 7 shows a flowchart of another control method of a storage device provided by at least one embodiment of the present disclosure. As shown in FIG. 7, the control method can include steps S330-S333.

[0167] Step S330: determine that the non-volatile storage operation circuit performs data backup.

[0168] Step S331: connecting the coupling between the non-volatile storage operation circuit and the NVSRAM array.

[0169] Step S332: controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array.

[0170] Step S333: controlling the second input / output interface circuit to disconnect the coupling with the NVSRAM array.

[0171] In the case of determining that the non-volatile storage operation circuit performs the data backup operation, it is necessary to isolate the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit and the operation of the second input / output interface circuit from each other so as not to affect each other and further affect the reliability of the data backup operation. Therefore, it is necessary to connect the coupling between the non-volatile storage operation circuit and the NVSRAM array, control the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array, and control the second input / output interface circuit to disconnect the coupling with the NVSRAM array, so as to isolate the operation of the non-volatile storage operation circuit and the SRAM operation circuit and the second input / output interface circuit.

[0172] For step S332, in one example, for example, the column selection circuit stops the operation of the column selection circuit according to the received instruction that the non-volatile storage operation circuit performs the data backup operation. For another example, in the case that the column selection circuit further comprises a switch array, step S332 further comprises step S3321 (not shown in the figure). Step S3321: controlling the column selection circuit to disconnect the switch array coupled with the NVSRAM array. The method of isolating the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit can refer to the related description hereinabove, which will not be described herein again.

[0173] For step S333, in one example, for example, the second input / output interface circuit stops the operation of the second input / output interface circuit according to the received instruction that the non-volatile storage operation circuit performs the data backup operation. For another example, in the case that the second input / output interface circuit further comprises an isolation sub-circuit, step S333 further comprises step S3331 (not shown in the figure). Step S3331: controlling the isolation sub-circuit to disconnect the coupling between the second input / output interface circuit and the NVSRAM array. The method of isolating the operation of the non-volatile storage operation circuit and the operation of the second input / output interface circuit can refer to the related description hereinabove, which will not be described herein again.

[0174] In some embodiments, the method shown in FIG. 7 can further comprise step S334 (not shown in the figure). Step S334: controlling the column selection circuit to stop the data recovery operation.

[0175] In the case where it is determined that the column selection circuit performs the data recovery operation, the data recovery operation of the column selection circuit and the operation of the non-volatile storage operation circuit need to be isolated from each other so as not to affect each other and further affect the reliability of the data backup. Therefore, the column selection circuit needs to be controlled to stop the data recovery operation so as to isolate the data recovery operation and the operation of the non-volatile storage operation circuit. For example, in the case where the column selection circuit includes a data recovery operation sub-circuit, step S334 can further include controlling the data recovery operation sub-circuit to stop performing the data recovery operation.

[0176] FIG. 8 shows a flowchart of another control method of a storage device according to at least one embodiment of the present disclosure. As shown in FIG. 8, the control method can include steps S340-S343.

[0177] Step S340: determining that the column selection circuit performs the data recovery operation.

[0178] Step S341: disconnecting the non-volatile storage operation circuit from the NVSRAM array.

[0179] Step S342: controlling the column selection circuit to disconnect the SRAM operation circuit from the NVSRAM array.

[0180] Step S343: controlling the second input / output interface circuit to disconnect from the NVSRAM array.

[0181] In the case where it is determined that the column selection circuit performs the data recovery operation, the operation of the non-volatile storage operation circuit, the operation of the SRAM operation circuit, the operation of the second input / output interface circuit and the data recovery operation of the column selection circuit need to be isolated from each other so as not to affect each other and further affect the reliability of the data recovery operation. Therefore, the non-volatile storage operation circuit needs to be disconnected from the NVSRAM array, the column selection circuit needs to be controlled to disconnect the SRAM operation circuit from the NVSRAM array, and the second input / output interface circuit needs to be controlled to disconnect from the NVSRAM array, so as to isolate the operation of the non-volatile storage operation circuit, the operation of the SRAM operation circuit, the operation of the second input / output interface circuit and the data recovery operation of the column selection circuit.

[0182] For step S342, in one example, for example, in the case where the column selection circuit further includes a switch array, step S342 further includes step S344 (not shown in the figure). Step S344: controlling the column selection circuit to disconnect the switch array coupled with the NVSRAM array. The method of isolating the operation of the non-volatile storage operation circuit and the data recovery operation of the column selection circuit can be referred to the relevant description above, which will not be described herein again.

[0183] For step S343, in one example, the second input / output interface circuit stops operation of the second input / output interface circuit according to the received instruction of the non-volatile storage operation circuit to perform the data backup operation. For another example, in the case that the second input / output interface circuit further comprises an isolation sub-circuit, step S343 further comprises step S345 (not shown in the figure). Step S345: control the isolation sub-circuit to disconnect the switch coupling the second input / output interface circuit and the NVSRAM array. The method of the data recovery operation of the isolation column selection circuit and the operation of the second input / output interface circuit can be referred to the relevant description above, and will not be described here again.

[0184] In some embodiments of the present disclosure, the control method of the storage device can further comprise steps S400-S420 (not shown in the figure).

[0185] Step S400: receive an operation mode signal.

[0186] Step S410: generate a control signal for the first data read / write operation, the data backup operation, the data recovery operation or the second data read / write operation according to the operation mode signal.

[0187] Step S420: provide the control signal to the SRAM operation circuit, the non-volatile storage operation circuit, the first input / output interface circuit, the column selection circuit or the second input / output interface circuit correspondingly.

[0188] For step S400, the control circuit receives an operation mode signal, which can be used to indicate which operation mode the storage device performs, for example, the operation mode signal can be used to indicate that the storage device performs data read / write operation, data backup operation or data recovery operation, etc.

[0189] For step S410, after the control circuit receives the working mode signal, the control circuit can generate corresponding control signals according to the received working mode signal, for example, generate control signals for the first data read-write operation, the data backup operation, the data recovery operation or the second data read-write operation. For example, the control signal for the first data read-write operation can include controlling the SRAM operation circuit to perform the first data read-write operation; for example, the control signal for the first data read-write operation can also include controlling the non-volatile storage operation circuit to disconnect the coupling with the NVSRAM array. For example, the control signal for the data backup operation can include controlling the non-volatile storage operation circuit to perform the data backup operation; for example, the control signal for the data backup operation can also include controlling the SRAM operation circuit and the second input-output interface circuit to disconnect the coupling with the NVSRAM array; for example, the control signal for the data recovery operation can include controlling the column selection circuit to perform the data recovery operation, controlling the non-volatile storage operation circuit to disconnect the coupling with the NVSRAM array, controlling the second input-output interface circuit to disconnect the coupling with the NVSRAM array, and controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array.

[0190] For step S420, the control circuit provides the generated control signals to the corresponding operation circuits. For example, the control circuit can provide the control signal for the first data read-write operation to the SRAM operation circuit; for example, the control circuit can also provide the control signal for the first data read-write operation or the data recovery operation to the non-volatile storage operation circuit. For example, the control circuit can provide the control signal for the data backup operation to the non-volatile storage operation circuit; for example, the control circuit can also provide the control signal for the data backup operation to the SRAM operation circuit and the second input-output interface circuit. For example, the control circuit can provide the control signal for the second data read-write operation to the second input-output interface circuit; for example, the control circuit can also provide the control signal for the second data read-write operation to the non-volatile storage operation circuit. For example, the control circuit can also provide the control signal for the data recovery operation to the column selection circuit.

[0191] In at least one embodiment of the present disclosure, the control circuit generates corresponding control signals according to the received working mode signal, and provides each control signal to the corresponding operation circuit, so as to improve the reliability and efficiency of data read-write, backup, recovery and other operations.

[0192] FIG. 9 shows a flowchart of a method of operating a storage device according to at least one embodiment of the present disclosure. As shown in FIG. 9, in some embodiments of the present disclosure, the method of operating the storage device includes steps S500-S560. The method of operating the storage device can be used in the storage device shown in FIG. 2 or FIG. 3, for example.

[0193] Step S500: Power on the storage device.

[0194] For step S500, the storage device starts to power on, i.e., the storage device is connected to a power supply and starts to operate. The process can be controlled by a power supply circuit, which can provide the required voltage and current to the storage device to ensure its normal operation.

[0195] Step S510: Determine whether to perform data recovery.

[0196] For step S510, the storage device can determine whether to perform a data recovery operation according to a received instruction or the state of the electronic device. If data recovery is needed, proceed to step S520; otherwise, proceed to step S530.

[0197] Step S520: Perform data recovery.

[0198] For step S520, data previously backed up to the RRAM storage subunit is restored to the SRAM storage subunit, for example. This step can be controlled by a column selection circuit, for example. In some embodiments, step S520 further includes steps S700-S750 shown in FIG. 11 (described below), for example.

[0199] Step S530: Perform data read / write.

[0200] For step S530, this step can be controlled by an SRAM operation circuit or a shift register operation circuit, for example. For example, the SRAM operation circuit (in combination with the selection operation of the word line driving circuit, the column selection circuit) reads data in the SRAM storage subunit of the NVSRAM array. For example, the shift register operation circuit (in combination with the selection operation of the word line driving circuit) reads data in the SRAM storage subunit of the NVSRAM array.

[0201] Step S540: Determine whether to perform data backup.

[0202] For step S540, the storage device determines whether to perform a data backup operation. If data backup is needed, proceed to step S550; otherwise, proceed to step S560.

[0203] Step S550: Perform data backup.

[0204] For step S550, the storage device performs a data backup operation, which backs up the data in the SRAM storage subunit in the storage device to the RRAM storage subunit. This step can be controlled by the non-volatile storage operation circuit. For example, in some embodiments, step S550 further includes steps S600-S650 shown in FIG. 10 (to be described below).

[0205] Step S560: Determine whether a power failure occurs.

[0206] For step S560, the electronic device determines whether a power failure occurs in the storage device. If a power failure occurs, the operation of the storage device ends; otherwise, it returns to step S510 to continue determining whether a data recovery operation is needed. This process ensures that the storage device can continue to operate in a normal working state, while protecting the integrity of the data in the case of a power failure.

[0207] FIG. 10 shows a flowchart of a data backup method of a storage device according to at least one embodiment of the present disclosure.

[0208] As shown in FIG. 10, the data backup method includes steps S600-S650. The data backup method can be used in a storage device such as shown in FIG. 2 or FIG. 3, for example.

[0209] Step S600: Perform data read / write.

[0210] For step S600, in the case of data writing, the data can be written into the SRAM storage subunit in the NVSRAM unit through the SRAM operation circuit, or the data can be written into the SRAM storage subunit in the NVSRAM unit through the shift register operation circuit. In the case of data reading, the data stored in the SRAM storage subunit can be read through the SRAM operation circuit (which can be combined with the selection operation of the word line driving circuit and the column selection circuit) and output through the first input / output interface circuit. Alternatively, the data stored in the SRAM storage subunit can be read through the shift register operation circuit (which can be combined with the selection operation of the word line driving circuit) and output through the output interface circuit.

[0211] Step S610: Determine whether a data backup operation is needed.

[0212] For step S610, the storage device determines whether a data backup operation is needed according to the received instruction, for example. If a data backup operation is needed, step S620 is performed; otherwise, step S600 is continued to continue the data read / write operation.

[0213] Step S620: Select the Ith row of NVSRAM unit.

[0214] For step S620, in some embodiments of the present disclosure, in case the storage device determines to perform the data backup operation, the word line driving circuit determines the I rows of data in the NVSRAM cells according to the address information. I is an integer and 0

[0215] Step S630: backup the data in the selected I rows of SRAM storage sub-cells to the RRAM storage sub-cells simultaneously.

[0216] For step S630, the non-volatile storage operation circuit performs parallel operation to backup the I rows of data in the determined SRAM storage sub-cells to the RRAM storage sub-cells simultaneously. For example, the non-volatile storage operation circuit backups the data in the selected 1st to Ith rows of SRAM storage sub-cells to the RRAM storage sub-cells.

[0217] Step S640: determine whether the data backup is completed.

[0218] For step S640, the non-volatile storage operation circuit determines whether the data backup is completed. If the backup is not completed, step S650 is performed; if it is determined that the data backup is completed, the data backup operation is ended.

[0219] Step S650: increase the row address of the SRAM storage sub-cells by I again. Then the data backup operation of steps S620-S640 is continued.

[0220] For step S650, the word line driving circuit updates the row address of the SRAM storage sub-cells and increases the row address by I again so as to continue the next step of data backup operation. For example, the non-volatile storage operation circuit backups the data in the determined (I+1)th to 2th rows of SRAM storage sub-cells to the RRAM storage sub-cells. Then the data backup operation of steps S620-S640 is continued until all the data to be backed up is backed up to the RRAM storage sub-cells.

[0221] FIG. 11 shows a flow diagram of a data recovery method of a storage device according to at least one embodiment of the present disclosure. As shown in FIG. 11, the data recovery method includes steps S700-S750. The data recovery method can be used in the storage device shown in FIG. 2 or FIG. 3, for example.

[0222] Step S700: determine whether to perform a data recovery operation.

[0223] For step S700, in some embodiments of the present disclosure, the storage device determines whether to perform the data recovery operation according to the received instruction or a preset instruction. If it is determined to perform the data recovery operation, step S710 is performed; if it is determined not to perform the data recovery operation, step S740 is directly performed.

[0224] Step S710: Selecting I rows of NVSRAM cells.

[0225] For step S710, the word line driving circuit determines the data in the I rows of NVSRAM cells according to the address information. I is an integer and 0

[0226] Step S720: Simultaneously recovering the data of the selected I rows of RRAM storage sub-cells into the SRAM storage sub-cells.

[0227] For step S720, the column selection circuit performs parallel operation to recover the data in the determined I rows of RRAM storage sub-cells into the SRAM storage sub-cells. Then, step S730 is performed.

[0228] Step S730: Determining whether the data recovery operation is completed.

[0229] For step S730, if the data recovery operation is not completed, step S750 is performed; if the data recovery operation is completed, step S740 is performed.

[0230] Step S740: The SRAM operation circuit or the shift register operation circuit performs read and write operations on the data in the SRAM storage sub-cells.

[0231] For step S740, for example, after the data recovery operation is completed, the data in the SRAM storage sub-cells can be read by the SRAM operation circuit, and the read data can be input into the first input and output interface circuit for subsequent processing and use. Alternatively, the data in the SRAM storage sub-cells can be read by the shift register operation circuit, and the read data can be input into the output interface circuit for subsequent processing and use. For example, the data in the SRAM storage sub-cells can be read by the SRAM operation circuit or the shift register operation circuit according to the bit width of the data, for example, the first input and output interface circuit can be preset to transmit high-bit-width data, and the input interface circuit and the output interface circuit can be preset to transmit low-bit-width data. Therefore, when the transmitted data is high-bit-width data, the data in the SRAM storage sub-cells can be read by the SRAM operation circuit, and when the transmitted data is low-bit-width data, the data in the SRAM storage sub-cells can be read by the shift register operation circuit.

[0232] Step S750: The row address is increased by I rows again.

[0233] For step S750, in the case that the data recovery operation is not completed, the row address of the data in the RRAM storage subunit that needs to be recovered is updated, the row address is increased by I rows again, so as to continue the next step of data recovery operation. For example, the column selection circuit recovers the data in the determined (I+1)th row to 2Ith row RRAM storage subunit into the SRAM storage subunit. Then, the data recovery operation of steps S710-S730 will be continued until all the data that needs to be recovered is recovered into the SRAM storage subunit.

[0234] Some embodiments of the present disclosure provide a storage device, an electronic device comprising the storage device, and a storage device control method.

[0235] The storage device comprises an NVSRAM array, an SRAM operation circuit, a non-volatile storage operation circuit, an error detection and correction circuit, a first input and output interface circuit, a column selection circuit, and a second input and output interface circuit, wherein the error detection and correction circuit is coupled with the SRAM operation circuit, the SRAM operation circuit is coupled with the column selection circuit, the column selection circuit is coupled with the NVSRAM array, and the non-volatile storage operation circuit is coupled with the NVSRAM array.

[0236] The NVSRAM array comprises a plurality of NVSRAM units arranged in an array, and each NVSRAM unit comprises an SRAM storage subunit and a non-volatile storage subunit, and the non-volatile storage subunit is configured to back up the data stored in the SRAM storage subunit.

[0237] The non-volatile storage operation circuit is configured to perform a data backup operation on the SRAM storage subcell data in the selected NVSRAM cell in the NVSRAM array; the SRAM operation circuit is configured to perform a first data read-write operation on the SRAM storage subcell data; the column selection circuit is configured to perform a data recovery operation on the non-volatile storage subcell data; the column selection circuit is further configured to select the object cell column in the NVSRAM array that needs to be operated in the case of performing the data recovery operation or in the case of the first data read-write operation performed by the SRAM operation circuit; the first input-output interface circuit is coupled with the SRAM operation circuit and is configured to provide the received first input data to the SRAM operation circuit and receive the first output data to be output from the SRAM operation circuit; the error detection and correction circuit is configured to encode and decode the target data and determine whether the target data has an error and correct the error; the column selection circuit is further configured to isolate the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit, and isolate the first data read-write operation, the second data read-write operation, and the data recovery operation; the second input-output interface circuit is coupled with the NVSRAM array and is configured to perform a second data read-write operation on the NVSRAM array.

[0238] The storage device backs up the data of the SRAM storage subcell by using the non-volatile storage subcell, detects and corrects the erroneous storage data by using the error detection and correction circuit, isolates the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit by using the column selection circuit, and isolates the first data read-write operation, the second data read-write operation, and the data recovery operation, and transmits the input or output data of the storage device by using the first input-output interface circuit or the second input-output interface circuit, thereby improving the reliability and flexibility of data read-write, backup, and recovery.

[0239] FIG. 12 shows a schematic block diagram of a storage device provided in at least one embodiment of the present disclosure.

[0240] In some embodiments of the present disclosure, as shown in FIG. 12, the storage device 2000 includes an NVSRAM array 220, an SRAM operation circuit 200, a non-volatile storage operation circuit 230, a column selection circuit 210, a first input-output interface circuit 250, a second input-output interface circuit 270, and an error detection and correction circuit 260.

[0241] The error detection and correction circuit 260 is coupled with the SRAM operation circuit 200, the SRAM operation circuit 200 is coupled with the column selection circuit 210, the column selection circuit 210 is coupled with the NVSRAM array 220, the non-volatile storage operation circuit 230 is coupled with the NVSRAM array 220, the first input-output interface circuit 250 is coupled with the SRAM operation circuit 200, and the second input-output interface circuit 270 is coupled with the NVSRAM array 220.

[0242] In the present disclosure, "coupling" is used to refer to a description of the connection between objects, when the coupling between the description objects is established, signal transmission can be carried out, and when the coupling between the description objects is disconnected, signal connection cannot be carried out, and the coupling can be realized by means such as electrical connection. For example, in the embodiments of the present disclosure, "coupling" can include the connection of two or more electronic elements or circuits in a certain way, so that the signals between them are transmitted to each other. For example, two storage subunits can be directly connected, and the transmission of information can be realized by signal or energy transmission, or two storage subunits are connected through other circuit elements, such as through resistors, capacitors, switches, optoelectronic elements, etc. or transmission line networks, etc. to realize the transmission of signals.

[0243] The NVSRAM array 220 includes a plurality of NVSRAM units 221 arranged in an array, and each NVSRAM unit 221 includes an SRAM storage subunit 222 and a non-volatile storage subunit 231 configured to back up data stored by the SRAM storage subunit 222. The array formed by the plurality of NVSRAM units 221 includes a plurality of rows and a plurality of columns. For example, the plurality of NVSRAM units 221 can form a storage array including M rows and N columns, where M and N are integers and 1≤M, 1≤N. The NVSRAM unit 221 may, for example, take the form shown in FIG. 1, but embodiments of the present disclosure are not limited to this specific form.

[0244] The NVSRAM unit 221 of the NVSRAM array 220 combines the characteristics of the SRAM storage subunit and the non-volatile storage subunit. The SRAM storage subunit 222 can be configured to store data and can quickly read and write data. The non-volatile storage subunit 231 is configured to back up data stored by the SRAM storage subunit 222 to prevent data stored in the SRAM storage subunit 222 from being lost in the event of power failure or system crash.

[0245] For example, the non-volatile storage subunit 231 can include RRAM, FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), PCM (Phase Change Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), PRAM, flash memory, and the like. Corresponding to different types of non-volatile storage subunits 231, the non-volatile storage operation circuit 230 in the embodiments of the present disclosure is adjusted accordingly, and the present disclosure is not limited thereto. For example, when the non-volatile storage subunit 231 includes an RRAM storage subunit, the non-volatile storage operation circuit 230 can include an RRAM operation circuit.

[0246] The non-volatile storage operation circuit 230 is configured to perform a data backup operation on the data in the SRAM storage subunit 222 in the selected NVSRAM cell 221 in the NVSRAM array 220.

[0247] In some embodiments, the non-volatile storage operation circuit 230 can communicate with a plurality of SRAM storage subunits 222, and the non-volatile storage operation circuit 230 can perform a data backup operation on the data in the SRAM storage subunit 222 as needed, such as when the electronic device detects that a certain application program fails or abnormally, the non-volatile storage operation circuit 230 performs a backup operation. For example, the non-volatile storage operation circuit 230 can also perform a data backup operation on the data in the SRAM storage subunit 222 in response to a backup instruction, or perform a periodic data backup operation on the SRAM storage subunit 222 based on a preset time, or perform a real-time data backup operation on the SRAM storage subunit 222.

[0248] To improve the efficiency of data backup, the non-volatile storage operation circuit 230 can use a parallel processing method to simultaneously perform a data backup operation on a plurality of selected SRAM storage subunits 222. For example, the non-volatile storage operation circuit 230 can simultaneously perform a data backup operation on the data in a row of SRAM storage subunits 222, or the non-volatile storage operation circuit 230 can simultaneously perform a data backup operation on the data in multiple rows of SRAM storage subunits 222.

[0249] To improve the reliability and stability of data backup, at least one embodiment of the present disclosure also takes some safety design to improve the redundancy of the non-volatile storage operation circuit 230, for example, the non-volatile storage operation circuit 230 can take a double backup mechanism, the data of each SRAM storage subunit 222 can be backed up twice or more times to reduce the risk of data loss.

[0250] For example, in at least one example, the non-volatile storage operation circuit 230 can adopt an ECC (Error Checking and Correcting) mechanism, which can add additional check bits when data is backed up to the non-volatile storage subunit 231, so as to detect and correct errors when data is read. The ECC mechanism can improve the reliability of the data and reduce the risk of data loss due to hardware failure or data corruption.

[0251] For example, in at least one example, the non-volatile storage operation circuit 230 can also adopt a CRC (Cyclic Redundancy Check) mechanism to calculate the CRC value of the data before and after the data backup operation to ensure the integrity of the data. If the CRC value does not match, the non-volatile storage operation circuit 230 can take appropriate measures to recover the data or handle errors. Other embodiments of the present disclosure can also adopt other data checking and error correction mechanisms, including but not limited to parity check, SED (Single-bit Error Detection), SEC (Single-bit Error Correction), DED (Double-bit Error Detection), or FED (Fatal Error Detection), etc. Embodiments of the present disclosure are not limited thereto.

[0252] In some embodiments of the present disclosure, the first input / output interface circuit 250 is configured to provide the received first input data to the SRAM operation circuit 200 and receive the first output data to be output from the SRAM operation circuit 200. The SRAM operation circuit 200 is configured to perform first data read / write operations on the SRAM storage subunit 222. The second input / output interface circuit 270 is configured to perform second data read / write operations on the NVSRAM array 220.

[0253] Herein, the first data read-write operation refers to the data read-write operation of the SRAM operation circuit 200 on the SRAM storage sub-unit 222. The second data read-write operation refers to the data read-write operation of the second input-output interface circuit 270 on the SRAM storage sub-unit 222. For example, the first input-output interface circuit 250 can be configured to receive the first input data of the input storage device 2000 and provide the first input data to the SRAM operation circuit 200. When the SRAM operation circuit 200 needs to perform data output, the first input-output interface circuit 250 can be configured to receive the first output data to be output from the SRAM operation circuit 200.

[0254] For example, the storage device 2000 can determine the input of the data of the input storage device 2000 into the storage device 2000 from the first input-output interface circuit 250 or from the second input-output interface circuit 270 according to the received control instruction, the data bit width or data type of the input storage device 2000, the working conditions of the circuits in the storage device 2000, etc. For example, in the case of the data recovery operation of the column selection circuit 210, the data of the input storage device 2000 can be input from the second data input-output interface circuit 260. For example, in the case of the second data read-write operation of the second input-output interface circuit 270, the data of the input storage device 2000 can be input from the second input-output interface circuit 270. For example, the bit width of the input or output data of the first input-output interface circuit 250 and the second input-output interface circuit 270 can be preset, for example, the data bit width of the input or output of the first input-output interface circuit 250 can be greater than that of the second input-output interface circuit 270; for example, the data bit width of the input or output of the first input-output interface circuit 250 is 32 bits, and the data bit width of the input or output of the second input-output interface circuit 270 is 512 bits, then when the data bit width of the input storage device 2000 is 32 bits, the data can be input from the first input-output interface circuit 250, and the embodiments of the present disclosure are not limited thereto.

[0255] For example, the first data read-write operation of the selected SRAM storage sub-unit 222 by the SRAM operation circuit 200 or the second data read-write operation of the selected SRAM storage sub-unit 222 by the second input-output interface circuit 250 can be determined according to the received read-write instruction, the data bit width or data type, the working conditions of the circuits in the storage device 2000, etc.

[0256] For example, the SRAM operation circuit 200 performs a first data read / write operation on the selected SRAM storage sub-unit 222 by receiving a corresponding data read / write instruction. When data in the non-volatile storage sub-unit 231 needs to be restored to the SRAM storage sub-unit 222, the column selection circuit 210 performs a data restoration operation, and the SRAM operation circuit 200 reads the data in the SRAM storage sub-unit 222 and inputs the data into the error detection and correction circuit 260.

[0257] In some embodiments, the column selection circuit 210 is configured to select a target cell column in the NVSRAM array 220 that needs to be operated in the case of performing a data restoration operation or in the case of the SRAM operation circuit 200 performing a first data read / write operation. For example, in the case of the SRAM operation circuit 200 performing a first data read / write operation or in the case of the column selection circuit 210 performing a data restoration operation, the column selection circuit 210 responds to the received address signal and converts it into an electrical signal to select a corresponding target cell column in the NVSRAM array 220; for example, the column selection circuit 210 can select a corresponding target cell column in the NVSRAM array 220 according to an instruction that the SRAM operation circuit 200 needs to perform a first data read / write operation or the column selection circuit 210 needs to perform a data restoration operation.

[0258] Here, the "target cell column" is used to refer to a column of storage cells that is a target of an operation, which can be any column in a plurality of storage arrays. The "address signal" includes a row selection signal and a column selection signal, and the row selection signal is used for row addressing by a word line driving circuit (to be described below) and the column selection signal is used for column addressing by the column selection circuit.

[0259] As described above, in the process of the non-volatile storage operation circuit 230 performing a data backup operation, or in the process of the SRAM operation circuit 200 performing a first data read / write operation or the column selection circuit 210 performing a data restoration operation, or in the process of the second input / output interface circuit 270 performing a second data read / write operation, the operation of the non-volatile storage operation circuit 230, the operation of the SRAM operation circuit 200, the operation of the second input / output interface circuit 270, and the data restoration operation of the column selection circuit 210 can affect each other, thereby affecting the stability of data backup and data restoration.

[0260] In at least some embodiments of the present disclosure, the column selection circuit 210 can also be configured to isolate the operation of the SRAM operation circuit 200 and the operation of the non-volatile storage operation circuit 230. For example, the second input / output interface circuit 270 can also be configured to isolate the operation of the second input / output interface circuit 270 and the operation of the non-volatile storage operation circuit 230.

[0261] For example, the non-volatile storage operation circuit 230 and the SRAM operation circuit 200 can be respectively provided with independent column selection circuits 210 to reduce the interference between them, and the independent column selection circuits 210 can have different circuit structures and elements to adapt to the characteristics and operation requirements of the non-volatile storage operation circuit 230 and the SRAM operation circuit 200.

[0262] For example, the column selection circuit 210 can also not perform the data recovery operation in the case that the SRAM operation circuit 200 performs the first data read-write operation, the second input-output interface circuit 270 performs the second data read-write operation, or the non-volatile storage operation circuit 230 performs the data backup operation, so as to isolate the first data read-write operation, the second data read-write operation, the data backup operation, and the data recovery operation.

[0263] In some embodiments, the non-volatile storage operation circuit 230, the SRAM operation circuit 200, or the second input-output interface circuit 270 can also be power-isolated, such as being respectively provided with independent power supplies or power supply lines. For example, a voltage stabilizer can also be added to the non-volatile storage operation circuit 230, the SRAM operation circuit 200, or the second input-output interface circuit 270 to improve the power supply stability of the circuit. For example, an optical coupler can also be used to transmit the data of the non-volatile storage operation circuit 230, the SRAM operation circuit 200, or the second input-output interface circuit 270 through optical signals. For example, the operation of the non-volatile storage operation circuit 230, the operation of the SRAM operation circuit 200, or the operation of the second input-output interface circuit 270 can also be controlled through logic design, such as allowing only the operation of the non-volatile storage operation circuit 230, or allowing only the operation of the SRAM operation circuit 200, or allowing only the operation of the second input-output interface circuit 270 in a specific situation, and prohibiting the non-volatile storage operation circuit 230 and the SRAM operation circuit 200 or the second input-output interface circuit 270 from operating at the same time.

[0264] In some embodiments, as shown in FIG. 12, the first input-output interface circuit 250 is configured to provide the received first input data to the SRAM operation circuit 200 and receive the first output data to be output from the SRAM operation circuit 200; and the error detection and correction circuit 260 is configured to encode and decode the target data and determine whether the target data has an error and correct the error.

[0265] In at least some embodiments of the present disclosure, for example, the error correction circuit 260 can encode data by using a parity code, can add an extra data check bit to the data so that the number of 1s in the entire byte is even (even parity) or odd (odd parity), and can check the check bit when the error correction circuit 260 receives the data to be checked. For example, the error correction circuit 260 can also encode data by using a Hamming code, can divide the data into multiple groups, and add a check bit to each group so that the erroneous data in each group can be detected and corrected. For another example, the error correction circuit 260 can also encode data by using a cyclic redundancy check (CRC) method, can add a redundant check code to the data, and can treat the data as a binary polynomial, use a generator polynomial to perform a modulo 2 division operation on the binary polynomial, and obtain a remainder as the CRC check code.

[0266] In at least some embodiments of the present disclosure, for example, the error correction circuit 260 can also include a data encoder and a data decoder. The data encoder can be configured to convert input data into a specific encoding format and increase the redundancy information of the data, such as a parity code, a Hamming code, a cyclic redundancy check code, and the like. The data decoder can be configured to decode the received encoded data into original data, and at the same time, can also perform error detection on the data, such as by using a parity check, a CRC check, and the like.

[0267] In at least some embodiments of the present disclosure, for example, the error correction circuit 260 can also include error detection and correction logic and control logic. The error detection and correction logic can perform error detection on the decoded data and determine whether the error can be corrected according to the encoding method. For example, if a parity code is used, the logic can check the check bit and determine the error bit, and then correct the error bit. For some complex error conditions, multiple error corrections or degradation processes can be required. The control logic is used to control the entire process of data encoding, transmission, decoding, and error correction, and can also be used to interact with other circuits, such as sending a control signal to the column selection circuit 210 to control data transmission.

[0268] In at least some embodiments of the present disclosure, the error correction circuit 260 can also be configured to: encode target data input from the SRAM operation circuit 200 to the error correction circuit 260 in the case that the non-volatile storage operation circuit 230 performs a data backup operation; and determine whether the target data read from the NVSRAM array 220 by the SRAM operation circuit 200 and input to the error correction circuit 260 has an error and corrects the error in the case that the column selection circuit 210 completes a data recovery operation.

[0269] In one example of the present disclosure, for example, in the case where a data backup operation is required according to system instructions, the SRAM operation circuit 200 reads data from the SRAM storage subunit 222 of the NVSRAM array and inputs the data to the error correction circuit 260. After receiving the data from the SRAM operation circuit 200, the error correction circuit 260 encodes the data. The encoding can be performed by adding additional check bits to increase the redundancy of the data, so that even if part of the data is damaged or lost after the data is written to the NVSRAM array 220 again, the error can be detected and corrected by the check bits. The encoded data will be written to the SRAM operation circuit 200 by the error correction circuit 260. The SRAM operation circuit 200 receives the encoded data from the error correction circuit 260 and writes it to the NVSRAM array 220 through the column selection circuit.

[0270] Further, when encoding, the error correction circuit 260 encodes the K-bit information code of the target data to obtain an R-bit check code, which is written to the SRAM storage subunit 222 of the NVSRAM array 220 by the SRAM operation circuit 200. Wherein, K and R are positive integers.

[0271] For example, when encoding, the error correction circuit 260 obtains the K-bit information code of the target data, which can then be processed by a specific encoding algorithm. The algorithm can generate an R-bit check code corresponding to the K-bit information code according to the content of the K-bit information code. The generated R-bit check code can be used to detect and correct errors that may occur during data transmission or storage. After generating the R-bit check code, the error correction circuit 260 writes the data including the R-bit check code to the SRAM storage subunit 222 of the NVSRAM array 220 through the SRAM operation circuit 200. By storing the check code in the NVSRAM array 220, the data can be protected during subsequent transmission or storage. Even if data transmission errors or storage medium damage occur, the data can be recovered and corrected by the check code, thereby improving the reliability of the data and the stability of the system.

[0272] In one example of the disclosure, the column select circuit can turn on the coupling between the SRAM operation circuit 200 and the NVSRAM array 220 in the case that the storage device completes the data recovery operation according to system instructions, and after the SRAM operation circuit 200 reads the already encoded data from the NVSRAM array 220 and inputs it to the error correction circuit 260, the error correction circuit 260 can determine whether the read data has errors and correct them. For example, this can be done by comparing the read data with the expected data. If an error is found, the error correction circuit 260 will use the check bits added during the encoding process to correct the error. For example, if one bit in the read data is incorrect, the error correction circuit 260 can detect this error using the check bits and correct it using the correct value expected during the encoding process.

[0273] Further, the error correction circuit 260 decodes the already encoded target data read by the SRAM operation circuit 200 from the NVSRAM array 220. In the decoding process, the error correction circuit 260 decodes and corrects errors in the K-bit information code and the R-bit check code of the read target data, and writes the K-bit corrected information code into the NVSRAM array 220 through the SRAM operation circuit 200. For example, in the decoding process, the SRAM operation circuit 200 reads the target data containing the K-bit information code and the R-bit check code from the NVSRAM array 220 and passes it to the error correction circuit 260. Then, the error correction circuit 260 decodes and corrects errors in the read data using a specific decoding algorithm. In this process, the error correction circuit 260 can check the integrity of the data and detect whether there is an error through the check code. If an error is found during decoding, the error correction circuit 260 can activate the error correction mechanism. The error correction circuit 260 can then take appropriate error correction measures according to the type and extent of the error. For example, the error correction circuit 260 can write the K-bit corrected information code into the SRAM storage subunit 222 of the NVSRAM array 220 through the SRAM operation circuit 200 to replace the original erroneous data. Not only can this improve the accuracy of the data, but also the security and reliability of the stored data.

[0274] In one example of the present disclosure, for example, in the case where the non-volatile storage operation circuit 230 performs a data backup operation, the error detection and correction circuit 260 encodes the data including the K-bit information code input from the SRAM operation circuit 200 to the error detection and correction circuit 260, and obtains R-bit check code data. Then, the error detection and correction circuit 260 writes the encoded data including the R-bit check code into the SRAM operation circuit 200. The SRAM operation circuit 200 writes the data including the R-bit check code into the NVSRAM array 220 through the column selection circuit. In the case where the column selection circuit 210 completes the data recovery operation, the error detection and correction circuit 260 decodes the data including the K-bit information code and the R-bit check code read from the NVSRAM array 220 by the SRAM operation circuit 200 and input to the error detection and correction circuit 260, and determines whether an error occurs in the decoding result, and performs error correction if an error occurs.

[0275] For example, in some embodiments of the present disclosure, the storage device 2000 can perform error detection and correction operation when performing data backup operation or when performing data recovery operation, and can not perform error detection and correction operation when performing first data read-write operation or second data read-write operation, so as to improve the speed of data read-write.

[0276] The above describes a basic error detection and correction and storage operation process of an embodiment of the present disclosure. In different embodiments, the error detection and correction circuit 260 can use different encoding and decoding algorithms, for example, use different check methods such as parity check and CRC check, and the embodiments of the present disclosure are not limited thereto. In addition, the process of data writing and reading can also be different due to specific hardware and interface design.

[0277] FIG. 13 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure.

[0278] As shown in FIG. 13, in some embodiments of the present disclosure, the second input-output interface circuit 270 includes a shift register operation circuit 271, an input interface circuit 272 and an output interface circuit 273. The shift register operation circuit 271 is coupled with the NVSRAM array 220 and is configured to perform second data read-write operation on the NVSRAM array 220; the input interface circuit 272 is coupled with the shift register operation circuit 271 and is configured to receive second input data and provide the received second input data to the shift register operation circuit 271; and the output interface circuit 273 is coupled with the shift register operation circuit 271 and is configured to receive second output data to be output from the shift register operation circuit 271.

[0279] Here, the "second input data" refers to data input to the storage device 2000 through the input interface circuit 272 in the second input / output interface circuit 270. The "second output data" refers to data output from the storage device 2000 through the output interface circuit 273 in the second input / output interface circuit 270, and embodiments of the present disclosure do not limit the content and form of the data, etc.

[0280] For example, the shift register operation circuit 271 can input the received second input data into the SRAM storage subunit 222 of the NVSRAM array 220, or the shift register operation circuit 271 can read the second output data from the SRAM storage subunit 222 of the NVSRAM array 220 and output the data from the storage device 2000 through the output interface circuit 273.

[0281] For example, the shift register operation circuit 271 can temporarily store the received second input data, and then input the second input data into the SRAM storage subunit 222 in the NVSRAM array 220.

[0282] For example, the shift register operation circuit 271 can also convert the received second input data. For example, the shift register operation circuit 271 can convert the serially received second input data into parallel input into the SRAM storage subunit 222 in the NVSRAM array 220.

[0283] In some embodiments of the present disclosure, as shown in FIG. 12 or FIG. 13, the NVSRAM array 220 can also be configured to be coupled with the word line driving circuit 240. The word line driving circuit 240 is configured to select the object unit row in the NVSRAM array 220 that needs to be operated in the case of the first data read / write operation of the SRAM operation circuit 200, or in the case of the second data read / write operation of the second input / output interface circuit 270, or in the case of the data backup operation of the non-volatile storage operation circuit, or in the case of the data recovery operation of the column selection circuit, or in the case of the data backup operation of the non-volatile storage operation circuit.

[0284] Here, the "object unit row" is used to refer to the storage unit row that is the object of operation, which can be any row in the plurality of storage arrays.

[0285] The word line driver circuit 240 (Word Line Driver) for the NVSRAM array 220 is configured to control the rows (word lines) of memory cells in the NVSRAM array 220. In the NVSRAM array 220, for example, each memory cell is located at the intersection of signal lines, i.e., the horizontal signal lines are word lines, and the vertical signal lines are bit lines. For example, the word line driver circuit 240 is responsible for controlling the switches connected to the word lines to determine which row of memory cells is selected for the desired operation (correspondingly, the column select circuit 210 is responsible for determining which column of memory cells is selected for the desired operation via the bit lines).

[0286] For example, in some embodiments, word line driver circuit 240 may include a decoder and a selector. The decoder receives an address signal and decodes it into a row address for the corresponding word line. The selector selects the corresponding word line based on the row address and applies a drive signal. When reading or writing data from or into a selected memory cell, word line driver circuit 240 ensures correct access to the selected memory cell while avoiding interference or malfunction in other unselected memory cells.

[0287] For example, in some embodiments, when the second input / output interface circuit 270 performs a second data read / write operation, the word line driver circuit 240 may be configured to select a row of memory cells in the NVSRAM array 220 to be selected for the second data read / write operation. When performing a data read operation, the second input / output interface circuit 270 may read data from the selected row; when performing a data write operation, the second input / output interface circuit 270 may write data to the selected row of memory cells.

[0288] For example, in some embodiments, when the second input-output interface circuit 270 performs a second data read and write operation, the column selection circuit can be used to determine which column of storage cells is selected for the second data read and write operation, or the second data read and write operation can be performed on all columns of storage cells in the NVSRAM array 220. The embodiments of the present disclosure are not limited to this.

[0289] For example, in some embodiments, in the case that the SRAM operation circuit 200 performs a first data read / write operation or the column selection circuit 210 performs a data recovery operation, the word line driving circuit 240 can be configured to select which row of memory cells in the NVSRAM array 220 is selected for performing the first data read / write operation or the data recovery operation. For example, in the case that the SRAM operation circuit 200 performs a first data read / write operation, in the case of performing a data read operation, the SRAM operation circuit 200 can read the data of the selected row; in the case of performing a data write operation, the SRAM operation circuit 200 can write data into the selected row of memory cells.

[0290] For example, in some embodiments, in the case that the non-volatile storage operation circuit 230 performs a data backup operation, the word line driving circuit 240 can be configured to select which row of memory cells in the NVSRAM array 220 is selected for performing the data backup operation. For example, in the case of performing a data backup operation, the non-volatile storage operation circuit 230 can read the data of the selected row in the SRAM storage subarray 222 and backup the data of the row in the SRAM storage subarray 222 to the non-volatile storage subarray 231.

[0291] For example, in some embodiments, in the case that the column selection circuit 210 performs a data recovery operation, the word line driving circuit 240 can be configured to select which row of memory cells in the NVSRAM array 220 is selected for performing the data recovery operation. For example, in the case of performing a data recovery operation, the column selection circuit 210 can recover the data of the selected row in the non-volatile storage subarray 231 to the SRAM storage subarray 222.

[0292] FIG. 14 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure.

[0293] As shown in FIG. 14, in some embodiments of the present disclosure, the second input / output interface circuit 270 can further include an isolation sub-circuit 274. The isolation sub-circuit 274 is coupled between the NVSRAM array 220 and the shift register operation circuit 271. The isolation sub-circuit 274 can be configured to turn on the switch coupling the shift register operation circuit 271 and the NVSRAM array 220 in the case that the shift register operation circuit 271 performs a second data read / write operation. Alternatively, the isolation sub-circuit 274 can be further configured to turn off the switch coupling the shift register operation circuit 271 and the NVSRAM array 220 in the case that the non-volatile storage operation circuit 230 performs a data backup operation.

[0294] For example, in at least some embodiments of the present disclosure, when the shift register operation circuit 271 performs the second data read-write operation, the isolator circuit 274 can couple the shift register operation circuit 271 and the NVSRAM array 220, and then the shift register operation circuit 271 can perform the second data read-write operation on the SRAM storage subunit 222 in the NVSRAM array 220 to realize fast data read-write transmission. At the same time, since the connection between the non-volatile storage operation circuit 230 and the NVSRAM array 220 is disconnected, the read-write operation of the shift register operation circuit 271 will not be affected.

[0295] When the non-volatile storage operation circuit 230 needs to perform a data backup operation, the isolator circuit 274 can disconnect the coupling between the shift register operation circuit 271 and the NVSRAM array 220, and the non-volatile storage operation circuit 230 is coupled with the NVSRAM array 220. The non-volatile storage operation circuit 230 can perform a data backup operation, and the shift register operation circuit 271 will not affect the data backup operation of the non-volatile storage operation circuit 230.

[0296] In some embodiments of the present disclosure, when the SRAM operation circuit 200 performs the first data read-write operation, the column selection circuit 210 can also be configured to connect the coupling between the SRAM operation circuit 200 and the NVSRAM array 220, the non-volatile storage operation circuit 230 can be configured to disconnect the coupling with the NVSRAM array 220, and the second input-output interface circuit 260 can be configured to disconnect the coupling with the NVSRAM array 220.

[0297] In some embodiments of the present disclosure, when the non-volatile storage operation circuit 230 performs a data backup operation, the column selection circuit 210 can also be configured to disconnect the coupling between the SRAM operation circuit 200 and the NVSRAM array 220, the non-volatile storage operation circuit 230 can also be configured to connect the coupling with the NVSRAM array 220, and the second input-output interface circuit 260 can be configured to disconnect the coupling with the NVSRAM array 220.

[0298] In some embodiments of the present disclosure, when the column selection circuit 210 performs a data recovery operation, the column selection circuit can also be configured to disconnect the coupling between the SRAM operation circuit 200 and the NVSRAM array 220, the non-volatile storage operation circuit 230 can be configured to disconnect the coupling with the NVSRAM array 220, and the second input-output interface circuit 260 can be configured to disconnect the coupling with the NVSRAM array 220.

[0299] In some embodiments of the present disclosure, in the case of the second data read-write operation of the second input-output interface circuit 260, the column selection circuit 210 can also be configured to disconnect the coupling of the SRAM operation circuit 200 and the NVSRAM array 220, and the non-volatile storage operation circuit 230 can also be configured to disconnect the coupling with the NVSRAM array 220.

[0300] For example, in at least some embodiments of the present disclosure, in the case of the first data read-write operation of the SRAM operation circuit 200, the column selection circuit 210 couples the SRAM operation circuit 200 and the NVSRAM array 220, and the SRAM operation circuit 200 can perform read-write operations on the SRAM storage subunit 222 in the NVSRAM array 220 to achieve fast data read-write transmission. At the same time, since the coupling of the non-volatile storage operation circuit 230 with the NVSRAM array 220 is disconnected, and the coupling of the second input-output interface circuit 260 with the NVSRAM array 220 is disconnected, the read-write operation of the SRAM operation circuit 200 will not be affected.

[0301] For example, in the case of data backup of the non-volatile storage operation circuit 230, the coupling of the second input-output interface circuit 260 with the NVSRAM array 220 is disconnected, the coupling of the SRAM operation circuit 200 and the NVSRAM array 220 is disconnected by the column selection circuit 210, and the non-volatile storage operation circuit 230 is coupled with the NVSRAM array 220. The non-volatile storage operation circuit 230 can perform backup operation, and the SRAM operation circuit 200 will not affect the data backup process.

[0302] For example, in the case of data recovery operation of the column selection circuit 210, the coupling of the second input-output interface circuit 260 with the NVSRAM array 220 is disconnected, the coupling of the SRAM operation circuit 200 and the NVSRAM array 220 is disconnected by the column selection circuit 210, and the coupling of the non-volatile storage operation circuit 230 with the NVSRAM array 220 is also disconnected. Therefore, the SRAM operation circuit 200, the non-volatile storage operation circuit 230, and the second input-output interface circuit 260 will not affect the data recovery operation process of the column selection circuit 210.

[0303] For example, in the case of the second data read-write operation of the second input-output interface circuit 260, the coupling of the non-volatile storage operation circuit 230 with the NVSRAM array 220 is disconnected, and the coupling of the SRAM operation circuit 200 and the NVSRAM array 220 is disconnected by the column selection circuit 210. Therefore, the operation of the SRAM operation circuit 200 and the non-volatile storage operation circuit 230 will not affect the second data read-write operation process of the second input-output interface circuit 260.

[0304] In some embodiments of the present disclosure, as shown in FIG. 14, the column selection circuit 210 further includes a data recovery operation sub-circuit 211.

[0305] For example, in some embodiments, the data recovery operation sub-circuit 211 can be configured to perform a data recovery operation on the non-volatile storage sub-cells 231 data in the object unit column. For example, the data recovery operation sub-circuit 211 can recover the data stored in the selected non-volatile storage sub-cells 231 to the SRAM storage sub-cells 222 upon receiving an instruction to perform a data recovery operation. For example, when performing a data recovery operation, the data recovery operation sub-circuit 211 needs to ensure isolation from the operations of the SRAM operation circuit 200, the second input / output interface circuit 260 and the non-volatile storage operation circuit 230 to prevent conflicts between the first data read / write operation, the second data read / write operation, the data backup operation and the data recovery operation, thereby improving the data integrity and the stability of the system.

[0306] For example, in some embodiments, the column selection circuit 210 or the isolation sub-circuit 264 can further include a switch array (not shown in the figure). For example, the column selection circuit 210 can control the coupling of the SRAM operation circuit 200 and the NVSRAM array 220 through the switch array. For example, the shift register operation circuit 261 can be coupled to the NVSRAM array 220 through the switch array of the isolation sub-circuit 264.

[0307] For example, when the SRAM operation circuit 200 performs the first data read / write operation, the column selection circuit 210 can be configured to turn on the switch array coupling between the column selection circuit 210 and the NVSRAM array 220. For example, when the non-volatile storage operation circuit 230 performs the data backup operation, the column selection circuit 210 can be further configured to turn off the switch array coupling between the column selection circuit 210 and the NVSRAM array 220.

[0308] For example, the switch array of the column selection circuit 210 or the isolation sub-circuit 264 can also be turned on or off according to the timing logic controlling the operation of the non-volatile storage operation circuit 230, the operation of the SRAM operation circuit 200 or the operation of the shift register operation circuit 261. For example, under a specific timing, the switch array of the column selection circuit 210 is turned on only when the SRAM operation circuit 200 is allowed to operate. For example, under a specific timing, the switch array of the column selection circuit 210 is turned off only when the non-volatile storage operation circuit 230 is allowed to operate.

[0309] As described above, as shown in FIG. 13, in some embodiments of the present disclosure, the array width of the NVSRAM array 220 can be configured as N, i.e., having N columns of storage units (or the number of bit lines being 2N). For example, each row in the NVSRAM array 220 can include N NVSRAM units. The array of the NVSRAM array 220 can also be configured to have M rows of storage units, e.g., each column in the NVSRAM array 220 can include M NVSRAM units. Each storage unit has a corresponding address for locating and accessing the storage unit. The array of the NVSRAM array 220 can also be configured to have M rows of storage units. For example, each row in the NVSRAM array 220 includes N storage units, each storage unit is configured with X bit lines (X is greater than or equal to 1), then the number of bit lines of the NVSRAM storage array is X*N, in the case of transmission lines being bit line pairs, X can be configured as 2, then the number of bit lines of the NVSRAM storage array can be configured as 2N. In some embodiments, for example, the NVSRAM array 220 can be configured in units of words. The non-volatile storage operation circuit 230 can be configured to be coupled to the NVSRAM array 220 through N groups of transmission lines. For example, in at least one example, in the case of transmission lines being bit lines or bit line pairs (e.g., bit lines BL and BLN as shown in FIG. 1), the non-volatile storage operation circuit 230 can also be configured to be coupled to the NVSRAM array 220 through N or 2N bit lines.

[0310] In some embodiments of the present disclosure, the N columns of storage units of the NVSRAM array 220 can include K columns of data columns and R columns of redundancy columns, the data columns store information codes, and the redundancy columns store additional check codes as needed for encoding. The NVSRAM array 220 is configured in units of words, each row of the NVSRAM array 220 stores P words of data, and the operation bit width of each word can be configured as W. The NVSRAM array 220 includes K columns of data columns to store information codes and R columns of redundancy columns to store check codes. For example, the information codes can be configured in units of "words", and the check codes can be configured in units of "pages", which are not limited by embodiments of the present disclosure. For example, K=W*P, N, W, P, K, and R are positive integers, 1≤K

[0311] In embodiments of the present disclosure, the data columns and the redundancy columns can have various arrangements. For example, as shown in FIG. 15, FIG. 16A, and FIG. 16B, all the data columns can be arranged adjacent to each other, and all the redundancy columns can be arranged adjacent to each other; or the data columns can be grouped, the redundancy columns can be grouped, and then the data column groups and the redundancy column groups can be arranged alternately, for example, K data columns and R redundancy columns can be arranged as one group, and the NVSRAM array can include N columns of the group; or the NVSRAM array can include multiple groups of K data columns and R data columns; or the NVSRAM array can include multiple groups of K data bits and R redundancy bits, for example, the K data bits can include multiple rows of information code data, and the R redundancy bits can include multiple rows of check code data. Embodiments of the present disclosure are not limited to the arrangement of the data columns and the redundancy columns.

[0312] In some embodiments of the present disclosure, as shown in FIG. 13, the error correction circuit 260 can be configured to be coupled to the SRAM operation circuit 200 through K+R groups of transmission lines. The SRAM operation circuit can be configured to be coupled to the first input / output interface circuit 250 through W1 groups of transmission lines. The SRAM operation circuit 200 can also be configured to be coupled to the column selection circuit 210 through W1 groups of transmission lines. The non-volatile storage operation circuit 230 is coupled to the NVSRAM array 220 through N groups of transmission lines. The column selection circuit 210 is coupled to the NVSRAM array 220 through N groups of transmission lines. For example, in the case of the transmission lines being bit lines or bit line pairs (for example, the bit lines BL and BLN as shown in FIG. 1), the column selection circuit 210 can also be configured to be coupled to the NVSRAM array 220 through N bit lines or 2N bit lines. In some embodiments, for example, in the case of the column selection circuit 210 performing a data recovery operation, the column selection circuit 210 can also be configured to set the voltages of the 2N bit lines to the same voltage value. In some embodiments, for example, the storage device 2000 can be configured as W1≤K+R≤N*M.

[0313] For example, the error correction circuit 260 is coupled to the SRAM operation circuit 200 through K+R groups of transmission lines, and the encoded data including R check code bits are written into the SRAM operation circuit 200, or the data including K information code bits and R check code bits read from the NVSRAM array 220 by the SRAM circuit are written into the error correction circuit 260 through K+R groups of transmission lines. The SRAM operation circuit 200 is connected to the column selection circuit 210 through W1 groups of transmission lines, for locating and accessing a specific storage unit in the NVSRAM array 220 according to the address provided by the column selection circuit 210, writing data including R check code bits into the NVSRAM array 220, and reading data including K information code bits and R check code bits from the NVSRAM array 220.

[0314] In some embodiments of the present disclosure, the shift register operation circuit 271 can be coupled with the NVSRAM array 220 through N groups of transmission lines, the input interface circuit 272 can be coupled with the shift register operation circuit 271 through W2 groups of transmission lines, and the output interface circuit 273 can be coupled with the shift register operation circuit 271 through W2 groups of transmission lines, where W2 and N are integers and N≥W2>1.

[0315] In the case of the transmission lines being bit lines, the shift register operation circuit 271 is connected with the NVSRAM array 220 through N groups of transmission lines, and in the case of the transmission lines being bit line pairs (for example, the bit lines BL and BLN as shown in FIG. 1), the shift register operation circuit 271 can also be connected with the NVSRAM array 220 through 2N bit lines.

[0316] In some embodiments of the present disclosure, W1 and W2 can be used to represent the operation bit width of each word in the transmission data. For example, in the case of W1 and W2 being the same, then the storage device 2000 can select any of the first input / output interface circuit 250 or the input interface circuit 272 to receive the data input into the storage device 2000, or select any of the first input / output interface circuit 250 or the output interface circuit 273 to output the data. For example, in the case of W1 being greater than W2 being the same, then the input interface of the data can be determined according to the bit width of the data input into the storage device 2000; for example, W1 can be 512 bits and W2 can be 32 bits, then in the case of the data input into or output from the storage device 2000 being 512 bits, the first input / output interface circuit 250 is selected to receive or output the data.

[0317] In some embodiments of the present disclosure, in the case of the non-volatile storage operation circuit 230 performing a data backup operation, the word line driving circuit 240 can also be configured to select the SRAM storage sub-unit 222 data in the I rows of NVSRAM units 221 of the NVSRAM array 220 for the data backup operation, where I is an integer and M≥I≥1.

[0318] For example, the word line driving circuit 240 can select the SRAM storage sub-unit 222 in the I rows of NVSRAM units 221 in the NVSRAM array 220 according to the received data backup operation instruction. For example, the word line driving circuit 240 can select the SRAM storage sub-unit 222 in the first row to the Ith row of NVSRAM units 221, and the non-volatile storage operation circuit 230 can be configured to perform a parallel data backup operation on the SRAM storage sub-unit 222 data in the first row to the Ith row of NVSRAM units 221 selected by the word line driving circuit 240, and backup all the I rows of SRAM storage sub-unit 222 data selected to the non-volatile storage sub-unit 231.

[0319] In some embodiments of the present disclosure, in the case that the column selection circuit 210 performs the data recovery operation, the word line driving circuit 240 can also be configured to select the non-volatile storage sub-cells 231 in the J rows of NVSRAM cells 221 of the NVSRAM array 220 to perform the data recovery operation, where J is an integer and M≥J≥1.

[0320] For example, the word line driving circuit 240 can select the non-volatile storage sub-cells 231 in the J rows of NVSRAM cells 221 in the NVSRAM array 220 according to the received data recovery operation instruction. For example, the word line driving circuit 240 can select the non-volatile storage sub-cells 231 in the first to Jth rows of NVSRAM cells 221, and the column selection circuit 210 can be configured to perform a parallel data recovery operation on the data of the non-volatile storage sub-cells 231 in the first to Jth rows of NVSRAM cells 221 selected by the word line driving circuit 240, and recover all the data of the selected J rows of non-volatile storage sub-cells 231 into the SRAM storage sub-cells 222.

[0321] In some embodiments of the present disclosure, the SRAM operation circuit 200 is further configured to perform a first data read-write operation on the data of the SRAM storage sub-cells 222 in the W1 NVSRAM cells 221 of the ith row of the selected NVSRAM array 220 in the case of performing the first data read-write operation. Wherein N≥W1≥1, M≥i≥1.

[0322] For example, the operation bit width of the first data read-write operation of the SRAM operation circuit 200 is W1. For example, the SRAM operation circuit 200 can perform a first data read-write operation on the data of the SRAM storage sub-cells 222 in the W1 NVSRAM cells 221 in a certain row (the ith row) of the selected NVSRAM array 220 according to the received first data read-write operation instruction.

[0323] In some embodiments of the present disclosure, the second input-output interface circuit 270 is further configured to perform a second data read-write operation on the data of the SRAM storage sub-cells 222 in the W2 NVSRAM cells 221 of the ith row of the selected NVSRAM array 220 in the case of performing the second data read-write operation. Wherein N≥W2≥1, M≥i≥1.

[0324] For example, the operation bit width of the second data read-write operation of the second input-output interface circuit 270 is W2. For example, the SRAM operation circuit 200 can perform a second data read-write operation on the data of the SRAM storage sub-cells 222 in the W2 NVSRAM cells 221 in a certain row (the i-th row) of the selected NVSRAM array 220 according to the received second data read-write operation instruction.

[0325] In some embodiments of the present disclosure, the non-volatile storage operation circuit 230 is further configured to perform a data backup operation on the data of the SRAM storage sub-cells 222 in the NVSRAM cells 221 in the E rows and / or the F columns of the selected NVSRAM array 220 in the case of performing the data backup operation. Wherein E, F are integers and M≥E≥1, N≥F≥1.

[0326] For example, the operation bit width of the data backup operation of the non-volatile storage operation circuit 230 is N*M.

[0327] For example, the non-volatile storage operation circuit 230 can perform a data backup operation on the data of the SRAM storage sub-cells 222 in the selected E rows or F columns of the NVSRAM cells 221 in the M rows and N columns of the NVSRAM cells 221 in the NVSRAM array 220 according to the received data backup operation instruction. Alternatively, the non-volatile storage operation circuit 230 can perform a data backup operation on all the data of the SRAM storage sub-cells 222 in the F columns of the NVSRAM cells 221 in the selected E rows of the NVSRAM cells 221 in the M rows and N columns of the NVSRAM cells 221 in the NVSRAM array 220.

[0328] In some embodiments of the present disclosure, the column selection circuit 210 is further configured to perform a data recovery operation on the data of the non-volatile storage sub-cells 231 in the NVSRAM cells 221 in the G rows and / or the H columns of the selected NVSRAM array 220 in the case of performing the data recovery operation. Wherein G, H are integers and M≥G≥1, N≥H≥1.

[0329] For example, the operation bit width of the data recovery operation of the column selection circuit 210 is N*M.

[0330] For example, the column selection circuit 210 can perform a data recovery operation on the data of the non-volatile storage sub-cells 231 in the selected G rows or H columns of the NVSRAM cells 221 in the M rows and N columns of the NVSRAM cells 221 in the NVSRAM array 220 according to the received data recovery operation instruction. Alternatively, the non-volatile storage operation circuit 230 can perform a data recovery operation on all the data of the non-volatile storage sub-cells 231 in the selected G rows of the NVSRAM cells 221 in the M rows and N columns of the NVSRAM cells 221 in the NVSRAM array 220.

[0331] In the storage device 2000 of at least one embodiment of the present disclosure, the number and type of these transmission lines and other parameters can be flexibly adjusted according to requirements and hardware conditions to optimize the performance and efficiency of the storage device 2000.

[0332] In the storage device 2000 of at least one embodiment of the present disclosure, in the case of the first data read-write operation of the SRAM operation circuit 200, the error correction circuit 260 does not perform error correction on the data, i.e., in the process of the SRAM operation circuit 200 reading the data input by the first input-output interface circuit 250 and writing the data into the NVSRAM array 220 through the column selection circuit 210, the error correction circuit 260 does not perform error correction on the data. In the case of the data backup operation of the non-volatile storage operation circuit 230 and the completion of the data recovery operation of the column selection circuit 210, the error correction circuit 260 performs the error correction function, which can improve the speed of data read-write, storage, backup, and recovery.

[0333] In some embodiments of the present disclosure, the storage device 2000 can further include a control circuit 280 (not shown in the figure), which can be coupled with the SRAM operation circuit 200, the non-volatile storage operation circuit 230, the first input-output interface circuit 250, the column selection circuit 210, the error correction circuit 260, and the second input-output interface circuit 270.

[0334] The control circuit 280 can be configured to provide corresponding control signals to the SRAM operation circuit 200, the non-volatile storage operation circuit 230, the first input-output interface circuit 250, the column selection circuit 210, the error correction circuit 260, and the second input-output interface circuit 270 according to the selected working mode.

[0335] For example, in the storage device 2000, the control circuit 280 can generate corresponding control signals according to the working mode of the storage device 2000 or specific requirements, and provide the generated control signals to the corresponding operation circuits.

[0336] For example, in the case where the storage device 2000 needs to perform data reading or data writing, the control circuit 280 can provide the SRAM operation circuit 200 with a control signal for performing a first data reading and writing operation, or provide the second input / output interface circuit 270 with a control signal for performing a second data reading and writing operation, according to a preset condition.

[0337] For example, in the case where the storage device 2000 needs to perform a data backup operation, the control circuit 280 can provide the non-volatile storage operation circuit 230 with a control signal for performing a data backup operation, and the non-volatile storage operation circuit 230 can perform a data backup operation on data in the selected SRAM storage subunit 222 according to the received data backup operation control signal.

[0338] For example, in the case where the storage device 2000 needs to perform a data recovery operation, the control circuit 270 can provide the column selection circuit 210 with a control signal for performing a data recovery operation, and the column selection circuit 210 can perform a data recovery operation on data in the selected non-volatile storage subunit 231 according to the received data recovery operation control signal.

[0339] For example, in the case where the storage device 2000 needs to perform a data backup operation or a data recovery operation, the control circuit 280 can also provide the error detection and correction circuit 260 with a control signal for performing an error detection and correction operation.

[0340] For example, the control circuit 280 can also monitor the working state or health state of the storage device 2000. For example, in the case where the first input / output interface circuit 250 fails, when the storage device 2000 needs to perform a data reading and writing operation, the control circuit 280 can provide the second input / output interface circuit 270 with a second data reading and writing operation control signal. The control circuit 280 can also take appropriate measures to repair the failed circuit or report error information, so as to improve the reliability and stability of the storage device 2000.

[0341] In at least one embodiment of the present disclosure, the control circuit 280 can improve the running efficiency of the storage device 2000 in different working modes through connection or interaction with other circuits and components of the storage device 2000. The control circuit 280 can also adjust the working state and parameters of each circuit and component as needed, so as to realize flexible control and management of the storage device 2000.

[0342] The control method of the storage device provided in at least one embodiment of the present disclosure includes controlling the error detection and correction circuit to encode and decode target data and determine whether an error occurs in the target data and correct the error. The control method can be used in the storage device shown in FIG. 12, for example.

[0343] For example, the error correction and detection circuit receives target data read from the SRAM storage subunit of the NVSRAM array input by the SRAM operation circuit according to the received control instruction, and encodes or decodes the target data. The error correction and detection circuit can further input the encoded target data to the SRAM operation circuit to write into the SRAM storage subunit of the NVSRAM array, or judge the decoded target data, confirm whether an error occurs and correct the error.

[0344] FIG. 17 shows a flowchart of a control method of a storage device according to at least one embodiment of the present disclosure.

[0345] As shown in FIG. 17, in some embodiments of the present disclosure, the control method of the storage device includes steps S810-S811. The control method can be used in the storage device shown in FIG. 12, for example.

[0346] Step S810: Determine that the non-volatile storage operation circuit performs a data backup operation.

[0347] Step S811: Encode target data input by the error correction and detection circuit from the SRAM operation circuit.

[0348] For example, the error correction and detection circuit encodes target data read from the SRAM storage subunit of the NVSRAM array input by the SRAM operation circuit in response to an instruction that the non-volatile storage operation circuit performs a data backup operation. Alternatively, the non-volatile storage operation circuit performs a data backup operation and the error correction and detection circuit encodes target data can be performed simultaneously, or the data backup can be performed first and then the target data is encoded, or the target data is encoded first and then the encoded target data is backed up. The embodiments of the present disclosure are not limited in this regard.

[0349] FIG. 18 shows a flowchart of another control method of a storage device according to at least one embodiment of the present disclosure.

[0350] As shown in FIG. 18, in some embodiments of the present disclosure, the control method of the storage device includes steps S820-S821. The control method can be used in the storage device shown in FIG. 12, for example.

[0351] Step S820: Determine that the column selection circuit completes a data recovery operation.

[0352] Step S821: Determine whether target data read by the SRAM operation circuit from the NVSRAM array and input by the error correction and detection circuit has an error and corrects the error.

[0353] For example, in response to an instruction that the column selection circuit completes the data recovery operation, the error correction circuit decodes the target data read by the SRAM operation circuit from the SRAM storage subunit of the NVSRAM array and input into the error correction circuit, and determines whether the decoded result is incorrect. If an error occurs, error correction is performed.

[0354] The method of encoding, decoding and error correction of the error correction circuit can refer to the related description above, which will not be repeated here.

[0355] FIG. 19 shows a flowchart of another method of controlling a storage device according to at least one embodiment of the present disclosure.

[0356] In some embodiments of the present disclosure, step S811 of the method of controlling a storage device shown in FIG. 17 can further include steps S910-S911 shown in FIG. 19.

[0357] Step S910: When encoding, the K-bit information code of the read target data is encoded to obtain an R-bit check code.

[0358] For step S910, the error correction circuit encodes the K-bit information code data of the received target data to generate R-bit check code data. The encoding method of the error correction circuit can refer to the related description above, which will not be repeated here. For example, after encoding, the R-bit check code data can be appended to the K-bit information code data to form data including the K-bit information code and the R-bit check code.

[0359] Step S911: Write the R-bit check code into the NVSRAM array by the SRAM operation circuit.

[0360] For step S911, for example, the error correction circuit sends a corresponding control signal to the SRAM operation circuit, and the SRAM operation circuit can write the data including the R-bit check code into the SRAM storage subunit of the NVSRAM array through the column selection circuit. The column selection circuit can be used to select a specific column in the NVSRAM array to write data into a designated storage unit. This step can reliably store data in the SRAM storage subunit of the NVSRAM array for subsequent data recovery operations or data backup operations.

[0361] FIG. 20 shows a flowchart of another method of controlling a storage device according to at least one embodiment of the present disclosure.

[0362] In some embodiments of the present disclosure, step S821 of the method of controlling a storage device shown in FIG. 18 can further include steps S920-S922 shown in FIG. 20.

[0363] Step S920: when decoding, the K-bit information code and R-bit check code of the read target data are decoded for error detection.

[0364] Step S921: whether the decoding result has error is judged.

[0365] Step S922: in response to the error, the K-bit error-corrected information code is written into the NVSRAM array through the SRAM operation circuit for error correction. K and R are positive integers.

[0366] For step S920, for example, in response to the instruction of the column selection circuit completing the data recovery operation, the SRAM operation circuit selects the data (i.e. target data) stored in a specific column of the SRAM storage subunit of the NVSRAM array through the column selection circuit, and the SRAM operation circuit reads the target data from the NVSRAM array. The read target data is input to the error correction and detection circuit by the SRAM operation circuit for subsequent decoding and error detection operations. The error correction and detection circuit decodes the target data including K-bit information code and R-bit check code read from the SRAM storage subunit of the NVSRAM array input by the SRAM operation circuit. In some embodiments, the decoding process can be the inverse operation of the encoding process, and the R-bit check code data is separated from the data according to a specific decoding algorithm, and the K-bit information code data is checked according to the check code. Then the error correction and detection circuit performs step S921 to judge whether the decoding result has error, and if error occurs, step S922 is started to correct error, and the K-bit error-corrected information code is written into the SRAM storage subunit of the NVSRAM array through the SRAM operation circuit to replace the error data. If there is no error, the target data is input to the input and output interface circuit through the SRAM operation circuit for data output. The input and output interface circuit can send the target data to the corresponding external device or other circuit in the electronic device for subsequent operation. The method of encoding, decoding and error correction of the error correction and detection circuit can refer to the related description in the foregoing, which will not be described here.

[0367] FIG. 21 shows a flowchart of a control method of a storage device according to at least one embodiment of the present disclosure. As shown in FIG. 21, the method can include steps S1000-S1030.

[0368] Step S1000: determining that the SRAM operation circuit performs a first data read / write operation.

[0369] Step S1010: disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array.

[0370] Step S1020: controlling the column selection circuit to couple the SRAM operation circuit and the NVSRAM array.

[0371] Step S1030: controlling the second input / output interface circuit to disconnect the coupling with the NVSRAM array.

[0372] In the case of determining that the SRAM operation circuit performs the first data read / write operation, it is necessary to isolate the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit to avoid mutual influence and affect the reliability of the first data read / write operation. Therefore, it is necessary to disconnect the coupling of the non-volatile storage operation circuit with the NVSRAM array, and control the column selection circuit to connect the coupling of the SRAM operation circuit with the NVSRAM array, so as to isolate the operation of the non-volatile storage operation circuit and the SRAM operation circuit.

[0373] For step S1010, in one example, for example, the non-volatile storage operation circuit stops the operation of the non-volatile storage operation circuit according to the received instruction that the SRAM operation circuit performs the first data read / write operation.

[0374] For step S1020, in one example, for example, in the case where the column selection circuit includes a switch array, step S1020 further includes step S1021 (not shown in the figure).

[0375] Step S1021: controlling the column selection circuit to turn on the switch array coupled with the NVSRAM array. The method of isolating the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit can refer to the related description above, which will not be repeated here.

[0376] For step S1030, in one example, for example, the second input / output interface circuit stops the second data read / write operation according to the received instruction that the SRAM operation circuit performs the first data read / write operation, and controls the second input / output interface circuit to disconnect the coupling with the NVSRAM array to avoid affecting the operation of the SRAM operation circuit.

[0377] In some embodiments, the method shown in FIG. 21 can further include step S1040 (not shown in the figure). Step S1040: controlling the column selection circuit to stop the data recovery operation.

[0378] In the case of determining that the SRAM operation circuit performs the first data read / write operation, it is necessary to isolate the data recovery operation of the column selection circuit and the operation of the SRAM operation circuit to avoid mutual influence and affect the reliability of the data read / write. Therefore, it is necessary to control the column selection circuit to stop the data recovery operation, so as to isolate the data recovery operation of the column selection circuit and the first data read / write operation of the SRAM operation circuit.

[0379] FIG. 22 shows a flowchart of a method of controlling a storage device according to at least one embodiment of the present disclosure. As shown in FIG. 22, the method can include steps S1050-S1080.

[0380] Step S1050: determining that the second input / output interface circuit performs the second data read / write operation.

[0381] Step S1060: disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array.

[0382] Step S1070: connecting the coupling between the second input / output interface circuit and the NVSRAM array.

[0383] Step S1080: controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array.

[0384] In the case of determining that the second input / output interface circuit performs the second data read / write operation, the operation of the non-volatile storage operation circuit and the operation of the second input / output interface circuit need to be isolated from each other to avoid affecting the reliability of the second data read / write operation. Therefore, the coupling between the non-volatile storage operation circuit and the NVSRAM array needs to be disconnected, and the coupling between the second input / output interface circuit and the NVSRAM array needs to be connected, so as to isolate the operation of the non-volatile storage operation circuit and the second input / output interface circuit.

[0385] For step S1060, in one example, for example, the non-volatile storage operation circuit can stop the operation of the non-volatile storage operation circuit according to the received instruction that the second input / output interface circuit performs the second data read / write operation.

[0386] For step S1070, in one example, for example, in the case where the second input / output interface circuit includes an isolation sub-circuit, step S1070 further includes step S1071 (not shown in the figure).

[0387] Step S1071: controlling the isolation sub-circuit to connect the coupling between the second input / output interface circuit and the NVSRAM array. The method of isolating the operation of the non-volatile storage operation circuit and the operation of the second input / output interface circuit can refer to the related description above, which will not be described here again.

[0388] For step S1080, in one example, for example, the column selection circuit disconnects the coupling between the SRAM operation circuit and the NVSRAM array according to the received instruction that the second input / output interface circuit performs the second data read / write operation, so as to avoid affecting the second data read / write operation performed by the second input / output interface circuit.

[0389] In some embodiments, the method shown in FIG. 22 can further include step S1090 (not shown in the figure). Step S1090: controlling the column selection circuit to stop the data recovery operation.

[0390] In the case where it is determined that the second input / output interface circuit performs the second data read / write operation, the data recovery operation of the column selection circuit and the operation of the second input / output interface circuit need to be isolated from each other so as not to affect each other and further affect the reliability of data read / write. Therefore, the data recovery operation of the column selection circuit needs to be controlled to stop, so as to isolate the data recovery operation of the column selection circuit and the second data read / write operation of the second input / output interface circuit from each other.

[0391] FIG. 23 shows a flow diagram of another control method of a storage device according to at least one embodiment of the present disclosure. As shown in FIG. 23, the control method can include steps S1100-S1130.

[0392] Step S1100: determining that the non-volatile storage operation circuit performs the data backup operation.

[0393] Step S1110: connecting the non-volatile storage operation circuit and the NVSRAM array.

[0394] Step S1120: controlling the column selection circuit to disconnect the SRAM operation circuit and the NVSRAM array.

[0395] Step S1130: controlling the second input / output interface circuit to disconnect the NVSRAM array.

[0396] In the case where it is determined that the non-volatile storage operation circuit performs the data backup operation, the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit and the operation of the second input / output interface circuit need to be isolated from each other so as not to affect each other and further affect the reliability of the data backup operation. Therefore, the non-volatile storage operation circuit needs to be connected with the NVSRAM array, the column selection circuit needs to be controlled to disconnect the SRAM operation circuit and the NVSRAM array, and the second input / output interface circuit needs to be controlled to disconnect the NVSRAM array, so as to isolate the non-volatile storage operation circuit and the SRAM operation circuit and the second input / output interface circuit from each other.

[0397] For step S1120, in one example, the column selection circuit stops the operation of the column selection circuit according to the received instruction that the non-volatile storage operation circuit performs the data backup operation. For another example, in the case where the column selection circuit further includes a switch array, step S1120 further includes step S1121 (not shown in the figure).

[0398] Step S1121: controlling the column selection circuit to disconnect the switch array coupled with the NVSRAM array. The method of isolating the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit can refer to the related description above, and will not be described here again.

[0399] For step S1130, in one example, the second input / output interface circuit stops the operation of the second input / output interface circuit according to the received instruction of the non-volatile storage operation circuit to perform the data backup operation. For another example, in the case that the second input / output interface circuit further comprises an isolation sub-circuit, step S1130 further comprises step S1131 (not shown in the figure).

[0400] Step S1131: controlling the isolation sub-circuit to disconnect the coupling between the second input / output interface circuit and the NVSRAM array. The method of isolating the operation of the non-volatile storage operation circuit and the operation of the second input / output interface circuit can refer to the related description above, and will not be described here again.

[0401] In some embodiments, the method shown in FIG. 23 can further comprise step S1140 (not shown in the figure). Step S1140: controlling the column selection circuit to stop the data recovery operation.

[0402] In the case of determining that the non-volatile storage operation circuit performs the data backup operation, it is necessary to isolate the data recovery operation of the column selection circuit and the operation of the non-volatile storage operation circuit to avoid mutual influence and affect the reliability of the data backup. Therefore, it is necessary to control the column selection circuit to stop the data recovery operation to isolate the operation of the data recovery operation and the non-volatile storage operation circuit. For example, in the case that the column selection circuit comprises a data recovery operation sub-circuit, step S1140 can further comprise controlling the data recovery operation sub-circuit to stop performing the data recovery operation.

[0403] FIG. 24 shows a flow diagram of another control method of a storage device provided by at least one embodiment of the present disclosure. As shown in FIG. 24, the control method can comprise steps S1150-S1180.

[0404] Step S1150: determining that the column selection circuit performs the data recovery operation.

[0405] Step S1160: disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array.

[0406] Step S1170: controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array.

[0407] Step S1180: controlling the second input / output interface circuit to disconnect the coupling with the NVSRAM array.

[0408] In the case of determining that the column selection circuit performs the data recovery operation, the operation of the non-volatile storage operation circuit, the operation of the SRAM operation circuit, the operation of the second input / output interface circuit, and the data recovery operation of the column selection circuit need to be isolated from each other to avoid affecting the reliability of the data recovery operation. Therefore, the coupling between the non-volatile storage operation circuit and the NVSRAM array needs to be disconnected, the coupling between the SRAM operation circuit and the NVSRAM array needs to be disconnected by controlling the column selection circuit, and the coupling between the second input / output interface circuit and the NVSRAM array needs to be disconnected to isolate the operation of the non-volatile storage operation circuit, the SRAM operation circuit, and the second input / output interface circuit from the data recovery operation of the column selection circuit.

[0409] For step S1170, in one example, for example, in the case where the column selection circuit further includes a switch array, step S1170 further includes step S1171 (not shown in the figure). Step S1171: control the column selection circuit to disconnect the switch array coupled with the NVSRAM array. The method of isolating the operation of the non-volatile storage operation circuit and the data recovery operation of the column selection circuit can be referred to the related description above, which will not be repeated here.

[0410] For step S1180, in one example, for example, the second input / output interface circuit stops the operation of the second input / output interface circuit according to the received instruction of the non-volatile storage operation circuit performing the data backup operation. For another example, in the case where the second input / output interface circuit further includes an isolation sub-circuit, step S1180 further includes step S1181 (not shown in the figure). Step S1181: control the isolation sub-circuit to disconnect the switch coupled between the second input / output interface circuit and the NVSRAM array. The method of isolating the data recovery operation of the column selection circuit and the operation of the second input / output interface circuit can be referred to the related description above, which will not be repeated here.

[0411] In some embodiments of the present disclosure, the control method of the storage device can further include steps S1190-S1192 (not shown in the figure).

[0412] Step S1190: receive a working mode signal.

[0413] Step S1191: generate a control signal for the first data read / write operation, the data backup operation, the data recovery operation, the second data read / write operation, or the data error correction according to the working mode signal.

[0414] Step S1192: provide the control signal to the SRAM operation circuit, the non-volatile storage operation circuit, the first input / output interface circuit, the column selection circuit, the second input / output interface circuit, or the error correction circuit correspondingly.

[0415] For step S1190, the control circuit receives a working mode signal, which can be used to indicate which working mode the storage device is to perform, for example, the working mode signal can be used to indicate the storage device to perform a data read / write operation, a data backup operation, or a data recovery operation, etc.

[0416] For step S1191, after the control circuit receives the working mode signal, the control circuit can generate a corresponding control signal according to the received working mode signal, for example, generate a control signal for a first data read / write operation, a data backup operation, a data recovery operation, a second data read / write operation, or data error correction. For example, the control signal for the first data read / write operation can include controlling the SRAM operation circuit to perform the first data read / write operation; for example, the control signal for the first data read / write operation can also include controlling the non-volatile storage operation circuit to disconnect the coupling with the NVSRAM array. For example, the control signal for the data backup operation can include controlling the non-volatile storage operation circuit to perform the data backup operation; for example, the control signal for the data backup operation can also include controlling the SRAM operation circuit and the second input / output interface circuit to disconnect the coupling with the NVSRAM array; for example, the control signal for the data recovery operation can also include controlling the error correction circuit to perform the data error correction operation; for example, the control signal for the data recovery operation can be used to include controlling the column selection circuit to perform the data recovery operation, controlling the non-volatile storage operation circuit to disconnect the coupling with the NVSRAM array, controlling the second input / output interface circuit to disconnect the coupling with the NVSRAM array, and controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array.

[0417] For step S1192, the control circuit correspondingly provides the generated control signals to the corresponding operation circuit. For example, the control circuit can correspondingly provide the control signals for the first data read / write operation or the data recovery operation to the SRAM operation circuit; for example, the control circuit can also provide the control signals for the first data read / write operation or the data recovery operation to the non-volatile storage operation circuit. For example, the control circuit can correspondingly provide the control signals for the data backup operation to the non-volatile storage operation circuit; for example, the control circuit can also provide the control signals for the data backup operation to the SRAM operation circuit and the second input / output interface circuit. For example, the control circuit can correspondingly provide the control signals for the second data read / write operation to the second input / output interface circuit; for example, the control circuit can also provide the control signals for the second data read / write operation to the non-volatile storage operation circuit. For example, the control circuit can provide the control signals for the data backup operation to the error detection and correction circuit. For example, the control circuit can also provide the control signals for the data recovery operation to the error detection and correction circuit. For example, the control circuit can also provide the control signals for the data recovery operation to the column selection circuit.

[0418] In at least one embodiment of the present disclosure, the control circuit generates corresponding control signals according to the received working mode signal, and correspondingly provides each control signal to the corresponding operation circuit, so that the reliability and efficiency of data read / write, backup, recovery and other operations can be improved.

[0419] FIG. 25 shows a flowchart of a data backup method of a storage device according to at least one embodiment of the present disclosure.

[0420] As shown in FIG. 25, the data backup method includes steps S1200-S1291. The data backup method can be used in the storage device shown in FIG. 12 or FIG. 13, for example.

[0421] Step S1200: Perform data read / write.

[0422] For step S1200, the SRAM operation circuit can perform the first data read / write operation, or the second input / output interface circuit can perform the second data read / write operation. For example, the SRAM operation circuit can write the first input data received from the first input / output interface circuit into the NVSRAM array, or the SRAM operation circuit can provide the first output data read from the NVSRAM array to the first input / output interface circuit, and output the first output data from the first input / output interface circuit to the storage device. For example, the second input / output interface circuit can also write the received second input data into the NVSRAM array, or the second input / output interface circuit can output the second output data read from the NVSRAM array to the storage device.

[0423] Step S1210: judging whether data backup operation is needed.

[0424] For step S1210, in some embodiments of the present disclosure, the storage device determines whether data backup operation is needed according to the received instruction. If data backup operation is needed, step S1220 is performed; otherwise, step S1200 is continued to write data into the SRAM storage sub-unit in the NVSRAM unit.

[0425] Step S1220: reading the i-th row data K-bit information code.

[0426] For step S1220, the SRAM operation circuit reads the i-th row data of the SRAM storage sub-unit in the NVSRAM array through the column selection circuit, the data including K-bit information code, and inputs the data into the error correction circuit. i and K are integers and 0 < i < N and K > 1.

[0427] Step S1230: encoding the K-bit information code data of the i-th row to obtain R-bit check code.

[0428] For step S1230, the error correction circuit encodes the received K-bit information code of the i-th row data to obtain R-bit check code.

[0429] Step S1240: writing the R-bit check code of the i-th row.

[0430] For step S1240, for example, the error correction circuit writes the R-bit check code into the i-th row data of the SRAM storage sub-unit in the NVSRAM array through the SRAM operation circuit, for subsequent data backup operation. For example, in some embodiments, steps S1230-S1240 can correspond to steps S910-S911 shown in FIG. 19. The method of encoding data by the error correction circuit can refer to the related description above, which will not be described here again. Then step S1250 is performed.

[0431] Step S1250: judging whether encoding is completed.

[0432] For step S1250, it is judged whether all the data to be backed up in the NVSRAM array are encoded. If not, step S1291 is performed. If yes, step S1260 is performed.

[0433] Step S1291: increasing the row address by 1.

[0434] For step S1291, if the data encoding operation is not completed, the row address of the data to be encoded in the SRAM storage subunit is updated, and the row address is increased by 1 row. Then the data encoding operation of steps S1220-S1250 is continued until all the data to be encoded is encoded and written into the SRAM storage subunit.

[0435] Step S1260: Selecting J rows of NVSRAM units.

[0436] For step S1260, after the data encoding operation is completed by the error detection and correction circuit, the data backup operation is performed. For example, the word line driving circuit determines the J rows of data in the NVSRAM units according to the address information. J is an integer and 0

[0437] Step S1270: Simultaneously performing data backup on all the data (including data bits and check bits) in the SRAM storage subunits in the J rows of storage units.

[0438] For step S1270, the non-volatile storage operation circuit performs parallel operation to simultaneously perform data backup on the data including K-bit information code and R-bit check code in all the storage subunits in the J rows of SRAM storage subunits to the RRAM storage subunits.

[0439] Step S1280: Determining whether the data backup is completed.

[0440] For step S1280, the non-volatile storage operation circuit determines whether the data backup is completed. If the backup is not completed, step S1290 is performed; if it is determined that the data backup is completed, the data backup operation is ended.

[0441] Step S1290: Increasing the row address by J.

[0442] For step S1290, the word line driving circuit updates the row address of the SRAM storage subunit and increases the row address by J to continue the next data backup operation. For example, the non-volatile storage operation circuit determines the (J+1)th row to the 2Jth row of data in the SRAM storage subunit to be backed up to the RRAM storage subunit. Then the data backup operation of steps S1260-S1280 is continued until all the data to be backed up is backed up to the RRAM storage subunit.

[0443] FIG. 26 shows a flowchart of a data recovery method of a storage device according to at least one embodiment of the present disclosure.

[0444] As shown in FIG. 26, the data recovery method includes steps S1300-S1393. The data recovery method can be used in the storage device as shown in FIG. 12 or FIG. 13, for example.

[0445] Step S1300: whether data recovery.

[0446] For step S1300, it is determined whether the storage device performs a data recovery operation. The storage device can determine whether to perform data recovery according to actual needs, or receive an instruction to perform data recovery, to determine to perform a data recovery operation. If it is determined that the data recovery operation needs to be performed, step S1310 will be performed; if it is determined that the data recovery operation is not performed, step S1391 will be performed directly.

[0447] Step S1310: select I rows of NVSRAM cells.

[0448] For step S1310, the word line driving circuit determines I rows of data in the NVSRAM cell according to the address information. I is an integer and 0

[0449] Step S1320: simultaneously perform data recovery on all storage cells in I rows.

[0450] For step S1320, this step can be performed by the column selection circuit, for example. For example, the column selection circuit performs a parallel operation to simultaneously restore I rows of data in the determined RRAM storage subcell to the SRAM storage subcell. Then step S1330 is performed.

[0451] Step S1330: whether data recovery is complete.

[0452] For step S1330, it is determined whether the data recovery operation is completed, and if so, step S1340 is performed, and if not, step S1393 is performed.

[0453] Step S1393: increase the row address by I.

[0454] For step S1393, in the case where the data recovery operation is not completed, the row address of the data to be recovered in the RRAM storage subcell is increased by I again. For example, the word line driving circuit can determine the data in the (I+1)th row to the 2Ith row in the RRAM storage subcell according to the address information. Then steps S1310-S1330 are continued until all the data to be recovered is recovered.

[0455] Step S1340: read the data of the jth row including K-bit information code and R-bit check code.

[0456] For step S1340, when the data recovery operation is completed, the SRAM operation circuit reads the data including K-bit information code and R-bit check code in the jth row of the SRAM storage subunit, and inputs the read data into the error correction circuit for subsequent processing and use. j is an integer and 0 < j.

[0457] Step S1350: decoding and error checking the read data including K-bit information code and R-bit check code in the jth row.

[0458] For step S1350, the error correction circuit decodes and error checks the data including K-bit information code and R-bit check code in the jth row input from the SRAM operation circuit. In some embodiments, the decoding process can be the inverse operation of the encoding process, separating the R-bit check code data from the data according to a specific decoding algorithm, and checking the K-bit information code data according to the check code. The decoding method of the error correction circuit for data can refer to the related description above, which will not be described here.

[0459] Step S1360: determining whether there is an error.

[0460] For step S1360, the error correction circuit judges the decoding result to determine whether the data has an error. If the decoding result has an error, error correction operation is needed, and step S1370 is performed; if the decoding result has no error, step S1390 is performed.

[0461] Step S1370: correcting the jth row data to obtain K-bit corrected information code.

[0462] For step S1370, if the error correction circuit determines that the decoding result has an error, the data is corrected. The error correction circuit corrects the data in the jth row to obtain K-bit corrected information code. The error correction encoding method of the error correction circuit for data can refer to the related description above, which will not be described here.

[0463] Step S1380: writing K-bit corrected information code in the jth row.

[0464] For step S1380, the error correction circuit writes the K-bit corrected information code data through the SRAM operation circuit into the SRAM storage subunit of the NVSRAM array to replace the original error data.

[0465] Step S1390: determining whether the error correction is completed.

[0466] For step S1390, it is determined whether the error correction operation of the error correction circuit is completed. If it is completed, step S1391 is performed; if it is not completed, step S1392 is performed.

[0467] Step S1391: data read / write.

[0468] For step S1391, after the error detection and correction circuit completes the error detection and correction operation, a first data read / write operation can be performed by the SRAM operation circuit through the column selection circuit to read the data after the error detection and correction in the NVSRAM array, and input the data to the first input / output interface circuit for subsequent processing. For example, a second data read / write operation can also be performed by the second input / output interface circuit to read the data after the error detection and correction in the NVSRAM array.

[0469] Step S1392: the row address is increased by 1.

[0470] For step S1392, in the case where the error correction operation is not completed, the row address of the data in the SRAM storage subunit that needs to be subjected to the error detection and correction operation is updated, and the row address is increased by 1. Then, the SRAM operation circuit can read the data including K-bit information code and R-bit check code in the j+1th row in the SRAM storage subunit, and input the read data to the error detection and correction circuit. Then, steps S1340-S1390 are continued until all the data to be subjected to error detection and correction are completed.

[0471] At least one embodiment of the present disclosure also provides an electronic device including the storage device described above. The electronic device can improve the reliability of data read / write, backup, and storage.

[0472] FIG. 27 shows a schematic block diagram of an electronic device according to at least one embodiment of the present disclosure. As shown in FIG. 27, the electronic device 3000 includes a storage device, which includes the storage device 1000 or the storage device 2000 according to any of the embodiments described above.

[0473] The electronic device 3000 in the embodiments of the present disclosure can include, but is not limited to, a mobile terminal such as a mobile phone, a notebook computer, a digital broadcast receiver, a PDA (Personal Digital Assistant), a PAD (Tablet Personal Computer), a PMP (Portable Multimedia Player), a vehicle terminal (e.g., a car navigation terminal), and the like, and a fixed terminal such as a digital TV, a desktop computer, and the like.

[0474] The specific functions and technical effects of the electronic device 3000 in the above-described embodiments of the present disclosure can be referred to the descriptions of the storage device 1000 or the storage device 2000 above, which will not be described herein again.

[0475] The following points need to be explained:

[0476] (1) The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0477] (2) In the case of no conflict, the embodiments and features in the embodiments can be combined with each other to obtain new embodiments.

[0478] The above merely describes the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A storage device, comprising: The NVSRAM array, the SRAM operation circuit, the non-volatile storage operation circuit, the first input / output interface circuit, the column selection circuit, the second input / output interface circuit, The column selection circuit is coupled with the NVSRAM array, the SRAM operation circuit is coupled with the column selection circuit, and the non-volatile storage operation circuit is coupled with the NVSRAM array. The NVSRAM array includes a plurality of NVSRAM units arranged in an array, and each NVSRAM unit includes an SRAM storage subunit and a non-volatile storage subunit, the non-volatile storage subunit is configured to back up data stored in the SRAM storage subunit; The non-volatile storage operation circuit is configured to perform a data backup operation on the SRAM storage subunit data in the selected NVSRAM unit in the NVSRAM array; The SRAM operation circuit is configured to perform a first data read / write operation on the SRAM storage subunit data; The column selection circuit is configured to perform a data recovery operation on the non-volatile storage subunit data; The column selection circuit is further configured to select the object unit column in the NVSRAM array that needs to be operated in the case of performing the data recovery operation or in the case of the SRAM operation circuit performing the first data read / write operation; The first input / output interface circuit is coupled with the SRAM operation circuit and is configured to provide the received first input data to the SRAM operation circuit and receive the first output data to be output from the SRAM operation circuit; The column selection circuit is further configured to isolate the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit, and to isolate the first data read / write operation, the second data read / write operation and the data recovery operation; The second input / output interface circuit is coupled with the NVSRAM array and is configured to perform a second data read / write operation on the NVSRAM array.

2. The memory device of claim 1, wherein, The second input / output interface circuit includes a shift register operation circuit, an input interface circuit and an output interface circuit, The shift register operation circuit is coupled with the NVSRAM array and is configured to perform the second data read / write operation on the NVSRAM array; The input interface circuit is coupled with the shift register operation circuit and is configured to receive second input data and provide the received second input data to the shift register operation circuit; The output interface circuit is coupled with the shift register operation circuit and is configured to receive the second output data to be output from the shift register operation circuit.

3. The storage device of claim 1, further comprising: The word line driving circuit, The word line drive circuit is configured to select a target cell row in the NVSRAM array to be operated in a case where the SRAM operation circuit performs the first data read / write operation, or in a case where the column selection circuit performs the data recovery operation, or in a case where the second input / output interface circuit performs the second data read / write operation, or in a case where the non-volatile storage operation circuit performs the data backup operation.

4. The memory device of claim 2, wherein, The second output interface circuit further comprises an isolation sub-circuit, wherein the isolation sub-circuit is coupled between the NVSRAM array and the shift register operation circuit; The isolation sub-circuit is configured to turn on the coupling between the shift register operation circuit and the NVSRAM array in a case where the shift register operation circuit performs the second data read / write operation.

5. The storage device of claim 4, wherein, The isolation sub-circuit is further configured to turn off the coupling between the shift register operation circuit and the NVSRAM array in a case where the non-volatile storage operation circuit performs the data backup operation, or in a case where the column selection circuit performs the data recovery operation, or in a case where the SRAM operation circuit performs the first data read / write operation.

6. The memory device of claim 2, wherein, The shift register operation circuit is coupled to the NVSRAM array through N groups of transmission lines; The input interface circuit is coupled to the shift register operation circuit through W2 transmission lines; The output interface circuit is coupled to the shift register operation circuit through W2 transmission lines, wherein W2 and N are integers and N≥W2>1.

7. The memory device of claim 1, wherein, The non-volatile storage operation circuit is further configured to turn off the coupling to the NVSRAM array in a case where the SRAM operation circuit performs the first data read / write operation, or in a case where the column selection circuit performs the data recovery operation, or in a case where the second input / output interface circuit performs the second data read / write operation. The column selection circuit is further configured to turn on the coupling between the SRAM operation circuit and the NVSRAM array in a case where the SRAM operation circuit performs the first data read / write operation. The column selection circuit is further configured to turn off the coupling between the SRAM operation circuit and the NVSRAM array in a case where the data recovery operation is performed. The column selection circuit is further configured to turn off the coupling between the SRAM operation circuit and the NVSRAM array in a case where the second input / output interface circuit performs the second data read / write operation.

8. The memory device of claim 7, wherein, The non-volatile storage operation circuit is further configured to turn on the coupling to the NVSRAM array in a case where the non-volatile storage operation circuit performs the data backup operation. The column selection circuit is further configured to turn off the coupling between the SRAM operation circuit and the NVSRAM array in a case where the non-volatile storage operation circuit performs the data backup operation. The second input / output interface circuit is further configured to turn off the coupling to the NVSRAM array.

9. The memory device of claim 1, wherein, The column selection circuit further comprises a data recovery operation sub-circuit; The data recovery operation sub-circuit is configured to perform the data recovery operation on the non-volatile storage sub-cell data in the object cell column.

10. The storage device of any one of claims 1-9, wherein, The array width of the NVSRAM array is N; The NVSRAM array comprises M rows of the NVSRAM cells; The non-volatile storage operation circuit is coupled with the NVSRAM array through N groups of transmission lines; The SRAM operation circuit is coupled with the input / output interface circuit through W1 groups of transmission lines; The SRAM operation circuit is coupled with the column selection circuit through W1 groups of transmission lines; The column selection circuit is coupled with the NVSRAM array through N groups of transmission lines, wherein W1, N and M are integers and N≥W1>1, M≥1.

11. The memory device of claim 10, wherein, The word line driving circuit is further configured to, in the case that the non-volatile storage operation circuit performs the data backup operation, select SRAM storage sub-cell data in I rows of NVSRAM cells of the NVSRAM array to perform the data backup operation; Or, In the case that the column selection circuit performs the data recovery operation, select non-volatile storage sub-cell data in J rows of NVSRAM cells of the NVSRAM array to perform the data recovery operation, wherein I and J are integers, and M≥I≥1, M≥J≥1.

12. The memory device of claim 10, wherein, The SRAM operation circuit is further configured to, in the case that the first data read / write operation is performed, perform the first data read / write operation on the data of the SRAM storage sub-cell in the selected i-th row of W1 NVSRAM cells of the NVSRAM array; The second input / output interface circuit is further configured to, in the case that the second data read / write operation is performed, perform the second data read / write operation on the data of the SRAM storage sub-cell in the selected i-th row of W2 NVSRAM cells of the NVSRAM array; The non-volatile storage operation circuit is further configured to, in the case that the data backup operation is performed, perform the data backup operation on the data of the SRAM storage sub-cell in the selected E rows and / or F columns of NVSRAM cells of the NVSRAM array; The column selection circuit is further configured to, in the case that the data recovery operation is performed, perform the data recovery operation on the data of the non-volatile storage sub-cell in the selected G rows and / or H columns of NVSRAM cells of the NVSRAM array, wherein i, E, F, G, H, W are integers, and N≥W1≥1, N≥W2≥1, M≥E≥1, M≥G≥1, N≥F≥1, N≥H≥1, M≥i≥1.

13. The storage device of claim 1, further comprising a control circuit, wherein, The control circuit is coupled with the SRAM operation circuit, the non-volatile storage operation circuit, the first input / output interface circuit, the column selection circuit and the second input / output interface circuit, and is configured to provide corresponding control signals to the SRAM operation circuit, the non-volatile storage operation circuit, the first input / output interface circuit, the column selection circuit and the second input / output interface circuit according to the selected working mode.

14. A control method for the storage device of any one of claims 1-13, comprising: in a case where it is determined that the SRAM operation circuit performs the first data read / write operation, disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, controlling the column selection circuit to connect the coupling between the SRAM operation circuit and the NVSRAM array, and controlling the second input / output circuit to disconnect the coupling with the NVSRAM array; or, in a case where it is determined that the second input / output interface circuit performs the second data read / write operation, disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, connecting the coupling between the second input / output interface circuit and the NVSRAM array, and controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array; or, in a case where it is determined that the non-volatile storage operation circuit performs the data backup operation, connecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array, and controlling the second input / output circuit to disconnect the coupling with the NVSRAM array; or, in a case where it is determined that the column selection circuit performs the data recovery operation, disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array, and controlling the second input / output interface circuit to disconnect the coupling with the NVSRAM array.

15. The control method of claim 14, further comprising: receiving a working mode signal; generating a control signal for the first data read / write operation, the data backup operation, the data recovery operation or the second data read / write operation according to the working mode signal; providing the control signal to the SRAM operation circuit, the non-volatile storage operation circuit, the first input / output interface circuit, the column selection circuit or the second input / output interface circuit correspondingly.

16. A storage device comprising: an NVSRAM array, an SRAM operation circuit, a non-volatile storage operation circuit, an error correction circuit, a first input / output interface circuit, a column selection circuit, a second input / output interface circuit, wherein the error correction circuit is coupled with the SRAM operation circuit, the SRAM operation circuit is coupled with the column selection circuit, the column selection circuit is coupled with the NVSRAM array, and the non-volatile storage operation circuit is coupled with the NVSRAM array. The NVSRAM array includes a plurality of NVSRAM units arranged in an array, and each NVSRAM unit includes an SRAM storage subunit and a nonvolatile storage subunit configured to back up data stored in the SRAM storage subunit; The nonvolatile storage operation circuit is configured to perform a data backup operation on the SRAM storage subunit data in the selected NVSRAM unit in the NVSRAM array; The SRAM operation circuit is configured to perform a first data read-write operation on the SRAM storage subunit data; The column selection circuit is configured to perform a data recovery operation on the nonvolatile storage subunit data; The column selection circuit is further configured to select a target unit column in the NVSRAM array to be operated in the case of performing the data recovery operation or in the case of the SRAM operation circuit performing the first data read-write operation; The first input-output interface circuit is coupled to the SRAM operation circuit and configured to provide the received first input data to the SRAM operation circuit and receive the first output data to be output from the SRAM operation circuit; The error detection and correction circuit is configured to encode and decode the target data and determine whether an error occurs in the target data and correct the error; The column selection circuit is further configured to isolate the operation of the SRAM operation circuit and the operation of the nonvolatile storage operation circuit, and isolate the first data read-write operation, the second data read-write operation, and the data recovery operation; The second input-output interface circuit is coupled to the NVSRAM array and configured to perform a second data read-write operation on the NVSRAM array.

17. The memory device of claim 16, wherein, The error detection and correction circuit is further configured to encode the target data input from the SRAM operation circuit to the error detection and correction circuit in the case of the nonvolatile storage operation circuit performing the data backup operation; and The error detection and correction circuit is further configured to determine whether an error occurs in the target data read by the SRAM operation circuit from the NVSRAM array and input to the error detection and correction circuit and correct the error in the case of the column selection circuit completing the data recovery operation. The error detection and correction circuit is further configured to, when encoding, encode the K-bit information code of the read target data to obtain an R-bit check code, and write the R-bit check code into the NVSRAM array through the SRAM operation circuit; and 18. The memory device of claim 17, wherein, The error detection and correction circuit is further configured to, when decoding, decode and detect errors in the K-bit information code and the R-bit check code of the read target data, and perform error correction in response to an error, and write the K-bit corrected information code into the NVSRAM array through the SRAM operation circuit, wherein K and R are positive integers. The second input-output interface circuit includes a shift register operation circuit, an input interface circuit, and an output interface circuit, 19. The memory device of claim 16, wherein, ​ The shift register operation circuit is coupled with the NVSRAM array and is configured to perform the second data read-write operation on the NVSRAM array; The input interface circuit is coupled with the shift register operation circuit and is configured to receive second input data and provide the received second input data to the shift register operation circuit; The output interface circuit is coupled with the shift register operation circuit and is configured to receive second output data to be output from the shift register operation circuit.

20. The storage device of claim 16, further comprising: A word line driving circuit, The word line driving circuit is configured to select a target cell row in the NVSRAM array to be operated in a case where the SRAM operation circuit performs the first data read-write operation, or in a case where the column selection circuit performs the data recovery operation, or in a case where the second input-output interface circuit performs the second data read-write operation, or in a case where the non-volatile storage operation circuit performs the data backup operation.

21. The memory device of claim 19, wherein, The second output interface circuit further comprises an isolation sub-circuit, wherein the isolation sub-circuit is coupled between the NVSRAM array and the shift register operation circuit; The isolation sub-circuit is configured to turn on the coupling between the shift register operation circuit and the NVSRAM array in a case where the shift register operation circuit performs the second data read-write operation.

22. The storage device of claim 21, wherein, The isolation sub-circuit is further configured to turn off the coupling between the shift register operation circuit and the NVSRAM array in a case where the non-volatile storage operation circuit performs the data backup operation, or in a case where the column selection circuit performs the data recovery operation, or in a case where the SRAM operation circuit performs the first data read-write operation.

23. The memory device of claim 19, wherein, The shift register operation circuit is coupled with the NVSRAM array through N groups of transmission lines; The input interface circuit is coupled with the shift register operation circuit through W2 groups of transmission lines; The output interface circuit is coupled with the shift register operation circuit through W2 groups of transmission lines, wherein W2 and N are integers and N≥W2>1.

24. The memory device of claim 16, wherein, The non-volatile storage operation circuit is further configured to turn off the coupling with the NVSRAM array in a case where the SRAM operation circuit performs the first data read-write operation, or in a case where the column selection circuit performs the data recovery operation, or in a case where the second input-output interface circuit performs the second data read-write operation; The column selection circuit is further configured to turn on the coupling between the SRAM operation circuit and the NVSRAM array in a case where the SRAM operation circuit performs the first data read-write operation; The column selection circuit is further configured to turn off the coupling between the SRAM operation circuit and the NVSRAM array in a case where the data recovery operation is performed; The column selection circuit is further configured to disconnect the coupling between the SRAM operation circuit and the NVSRAM array when the second input / output interface circuit performs the second data read / write operation.

25. The memory device of claim 24, wherein, The non-volatile storage operation circuit is further configured to connect the coupling with the NVSRAM array when the non-volatile storage operation circuit performs the data backup operation. The column selection circuit is further configured to disconnect the coupling between the SRAM operation circuit and the NVSRAM array when the non-volatile storage operation circuit performs the data backup operation. The second input / output interface circuit is further configured to disconnect the coupling with the NVSRAM array.

26. The memory device of claim 24, wherein, The column selection circuit further comprises a data recovery operation sub-circuit. The data recovery operation sub-circuit is configured to perform the data recovery operation on the non-volatile storage sub-cell data in the object cell column.

27. The storage device of any of claims 16-26, wherein, The array width of the NVSRAM array is N; The NVSRAM array comprises M rows of NVSRAM cells; The error detection and correction circuit is coupled with the SRAM operation circuit through a transmission line; The SRAM operation circuit is coupled with the input / output interface circuit through a W1 group of transmission lines; The SRAM operation circuit is coupled with the column selection circuit through a W1 group of transmission lines; The column selection circuit is coupled with the NVSRAM array through an N group of transmission lines; The non-volatile storage operation circuit is coupled with the NVSRAM array through an N group of transmission lines, wherein W1, N and M are integers and 1 28. The storage device of claim 27, wherein, The word line driving circuit is further configured to select the SRAM storage sub-cell data in the I row of NVSRAM cells of the NVSRAM array to perform the data backup operation when the non-volatile storage operation circuit performs the data backup operation. Or, The column selection circuit is further configured to select the non-volatile storage sub-cell data in the J row of NVSRAM cells of the NVSRAM array to perform the data recovery operation when the column selection circuit performs the data recovery operation, wherein I and J are integers and M≥I≥1, M≥J≥1.

29. The memory device of claim 27, wherein, The SRAM operation circuit is further configured to perform the first data read / write operation on the data of the SRAM storage sub-cell in the selected W1 NVSRAM cells of the i-th row of the NVSRAM array when performing the first data read / write operation; The second input / output interface circuit is further configured to perform the second data read / write operation on the data of the SRAM storage sub-cell in the selected W2 NVSRAM cells of the i-th row of the NVSRAM array when performing the second data read / write operation; The non-volatile storage operation circuit is further configured to perform the data backup operation on the data of the SRAM storage sub-cell in the selected NVSRAM cells of the E row and / or F column of the NVSRAM array when performing the data backup operation; The column selection circuit is further configured to, in the case of performing the data recovery operation, perform the data recovery operation on the data of the nonvolatile storage sub-cells in the G rows and / or H columns of the NVSRAM cells of the selected NVSRAM array, wherein i, E, F, G, H, W are integers, and N ≥ W1 ≥ 1, N ≥ W2 ≥ 1, M ≥ E ≥ 1, M ≥ G ≥ 1, N ≥ F ≥ 1, N ≥ H ≥ 1, M ≥ i ≥ 1.

30. The storage device of any one of claims 16-29, further comprising a control circuit, wherein, The control circuit is coupled to the SRAM operation circuit, the nonvolatile storage operation circuit, the error detection and correction circuit, the first input / output interface circuit, the column selection circuit, and the second input / output interface circuit, and is configured to provide corresponding control signals to the SRAM operation circuit, the nonvolatile storage operation circuit, the error detection and correction circuit, the first input / output interface circuit, the column selection circuit, and the second input / output interface circuit according to the selected operating mode.

31. A control method for the storage device of any one of claims 16-30, comprising: controlling the error detection and correction circuit to encode and decode the target data and determine whether an error occurs in the target data and correct the error.

32. The control method according to claim 31, wherein controlling the error detection and correction circuit to encode and decode the target data and determine whether an error occurs in the target data and correct the error, comprising: in the case of the nonvolatile storage operation circuit performing the data backup operation, encoding the target data input from the SRAM operation circuit to the error detection and correction circuit; and in the case of the column selection circuit completing the data recovery operation, determining whether an error occurs in the target data read by the SRAM operation circuit from the NVSRAM array and input to the error detection and correction circuit and correcting the error.

33. The control method according to claim 32, wherein in the encoding, encoding the K-bit information code of the read target data to obtain an R-bit check code, and writing the R-bit check code into the NVSRAM array through the SRAM operation circuit; in the decoding, decoding and detecting errors on the K-bit information code and R-bit check code of the read target data, and in response to an error occurring, performing error correction, and writing the K-bit error-corrected information code into the NVSRAM array through the SRAM operation circuit, wherein K and R are positive integers.

34. The control method of claim 31 or 32, further comprising: in the case of determining that the SRAM operation circuit performs the first data read / write operation, disconnecting the coupling between the nonvolatile storage operation circuit and the NVSRAM array, controlling the column selection circuit to connect the coupling between the SRAM operation circuit and the NVSRAM array, and controlling the second input / output circuit to disconnect the coupling with the NVSRAM array; or, in a case where it is determined that the second input / output interface circuit performs the second data read / write operation, disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, connecting the coupling between the second input / output interface circuit and the NVSRAM array, and controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array; or, in a case where it is determined that the non-volatile storage operation circuit performs the data backup operation, connecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, controlling the column selection circuit to disconnect the coupling between the SRAM and the NVSRAM array, and controlling the shift register operation circuit to disconnect the coupling with the NVSRAM array; or, in a case where it is determined that the column selection circuit performs the data recovery operation, disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, controlling the column selection circuit to disconnect the coupling between the SRAM operation circuit and the NVSRAM array, and controlling the second input / output interface circuit to disconnect the coupling with the NVSRAM array.

35. The control method of claim 31, further comprising: receiving an operation mode signal; generating a control signal for the first data read / write operation, the data backup operation, the data recovery operation, the second data read / write operation, or a data error correction operation according to the operation mode signal; providing the control signal to the SRAM operation circuit, the non-volatile storage operation circuit, the column selection circuit, the second input / output interface circuit, the error correction circuit, or the first input / output interface circuit, respectively.

36. The memory device of any one of claims 1-13, 16-30, wherein, The non-volatile storage subunit includes an RRAM, MRAM storage subunit, or PRAM storage subunit.

37. An electronic device, comprising: The storage device of any one of claims 1-13, 16-30. The storage device of any one of claims 1-13, 16-30.

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