Semiconductor device

Abstract

This semiconductor device comprises a first base plate (1) and a second base plate (2) that are joined by a conductive bonding material (3). The second base plate (2) has a lower thermal conductivity than the first base plate (1). A semiconductor chip (4) is provided on the first base plate (1). An electronic component (5) is provided on the second base plate (2). An outer frame (9) is provided on the first base plate (1) and the second base plate (2), and surrounds the semiconductor chip (4) and the electronic component (5). A cap (12) is joined onto the outer frame (9) to hermetically seal the semiconductor chip (4) and the electronic component (5).

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] In a semiconductor device in which a semiconductor chip and electronic components are mounted on a base plate, heat is transferred from the semiconductor chip, which is the heat source, to the electronic components via the base plate. For this reason, when a semiconductor chip that generates a large amount of heat is used, electronic components with a low rated temperature cannot be used. In response to this, it has been proposed to suppress heat transfer by separating the chip and the electronic components from each other by using a base plate (see, for example, Patent Document 1).

[0003] WO 2002 / 017400

[0004] In a semiconductor device in which a semiconductor chip and electronic components are hermetically sealed in a package, there has been a problem in that the hermeticity is lost when the base plate is separated.

[0005] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to obtain a semiconductor device that can ensure airtightness while suppressing heat transfer from a semiconductor chip to electronic components.

[0006] The semiconductor device according to the present disclosure is characterized by comprising a first base plate, a second base plate joined to the first base plate with a conductive bonding material and having a lower thermal conductivity than the first base plate, a semiconductor chip provided on the first base plate, electronic components provided on the second base plate, an outer frame provided on the first base plate and the second base plate and surrounding the semiconductor chip and the electronic components, and a cap joined on the outer frame and hermetically sealing the semiconductor chip and the electronic components.

[0007] In the present disclosure, the second base plate on which the electronic components are mounted has a lower thermal conductivity than the first base plate on which the semiconductor chip is mounted. This makes it possible to suppress heat transfer from the semiconductor chip to the electronic components. Furthermore, because the first base plate and the second base plate are joined with a bonding material, the inside of the package can be hermetically sealed.

[0008] 5 is a cross-sectional view showing a semiconductor device according to a first embodiment. FIG. 6 is a view showing the top surfaces of first and second base plates according to the first embodiment. FIG. 7 is a cross-sectional view showing a semiconductor device according to a second embodiment. FIG. 8 is a cross-sectional view showing a semiconductor device according to a third embodiment. FIG. 9 is a view showing the top surfaces of first and second base plates according to the third embodiment. FIG. 10 is a cross-sectional view taken along line A-A' in FIG. 5. FIG. 11 is a cross-sectional view taken along line B-B' in FIG. 12 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. FIG. 12 is a view showing the top surfaces of first and second base plates according to the fourth embodiment. FIG. 13 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. FIG. 14 is a view showing the top surface of the first base plate according to the fifth embodiment. FIG. 15 is a cross-sectional view showing a semiconductor device according to a sixth embodiment. FIG. 16 is a view showing the top surface of the first base plate according to the sixth embodiment.

[0009] A semiconductor device according to an embodiment will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

[0010] First Embodiment FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. FIG. 2 is a diagram showing the top surfaces of first and second base plates according to the first embodiment. The first base plate 1 and the second base plate 2 are joined by a conductive joining material 3. The joining material 3 is, for example, an Ag brazing material or an AuSn solder. The first base plate 1 is made of, for example, a Cu-Mo alloy. The second base plate 2 is made of an Fe-Ni-Co alloy. The second base plate 2 has a lower thermal conductivity than the first base plate 1. A cheaper material can be selected for the second base plate 2, which has low heat dissipation properties, than for the first base plate 1, which has high heat dissipation properties, thereby reducing costs.

[0011] A semiconductor chip 4 is provided on a first base plate 1. An electronic component 5 is provided on a second base plate 2. A lower electrode 4a of the semiconductor chip 4 is electrically connected to the first base plate 1 via a bonding material 6. A lower electrode 5a of the electronic component 5 is electrically connected to the second base plate 2 via a bonding material 7. Because the first base plate 1 and the second base plate 2 are electrically connected via the bonding material 3, the lower electrode 4a of the semiconductor chip 4 and the lower electrode 5a of the electronic component 5 can be connected to a common ground potential.

[0012] The top electrode 4b of the semiconductor chip 4 and the top electrode 5b of the electronic component 5 are electrically connected by a wire 8. The semiconductor chip 4 is, for example, a high-frequency amplifier of a monolithic microwave integrated circuit (MMIC). The electronic component 5 is, for example, a capacitor shunt-connected to the input side of the semiconductor chip 4.

[0013] An outer frame 9 is provided on the first base plate 1 and the second base plate 2 and surrounds the semiconductor chip 4 and electronic components 5. The outer frame 9 has a three-layer structure of ceramics 9a to 9c and a seal ring 9d. The upper surface of the upper ceramic 9c is metallized and is bonded to the lower surface of the seal ring 9d with a bonding material 10. The lower surface of the middle ceramic 9b is metallized and is bonded to the outer periphery of the upper surfaces of the first base plate 1 and the second base plate 2 with a bonding material 11. A cap 12 is bonded to the upper surface of the seal ring 9d with a bonding material 13, hermetically sealing the semiconductor chip 4 and electronic components 5 inside the package. The space between the first base plate 1 and the second base plate 2 is completely filled with a bonding material 3, and the spaces between the middle ceramic 9b and the first base plate 1 and the second base plate 2 are also completely filled with a bonding material 11, ensuring airtightness.

[0014] The same material may be used for the bonding materials 3, 6, 7, 10, 11, and 13. However, while brazing filler metal can be used to bond metal and ceramic, solder cannot be used as is. Therefore, when solder is used as the bonding materials 10 and 11, it is necessary to metallize the upper surface of the upper ceramic 9c and the lower surface of the middle ceramic 9b.

[0015] As described above, in this embodiment, the second base plate 2 on which the electronic components 5 are mounted has a lower thermal conductivity than the first base plate 1 on which the semiconductor chip 4 is mounted. This makes it possible to suppress heat transfer from the semiconductor chip 4 to the electronic components 5 while dissipating heat from the semiconductor chip 4. As a result, even when a semiconductor chip 4 that generates a large amount of heat is used, electronic components 5 with a low rated temperature can be used. Furthermore, because the first base plate 1 and the second base plate 2 are bonded with the bonding material 3, the inside of the package can be hermetically sealed. This makes it possible to prevent deterioration of the semiconductor chip 4 due to moisture or gas outside the package.

[0016] Ceramic capacitors used in high-frequency devices mainly use high-dielectric-constant barium titanate-based materials. This material has temperature characteristics, and its rated temperature is low because its capacitance changes significantly at high temperatures. Therefore, this embodiment is particularly effective when the electronic component 5 is a ceramic capacitor that uses high-dielectric-constant barium titanate-based material.

[0017] The bandgap of GaN is 3.4 eV, which is larger than the bandgap of GaAs, which is 1.424 eV. A semiconductor material with a high bandgap has a high breakdown voltage and can operate at high voltages. GaN devices generate more heat than GaAs devices, so this embodiment is particularly effective when the semiconductor chip 4 is a GaN device.

[0018] 3 is a cross-sectional view showing a semiconductor device according to a second embodiment. The joining surfaces of the first base plate 1 and the second base plate 2 are inclined. Therefore, when the first base plate 1 and the second base plate 2 are placed in a high-temperature furnace for joining, the first base plate 1 and the second base plate 2 are held in contact with each other by friction. Therefore, it is sufficient to place the first base plate 1 and the second base plate 2 on a flat jig; there is no need to use a jig that forces the two plates into contact.

[0019] The spread of heat downward from the semiconductor chip 4 follows the 45-degree rule. For this reason, it is desirable that the bonding surface of the first base plate 1 be inclined at 45 degrees with respect to the bottom surface of the first base plate 1. This ensures that heat dissipation from the semiconductor chip 4 is not hindered. The other configurations and effects are the same as those of the first embodiment.

[0020] Third Embodiment FIG. 4 is a cross-sectional view showing a semiconductor device according to a third embodiment. FIG. 5 is a view showing the top surfaces of first and second base plates according to the third embodiment. FIG. 6 is a cross-sectional view taken along line A-A' in FIG. 5. FIG. 7 is a cross-sectional view taken along line B-B' in FIG. 5. The lower region of the bonding surface of the first base plate 1 and the lower region of the bonding surface of the second base plate 2 are bonded by a bonding material 3. An alumina coating 14 is applied to the upper region of the bonding surface of the second base plate 2. The alumina coating 14 has poorer wettability with the bonding material 3 than the material of the second base plate 2. Note that the alumina coating 14 may also be applied to the upper region of the bonding surface of the first base plate 1. That is, the upper region of the bonding surface of the first base plate 1 or the second base plate 2 is treated to prevent the bonding material 3 from spreading. Therefore, the bonding material 3 does not spread between the upper region of the bonding surface of the first base plate 1 and the upper region of the bonding surface of the second base plate 2, and an air layer 15 exists. This air layer 15 can further suppress the heat transfer from the semiconductor chip 4 to the electronic component 5. As a result, it is possible to further suppress the temperature rise of the electronic component 5. The other configurations and effects are the same as those of the first embodiment.

[0021] Fourth Embodiment Fig. 8 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. Fig. 9 is a view showing the top surfaces of first and second base plates according to the fourth embodiment. The second base plate 2 is disposed on the first base plate 1 and has an opening 2a. The semiconductor chip 4 is provided on the first base plate 1 in the opening 2a of the second base plate 2 without going through the second base plate 2. Even with this configuration, heat transfer from the semiconductor chip 4 to the electronic component can be suppressed, and the inside of the package can be hermetically sealed. The other configurations and effects are the same as those of the first embodiment.

[0022] Fifth Embodiment FIG. 10 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. FIG. 11 is a view showing the top surface of a first base plate according to the fifth embodiment. An alumina coating 14 is applied to the top surface of the first base plate 1 below the electronic components 5. The alumina coating 14 has poorer wettability with the bonding material 3 than the material of the first base plate 1. That is, the top surface of the first base plate 1 below the electronic components 5 is treated to prevent the bonding material 3 from spreading. Therefore, the bonding material 3 does not spread below the electronic components 5, and an air layer 15 exists between the first base plate 1 and the second base plate 2. This air layer 15 further suppresses heat transfer from the semiconductor chip 4 to the electronic components 5. As a result, the temperature rise of the electronic components 5 can be further suppressed. The other configurations and effects are the same as those of the fourth embodiment.

[0023] Sixth Embodiment Fig. 12 is a cross-sectional view showing a semiconductor device according to a sixth embodiment. Fig. 13 is a view showing the top surface of a first base plate according to the sixth embodiment. In the fifth embodiment, the second base plate 2 is not bonded to the first base plate 1 between the air layer 15 and the semiconductor chip 4, and has a floating cantilever structure. In contrast, in the present embodiment, the first base plate 1 and the second base plate 2 are bonded by a bonding material 3 in an area surrounding the entire periphery of the air layer 15. By supporting the entire periphery of the air layer 15, the second base plate 2 is less likely to break than the cantilever structure of the fifth embodiment. Other configurations and effects are the same as those of the fifth embodiment.

[0024] REFERENCE SIGNS LIST 1 First base plate, 2 Second base plate, 2a Opening, 3 Bonding material, 4 Semiconductor chip, 4a, 5a Lower electrode, 4b, 5b Upper electrode, 5 Electronic component, 8 Wire, 9 Outer frame, 12 Cap, 14 Alumina coating (treatment to prevent wetting and spreading of bonding material), 15 Air layer

Claims

1. A semiconductor device comprising: a first base plate; a second base plate joined to the first base plate with a conductive bonding material and having a lower thermal conductivity than the first base plate; a semiconductor chip provided on the first base plate; electronic components provided on the second base plate; an outer frame provided on the first base plate and the second base plate and surrounding the semiconductor chip and the electronic components; and a cap joined on the outer frame and hermetically sealing the semiconductor chip and the electronic components.

2. The semiconductor device described in claim 1, characterized in that the first base plate and the second base plate are electrically connected via the bonding material, the bottom electrode of the semiconductor chip is electrically connected to the first base plate, the bottom electrode of the electronic component is electrically connected to the second base plate, and the top electrode of the semiconductor chip and the top electrode of the electronic component are electrically connected by wires.

3. The semiconductor device according to claim 2, wherein the semiconductor chip is a high-frequency amplifier, and the electronic component is a capacitor.

4. The semiconductor device according to claim 3, wherein the electronic component is a ceramic capacitor using a high dielectric constant barium titanate material.

5. The semiconductor device according to claim 3 or 4, wherein the semiconductor chip is a GaN device.

6. The semiconductor device according to any one of claims 1 to 5, wherein the bonding surfaces of the first base plate and the second base plate are inclined.

7. The semiconductor device according to claim 6, wherein the bonding surface is inclined at 45 degrees with respect to the bottom surface of the first base plate.

8. A semiconductor device as described in any one of claims 1 to 5, characterized in that the lower region of the bonding surface of the first base plate and the lower region of the bonding surface of the second base plate are bonded by the bonding material, the upper region of the bonding surface of the first base plate or the second base plate is treated to prevent the bonding material from spreading by wetting, and an air layer exists between the upper region of the bonding surface of the first base plate and the upper region of the bonding surface of the second base plate.

9. A semiconductor device according to any one of claims 1 to 5, characterized in that the second base plate is disposed on the first base plate and has an opening, and the semiconductor chip is provided on the first base plate in the opening.

10. A semiconductor device as described in claim 9, characterized in that below the electronic components, the upper surface of the first base plate is treated to prevent the bonding material from spreading, and an air layer exists between the first base plate and the second base plate.

11. The semiconductor device according to claim 10, wherein the first base plate and the second base plate are bonded together by the bonding material in the region surrounding the air layer.

Images