Display device and method for manufacturing same

Abstract

This display device (50a) comprises: a TFT layer (20a) including a lower metal layer (LW), an interlayer insulating film (IL) covering the lower metal layer, and an upper metal layer (UW) provided on the interlayer insulating film; a display region (D); a frame region (F); a terminal part (T) provided at one end of the frame region (F); a wiring part (W) provided between the display region (F) and the terminal part (T); and a plurality of first wires (18h, 18i) provided in the display region (D) and the terminal part (T) and formed by the same material in the same layer as the upper metal layer (UW). The wiring part (W) is provided with at least one wiring dummy pattern (18ja) formed by the same material in the same layer as the upper metal layer (UW).

Description

Display device and manufacturing method thereof

[0001] The present invention relates to a display device and a manufacturing method thereof.

[0002] In recent years, self-luminous organic electroluminescence (EL) display devices using organic electroluminescence (EL) elements have been attracting attention as a display device to replace liquid crystal display devices. For example, a display device has been proposed that includes a TFT layer on a substrate, in which a plurality of thin film transistors (TFTs) are formed on the substrate to drive the organic EL elements for each subpixel that constitutes a display area. The TFT layer has a laminated structure in which a plurality of metal layers are stacked with an interlayer insulating film interposed therebetween.

[0003] For example, Patent Document 1 proposes a display device including a TFT array substrate on which multiple wiring lines are formed and an opposing substrate facing the TFT array substrate. In this display device, the TFT array substrate has a conductive dummy pattern formed above the wiring lines via an insulating film near the edge of the display panel where the wiring terminals are formed. This allows the dummy pattern on the TFT array substrate to absorb impacts on the wiring lines when the opposing substrate is cut.

[0004] JP 2010-230885 A

[0005] In a display device including a TFT layer having the above-described laminated structure, for example, a metal layer is formed on a substrate surface, and then the metal layer is patterned to form multiple wirings. For example, in a wiring structure in which a region where multiple wirings are densely arranged is adjacent to a region where no wirings are arranged, the pattern density of the wirings may differ significantly between adjacent regions. In a region where the pattern density of the wirings is significantly smaller than that of adjacent regions, the etching area of ​​the metal layer (the area from which the metal layer is removed) becomes significantly larger, resulting in a slow etching rate. In this case, a film residue (metal layer residue) may be generated after etching the metal layer, which may cause leakage defects between wirings (hereinafter also referred to as "inter-wiring leakage") due to the film residue.

[0006] Although Patent Document 1 describes the protection of wiring from impact, it does not describe the pattern density of wiring or the film residue caused by the decrease in the pattern density.

[0007] The present invention has been made in view of the above points, and an object of the present invention is to reduce the film residue of the metal layer caused by a decrease in the pattern density of the wiring.

[0008] In order to achieve the above-mentioned object, the display device of the present invention is a display device comprising: a base substrate; a thin-film transistor layer provided on the base substrate and including a lower metal layer, an interlayer insulating film provided to cover the lower metal layer, and an upper metal layer provided on the interlayer insulating film; a light-emitting element layer provided on the thin-film transistor layer and constituting a display area; a frame region provided around the display area; a terminal portion provided at one end of the frame region; a wiring portion provided between the display area and the terminal portion; and a plurality of first wirings provided in the display area and the terminal portion and formed in the same layer using the same material as the upper metal layer, wherein the wiring portion is provided with at least one wiring dummy pattern formed in the same layer using the same material as the upper metal layer.

[0009] The manufacturing method of the display device according to the present invention is a manufacturing method of a display device comprising: a base substrate; a thin-film transistor layer provided on the base substrate, the thin-film transistor layer including a lower metal layer, an interlayer insulating film provided to cover the lower metal layer, and an upper metal layer provided on the interlayer insulating film; a light-emitting element layer provided on the thin-film transistor layer and constituting a display area; a frame region provided around the display area; a terminal portion provided at one end of the frame region; a wiring portion provided between the display area and the terminal portion; and a plurality of first wirings provided in the display area and the terminal portion and formed in the same layer using the same material as the upper metal layer, wherein in a thin-film transistor layer formation process for forming the thin-film transistor layer, after the upper metal layer is formed on the surface of the substrate on which the interlayer insulating film is formed, at least one wiring dummy pattern is formed in the wiring portion when the upper metal layer is patterned to form the plurality of first wirings.

[0010] According to the present invention, it is possible to reduce the amount of metal layer film remaining due to a decrease in the pattern density of the wiring.

[0011] FIG. 1 is a plan view showing a schematic configuration of an organic EL display device according to a first embodiment of the present invention. FIG. 2 is a plan view of a display region of the organic EL display device according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view of the display region of the organic EL display device according to the first embodiment of the present invention. FIG. 4 is an equivalent circuit diagram of a TFT layer constituting the organic EL display device according to the first embodiment of the present invention. FIG. 5 is an enlarged plan view showing the wiring pattern of the wiring portion in the frame region of the organic EL display device according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5 showing the wiring pattern of the wiring portion in the frame region of the organic EL display device according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view of an organic EL layer constituting the organic EL display device according to the first embodiment of the present invention. FIG. 8 is an enlarged plan view showing the wiring pattern of the wiring portion in the frame region of an organic EL display device according to a second embodiment of the present invention, and corresponds to FIG. 5. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 8 showing the wiring pattern of the wiring portion in the frame region of the organic EL display device according to the second embodiment of the present invention. FIG. 10 is an enlarged plan view showing the electrode pattern of the organic EL element layer in the display region of an organic EL display device according to a third embodiment of the present invention.

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.

[0013] First Embodiment FIGS. 1 to 7 illustrate a first embodiment of a display device according to the present invention. In the following embodiments, an organic EL display device including organic EL elements is exemplified as a display device including light-emitting elements. FIG. 1 is a plan view showing a schematic configuration of an organic EL display device 50a according to this embodiment. FIG. 2 is a plan view of a display region D of the organic EL display device 50a. FIG. 3 is a cross-sectional view of the display region D of the organic EL display device 50a. FIG. 4 is an equivalent circuit diagram of a TFT layer 20a constituting the organic EL display device 50a. FIG. 5 is an enlarged plan view showing the wiring pattern of the wiring unit W in the frame region F of the organic EL display device 50a. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5 showing the wiring pattern of the wiring unit W in the frame region F of the organic EL display device 50a. FIG. 7 is a cross-sectional view of an organic EL layer 33 constituting the organic EL display device 50a. Note that the upper layer of an upper metal layer UW, which will be described later, is omitted from FIG. 5.

[0014] 1 , the organic EL display device 50a includes, for example, a rectangular display area D for displaying an image, and a frame area F provided in a frame shape around the display area D. While the rectangular display area D is illustrated in the present embodiment, this rectangular shape also includes a substantially rectangular shape, such as a shape with arc-shaped sides, a shape with arc-shaped corners, or a shape with a notch in one side. The organic EL display device 50a has defined therein a first direction X parallel to the substrate surface of a resin substrate 10 (described later), a second direction Y perpendicular to the first direction X and parallel to the substrate surface, and a third direction Z perpendicular to the first direction X and the second direction Y (see FIG. 6 ).

[0015] In the display region D, a plurality of sub-pixels P are arranged in a matrix, as shown in Fig. 2. In the display region D, for example, a sub-pixel P having a red light-emitting region Lr for displaying red, a sub-pixel P having a green light-emitting region Lg for displaying green, and a sub-pixel P having a blue light-emitting region Lb for displaying blue are arranged adjacent to one another, as shown in Fig. 2. In the display region D, one pixel is formed by, for example, three adjacent sub-pixels P each having a red light-emitting region Lr, a green light-emitting region Lg, and a blue light-emitting region Lb. The arrangement of the sub-pixels P is not particularly limited, and examples thereof include a pentatile arrangement and a stripe arrangement.

[0016] 1, a terminal portion T is provided at one end (the lower end in FIG. 1) of the frame region F so as to extend in one direction (first direction X, the horizontal direction in FIG. 1). In the terminal portion T, for example, a plurality of terminals t for supplying signals to the display panel are arranged along the first direction X.

[0017] 1 , the organic EL display device 50a includes a wiring portion W in a frame region F between a display region D and a terminal portion T. Note that a folding portion (not shown) that can be folded, for example, 180 degrees (in a U-shape) with the first direction X as the folding axis may be provided in the frame region F between the display region D and the terminal portion T (a portion that overlaps with the wiring portion W in a plan view) so as to extend in one direction (the first direction X).

[0018] As shown in FIG. 3, the organic EL display device 50 a includes a resin substrate 10 provided as a base substrate, and a TFT layer 20 a provided on the resin substrate 10 .

[0019] The resin substrate 10 is made of, for example, polyimide resin.

[0020] As shown in FIG. 3, the TFT layer 20a includes a base coat film 11 provided on a resin substrate 10, a plurality of first TFTs 9a, a plurality of second TFTs 9b, and a plurality of capacitors 9c provided on the base coat film 11 for each subpixel P, and a planarization film 19 provided on each of the first TFTs 9a, each of the second TFTs 9b, and each of the capacitors 9c. 3, the TFT layer 20a includes a base coat film 11, semiconductor layers 12a and 12b, a gate insulating film 13, a first metal layer including gate lines 14 (see FIG. 2), gate electrodes 14a and 14b, and a lower conductive layer 14c, a first interlayer insulating film 15, a second metal layer including upper conductive layer 16, a second interlayer insulating film 17, a third metal layer including source lines 18f (see FIG. 2), source electrodes 18a and 18c, drain electrodes 18b and 18d, and a power line 18g, and a planarization film 19, which are stacked in this order on a resin substrate 10. Also, as shown in FIGS. 2 and 4, the TFT layer 20a includes a plurality of gate lines 14 extending parallel to one another in the horizontal direction in the drawings. Also, as shown in FIGS. 2 and 4, the TFT layer 20a includes a plurality of source lines 18f extending parallel to one another in a direction intersecting (orthogonal to) the plurality of gate lines 14, i.e., in the vertical direction in the drawings. 2 and 4, the TFT layer 20a is provided with a plurality of power supply lines 18g extending parallel to one another in the vertical direction in the drawings. Each power supply line 18g is provided adjacent to a corresponding source line 18f, as shown in Fig. 2. Furthermore, in the TFT layer 20a, a first TFT 9a, a second TFT 9b, and a capacitor 9c are provided in each sub-pixel P, as shown in Fig. 4.

[0021] The base coat film 11, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 may be made of, for example, silicon nitride (SiNx (x is a positive number)), silicon oxide (SiO ２The semiconductor layers 12a and 12b are each composed of a single layer or a stacked layer of an inorganic insulating film such as silicon oxynitride (SiON). The semiconductor layers 12a and 12b are composed of, for example, a low-temperature polysilicon film or an In—Ga—Zn—O-based oxide semiconductor film. The first metal layer, the second metal layer, and the third metal layer are each composed of, for example, a metal single layer film of molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), tungsten (W), or the like, or a metal stacked layer film of Mo (upper layer) / Al (middle layer) / Mo (lower layer), Ti / Al / Ti, Al (upper layer) / Ti (lower layer), Cu / Mo, Cu / Ti, or the like.

[0022] The first TFT 9a and the second TFT 9b are p-type TFTs in which semiconductor layers 12a and 12b (described later) are doped with impurities such as boron.

[0023] As shown in FIG. 4 , the first TFT 9a is electrically connected to the corresponding gate line 14 and source line 18f in each subpixel P. As shown in FIG. 3 , the first TFT 9a includes a semiconductor layer 12a, a gate insulating film 13, a gate electrode 14a, a first interlayer insulating film 15, a second interlayer insulating film 17, a source electrode 18a, and a drain electrode 18b, which are sequentially disposed on a base coat film 11. As shown in FIG. 3 , the semiconductor layer 12a is disposed on the base coat film 11 in an island shape and has, for example, a channel region, a source region, and a drain region. As shown in FIG. 3 , the gate insulating film 13 is disposed so as to cover the semiconductor layer 12a. As shown in FIG. 3 , the gate electrode 14a is disposed on the gate insulating film 13 so as to overlap the channel region of the semiconductor layer 12a. As shown in FIG. 3 , the first interlayer insulating film 15 and the second interlayer insulating film 17 are disposed so as to cover the gate electrode 14a. 3, the source electrode 18a and the drain electrode 18b are provided spaced apart from each other on the second interlayer insulating film 17. The source electrode 18a and the drain electrode 18b are electrically connected to the source region and the drain region of the semiconductor layer 12a, respectively, through contact holes formed in the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17.

[0024] As shown in FIG. 4 , the second TFT 9b is electrically connected to the corresponding first TFT 9a and power line 18g in each subpixel P. As shown in FIG. 3 , the second TFT 9b includes a semiconductor layer 12b, a gate insulating film 13, a gate electrode 14b, a first interlayer insulating film 15, a second interlayer insulating film 17, a source electrode 18c, and a drain electrode 18d, which are sequentially disposed on a base coat film 11. As shown in FIG. 3 , the semiconductor layer 12b is disposed on the base coat film 11 in an island shape and has, for example, a channel region, a source region, and a drain region. As shown in FIG. 3 , the gate insulating film 13 is disposed so as to cover the semiconductor layer 12b. As shown in FIG. 3 , the gate electrode 14b is disposed on the gate insulating film 13 so as to overlap the channel region of the semiconductor layer 12b. As shown in FIG. 3 , the first interlayer insulating film 15 and the second interlayer insulating film 17 are sequentially disposed so as to cover the gate electrode 14b. 3, the source electrode 18c and the drain electrode 18d are provided spaced apart from each other on the second interlayer insulating film 17. The source electrode 18c and the drain electrode 18d are electrically connected to the source region and the drain region of the semiconductor layer 12b, respectively, through contact holes formed in the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17.

[0025] In this embodiment, the first TFT 9a and the second TFT 9b are top-gate type TFTs, but the first TFT 9a and the second TFT 9b may be bottom-gate type TFTs.

[0026] As shown in Fig. 4, the capacitor 9c is electrically connected to the corresponding first TFT 9a and power supply line 18g in each subpixel P. Here, as shown in Fig. 3, the capacitor 9c includes a lower conductive layer 14c formed in the same layer and made of the same material as the gate electrodes 14a and 14b, a first interlayer insulating film 15 provided so as to cover the lower conductive layer 14c, and an upper conductive layer 16 provided on the first interlayer insulating film 15 so as to overlap the lower conductive layer 14c. Note that the upper conductive layer 16 is electrically connected to the power supply line 18g via a contact hole formed in a second interlayer insulating film 17, as shown in Fig. 3.

[0027] The planarization film 19 has a flat surface in the display region D, and is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG (spin on glass) material.

[0028] The TFT layer 20a configured as described above has a laminated structure in which a lower metal layer LW, an interlayer insulating film IL, and an upper metal layer UW are laminated in this order, as shown in FIGS.

[0029] The lower metal layer LW is formed in the same layer and made of the same material as the first metal layer (gate line 14, gate electrodes 14a and 14b, lower conductive layer 14c, etc.) and the second metal layer (upper conductive layer 16, etc.) provided in the TFT layer 20a. The lower metal layer LW made of the first metal layer is provided on the gate insulating film 13 that constitutes the TFT layer 20a. The lower metal layer LW made of the second metal layer is provided on the first interlayer insulating film 15 that constitutes the TFT layer 20a.

[0030] The interlayer insulating film IL is provided so as to cover the lower metal layer LW. Examples of the interlayer insulating film IL include a first interlayer insulating film 15 that covers the lower metal layer LW made of a first metal layer, and a second interlayer insulating film 17 that covers the lower metal layer LW made of a second metal layer. The interlayer insulating film IL may be a single layer film or a multilayer film.

[0031] The upper metal layer UW refers to a metal layer located above the lower metal layer LW. The upper metal layer UW is formed in the same layer and made of the same material as, for example, the second metal layer (upper conductive layer 16, etc.) and the third metal layer (source line 18f, source electrodes 18a and 18c, drain electrodes 18b and 18d, power line 18g, etc.) (see FIG. 3). The upper metal layer UW, which is made of the second metal layer, is provided on the first interlayer insulating film 15 as an interlayer insulating film IL. The lower metal layer LW, which is made of the same layer as the third metal layer, is provided on the second interlayer insulating film 17 as an interlayer insulating film IL.

[0032] The lower metal layer LW, the interlayer insulating film IL, and the upper metal layer UW are not limited to those exemplified above, and may be applied to a laminated structure in which a metal layer, an insulating film, and a metal layer are laminated in this order. For example, when a fourth metal layer (such as a conductive layer between the third metal layer and the first electrode 31 described later) is provided above the third metal layer, the upper metal layer UW may be formed in the same layer as the fourth metal layer using the same material.

[0033] Below, the organic EL display device 50a will be described using as an example a TFT layer 20a having a lower metal layer LW made of a first metal layer, an interlayer insulating film IL made of a stacked film of a first interlayer insulating film 15 and a second interlayer insulating film 17, and an upper metal layer UW made of a third metal layer.

[0034] As shown in Figures 1, 5, and 6, first wirings 18h and 18i (hereinafter also collectively referred to as "first wirings 18h, 18i") formed in the same layer as the third metal layer and made of the same material as the upper metal layer are provided on the second interlayer insulating film 17 (interlayer insulating film IL).

[0035] A plurality of first wirings 18h (upper metal layer UW) are provided so as to extend parallel to each other in the second direction Y from the display region D toward the terminal portion T. The plurality of first wirings 18h are arranged in a region spanning from the display region D to the wiring portion W. The plurality of first wirings 18h are provided up to the corresponding plurality of contact holes Ha.

[0036] A plurality of first wirings 18i (upper metal layer UW) are provided so as to extend parallel to each other in the second direction Y from the contact hole Hb toward the terminal portion T. The plurality of first wirings 18i are arranged in a region spanning from the wiring portion W to the terminal portion T. The plurality of first wirings 18i are provided up to the corresponding plurality of terminals t. The plurality of first wirings 18i are electrically connected to the corresponding plurality of terminals t, respectively.

[0037] As shown in FIGS. 1, 5 and 6, a plurality of second wirings 14d are provided on the gate insulating film 13 as a lower metal layer LW, and are formed in the same layer as the first metal layer using the same material.

[0038] A plurality of second wirings 14d (lower metal layers LW) are provided so as to extend parallel to each other in the second direction Y from the contact hole Ha to the contact hole Hb. The plurality of second wirings 14d are arranged in a wiring portion W, which is a region spanning from the contact hole Ha to the contact hole Hb.

[0039] The contact holes Ha are portions (contact portions) that connect the second wirings 14d and the corresponding first wirings 18h. As shown in FIG. 6 , a plurality of contact holes Ha are formed in the interlayer insulating film IL so as to penetrate the stacked film (interlayer insulating film IL) of the first interlayer insulating film 15 and the second interlayer insulating film 17. The contact holes Ha are formed for each second wiring 14d so as to expose at least a portion of one end (end on the display area D side) of the second wiring 14d. As a result, the plurality of second wirings 14d are electrically connected to the corresponding plurality of first wirings 18h via the plurality of contact holes Ha.

[0040] The contact holes Hb are portions (contact portions) that connect the second wirings 14d and the corresponding first wirings 18i. As shown in FIG. 6 , a plurality of contact holes Hb are formed in the interlayer insulating film IL so as to penetrate the stacked film (interlayer insulating film IL) of the first interlayer insulating film 15 and the second interlayer insulating film 17. The contact holes Hb are formed for each second wiring 14d so as to expose at least a portion of the other end (end on the terminal portion T side) of the second wiring 14d. As a result, the plurality of second wirings 14d are electrically connected to the corresponding plurality of first wirings 18i via the plurality of contact holes Hb.

[0041] 1, 5, and 6, in the organic EL display device 50a configured as described above, the first wirings 18h and 18i (upper metal layer UW) are reconnected to the second wirings 14d (lower metal layer LW) located below the upper metal layer UW and the interlayer insulating film IL in the wiring portion W in the frame region F. In other words, the first wirings 18h and 18i do not exist in the wiring portion W.

[0042] In the wiring structure (wiring pattern) of the TFT layer constituting a conventional organic EL display device, the pattern density of the upper metal layer UW in the wiring section W is significantly lower than the pattern density in the adjacent display area D and terminal section T. In wiring sections W with low pattern density, the etching area of ​​the upper metal layer UW (the area from which the upper metal layer UW is removed) is extremely large, resulting in a slow etching rate and making it more likely that film residue (residue of the upper metal layer UW) of the upper metal layer UW will remain after etching. Specifically, in areas with low pattern density, dry etching gas is used to remove the film, resulting in film residue on the mother glass surface. This may cause leakage between wirings due to the film residue of the upper metal layer UW. Furthermore, if there is a crack in the interlayer insulating film IL below the upper metal layer UW, etching the upper metal layer UW may etch the lower metal layer LW below the interlayer insulating film IL, potentially resulting in a disconnection of the lower metal layer LW. As described above, in the conventional organic EL display device, there is a risk of wiring defects occurring in the area (wiring portion W) where the pattern density is low.

[0043] In contrast, in the organic EL display device 50a, as shown in Figures 5 and 6, in the region (wiring portion W) where the pattern density of the upper metal layer UW is low, a plurality of wiring dummy patterns 18ja made of the third metal layer are provided as the upper metal layer UW. The wiring dummy patterns 18ja are arranged in areas that overlap, in a plan view, with the wiring patterns of the second wiring 14d made of the first metal layer as the lower metal layer LW. By arranging the wiring dummy patterns 18ja in the wiring portion W, the pattern density of the upper metal layer UW in the wiring portion W is increased (the etching area is reduced), and a decrease in the etching rate is suppressed. As a result, in the organic EL display device 50a, the occurrence of film residue after etching of the upper metal layer UW is suppressed, making the above-mentioned wiring defects less likely to occur.

[0044] The region with low pattern density (wiring portion W) refers to a region having a size (area) of, for example, 100 μm × 100 μm or more. A standard (guideline) for arranging the wiring dummy patterns 18ja is, for example, a pattern density of less than 20% when the area of ​​the upper metal layer UW provided in the wiring portion W is taken as 100%. From the perspective of reducing the above-mentioned wiring defects, as described in the following examples, it is preferable that the total area (pattern density) of the multiple wiring dummy patterns 18ja be 20% or more when the area of ​​the upper metal layer UW provided in the wiring portion W is taken as 100%. The number of wiring dummy patterns 18ja to be arranged in the wiring portion W, as well as their respective shapes, pitches, intervals, size (areas), etc., can be appropriately determined based on the above.

[0045] A plurality of wiring dummy patterns 18ja are provided in a floating island structure, and adjacent patterns are not electrically connected to each other. The wiring dummy patterns 18ja are also not electrically connected to the upper metal layer UW (the third metal layer including the first wirings 18h, 18i, etc.), the lower metal layer LW (the first metal layer including the second wirings 14d, etc.), or the fourth metal layer. That is, the wiring dummy patterns 18ja are not electrically connected to any of the metal layers.

[0046] The planar shape of each wiring dummy pattern 18ja is not particularly limited as long as it is island-shaped, and may be, for example, rectangular, circular, elliptical, or the like. It may also be strip-shaped extending in the direction in which the first wirings 18h and 18i extend (second direction Y), or strip-shaped extending in a direction perpendicular to (intersecting) the second direction Y (first direction X). For example, in the case of a rectangular shape, the size (area) of each wiring dummy pattern 18ja is approximately 30 μm × 50 μm. Furthermore, the planar shape of an assembly (block B18ja indicated by dotted lines in FIG. 5 ) of multiple wiring dummy patterns 18ja is not particularly limited, and may be, for example, rectangular (strip-shaped), circular, elliptical, or the like.

[0047] 5 , the distance (spacing) D18hj between the first wiring 18h (its terminal T-side end) and the wiring dummy pattern 18ja (its display area D-side end) in the extension direction of the first wiring 18h (second direction Y) is larger than the pitch P18h between adjacent first wirings 18h in the direction (first direction X) perpendicular to (intersecting) the extension direction of the first wiring 18h (D18hj>P18h). Similarly, the distance D18ij between the first wiring 18i (its display area D-side end) and the wiring dummy pattern 18ja (its terminal T-side end) in the extension direction of the first wiring 18i (second direction Y) is larger than the pitch P18i between adjacent first wirings 18i in the direction (first direction X) perpendicular to (intersecting) the extension direction of the first wiring 18i (D18ij>P18i).

[0048] In the direction (first direction X) perpendicular to the direction in which the first wirings 18h extend, the pitch P18h between adjacent first wirings 18h is different from the pitch P18j between adjacent wiring dummy patterns 18ja (P18h ≠ P18j). Similarly, in the direction (first direction X) perpendicular to the direction in which the first wirings 18i extend, the pitch P18i between adjacent first wirings 18i is different from the pitch P18j (P18i ≠ P18j).

[0049] The distance (interval) between adjacent wiring dummy patterns 18ja in the first direction X may be the same as or different from the distance between adjacent wiring dummy patterns 18ja in the second direction Y. For example, the distance between adjacent wiring dummy patterns 18ja is about 20 μm.

[0050] As shown in FIG. 3, the organic EL display device 50a includes an organic EL element layer 30a provided as an upper layer of the TFT layer 20a as a light-emitting element layer constituting the display region D, and a sealing film 40 provided on the organic EL element layer 30a.

[0051] As shown in FIG. 3, the organic EL element layer 30a includes a plurality of organic EL elements 35 as a plurality of light-emitting elements arranged in a matrix corresponding to a plurality of sub-pixels P.

[0052] 3, the organic EL element 35 includes a plurality of first electrodes 31 provided in order on the planarization film 19, a plurality of organic EL layers 33 provided on the first electrodes 31 in respective sub-pixels P, and a second electrode 34 provided on the organic EL layer 33 in common to the plurality of sub-pixels P. In addition, as shown in FIG. 3, the organic EL element 35 is covered with a sealing film 40.

[0053] 3, the first electrodes 31 are provided in a matrix on the planarization film 19 so as to correspond to a plurality of sub-pixels P. Also, as shown in FIG. 3, each first electrode 31 is electrically connected to the drain electrode 18d (or source electrode 18c) of each second TFT 9b via a contact hole formed in the planarization film 19. Also, the first electrode 31 has a function of injecting holes (positive holes) into the organic EL layer 33. Also, it is more preferable that the first electrode 31 be formed of a material with a large work function in order to improve the efficiency of hole injection into the organic EL layer 33. Here, examples of materials constituting the first electrode 31 include metal materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn). Examples of materials constituting the first electrode 31 include astatine (At) / astatine oxide (AtO ２ The first electrode 31 may be made of an alloy of tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO), or another conductive oxide. The first electrode 31 may be formed by stacking multiple layers made of the above materials. Examples of compound materials with a large work function include indium tin oxide (ITO) and indium zinc oxide (IZO).

[0054] The peripheral edge of the first electrode 31 is covered with an edge cover 32 provided in a lattice pattern and shared by multiple sub-pixels P. Examples of materials that form the edge cover 32 include positive photosensitive resin materials such as polyimide resin, acrylic resin, polysiloxane resin, and novolac resin, as well as polysiloxane-based SOG materials. As shown in FIG. 3 , a portion of the surface of the edge cover 32 protrudes upward in the drawing to form island-shaped pixel photospacers.

[0055] 3, the organic EL layer 33 is disposed on each first electrode 31 and is provided in a matrix so as to correspond to a plurality of sub-pixels P. Here, each organic EL layer 33 includes a hole injection layer 1, a hole transport layer 2, a light-emitting layer 3, an electron transport layer 4, and an electron injection layer 5, which are provided in this order on the first electrode 31, as shown in FIG.

[0056] The hole injection layer 1 is also called an anode buffer layer, and has the function of bringing the energy levels of the first electrode 31 and the organic EL layer 33 closer to each other, thereby improving the efficiency of hole injection from the first electrode 31 to the organic EL layer 33. Examples of materials constituting the hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.

[0057] The hole transport layer 2 has a function of improving the efficiency of transporting holes from the first electrode 31 to the organic EL layer 33. Examples of materials constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, poly-p-phenylenevinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, and zinc selenide.

[0058] The light-emitting layer 3 is a region into which holes and electrons are injected from the first electrode 31 and the second electrode 34, respectively, and where the holes and electrons recombine when a voltage is applied between the first electrode 31 and the second electrode 34. The light-emitting layer 3 is made of a material with high luminous efficiency. Examples of materials that can be used for the light-emitting layer 3 include metal oxinoid compounds (8-hydroxyquinoline metal complexes), naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinylacetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzthiazole derivatives, styryl derivatives, styrylamine derivatives, bisstyrylbenzene derivatives, trisstyrylbenzene derivatives, perylene derivatives, perinone derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, aquidin derivatives, phenoxazone, quinacridone derivatives, rubrene, poly-p-phenylenevinylene, and polysilane.

[0059] The electron transport layer 4 has a function of efficiently transferring electrons to the light-emitting layer 3. Examples of materials constituting the electron transport layer 4 include organic compounds such as oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, diphenoquinone derivatives, fluorenone derivatives, silole derivatives, and metal oxinoid compounds.

[0060] The electron injection layer 5 has a function of bringing the energy levels of the second electrode 34 and the organic EL layer 33 closer to each other and improving the efficiency of electron injection from the second electrode 34 to the organic EL layer 33, and this function can reduce the driving voltage of the organic EL element 35. The electron injection layer 5 is also called a cathode buffer layer. Here, examples of materials constituting the electron injection layer 5 include lithium fluoride (LiF), magnesium fluoride (MgF ２ ), calcium fluoride (CaF ２ ), strontium fluoride (SrF ２ ), barium fluoride (BaF ２ inorganic alkali compounds such as aluminum oxide (Al ２ O ３ ), strontium oxide (SrO), etc.

[0061] 3 , the second electrode 34 is provided to cover each organic EL layer 33 and the edge cover 32. The second electrode 34 has a function of injecting electrons into the organic EL layer 33. The second electrode 34 is preferably made of a material with a small work function to improve the efficiency of electron injection into the organic EL layer 33. Examples of materials that can be used for the second electrode 34 include silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), ruthenium (Ru), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF). The second electrode 34 may be made of, for example, magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), or astatine (At) / astatine oxide (AtO ２ The second electrode 34 may be formed of an alloy such as lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), or lithium fluoride (LiF) / calcium (Ca) / aluminum (Al). The second electrode 34 may be formed of a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). The second electrode 34 may be formed by stacking multiple layers made of the above materials. Examples of materials with a low work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), and lithium fluoride (LiF) / calcium (Ca) / aluminum (Al).

[0062] 3, the sealing film 40 (TFE film) is provided on the organic EL element layer 30a so as to cover each organic EL element 35. As shown in FIG. 3, the sealing film 40 includes a first inorganic sealing film 41 provided so as to cover the second electrode 34, an organic sealing film 42 provided on the first inorganic sealing film 41, and a second inorganic sealing film 43 provided so as to cover the organic sealing film 42, and has the function of protecting the organic EL layer 33 from moisture, oxygen, etc. The first inorganic sealing film 41 and the second inorganic sealing film 43 are made of, for example, silicon oxide (SiO ２ ) and aluminum oxide (Al ２ O ３ ), trisilicon tetranitride (Si ３ N ４ The organic sealing film 42 is made of an inorganic material such as silicon nitride (SiNx (x is a positive number)) or silicon carbonitride (SiCN). The organic sealing film 42 is made of an organic material such as acrylic resin, polyurea resin, parylene resin, polyimide resin, or polyamide resin.

[0063] The organic EL display device 50a described above is configured such that, in each subpixel P, a gate signal is input to the first TFT 9a via the gate line 14 to turn the first TFT 9a on, a data signal is written to the gate electrode 14b and capacitor 9c of the second TFT 9b via the source line 18f, and a current from the power supply line 18g corresponding to the gate voltage of the second TFT 9b is supplied to the organic EL layer 33, causing the light-emitting layer 3 of the organic EL layer 33 to emit light, thereby displaying an image. In the organic EL display device 50a, even if the first TFT 9a is turned off, the gate voltage of the second TFT 9b is held by the capacitor 9c, so that light emission by the light-emitting layer 3 is maintained until a gate signal for the next frame is input.

[0064] Next, a method for manufacturing the organic EL display device 50a of this embodiment will be described. The method for manufacturing the organic EL display device 50a of this embodiment includes a TFT layer forming step, an organic EL element layer forming step, and a sealing film forming step.

[0065] <TFT layer formation process> For example, a base coat film 11, a first TFT 9a, a second TFT 9b, a capacitor 9c, a planarization film 19, etc. are formed on the surface of a resin substrate 10 formed on a glass substrate using a well-known method, thereby forming a TFT layer 20a.

[0066] Specifically, on the substrate surface on which the second wirings 14d and the like are formed as the lower metal layer LW, a first interlayer insulating film 15 and a second interlayer insulating film 17 are formed as the interlayer insulating film IL so as to cover the second wirings 14d and the like. Subsequently, contact holes Ha and Hb are formed in the laminated film of the first interlayer insulating film 15 and the second interlayer insulating film 17 at portions where the second wirings 14d and the first wirings 18h and 18i to be formed later overlap in a planar view. Here, in the manufacturing method of the organic EL display device 50a, after forming the upper metal layer UW on the substrate surface on which the interlayer insulating film IL is formed, wiring dummy patterns 18ja are simultaneously formed in the wiring portion W when the upper metal layer UW is patterned to form the first wirings 18h and 18i. At this time, the number, shape, pitch, spacing, size (area), etc. of the wiring dummy patterns 18ja to be arranged in the wiring portion W are appropriately determined so that the total area (pattern density) of the plurality of wiring dummy patterns 18ja is, for example, 20% or more when the area of ​​the upper metal layer UW provided in the wiring portion W is 100%. Thereafter, a planarization film 19 is formed as the upper metal layer UW so as to cover the first wirings 18h, 18i, the wiring dummy patterns 18ja, etc.

[0067] <Organic EL element layer forming process> In the display region D, a first electrode 31, an edge cover 32, an organic EL layer 33 (hole injection layer 1, hole transport layer 2, light-emitting layer 3, electron transport layer 4, electron injection layer 5), and a second electrode 34 are formed by a well-known method on the planarization film 19 of the TFT layer 20a formed in the TFT layer forming process, thereby forming an organic EL element 35 and forming the organic EL element layer 30a.

[0068] <Sealing Film Forming Process> First, on the substrate surface on which the organic EL element layer 30a formed in the organic EL element layer forming process is formed, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD (chemical vapor deposition) using a CMM as a deposition mask so as to cover each organic EL element 35, thereby forming a first inorganic sealing film 41. Next, an organic resin material such as an acrylic resin is formed on the first inorganic sealing film 41 by, for example, an inkjet method, thereby forming an organic sealing film 42. Thereafter, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD using the CMM as a deposition mask so as to cover the organic sealing film 42, thereby forming a second inorganic sealing film 43. Through the above processes, a sealing film 40 is formed in which the first inorganic sealing film 41, the organic sealing film 42, and the second inorganic sealing film 43 are stacked in order.

[0069] Finally, a protective sheet (not shown) is attached to the surface of the substrate, and then laser light is irradiated from the glass substrate side of the resin substrate 10 to peel the glass substrate from the underside of the resin substrate 10, and a protective sheet (not shown) is attached to the underside of the resin substrate 10 from which the glass substrate has been peeled. In this manner, the organic EL display device 50a can be manufactured.

[0070] In the following examples, a substrate was fabricated on which a plurality of wiring dummy patterns 18ja with different pattern densities were arranged, and the preferred pattern density of the wiring dummy patterns 18ja was examined based on the presence or absence of film residue. Note that the present invention is not limited to the following examples, and the following examples can be modified or changed based on the spirit of the present invention, and such modifications and changes are not excluded from the scope of the present invention.

[0071] Example 1: Following the TFT layer formation process described above, an upper metal layer UW was formed on the surface of a substrate on which a lower metal layer LW (second wiring 14d, etc.) and an interlayer insulating film IL (first interlayer insulating film 15 and second interlayer insulating film 17) had been formed. Thereafter, when the upper metal layer UW was patterned to form first wirings 18h and 18i, multiple wiring dummy patterns 18ja were simultaneously formed in the wiring portion W. In this example, the total area (pattern density) of the multiple wiring dummy patterns 18ja was set to 10% when the area of ​​the upper metal layer UW provided in the wiring portion W was taken as 100%. As a result, when the wiring portion W was visually inspected for the presence or absence of film residues of the upper metal layer UW, film residues were confirmed (film residues present).

[0072] (Example 2) A plurality of wiring dummy patterns 18ja were formed in the same manner as in Example 1, except that the pattern density was changed to 20%. Specifically, the shape and size (area) of each wiring dummy pattern 18ja were the same as in Example 1, the spacing between adjacent patterns in the first direction Y and the second direction Y was narrowed, and the number of patterns was increased. As a result, when the presence or absence of film residue of the upper metal layer UW in the wiring portion W was visually observed, no film residue was confirmed (no film residue).

[0073] (Summary) From the above results, it was confirmed that the smaller the pattern density of the wiring dummy patterns 18ja, the more film residue of the upper metal layer UW occurs. Furthermore, from the viewpoint of reducing the above-mentioned wiring defects in conventional organic EL display devices, it was confirmed that when the area of ​​the upper metal layer UW provided in the wiring portion W is taken as 100%, the total area (pattern density) of the multiple wiring dummy patterns 18ja is preferably 20% or more.

[0074] <Effects> As described above, the organic EL display device 50a of this embodiment can provide the following effects: (1) In the organic EL display device 50a, in the TFT layer 20a having a laminated structure in which a lower metal layer LW (second wiring 14d, etc.), an interlayer insulating film IL (first interlayer insulating film 15 and second interlayer insulating film 17), and an upper metal layer UW (first wirings 18h, 18i) are laminated in this order, a wiring portion W provided between the display region D and the terminal portion T is provided with a plurality of wiring dummy patterns 18ja formed in the same layer and made of the same material as the upper metal layer UW. In conventional organic EL display devices, the wiring portion W is a region where the pattern density of the upper metal layer UW is extremely low. However, in the organic EL display device 50a, the arrangement of the wiring dummy patterns 18ja increases the pattern density of the upper metal layer UW in the wiring portion W (for example, when the area of ​​the upper metal layer UW provided in the wiring portion W is taken as 100%, the total area (pattern density) of the multiple wiring dummy patterns 18ja is set to 20% or more). This prevents a decrease in the etching rate of the upper metal layer UW in the organic EL display device 50a, thereby reducing film residue after etching of the upper metal layer UW due to a decrease in pattern density. (2) In the organic EL display device 50a, even if there is a crack in the interlayer insulating film IL, the wiring dummy patterns 18ja prevent etching of the underlying lower metal layer LW during etching of the upper metal layer UW, thereby preventing disconnections in the lower metal layer LW. (3) In the organic EL display device 50a, due to the above (1) and (2), leakage between wirings caused by film residue of the upper metal layer UW is suppressed, and the reliability of the display device can be improved.

[0075] Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIGS. 8 and 9. FIG. 8 is an enlarged plan view showing the wiring pattern of the wiring portion W in the frame region F of an organic EL display device 50b of this embodiment, and corresponds to FIG. 5. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 8, showing the wiring pattern of the wiring portion W in the frame region F of the organic EL display device 50b. Note that FIG. 8 omits the upper layer of the upper metal layer UW. The overall configuration of the organic EL display device 50b is the same as that of the first embodiment described above, except for the configuration of the wiring portion W, and therefore a detailed description thereof will be omitted here. Components similar to those of the first embodiment will be assigned the same reference numerals and their description will be omitted.

[0076] As shown in Figures 8 and 9, in the organic EL display device 50b of this embodiment, in the wiring portion W, the planar shape and arrangement (pitch, spacing) of the wiring dummy patterns 18jb that constitute the TFT layer 20b are different from those of the wiring dummy patterns 18ja of the organic EL display device 50a of the first embodiment.

[0077] 8, the wiring dummy patterns 18jb extend in the direction in which the second wirings 14d extend (second direction Y). That is, the planar shape of each wiring dummy pattern 18jb is a strip shape extending in the second direction Y.

[0078] 8 and 9, the strip-shaped wiring dummy patterns 18jb overlap the second wirings 14d in plan view. Here, the line width W18j of the strip-shaped wiring dummy patterns 18jb is narrower than the line width W14d of the second wirings 14d (W18j<W14d). As a result, in the first direction X, the pitch P18h between adjacent first wirings 18h is equal to the pitch P18j between adjacent wiring dummy patterns 18jb (P18h≈P18j). Similarly, in the first direction X, the pitch P18i between adjacent first wirings 18i is equal to the pitch P18j (P18i≈P18j).

[0079] In the TFT layer formation process of the organic EL display device 50b described above, the pitch, spacing, size (area), number, etc. of the strip-shaped wiring dummy patterns 18jb to be arranged in the wiring portion W can be appropriately determined in accordance with the wiring pattern of the second wiring 14d so that, for example, when the area of ​​the upper metal layer UW provided in the wiring portion W is 100%, the total area (pattern density) of the multiple wiring dummy patterns 18ja is 20% or more.

[0080] <Effects> The organic EL display device 50b described above can achieve the same effects as the organic EL display device 50a. Specifically, in the organic EL display device 50b, the wiring dummy patterns 18jb are arranged in a strip shape extending along the direction of the second wiring 14d. The strip-shaped wiring dummy patterns 18jb are arranged so as to overlap the second wiring 14d in a planar view. By making the line width W18j of the wiring dummy patterns 18jb narrower than the line width W14d of the second wiring 14d (W18j<W14d), even if film residue of the upper metal layer UW occurs between adjacent wiring dummy patterns 18jb in the first direction X, the step at the edge of the wiring dummy pattern 18jb can separate the film residue. As a result, in the organic EL display device 50b, inter-wiring leakage caused by film residue of the upper metal layer UW is suppressed, thereby improving the reliability of the display device.

[0081] Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIG. 10 . FIG. 10 is an enlarged plan view showing the electrode pattern of the organic EL element layer 30b in the display region D of an organic EL display device 50c of this embodiment. Note that the upper layer of the first electrode 31 is omitted in FIG. 10 . The overall configuration of the organic EL display device 50c is the same as that of the first and second embodiments described above, except for the configuration of the display region D (organic EL element layer 30b), and therefore a detailed description thereof will be omitted here. Furthermore, components similar to those of the first and second embodiments will be assigned the same reference numerals and their description will be omitted.

[0082] The organic EL display device 50c of this embodiment includes an electrode dummy pattern 31a in addition to the wiring dummy pattern 18ja of the organic EL display device 50a of the first embodiment or the wiring dummy pattern 18jb of the organic EL display device 50b of the second embodiment. In other words, the electrode dummy pattern 31a may be applied to both the organic EL display devices 50a and 50b.

[0083] As shown in Figure 10, in the organic EL display device 50c, in the display region D, the electrode pattern around the first electrode 31 that constitutes the organic EL element layer 30b is different from the electrode pattern around the first electrode 31 that constitutes the organic EL element layer 30a of the organic EL display devices 50a and 50b.

[0084] In the organic EL display device 50c, a plurality of electrode dummy patterns 31a formed in the same layer and made of the same material as the first electrodes 31 (the electrode layer constituting them) are provided in the display region D along the periphery (outer periphery) of the plurality of first electrodes 31 constituting the organic EL elements 35.

[0085] A plurality of electrode dummy patterns 31a are provided in a floating island structure, and adjacent patterns are not electrically connected to each other. Furthermore, the electrode dummy patterns 31a are not electrically connected to the first electrode 31, the organic EL layer 33 and the second electrode 34 that are located above it. In other words, the electrode dummy patterns 31a are not electrically connected to the organic EL element 35.

[0086] The plurality of electrode dummy patterns 31a are provided so as to surround the outer periphery of an assembly (block B31 shown by dotted lines in FIG. 10) of the plurality of first electrodes 31. In other words, the block B31 of the plurality of first electrodes 31 (their electrode patterns) is disposed inside the assembly (block B31a shown by dotted lines in FIG. 10) of the plurality of electrode dummy patterns 31a.

[0087] The planar shape of each electrode dummy pattern 31a is not particularly limited as long as it is island-shaped, and may be, for example, rectangular, circular, elliptical, or strip-like extending in one direction. For example, in the case of a rectangular shape, the size (area) of each electrode dummy pattern 31a is approximately 30 μm × 50 μm. Furthermore, the planar shape of the block B31a of the multiple electrode dummy patterns 31a may be determined appropriately depending on the shape of the block B31 of the multiple first electrodes 31, and may be, for example, a rectangular frame shape, a U-shape, a strip-like shape extending in one direction (the first direction X or the second direction Y), or the like.

[0088] The distance (interval) between adjacent electrode dummy patterns 31 a in one direction may be the same as or different from the distance between adjacent electrode dummy patterns 31 a in a direction perpendicular to (intersecting) the one direction. For example, the distance between adjacent electrode dummy patterns 31 a is about 20 μm.

[0089] In the electrode pattern of the organic EL element layer constituting the conventional organic EL display device, the pattern density varies locally at the boundaries of blocks of multiple first electrodes, which makes it easy for the etching rate to vary around the periphery of the blocks. Therefore, in the conventional organic EL display device, when the electrode layer constituting the first electrodes is wet-etched, the variation in the etching rate easily causes variations in the electrode width of the first electrodes.

[0090] In contrast, in the organic EL display device 50c, a plurality of electrode dummy patterns 31a formed in the same layer and made of the same material as the first electrodes 31 are arranged along the periphery of a block B31 of a plurality of first electrodes 31, where the pattern density may vary locally, so as to surround the block B31. By arranging the plurality of first electrode 31 patterns (block B31) inside the block B31a of the plurality of electrode dummy patterns 31a, the variation in pattern density is reduced, and the variation in etching rate is suppressed. As a result, the organic EL display device 50c suppresses the occurrence of variations in the electrode width of the first electrodes 31.

[0091] A standard (guideline) for arranging the electrode dummy patterns 31a is, for example, that the pattern density be less than 10% when the area of ​​the electrode layer constituting the first electrode 31 provided in the display region D is taken as 100%. From the viewpoint of reducing the occurrence of the above-mentioned variation, it is preferable that the total area (pattern density) of the plurality of electrode dummy patterns 31a be 10% or more when the area of ​​the electrode layer constituting the first electrode 31 provided in the display region D is taken as 100%. In accordance with the above, the number of electrode dummy patterns 31a to be arranged in the display region D, their respective shapes, pitches, intervals, size (areas), etc. may be appropriately determined. Note that silver (Ag) is preferred as the material constituting the first electrode 31 and the electrode dummy patterns 31a.

[0092] The organic EL display device 50c can be obtained by modifying the organic EL element layer formation process of the organic EL display device 50a described above as follows. For example, after forming an electrode layer constituting the first electrodes 31 on the planarization film 19 of the TFT layer 20a in the display region D (the substrate surface on which it is formed), the electrode layer is patterned to form the plurality of first electrodes 31, and then a plurality of electrode dummy patterns 31a are simultaneously formed around the peripheries of the plurality of first electrodes 31 (their blocks B31). At this time, the number, shape, pitch, spacing, size (area), and other factors of the electrode dummy patterns 31a to be arranged in the display region D are appropriately determined so that the total area (pattern density) of the plurality of electrode dummy patterns 31a is, for example, 10% or more, assuming that the area of ​​the electrode layer constituting the first electrodes 31 provided in the display region D is 100%. This allows the formation of an organic EL element layer 30b on which a plurality of electrode dummy patterns 31a are formed. A plurality of electrode dummy patterns 31a may be formed on the TFT layer 20b (the planarizing film 19 thereof) that constitutes the organic EL display device 50b.

[0093] <Effects> The organic EL display device 50c described above can achieve the following effect in addition to the effects of the organic EL display device 50a or the organic EL display device 50b described above. Specifically, in the organic EL display device 50c, in addition to the wiring dummy patterns 18ja or 18jb provided in the wiring portion W in the frame region F, a plurality of electrode dummy patterns 31a formed in the same layer and made of the same material as the first electrodes 31 are provided in the display region D (the organic EL element layer 30b constituting the display region D). In conventional display devices, the outer periphery of the block B31 of the plurality of first electrodes 31 is a region where the pattern density of the first electrodes 31 (the electrode layer constituting the first electrodes 31) is extremely low. However, in the organic EL display device 50c, the arrangement of the electrode dummy patterns 31a increases the pattern density of the electrode layer in this region (for example, when the area of ​​the electrode layer constituting the first electrodes 31 provided in the display region D is taken as 100%, the total area (pattern density) of the plurality of electrode dummy patterns 31a is 10% or more). As a result, in the organic EL display device 50c, the change in the etching rate of the electrode layer that constitutes the first electrode 31 is reduced, thereby reducing the variation in the electrode width of the first electrode 31, and as a result, the reliability of the display device can be improved.

[0094] Although a plurality of wiring dummy patterns are provided in the first and second embodiments, the present invention is not limited to this, and a configuration in which at least one wiring dummy pattern is provided is also possible. However, from the viewpoint of suppressing the occurrence of abnormal discharge and variations in etching rate, a configuration in which a plurality of wiring dummy patterns is provided is preferable.

[0095] In the first and second embodiments, the plurality of wiring dummy patterns are not electrically connected to each other adjacent patterns, but this is not limiting and the adjacent patterns may be electrically connected to each other. However, from the viewpoint of suppressing the occurrence of abnormal discharge and variations in etching rate, it is preferable that the plurality of wiring dummy patterns are not electrically connected to each other adjacent patterns.

[0096] In the second embodiment described above, an example was given of a strip-shaped wiring dummy pattern, each of whose planar shape extends along the direction in which the second wiring (lower metal layer) extends. However, this is not limited to this, and a plurality of island-shaped wiring dummy patterns may be arranged along the direction in which the second wiring extends, and the planar shape of the aggregate (block) in which the patterns are grouped may also be strip-shaped.

[0097] In the third embodiment, a plurality of electrode dummy patterns are provided, but the present invention is not limited to this, and a configuration in which at least one electrode dummy pattern is provided is also possible. However, from the viewpoint of suppressing the occurrence of abnormal discharge and variations in etching rate, a configuration in which a plurality of electrode dummy patterns are provided is preferable.

[0098] In each of the above embodiments, the inorganic laminated film is composed of four layers, namely, a gate insulating film, a first interlayer insulating film, and a second interlayer insulating film, which are laminated in this order on a base coat film. However, it may be composed of a single layer of the base coat film, or may be composed of two layers, namely, a base coat film and a gate insulating film.

[0099] In each of the above embodiments, an organic EL layer having a five-layer stacked structure of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer has been exemplified. However, the organic EL layer may have a three-layer stacked structure of, for example, a hole injection layer / hole transport layer, a light-emitting layer, and an electron transport layer / electron injection layer.

[0100] In addition, in each of the above embodiments, an organic EL display device in which the first electrode is an anode and the second electrode is a cathode is exemplified. However, the present invention can also be applied to an organic EL display device in which the stacked structure of the organic EL layer is reversed, and the first electrode is a cathode and the second electrode is an anode.

[0101] In each of the above embodiments, an organic EL display device is exemplified in which the electrode of the TFT connected to the first electrode is used as the drain electrode, but the present invention can also be applied to an organic EL display device in which the electrode of the TFT connected to the first electrode is called the source electrode.

[0102] In the above embodiments, an organic EL display device is used as the display device, but the present invention can also be applied to display devices such as an active matrix driving liquid crystal display device.

[0103] In the above embodiments, an organic EL display device has been described as an example of a display device, but the present invention is not limited to organic EL display devices and can be applied to any flexible display device. For example, the present invention can be applied to a flexible display device including a quantum-dot light emitting diode (QLED), which is a light emitting element using a quantum dot-containing layer.

[0104] As described above, the present invention is useful for flexible display devices.

[0105] D display area F frame area Ha, Hb contact holes IL interlayer insulating film LW lower metal layer T terminal section UW upper metal layer W wiring section 10 resin substrate (base substrate) 14d second wiring 15 first interlayer insulating film 17 second interlayer insulating film 18h, 18i first wiring 18ja, 18jb wiring dummy pattern 20a, 20b TFT (thin film transistor) layer 30a, 30b organic EL element layer (light emitting element layer) 31 first electrode 31a electrode dummy pattern 35 organic EL element (light emitting element) 40 sealing film 50a, 50b, 50c organic EL display device D18hj distance D18ij between first wiring 18h and wiring dummy pattern 18ja in the direction in which first wiring h extends P18h: The distance between the first wiring 18i and the wiring dummy pattern 18ja in the direction in which the first wiring i extends. P18h: The pitch between adjacent first wirings 18h in the direction perpendicular to the direction in which the first wirings 18h extend. P18i: The pitch between adjacent first wirings 18i in the direction perpendicular to the direction in which the first wirings 18i extend. P18j: The pitch between adjacent wiring dummy patterns 18ja in the direction perpendicular to the direction in which the first wirings 18h, 18i extend. W14d: The line width of the second wiring 14d. W18j: The line width of the wiring dummy pattern 18jb.

Claims

1. A display device comprising: a base substrate; a thin-film transistor layer provided on the base substrate and including a lower metal layer, an interlayer insulating film provided to cover the lower metal layer, and an upper metal layer provided on the interlayer insulating film; a light-emitting element layer provided on the thin-film transistor layer and constituting a display area; a frame area provided around the display area; a terminal section provided at one end of the frame area; a wiring section provided between the display area and the terminal section; and a plurality of first wirings provided in the display area and the terminal section and formed in the same layer and made of the same material as the upper metal layer, wherein the wiring section is provided with at least one wiring dummy pattern formed in the same layer and made of the same material as the upper metal layer.

2. A display device according to claim 1, characterized in that the distance between the first wiring and the wiring dummy pattern in the direction in which the first wiring extends is greater than the pitch between adjacent first wirings in a direction perpendicular to the direction in which the first wiring extends.

3. A display device according to claim 1 or 2, wherein the wiring section is provided with a plurality of second wirings formed in the same layer as the lower metal layer using the same material.

4. A display device according to claim 3, wherein a plurality of contact holes are formed in the interlayer insulating film, and the plurality of first wirings are electrically connected to the plurality of second wirings via the plurality of contact holes.

5. A display device according to claim 3 or 4, characterized in that a plurality of the wiring dummy patterns are provided, and extend in the direction in which the second wiring extends.

6. A display device according to claim 5, wherein the line width of the wiring dummy pattern is narrower than the line width of the second wiring.

7. A display device according to claim 5 or 6, wherein the wiring dummy pattern overlaps with the second wiring in a plan view.

8. A display device according to any one of claims 1 to 6, characterized in that a plurality of the wiring dummy patterns are provided, and the pitch between adjacent first wirings in a direction perpendicular to the direction in which the first wirings extend is different from the pitch between adjacent wiring dummy patterns.

9. A display device according to any one of claims 1 to 8, wherein the wiring dummy pattern is not electrically connected to the first wiring.

10. A display device according to any one of claims 1 to 9, characterized in that the wiring dummy patterns are provided in a floating island structure in multiple locations, and adjacent patterns are not electrically connected to each other.

11. A display device according to any one of claims 1 to 10, characterized in that when the area of ​​the upper metal layer provided in the wiring portion is taken as 100%, the total area of ​​the wiring dummy patterns is 20% or more.

12. A display device according to any one of claims 1 to 11, wherein the plurality of light-emitting elements constituting the light-emitting element layer are provided with a plurality of first electrodes, and the display area is provided with at least one dummy electrode pattern formed in the same layer and made of the same material as the first electrodes.

13. A display device according to claim 12, wherein the electrode dummy pattern is provided along the periphery of the plurality of first electrodes.

14. A display device according to claim 12 or 13, wherein the electrode dummy pattern is not electrically connected to the first electrode.

15. A display device according to any one of claims 12 to 14, characterized in that the electrode dummy patterns are provided in a plurality in a floating island structure, and adjacent patterns are not electrically connected to each other.

16. A display device according to any one of claims 12 to 15, characterized in that when the area of ​​the electrode layer constituting the first electrode provided in the display region is taken as 100%, the total area of ​​the electrode dummy patterns is 10% or more.

17. A display device according to any one of claims 1 to 16, characterized in that it comprises a sealing film provided so as to cover the light-emitting element layer, and in which a first inorganic sealing film, an organic sealing film and a second inorganic sealing film are laminated in this order.

18. A display device according to any one of claims 1 to 17, wherein the light emitting element layer is an organic electroluminescence element layer.

19. A method for manufacturing a display device comprising: a base substrate; a thin-film transistor layer provided on the base substrate and including a lower metal layer, an interlayer insulating film provided so as to cover the lower metal layer, and an upper metal layer provided on the interlayer insulating film; a light-emitting element layer provided on the thin-film transistor layer and constituting a display area; a frame area provided around the display area; a terminal section provided at one end of the frame area; a wiring section provided between the display area and the terminal section; and a plurality of first wirings provided in the display area and the terminal section and formed in the same layer and of the same material as the upper metal layer, wherein in a thin-film transistor layer formation step of forming the thin-film transistor layer, after forming the upper metal layer on the surface of the substrate on which the interlayer insulating film is formed, at least one wiring dummy pattern is formed in the wiring section when the upper metal layer is patterned to form the plurality of first wirings.

20. A method for manufacturing a display device according to claim 19, wherein the plurality of light-emitting elements constituting the light-emitting element layer are provided with a plurality of first electrodes, and in the light-emitting element layer forming step for forming the light-emitting element layer, after depositing an electrode layer constituting the first electrodes on the surface of the substrate on which the thin-film transistor layer is formed, when patterning the electrode layer to form the plurality of first electrodes, at least one electrode dummy pattern is formed in the display area.

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