Semiconductor device

Abstract

Provided is a semiconductor device comprising a transistor part and a diode part, the semiconductor device comprising a drift region of a first conductivity type, a plurality of trench parts, a base region of a second conductivity type, an emitter region of the first conductivity type and of which the doping concentration is higher than that of the drift region, and a contact region of the second conductivity type and of which the doping concentration is higher than that of the base region, wherein: the plurality of trench parts have a gate trench part; the transistor part has a first transistor region which includes an emitter region and a gate trench part and a second transistor region which includes an emitter region and a gate trench part and which is provided between the first transistor region and the diode part; a first mesa part of the first transistor region has a first region of the first conductivity type; and a second mesa part of the second transistor region has a second region of the first conductivity type and of which the doping concentration is higher than that of the first region.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Patent Document 1 states, "An optional n-doped carrier confinement region may be arranged between the p-doped body region 130 and the n-doped drift region 115, e.g., in a mesa region between neighboring second trench structures 128 (not illustrated in FIG. 4)." (

[0072] ) and "The drift region 115 arranged between the emitter efficiency adjustment region 114 and the second main surface 111 of the semiconductor substrate 102 may have a minority carrier lifetime that is larger than 100 μs." (machine translation: the drift region 115 disposed between the emitter efficiency adjustment region 114 and the second main surface 111 of the semiconductor substrate 102 may have a minority carrier lifetime longer than 100 μs) (

[0074] ). Patent Document 2 states, "The semiconductor device 200 has an accumulation region 16 in both the transistor section 70 and the diode section 80. The dopants (donors in this example) in the accumulation region 16 are accumulated at a higher concentration than in the drift region 18." (

[0083] ). [Prior art documents] [Patent documents] [Patent document 1] US2022 / 0384624 [Patent document 2] JP2018-174295 General disclosure

[0003] A first aspect of the present invention provides a semiconductor device including a transistor portion and a diode portion, the semiconductor device including: a drift region of a first conductivity type provided in a semiconductor substrate; a plurality of trenches extending in a predetermined trench extension direction on the front surface side of the semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of the first conductivity type provided on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; and a contact region of the second conductivity type provided above the drift region and having a doping concentration higher than that of the base region, the plurality of trenches having gate trenches, and the transistor portion including the emitter region and a front contact region of the second conductivity type. The semiconductor device includes a first transistor region including the gate trench portion, and a second transistor region including the emitter region and the gate trench portion and provided between the first transistor region and the diode portion, wherein the first mesa portion of the first transistor region has a first region of a first conductivity type provided between the depth position of the lower end of the base region and the depth position of the lower end of the trench portion, and the second mesa portion of the second transistor region has a second region of the first conductivity type having a doping concentration higher than that of the first region and provided between the depth position of the lower end of the base region and the depth position of the lower end of the trench portion.

[0004] Any of the above semiconductor devices may further include an accumulation region of the first conductivity type provided above the drift region and having a doping concentration higher than that of the drift region. In any of the above semiconductor devices, the accumulation region may be provided from the second mesa portion of the second transistor region to the third mesa portion of the diode region.

[0005] In any of the above semiconductor devices, the transistor section may have a boundary region that is closer to the diode section than the second transistor region. Any of the above semiconductor devices may include an accumulation region of the first conductivity type that is provided above the drift region and has a doping concentration higher than that of the drift region. In any of the above semiconductor devices, the accumulation region may be provided from the second mesa section of the second transistor region to a fourth mesa section of the boundary region.

[0006] In any of the above semiconductor devices, the first region may be the drift region.

[0007] In any of the above semiconductor devices, the peak doping concentration of the second region may be greater than the peak doping concentration of the first region.

[0008] In any of the above semiconductor devices, the number of peaks of the doping concentration in the second region may be greater than the number of peaks of the doping concentration in the first region.

[0009] Any of the above semiconductor devices may include an accumulation region of a first conductivity type provided above the drift region and having a doping concentration higher than that of the drift region. In any of the above semiconductor devices, the second region and the first region may include the accumulation region of the same doping concentration. In any of the above semiconductor devices, the width of the accumulation region in the second region in the depth direction may be larger than the width of the accumulation region in the first region in the depth direction.

[0010] In any of the above semiconductor devices, an integrated concentration of the dopant of the first conductivity type in the second region may be greater than an integrated concentration of the dopant of the first conductivity type in the first region.

[0011] In any of the above semiconductor devices, the diode section may have an anode region of a second conductivity type provided above the drift region. In any of the above semiconductor devices, the third mesa section of the diode section may have a third region of a first conductivity type provided between a depth position of a lower end of the anode region and a depth position of a lower end of the trench section. In any of the above semiconductor devices, the third region may have the first conductivity type and have a doping concentration higher than that of the drift region.

[0012] In any of the above semiconductor devices, the doping concentration of the anode region may be equal to or higher than the doping concentration of the base region.

[0013] In any of the above semiconductor devices, the doping concentration of the anode region may be the same as the doping concentration of the base region.

[0014] Any of the above semiconductor devices may include a lifetime control region provided on the front surface side of the semiconductor substrate relative to the center of the semiconductor substrate in a depth direction of the semiconductor substrate.

[0015] In any of the above semiconductor devices, the lifetime control region may extend from the diode portion to the second transistor region.

[0016] In any of the above semiconductor devices, the lifetime control region may be provided below the accumulation region.

[0017] In any of the above semiconductor devices, the second transistor region may be an adjustment region in which the lifetime control region is provided, and the first transistor region may be a non-adjustment region in which the lifetime control region is not provided.

[0018] In any of the above semiconductor devices, the semiconductor substrate may not include a lifetime control region.

[0019] In any of the above semiconductor devices, the transistor section may have a boundary region that is provided closer to the diode section than the second transistor region.

[0020] In any of the above semiconductor devices, the accumulation region may also be provided in the boundary region.

[0021] In any of the above semiconductor devices, the front surface of the semiconductor substrate in the boundary region may be the contact region.

[0022] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0023] FIG. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. It is an enlarged view of region D in FIG. 1. It is a diagram showing an example of an e-e cross section in FIG. 2. It is a diagram showing an example of an f-f cross section in FIG. 2. It is a diagram showing an example of a doping concentration distribution along the r-r' and s-s' lines in FIG. 3. It is an enlarged view of the periphery of a trench contact portion 58 in a boundary region 200. It is a diagram showing an example of the arrangement of a first transistor region 201 and a second transistor region 202 in a top view. It is a diagram showing another example of the configuration of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. It is a diagram showing an example of a doping concentration distribution along the r-r' and s-s' lines in FIG. 8. It is a diagram showing another example of the configuration of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. It is a diagram showing an example of a doping concentration distribution along the r-r' and s-s' lines in FIG. 10. It is a diagram showing another example of the configuration of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. 10 is a diagram showing an example of doping concentration distribution along the rr' line and the ss' line in FIG. 10. FIG. 11 is a diagram showing another example of the configuration of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. FIG. 12 is a diagram showing an example of doping concentration distribution along the rr' line and the ss' line in FIG. 14. FIG. 13 is a diagram showing another example of the ee cross section in FIG. 2. FIG. 14 is a diagram showing another example of the ee cross section in FIG. 2. FIG. 15 is another example of an enlarged view of region D in FIG. 1. FIG. 16 is another example of an enlarged view of region D in FIG. 1. FIG. 17 is a diagram showing an example of the ee cross section in FIG. 19.

[0024] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0025] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0026] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0027] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0028] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0029] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0030] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity or a P-type conductivity.

[0031] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is NＤ , acceptor concentration is N Ａ Then, the net doping concentration at any position is N Ｄ -N Ａ In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0032] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect in a semiconductor, in which a vacancy (V), oxygen (O), and hydrogen (H) are bonded, functions as a donor that supplies electrons. A hydrogen donor may be a donor in which at least a vacancy (V) and hydrogen (H) are bonded. Alternatively, an interstitial Si—H in a silicon semiconductor, in which interstitial silicon (Si-i) and hydrogen are bonded, also functions as a donor that supplies electrons. In this specification, a VOH defect or an interstitial Si—H may be referred to as a hydrogen donor.

[0033] In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. The bulk donors are donors due to dopants contained substantially uniformly in the ingot that is the base of the semiconductor substrate when the ingot is manufactured. In this example, the bulk donors are elements other than hydrogen. The dopants of the bulk donors include, but are not limited to, phosphorus, antimony, arsenic, selenium, or sulfur. In this example, the bulk donors are phosphorus. The bulk donors are also contained in the P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or may be a chip obtained by dividing the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), and the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration contained in the substrate manufactured by the MCZ method is 1×10 １７ ~7 x 10 １７ / cm ３ The oxygen concentration in the substrate manufactured by the FZ method is 1×10 １５ ~5 x 10 １６ / cm ３The higher the oxygen concentration, the more likely it is that hydrogen donors are generated. The bulk donor concentration may be the chemical concentration of bulk donors distributed throughout the semiconductor substrate, or may be a value between 90% and 100% of the chemical concentration. Alternatively, a non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In this case, the bulk donor concentration (D0) of the non-doped substrate is, for example, 1×10 １０ / cm ３ That's it, 5 x 10 １２ / cm ３ The bulk donor concentration (D0) of the non-doped substrate is preferably 1×10 １１ / cm ３ The bulk donor concentration (D0) of the non-doped substrate is preferably 5×10 １２ / cm ３ The concentrations in the present invention may be values ​​at room temperature, for example, values ​​at 300 K (Kelvin) (approximately 26.9° C.).

[0034] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Furthermore, when P++ type or N++ type is described in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0035] In this specification, chemical concentration refers to the atomic density of an impurity measured regardless of its state of electrical activation. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may also be used as the net doping concentration. The carrier concentration measured by CV or SR may be used as a value in a thermal equilibrium state. In addition, since the donor concentration in an N-type region is sufficiently greater than the acceptor concentration, the carrier concentration in that region may also be used as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be used as the acceptor concentration. In this specification, the doping concentration in an N-type region may also be referred to as the donor concentration, and the doping concentration in a P-type region may also be referred to as the acceptor concentration.

[0036] When the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor, or net doping in that region. In cases where the concentration of the donor, acceptor, or net doping is almost uniform, the average value of the concentration of the donor, acceptor, or net doping in that region may be taken as the concentration of the donor, acceptor, or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. ３ , or / cm ３ This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atoms notation may be omitted.

[0037] The carrier concentration measured by the SR method may be lower than the concentration of donors or acceptors. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when carriers are scattered due to disorder in the crystal structure caused by lattice defects or the like.

[0038] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen.

[0039] Fig. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0040] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has end edges 162 in a top view. In this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 in this example has two pairs of end edges 162 that face each other in a top view. In FIG. 1 , the X-axis and Y-axis are parallel to either of the end edges 162. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0041] An active portion 160 is provided in the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is omitted from FIG. 1 . The active portion 160 may refer to a region overlapped by the emitter electrode in a top view. The active portion 160 may also include a region sandwiched between the active portions 160 in a top view.

[0042] The active section 160 includes a transistor section 70 including a transistor element such as an insulated gate bipolar transistor (IGBT), and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of FIG. 1 , the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined first direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse conducting IGBT (RC-IGBT). A boundary region may be arranged between the transistor section 70 and the diode section 80 in the X-axis direction, but this is omitted in FIG. 1 .

[0043] In FIG. 1 , the region where the transistor section 70 is disposed is marked with the symbol "I," and the region where the diode section 80 is disposed is marked with the symbol "F." In this specification, a direction different from the first direction in a top view may be referred to as the second direction (the Y-axis direction in FIG. 1 ). The second direction may be perpendicular to the first direction. The transistor section 70 and the diode section 80 may each have a longitudinal direction in the second direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The second direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section and the longitudinal direction of a mesa section, which will be described later.

[0044] The diode section 80 has an N+ type cathode region in a region that contacts the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region of the lower surface of the semiconductor substrate 10 other than the cathode region. In this specification, an extension region 81 that extends the diode section 80 in the Y-axis direction to the gate wiring described below may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0045] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an edge 162. The vicinity of the edge 162 refers to the region between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0046] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is hatched with diagonal lines.

[0047] The gate wiring in this example has a peripheral gate wiring 130 and an active-side gate wiring 131. The peripheral gate wiring 130 is disposed between the active portion 160 and an edge 162 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160. In addition, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than a base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The region surrounded by the well region in a top view may be the active portion 160.

[0048] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring containing aluminum or the like, or a wiring formed from a semiconductor such as polysilicon doped with impurities.

[0049] The active side gate wiring 131 is provided in the active section 160. By providing the active side gate wiring 131 in the active section 160, it is possible to reduce variations in wiring length from the gate pad 164 for each region of the semiconductor substrate 10.

[0050] The peripheral gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active section 160. The peripheral gate wiring 130 and the active side gate wiring 131 are arranged above the semiconductor substrate 10. The peripheral gate wiring 130 and the active side gate wiring 131 may be metal wiring containing aluminum or the like, or wiring formed from a semiconductor such as polysilicon doped with impurities.

[0051] The active side gate wiring 131 may be connected to the peripheral gate wiring 130. In this example, the active side gate wiring 131 extends in the X axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 sandwiching the active section 160 therebetween, dividing the active section 160 into approximately equal parts in the Y axis direction and traversing the same. When the active section 160 is divided by the active side gate wiring 131, the transistor sections 70 and the diode sections 80 may be arranged alternately in the X axis direction in each divided region.

[0052] The semiconductor device 100 may include a temperature sensor (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detector (not shown) that simulates the operation of a transistor provided in the active section 160. The temperature sensor may be connected to an anode pad and a cathode pad that are arranged near the edge 162.

[0053] In the present example, the semiconductor device 100 includes an edge termination structure 90 between the active section 160 and the edge 162 when viewed from above. The edge termination structure 90 in the present example is disposed between the peripheral gate wiring 130 and the edge 162. The edge termination structure 90 relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are arranged in an annular shape surrounding the active section 160.

[0054] 2 is an enlarged view of region D in FIG. 1 . Region D is a region including the transistor section 70, the diode section 80, and the active-side gate wiring 131. Although omitted in FIG. 1 , a boundary region 200 is disposed between the transistor section 70 and the diode section 80 in the X-axis direction. In this example, the boundary region 200 may be a part of the transistor section 70, i.e., the transistor section 70 may have the boundary region 200. Alternatively, the boundary region 200 may be a part of the diode section 80. Note that in the following description, the transistor section 70, the diode section 80, and the boundary region 200 may be described separately as separate parts.

[0055] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of a semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion. The semiconductor device 100 of this example also includes an emitter electrode 52 and an active-side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 is an example of a metal electrode. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0056] An interlayer insulating film is provided between the emitter electrode 52 and the active side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is not shown in Fig. 2. In this example, contact holes 54 are provided in the interlayer insulating film so as to penetrate the interlayer insulating film. In Fig. 2, each contact hole 54 is hatched with diagonal lines.

[0057] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction. The dummy conductive portion of the dummy trench portion 30 does not need to be connected to the emitter electrode 52 and the gate conductive portion, and may be controlled to a potential different from the potential of the emitter electrode 52 and the potential of the gate conductive portion.

[0058] The active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0059] The emitter electrode 52 is made of a material containing metal. FIG. 2 shows the area where the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is made of aluminum or an alloy containing aluminum as a main component, such as a metal alloy such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal made of titanium or a titanium compound below the region made of aluminum or the like. Furthermore, the contact hole may have a plug portion formed by embedding tungsten or the like so as to contact the barrier metal and aluminum or the like.

[0060] The base region 14 is a region of the second conductivity type. The well region 11 is provided so as to overlap with the active side gate wiring 131. The well region 11 is also provided so as to extend by a predetermined width into an area where it does not overlap with the active side gate wiring 131. The well region 11 in this example is provided away from the end of the contact hole 54 in the Y-axis direction toward the active side gate wiring 131. The well region 11 is a region of the second conductivity type having a higher doping concentration than the base region 14. In this example, the base region 14 is P-type, and the well region 11 is P+-type.

[0061] Each of the transistor section 70, the diode section 80, and the boundary region 200 has a plurality of trench sections arranged in a first direction. The plurality of trench sections extend in a second direction perpendicular to the first direction on the front surface side of the semiconductor substrate 10. The second direction is an example of a predetermined trench extension direction. The plurality of trench sections includes a gate trench section 40.

[0062] In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the first direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the first direction. In the diode section 80 of this example, no gate trench section 40 is provided. In the boundary region 200 of this example, a plurality of dummy trench sections 30 are provided along the first direction. In the boundary region 200 of this example, no gate trench section 40 is provided.

[0063] The gate trench portion 40 in this example may have two straight line portions 39 extending along the second direction (portions of the trench that are linear along the second direction) and a tip portion 41 connecting the two straight line portions 39. The second direction in FIG. 2 is the Y-axis direction.

[0064] At least a portion of the tip portion 41 is preferably curved in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction with each other by the tip portion 41, electric field concentration at the ends of the straight portions 39 can be alleviated.

[0065] In the transistor section 70, the dummy trench section 30 is provided between each of the linear portions 39 of the gate trench section 40. One or more dummy trench sections 30 may be provided between each of the linear portions 39. The dummy trench section 30 may have a linear shape extending in the second direction, and may have a linear section 29 and an end portion 31, similar to the gate trench section 40. The semiconductor device 100 shown in FIG. 2 includes both linear dummy trench sections 30 without end portions 31 and dummy trench sections 30 with end portions 31.

[0066] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottom of each trench portion.

[0067] A mesa portion 60 is provided between each trench portion in the first direction. The mesa portion 60 refers to a region sandwiched between the trench portions inside the semiconductor substrate 10. As an example, the upper end of the mesa portion 60 is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion 60 is provided on the upper surface of the semiconductor substrate 10, extending in the second direction (Y-axis direction) along the trench. The mesa portion 60 of the transistor portion 70, the mesa portion 60 of the diode portion 80, and the mesa portion 60 of the boundary region 200 may have different structures. In this specification, the mesa portion 60 may simply refer to the mesa portion 60 of the transistor portion 70, the mesa portion 60 of the diode portion 80, and the mesa portion 60 of the boundary region 200.

[0068] A base region 14 is provided in the mesa portion 60 of the transistor portion 70 and the boundary region 200. The base region 14 is a region of the second conductivity type. In this example, the base region 14 is P-type. The doping concentration of the base region 14 in the boundary region 200 may be the same as or different from the doping concentration of the base region 14 in the transistor portion 70. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion 60 of the transistor portion 70 and the boundary region 200, the region closest to the active-side gate wiring 131 is referred to as the base region 14-e. While FIG. 2 shows the base region 14-e disposed at one end of each mesa portion 60 in the second direction, a base region 14-e is also disposed at the other end of each mesa portion 60.

[0069] In the mesa portion 60 of the transistor section 70, an emitter region 12 of a first conductivity type and a contact region 15 of a second conductivity type are provided in a region sandwiched between the base regions 14-e in a top view. In the mesa portion 60 of the boundary region 200, a contact region 15 of a second conductivity type may be provided in a region sandwiched between the base regions 14-e in a top view. The contact region 15 is a region of the second conductivity type having a higher doping concentration than the base region 14. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0070] An anode region 17 is provided in the mesa portion 60 of the diode portion 80. The anode region 17 is a region of the second conductivity type. In this example, the anode region 17 is of P type. Of the anode regions 17 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion 60 of the diode portion 80, the region that is arranged closest to the active-side gate wiring 131 is referred to as anode region 17-e. While FIG. 2 shows the anode region 17-e arranged at one end of the mesa portion 60 of the diode portion 80 in the second direction, an anode region 17-e is also arranged at the other end.

[0071] The mesa portion 60 of the diode portion 80 may be provided with a second conductivity type contact region 15 in a region sandwiched between the anode regions 17-e in a top view. The contact region 15 is a region of the second conductivity type having a doping concentration higher than that of the base region 14. The contact region 15 may be provided between the anode region 17 and the upper surface of the semiconductor substrate 10 in the depth direction. Note that the mesa portion 60 of the diode portion 80 may be provided with the anode region 17 over the entire region sandwiched between the anode regions 17-e in a top view, and the contact region 15 may not be provided.

[0072] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0073] The contact regions 15 and the emitter regions 12 in the mesa portion 60 are each provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and the emitter regions 12 in the mesa portion 60 are alternately arranged along the second direction (Y-axis direction) of the trench portion.

[0074] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe pattern along the second direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region that contacts the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0075] The emitter region 12 is not provided in the mesa portion 60 of the diode portion 80 and the boundary region 200. The boundary region 200 may be a region in which no channel is formed in the mesa portion 60. The boundary region 200 may be a region in which a channel is formed at a lower rate than in the transistor portion 70.

[0076] An anode region 17 may be provided in the region sandwiched between the contact regions 15 on the upper surface of the mesa portion 60 of the diode portion 80. The anode region 17 may be disposed over the entire region sandwiched between the contact regions 15. The mesa portion 60 of the boundary region 200 may have the same structure as the mesa portion 60 of the diode portion 80, or may have a different structure. In this example, the mesa portion 60 of the boundary region 200 has a contact region 15 provided over the entire region sandwiched between the base regions 14-e. In other words, the area of ​​the contact region 15 of the mesa portion 60 of the boundary region 200 may be larger than the area of ​​the contact region 15 of the mesa portion 60 of the diode portion 80. In this case, holes in the semiconductor substrate 10 are more easily extracted to the emitter electrode 52 via the mesa portion 60 of the boundary region 200.

[0077] Furthermore, an N-type impurity region having a doping concentration similar to or lower than that of the emitter region 12 may be provided in the mesa portion 60 of the boundary region 200. In this case, however, the gate trench portion 40 is not provided in the boundary region 200. In the following description, this impurity region may be referred to as an accumulation region.

[0078] Furthermore, the trench portion at the boundary position between the transistor portion 70 and the boundary region 200 is a dummy trench portion 30. In the mesa portion 60 in the boundary region 200, the N-type impurity region is not in contact with the gate trench portion 40, so that no more current flows in the boundary region 200 than in the transistor portion 70. This suppresses the injection of holes from the mesa portion 60 in the boundary region 200, thereby reducing reverse recovery loss.

[0079] A contact hole 54 is provided above each mesa portion 60. The contact hole 54 is arranged in a region sandwiched between the base regions 14-e. In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 are not provided in regions corresponding to the base region 14-e and the well region 11. The contact hole 54 may be arranged at the center of the mesa portion 60 in the first direction (X-axis direction).

[0080] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. A P+ type collector region 22 may be provided in a region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In FIG. 2 , the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line. Furthermore, in the transistor section 70 and the boundary region 200, a P+ type collector region 22 is provided in a region adjacent to the lower surface of the semiconductor substrate 10.

[0081] The cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and a P-type region (well region 11) that has a relatively high doping concentration and is formed deep, thereby improving the breakdown voltage. In this example, the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0082] Fig. 3 is a diagram showing an example of the e-e cross section in Fig. 2. The e-e cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0083] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with the contact holes 54 described with reference to FIG. 2 .

[0084] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 contacts the front surface 21 of the semiconductor substrate 10 through a contact hole 54 in the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (the Z-axis direction) is referred to as the depth direction. As will be described in detail later, the emitter electrode 52 may have a titanium-containing barrier metal in a portion that contacts the front surface 21 of the semiconductor substrate 10. The barrier metal may have a titanium nitride layer or a stacked structure of a titanium nitride layer and a titanium layer. As will be described in detail later, the emitter electrode 52 may have a plug portion made of tungsten or the like filled in the contact hole 54.

[0085] The semiconductor substrate 10 has a drift region 18 of a first conductivity type, for example, N-type or N-type. In this example, the drift region 18 is an N-type region. The drift region 18 is provided in each of the transistor section 70, the diode section 80, and the boundary region 200. The base region 14 and the contact region 15 are provided above the drift region 18.

[0086] The semiconductor substrate 10 also has an accumulation region 16 of a first conductivity type, for example, N-type or N+ type. The accumulation region 16 and the above-mentioned emitter region 12 are regions of the first conductivity type that are more highly doped than the drift region 18. In this example, the accumulation region 16 and the emitter region 12 are both N+ type regions.

[0087] The accumulation region 16 accumulates holes below the accumulation region 16. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The doping concentration of the accumulation region 16 may be 10 times or more, 50 times or more, or 100 times or more than the doping concentration of the drift region 18.

[0088] The transistor section 70 has a first transistor region 201 including the emitter region 12 and the gate trench section 40, and a second transistor region 202 including the emitter region 12 and the gate trench section 40. The second transistor region 202 is provided between the first transistor region 201 and the diode section 80.

[0089] As described above, the transistor section 70 has the boundary region 200 that is provided closer to the diode section 80 than the second transistor region 202. The accumulation region 16 is provided from the mesa section 60 of the second transistor region 202 to the mesa section 60 of the boundary region 200. In this example, the accumulation region 16 is provided from the mesa section 60 of the second transistor region 202 to the mesa section 60 of the boundary region 200 and the mesa section 60 of the diode section 80. Note that the accumulation region 16 does not necessarily have to be provided in the mesa section 60 of the diode section 80.

[0090] In this example, the front surface of the semiconductor substrate 10 in the boundary region 200 where the accumulation region 16 is provided in the mesa portion 60 is the contact region 15. If the front surface of the semiconductor substrate 10 in the boundary region 200 is the contact region 15, hole injection increases, but the accumulation region 16 of the mesa portion 60 in the boundary region 200 can suppress hole injection.

[0091] In this example, the multiple mesas 60 include one or more first mesas 61, one or more second mesas 62, one or more third mesas 63, and one or more fourth mesas 64. The first mesa 61 and the second mesa 62 are provided in the transistor section 70. More specifically, the first mesa 61 is provided in the first transistor region 201, and the second mesa 62 is provided in the second transistor region 202. That is, the second mesa 62 is disposed between the first mesa 61 and the diode section 80. The third mesa 63 is provided in the diode section 80, and the fourth mesa 64 is provided in the boundary region 200.

[0092] In the first mesa portion 61 of the first transistor region 201 and the second mesa portion 62 of the second transistor region 202, an N+ type emitter region 12 and a P type base region 14 are provided in this order from the front surface 21 side of the semiconductor substrate 10.

[0093] The emitter region 12 is exposed on the front surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60.

[0094] In the transistor portion 70, the base region 14 is provided below the emitter region 12. In the transistor portion 70 of this example, the base region 14 is provided in contact with the emitter region 12. In the transistor portion 70, the base region 14 may be in contact with the trench portions on both sides of the first mesa portion 61 and the second mesa portion 62.

[0095] The first mesa portion 61 of the first transistor region 201 has a first region 301 of a first conductivity type provided between the depth position of the lower end of the base region 14 and the depth position of the lower end of the trench portion. In this example, the first region 301 of the first conductivity type is the drift region 18 of the first conductivity type.

[0096] The second mesa portion 62 of the second transistor region 202 has a second region 302 of the first conductivity type provided between the depth position of the lower end of the base region 14 and the depth position of the lower end of the trench portion. The second region 302 includes an accumulation region 16 of the first conductivity type. The second region 302 of the second mesa portion 62 has a higher doping concentration than the first region 301 of the first mesa portion 61. This makes it possible to suppress hole injection near the diode portion 80. In addition, the width of the boundary region 200 in the X-axis direction can be narrowed.

[0097] The diode section 80 has a second conductivity type anode region 17 provided above the drift region 18. The anode region 17 in the diode section 80 is in contact with the front surface 21 of the semiconductor substrate 10. The doping concentration of the second conductivity type anode region 17 may be the same as or different from the doping concentration of the second conductivity type base region 14. The third mesa section 63 of the diode section 80 has a first conductivity type third region 303 provided between the depth position of the lower end of the anode region 17 and the depth position of the lower end of the trench section. In this example, the third region 303 includes the accumulation region 16. The first conductivity type third region 303 of the third mesa section 63 has a higher doping concentration than the first conductivity type drift region 18.

[0098] The doping concentration of the second conductivity type anode region 17 in the diode section 80 may be greater than, less than, or the same as the doping concentration of the base region 14 in the transistor section 70. Also, the doping concentration of the anode region 17 may be greater than, less than, or the same as the doping concentration of the base region 14 in the boundary region 200. As an example, the doping concentration of the second conductivity type anode region 17 in the diode section 80 is equal to or greater than the doping concentrations of the base region 14 in the transistor section 70 and the boundary region 200.

[0099] In this example, a P+ type contact region 15 is provided in the fourth mesa portion 64 of the boundary region 200 in contact with the front surface 21 of the semiconductor substrate 10. The fourth mesa portion 64 also has a base region 14 between the contact region 15 and the drift region 18. The fourth mesa portion 64 has a fourth region 304 of the first conductivity type provided between the depth position of the lower end of the base region 14 and the depth position of the lower end of the trench portion. The fourth region 304 includes the accumulation region 16. The fourth region 304 of the first conductivity type in the fourth mesa portion 64 has a higher doping concentration than the first region 301 of the first conductivity type in the first mesa portion 61.

[0100] Each of the first region 301 to the fourth region 304 may be provided across the entire X-axis direction of the respective mesa portion 60. Each of the first region 301 to the fourth region 304 may be provided so as to cover the entire lower surface of the base region 14 of the respective mesa portion 60. The doping concentrations of the multiple first regions 301, etc. in each of the transistor portion 70, the diode portion 80, and the boundary region 200 may be the same or different in each mesa portion 60. As an example, the doping concentration of the second region 302 in the second transistor region 202 may be higher in the second mesa portion 62 closer to the diode portion 80.

[0101] As described above, the first region 301 to the fourth region 304 are all regions provided between the depth position of the lower end of the base region 14 and the depth position of the lower end of the trench portion. In this example, the depth position of the lower end of the base region 14 is uniform in the transistor portion 70, the diode portion 80, and the boundary region 200. In addition, the depth position of the lower end of the trench portion in this example is also uniform in the transistor portion 70, the diode portion 80, and the boundary region 200. Therefore, in this example, the widths in the depth direction of the first region 301, the second region 302, the third region 303, and the fourth region 304 are generally uniform. If the spacing between adjacent trench portions is uniform in the transistor portion 70, the diode portion 80, and the boundary region 200, the volumes of the first region 301, the second region 302, the third region 303, and the fourth region 304 may also be generally uniform.

[0102] Trench contact portions 58 are provided in the first mesa portion 61, the second mesa portion 62, the third mesa portion 63, and the fourth mesa portion 64. The trench contact portions 58 are portions where metal electrodes such as the emitter electrode 52 are provided inside the semiconductor substrate 10. The trench contact portions 58 can be formed by forming grooves in the front surface 21 of the semiconductor substrate 10 exposed by the contact holes 54 and filling the interiors of the grooves with metal electrodes. The regions where the first mesa portion 61, etc., and the metal electrodes such as the emitter electrode 52 contact each other correspond to contact portions.

[0103] In this example, the width in the depth direction of the trench contact portion 58 is uniform in all of the first mesa portion 61, the second mesa portion 62, the third mesa portion 63, and the fourth mesa portion 64, but may be different from one another. For example, the trench contact portion 58 and the contact region 15 of the second mesa portion 62 may be deeper toward the drift region 18 than the trench contact portion 58 and the contact region 15 of the first mesa portion 61.

[0104] In each of the transistor section 70, the diode section 80, and the boundary region 200, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Furthermore, the doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0105] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peak of the buffer region 20 may be located at the same depth as the chemical concentration peak of hydrogen (protons) or phosphorus, for example. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0106] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0107] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than the donor concentration of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as the donor and acceptor in each region are not limited to the examples described above.

[0108] In the boundary region 200, a P+ type collector region 22 is provided below the buffer region 20. The collector region 22 in the boundary region 200 may have the same doping concentration as the collector region 22 in the transistor section 70. The boundary position in the X-axis direction between the cathode region 82 and the collector region 22 may be set as the boundary position in the X-axis direction between the diode section 80 and the boundary region 200.

[0109] In another example, in the boundary region 200, part or all of the collector region 22 may be replaced with the cathode region 82. When the cathode region 82 is provided on the lower surface of the boundary region 200, the region sandwiched between the anode regions 17-e and in which the contact regions 15 and the anode regions 17 are alternately arranged may be the diode section 80, and the region sandwiched between the base regions 14-e and in which the contact regions 15 are arranged entirely may be the boundary region 200. When the cathode region 82 is provided on the lower surface of the boundary region 200, the boundary region 200 may be regarded as part of the diode section 80.

[0110] Of the trenches adjacent to the mesa portion where the channel is formed, the trench that is closest to the diode portion 80 in the X-axis direction may be the boundary position in the X-axis direction between the transistor portion 70 and the boundary region 200 or the diode portion 80. Of the two trenches that contact the emitter region 12 that is closest to the diode portion 80 in the X-axis direction, the trench on the diode portion 80 side may be the dummy trench portion 30. In this case, the dummy trench portion 30 may be the boundary position in the X-axis direction between the transistor portion 70 and the boundary region 200 or the diode portion 80.

[0111] An emitter region 12 may be provided in the boundary region 200. However, in this case, a gate trench portion 40 is not provided in the boundary region 200. Furthermore, the trench portion at the boundary position between the transistor portion 70 and the boundary region 200 is a dummy trench portion 30. In other words, no transistor operation occurs in the boundary region 200. A gate trench portion 40 may be provided in the boundary region 200. However, in this case, no emitter region 12 is provided in the boundary region 200, or even if an emitter region 12 is provided, it does not contact the gate trench portion 40. In other words, no transistor operation occurs in the boundary region 200.

[0112] The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0113] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21 of the semiconductor substrate 10. Each trench extends from the front surface 21 of the semiconductor substrate 10, penetrating the base region 14, to below the base region 14 (until reaching the drift region 18). In regions where at least one of the emitter region 12 and the contact region 15 is provided, each trench also penetrates these doped regions. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed in the order of forming the doped regions and then the trenches. The trenches penetrating the doped regions also include trenches formed in the order of forming the doped regions and then the trenches.

[0114] As described above, the transistor section 70 is provided with the gate trench section 40 and the dummy trench section 30. In this example, the diode section 80 and the boundary region 200 are provided with the dummy trench section 30, but not with the gate trench section 40. However, the gate trench section 40 or the dummy trench section 30 may be arranged at the boundary between the boundary region 200 and the transistor section 70.

[0115] The boundary region 200 is a buffer structure for arranging the different structures of the transistor section 70 and the diode section 80 in parallel. Therefore, the width of the boundary region 200 in the X-axis direction may be short. For example, one or several fourth mesa sections 64 may be provided in the boundary region 200, and the boundary region 200 may not be provided at all.

[0116] Furthermore, the boundary region 200 may include a plurality of fourth mesa portions 64 in the X-axis direction. This makes it possible to suppress the influence of the transistor portion 70 on the characteristics of the diode portion 80, for example, the influence of the operation of the gate trench portion 40 and the injection or ejection of holes from or into the contact region 15 on the forward voltage and reverse recovery characteristics. Here, the number of mesa portions refers to the number of mesa portions arranged side by side in the X-axis direction.

[0117] The gate trench portion 40 has a gate trench provided on the front surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and further inside than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0118] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0119] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the front surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 covers the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44.

[0120] The gate trench portion 40 and the dummy trench portion 30 in this example are covered with an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may have a downwardly convex curved shape (a curved shape in cross section).

[0121] The semiconductor device 100 of this example includes a lifetime control region 206 that is provided on the front surface side of the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The lifetime control region 206 includes a lifetime killer that adjusts the lifetime of carriers. The lifetime control region 206 lowers the threshold voltage and also reduces the switching loss of the semiconductor device 100.

[0122] The lifetime control region 206 in this example is a region where the lifetime of charge carriers is locally short. Charge carriers are electrons or holes. Charge carriers may be simply referred to as carriers. The lifetime control region 206 in this example is formed by implanting charged particles such as helium ions from the front surface 21 side of the semiconductor substrate 10. In this example, the concentration distribution of helium or the like in the depth direction of the semiconductor substrate 10 may have a shape that trails from the lifetime control region 206 to the front surface 21 of the semiconductor substrate 10. In other words, the concentration ( / cm ) of helium or the like from the lifetime control region 206 to the front surface 21３ ) may decrease monotonically.

[0123] The concentration of helium or the like on the front surface 21 may be greater than zero. On the other hand, the concentration of helium or the like may also have a tail-like shape in the direction from the lifetime control region 206 toward the lower surface 23. However, the concentration of helium or the like decreases more steeply toward the bottom toward the lower surface 23 than toward the front surface 21. The concentration of helium or the like on the bottom surface 23 is lower than the concentration of helium or the like on the front surface 21. The concentration of helium or the like on the front surface 21 may be below the measurement limit, or may be zero. The lifetime control region 206 may be formed by implanting charged particles such as helium ions from the bottom surface 23 side of the semiconductor substrate 10.

[0124] By implanting charged particles such as helium ions into the semiconductor substrate 10, lattice defects 204 such as vacancies are formed near the implantation positions. The lattice defects 204 generate recombination centers. The lattice defects 204 may be primarily vacancies, such as monovacancies (V) and divacancies (VV), dislocations, interstitial atoms, transition metals, etc. For example, atoms adjacent to the vacancies have dangling bonds. In a broad sense, lattice defects 204 may also include donors and acceptors. However, in this specification, lattice defects 204 primarily composed of vacancies may be referred to as vacancy-type lattice defects, vacancy-type defects, or simply lattice defects. In this specification, the lattice defects 204, which are recombination centers that contribute to carrier recombination, may be simply referred to as recombination centers or lifetime killers.

[0125] The lifetime killer may be formed by implanting helium ions into the semiconductor substrate 10. The helium chemical concentration may be taken as the density of lattice defects 204. Note that the lifetime killer formed by implanting helium ions may be terminated by hydrogen present in the buffer region 20, so the depth position of the lifetime killer density peak may not coincide with the depth position of the helium chemical concentration peak. Alternatively, when hydrogen ions are implanted into the semiconductor substrate 10, the lifetime killer may be formed in a region through which the hydrogen ions pass, closer to the implanted surface than the range.

[0126] Lattice defects 204 are an example of a lifetime killer. In FIG. 3, lattice defects 204 at the injection position of charged particles are schematically indicated by an x ​​mark. In regions where many lattice defects 204 remain, carriers are captured by the lattice defects 204, shortening the carrier lifetime. By adjusting the carrier lifetime, it is possible to adjust the characteristics of the diode section 80, such as the reverse recovery time and reverse recovery loss. In the depth direction of the semiconductor substrate 10, the position where the carrier lifetime shows a minimum value may be set as the depth position of the lifetime control region 206.

[0127] The lifetime control region 206 is disposed on the front surface 21 side of the semiconductor substrate 10. The front surface 21 side is the region from the central position in the depth direction of the semiconductor substrate 10 to the front surface 21 of the semiconductor substrate 10. In this example, the lifetime control region 206 is disposed below the lower end of the trench portion.

[0128] Furthermore, when lifetime control region 206 is formed by irradiation with a particle beam having high penetrating power, such as an electron beam, lattice defects are formed substantially uniformly from front surface 21 to bottom surface 23 of semiconductor substrate 10. In this case as well, the depth position of lifetime control region 206 may be considered to be located on the front surface 21 side of semiconductor substrate 10.

[0129] The lifetime control region 206 extends from the diode section 80 to the second transistor region 202. When the semiconductor device 100 has the boundary region 200, the lifetime control region 206 is also provided in the boundary region 200. The lifetime control region 206 may be provided over the entire diode section 80 in the X-axis direction. The lifetime control region 206 is also provided over the entire boundary region 200. In this example, the lifetime control region 206 is provided below the accumulation region 16.

[0130] The lifetime control region 206 of the diode section 80 and the lifetime control region 206 of the transistor section 70 are provided at the same depth position. In the transistor section 70, the second transistor region 202 may be an adjustment region 208 in which the lifetime control region 206 is provided, and the first transistor region 201 may be a non-adjustment region 207 in which the lifetime control region 206 is not provided.

[0131] Here, the boundary between the adjustment region 208 and the non-adjustment region 207 does not have to coincide with the boundary between the first transistor region 201 and the second transistor region 202, and for example, the lattice defect 204 (lifetime control region 206) may be provided across a portion of the second transistor region 202 to the first transistor region 201.

[0132] The adjustment region 208 is a region that overlaps with the lifetime control region 206 in top view. The non-adjustment region 207 is a region that does not overlap with the lifetime control region 206 in top view. The non-adjustment region 207 is a region in which the carrier lifetime at the same depth position as the lifetime control region 206 is longer than the carrier lifetime of the lifetime control region 206 of the diode section 80. The non-adjustment region 207 may be a region into which charged particles such as helium ions for forming lifetime killers such as lattice defects 204 are not implanted. The chemical concentration ( / cm ３ ) may be the same as the chemical concentration of the charged particles at the center of the drift region 18 in the Z-axis direction.

[0133] Fig. 4 is a diagram showing an example of the ff cross section in Fig. 2. The ff cross section is an XZ plane passing through the contact region 15 and the cathode region 82. The cross section of this example has a structure in which the emitter region 12 in the example shown in Fig. 3 is replaced with the contact region 15. The structure other than the contact region 15 is the same as that of Fig. 3.

[0134] Fig. 5 is a diagram showing an example of the doping concentration distribution along the r-r' line and the s-s' line in Fig. 3. The r-r' line is a line that passes through the second region 302 and is parallel to the Z axis, and the s-s' line is a line that passes through the first region 301 and is parallel to the Z axis.

[0135] The integrated concentration of the dopant of the first conductivity type in the second region 302 is greater than the integrated concentration of the dopant of the first conductivity type in the first region 301. It can also be said that the dose amount ( / cm2) of the N-type dopant in the second region 302 is greater than the dose amount of the N-type dopant in the first region 301. The dose amount of each region may be calculated by integrating the doping concentration of each region.

[0136] In this example, the doping concentration of the first region 301 is equal to or greater than the doping concentration of the drift region 18 and less than the doping concentration of the second region 302. The doping concentration values ​​of each region may be peak values. The doping concentration of the first region 301 may be the same as the doping concentration of the drift region 18. In other words, the drift region 18 provided in the first mesa portion 61 may be treated as the first region 301. The doping concentration of the first region 301 may be higher than the doping concentration of the drift region 18. The doping concentration of the first region 301 may be half or less, 1 / 10 or less, or 1 / 100 or less of the doping concentration of the second region 302.

[0137] In this example, a PN junction is provided at the boundary between the second region 302 and the base region 14. The depth position of this boundary is designated Z14. The doping concentration distribution in the second region 302 has a peak. The doping concentration at the apex of this peak is designated P302. The doping concentration in the drift region 18 is designated D18. The peak concentration P302 is higher than the doping concentration D18. The depth position of the bottom end of the second region 302 is designated Z302.

[0138] In this example, a PN junction is provided at the boundary between the first region 301 and the base region 14. The depth position of this boundary is designated Z14. The doping concentration of the first region 301 in this example is the same as the doping concentration of the drift region 18. In this example, the number of doping concentration peaks in the first region 301 is 0. The doping concentration in the depth direction of the first region 301 in this example may be constant. The depth position of the bottom end of the first region 301 is designated Z301.

[0139] The dose per unit area of ​​the dopant ions in the first region 301 (ions / cm ２ The dose Do301 of the first region 301 may be a value obtained by integrating the doping concentration of the first region 301 from the depth position Z14 to Z301. The dose per unit area (ions / cm) of dopant ions in the second region 302 ２ ) is defined as Do302. The dose Do302 of the second region 302 may be a value obtained by integrating the doping concentration of the second region 302 from the depth position Z14 to Z302. The areas of the hatched portions in FIG. 5 correspond to the respective dose amounts.

[0140] The dose amount Do302 is greater than the dose amount Do301. The dose amount Do302 may be at least twice, at least 10 times, or at least 100 times the dose amount Do301. The doping concentration D18 of the first region 301 is smaller than the peak concentration P302. In this example, it can also be said that the number of doping concentration peaks in the second region 302 is greater than the number of doping concentration peaks in the first region 301.

[0141] 6 is an enlarged view of the periphery of the trench contact portion 58 in the boundary region 200. In the fourth mesa portion 64 in the boundary region 200, a barrier metal 53 is provided on the sidewalls and bottom surface of the contact hole 54. The barrier metal 53 may be provided on the entire bottom surface of the contact hole 54. The material of the barrier metal 53 may be titanium or a titanium compound. When the semiconductor substrate 10 is made of silicon, the barrier metal 53 may react with the semiconductor substrate 10 to form a silicide.

[0142] In the contact hole 54, a plug portion 59 is provided inside the barrier metal 53. The material of the plug portion 59 may be tungsten. The material of the plug portion 59 may be the same as the material of the emitter electrode 52. The barrier metal 53 and the plug portion 59 are similarly provided in each contact hole 54 of the transistor portion 70 and the diode portion 80.

[0143] At least some of the mesa portions 60 may have plug regions 13 in regions that contact the lower ends of the contact portions. The plug regions 13 are provided above the drift region 18 and have a higher doping concentration than the base region 14. The plug regions 13 in this example are provided below the trench contact portions 58. The plug regions 13 in this example contact the bottom surfaces of the trench contact portions 58. The plug regions 13 may contact the sidewalls of the trench contact portions 58. The plug regions 13 are regions of the second conductivity type that have a higher doping concentration than the base region 14. The plug regions 13 in this example have a higher doping concentration than the contact regions 15. The plug regions 13 in this example are P++ type regions.

[0144] The plug region 13 may be provided on the bottom surface of the trench contact portion 58, extending in the trench extension direction. The plug region 13 may be provided on the entire bottom surface of the trench contact portion 58. By providing each plug region 13, holes can be easily extracted in each mesa portion 60. This makes it possible to suppress a decrease in the withstand voltage.

[0145] 7 is a diagram showing an example of the arrangement of the adjustment region 208 and the non-adjustment region 207 in a top view. The arrangement of this example may be applied to any of the semiconductor devices 100 described in this specification. In FIG. 7, two diode sections 80 and one transistor section 70 are shown, and other regions are omitted. Also, in FIG. 7, the region where the lifetime control region 206 is provided is hatched with diagonal lines.

[0146] In this example, in the transistor portion 70, the adjustment region 208 in which the lifetime control region 206 is provided may include the second transistor region 202, and the non-adjustment region 207 in which the lifetime control region 206 is not provided may coincide with the first transistor region 201. The adjustment region 208 may also be provided in the entire diode portion 80 in the X-axis direction. The adjustment region 208 is also provided in a region in the transistor portion 70 that contacts the diode portion 80 or the boundary region 200. The area of ​​the first transistor region 201 in the transistor portion 70 may be larger than the area of ​​the second transistor region 202. That is, in this example, the area of ​​the non-adjustment region 207 in the transistor portion 70 may be larger than the area of ​​the adjustment region 208 in the transistor portion 70.

[0147] In the transistor section 70, the number of first mesa sections 61 may be greater than the number of second mesa sections 62. This makes it possible to suppress local current concentration even if the second transistor region 202 turns off slower than the first transistor region 201. In the transistor section 70, the threshold voltage of the first mesa section 61 may be lower than the threshold voltage of the second mesa section 62. The threshold voltage of each mesa section 60 can be adjusted by adjusting the depth of the trench contact section 58 in the second mesa section 62 and the dose amount of each plug region 13. The threshold voltage of a mesa section 60 is the voltage at which at least one channel region in the mesa section 60 transitions from off to on.

[0148] FIG. 8 is a diagram showing another example of the configuration of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. In this example, the first region 301 in the first mesa portion 61 includes an N-type accumulation region 16. In this example, the second region 302 in the second mesa portion 62 and the third region 303 in the third mesa portion 63 each include an N+-type accumulation region 16. The structure other than the first region 301, the second region 302, and the third region 303 may be the same as the embodiment described using FIGS. 1 to 7, and redundant description will be omitted. Also, as an example, the third region 303 may have the same doping concentration as the second region 302, and redundant description will be omitted. This also applies to the following embodiments.

[0149] 9 is a diagram showing an example of the doping concentration distribution along the rr' line and the ss' line in FIG. 8. The doping concentration distribution in the first region 301 in this example has a peak, unlike the example in FIG. 5. The doping concentration at the apex of the peak is designated as P301. The peak concentration P301 is higher than the doping concentration D18.

[0150] The integrated concentration of the dopant of the first conductivity type in the second region 302 is greater than the integrated concentration of the dopant of the first conductivity type in the first region 301. It can be said that the dose amount Do302 is greater than the dose amount Do301. The dose amount Do302 may be two or more times, ten or more times, or even one hundred or more times the dose amount Do301.

[0151] The peak doping concentration of the second region 302 is greater than the peak doping concentration of the first region 301. In this example, the peak concentration P302 is greater than the peak concentration P301. The peak concentration P301 may be at least two times, at least ten times, or at least one hundred times greater than the peak concentration P302.

[0152] FIG. 10 is a diagram showing another example of the configuration of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. This example differs from the example of FIG. 8 in that the second mesa portion 62 and the third mesa portion 63 have multiple accumulation regions 16 in the depth direction. The multiple accumulation regions 16 in the second mesa portion 62 and the like may have regions with a lower doping concentration than the accumulation regions 16 interposed therebetween, for example, N-type regions interposed therebetween, similar to the drift region 18. In another example, the regions between the multiple accumulation regions 16 may have a higher doping concentration than the drift region 18. The first region 301 of the first mesa portion 61, the second region 302 of the second mesa portion 62, and the third region 303 of the third mesa portion 63 each have one or more peaks of doping concentration in the depth direction.

[0153] In this example, the second region 302 in the second mesa portion 62 has a larger number of accumulation regions 16 than the number of accumulation regions 16 included in the first region 301 in the first mesa portion 61. In Fig. 10, the first region 301 has one accumulation region 16, and the second region 302 has two accumulation regions 16. That is, the number of doping concentration peaks in the second region 302 in this example is two.

[0154] Fig. 11 is a diagram showing an example of the doping concentration distribution along the r-r' line and the s-s' line in Fig. 10. One doping concentration P302-1 and another doping concentration P302-2 in the second region 302 may be the same as or different from each other.

[0155] The integrated concentration of the dopant of the first conductivity type in the second region 302 is greater than the integrated concentration of the dopant of the first conductivity type in the first region 301. It can be said that the dose amount Do302 is greater than the dose amount Do301. The dose amount Do302 may be two or more times, ten or more times, or even one hundred or more times the dose amount Do301.

[0156] The peak doping concentration of the second region 302 may be equal to or greater than the peak doping concentration of the first region 301. In this example, the peak concentration P302 is equal to the peak concentration P301. The peak concentration P301 may be equal to or greater than the peak concentration P302 by one or more times, two or more times, ten or more times, or even one hundred or more times. The number of doping concentration peaks P302-1 and P302-2 in the second region 302 is greater than the number of doping concentration peaks P301 in the first region 301.

[0157] 12 is a diagram showing another example of the configuration of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. This example differs from the example of the configuration of FIG. 10 in that the first mesa portion 61 also has a plurality of accumulation regions 16 in the depth direction. The plurality of accumulation regions 16 in the first mesa portion 61 may have regions with a lower doping concentration than the doping concentration of the accumulation regions 16 interposed between them, and for example, an N-type region may be interposed similarly to the drift region 18.

[0158] In another example, the region between the plurality of accumulation regions 16 may have a higher doping concentration than the drift region 18. The first region 301 of the first mesa portion 61, the second region 302 of the second mesa portion 62, and the third region 303 of the third mesa portion 63 each have multiple peaks of doping concentration in the depth direction.

[0159] In this example, the second region 302 in the second mesa portion 62 has the same number of accumulation regions 16 as the number of accumulation regions 16 included in the first region 301 in the first mesa portion 61. In Fig. 12, the first region 301 and the second region 302 each have two accumulation regions 16. That is, the number of doping concentration peaks in the first region 301 and the second region 302 in this example is two. In this example, the first region 301 has two N-type accumulation regions 16, and the second region 302 has two N+-type accumulation regions 16.

[0160] 13 is a diagram showing an example of doping concentration distributions along the r-r' and s-s' lines in FIG. 10. One doping concentration P301-1 and another doping concentration P301-2 in the first region 301 may be the same as or different from each other. Similarly, one doping concentration P302-1 and another doping concentration P302-2 in the second region 302 may be the same as or different from each other.

[0161] The integrated concentration of the dopant of the first conductivity type in the second region 302 is greater than the integrated concentration of the dopant of the first conductivity type in the first region 301. It can be said that the dose amount Do302 is greater than the dose amount Do301. The dose amount Do302 may be two or more times, ten or more times, or even one hundred or more times the dose amount Do301.

[0162] The peak doping concentration of the second region 302 is greater than the peak doping concentration of the first region 301. In this example, the peak concentrations P302-1 and P302-2 are both greater than the peak concentrations P301-1 and P301-2, respectively. The peak concentrations P302-1 and P302-2 may be at least twice, at least 10 times, or at least 100 times the peak concentrations P301-1 and P301-2, respectively.

[0163] 14 is a diagram showing another example of the configuration of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. This example differs from the example of FIG. 10 in that the second region 302 in the second mesa portion 62 and the third region 303 in the third mesa portion 63 have accumulation regions 16 that are relatively wider in the depth direction than the first region 301 in the first mesa portion 61.

[0164] In this example, the second region 302 and the first region 301 include accumulation regions 16 of the same doping concentration. The width of the accumulation region 16 in the second region 302 in the depth direction is greater than the width of the accumulation region 16 in the first region 301 in the depth direction.

[0165] 15 is a diagram showing an example of doping concentration distribution along the rr' line and the ss' line in FIG. 14. The integrated concentration of the dopant of the first conductivity type in the second region 302 is greater than the integrated concentration of the dopant of the first conductivity type in the first region 301. It can be said that the dose amount Do302 is greater than the dose amount Do301. The dose amount Do302 may be two times or more, ten times or more, or even one hundred times or more, of the dose amount Do301.

[0166] Figure 16 is a diagram showing another example of the e-e cross section in Figure 2. The semiconductor device 100 of this example differs from the semiconductor device 100 in the multiple embodiments described with reference to Figures 1 to 15 in that the semiconductor substrate 10 does not have a lifetime control region 206. Other structures in the semiconductor device 100 of this example are similar to the corresponding structures in the semiconductor device 100 in the multiple embodiments described with reference to Figures 1 to 15, and therefore corresponding reference numerals are used and duplicated descriptions will be omitted.

[0167] FIG. 16 shows an example in which the lifetime control region 206 is deleted from the structure shown in FIG. 3, but the lifetime control region 206 may also be deleted from the structures shown in the other figures.

[0168] Figure 17 is a diagram showing another example of the e-e cross section in Figure 2. The semiconductor device 100 of this example differs from the semiconductor device 100 in the multiple embodiments described with reference to Figures 1 to 16 in that the semiconductor substrate 10 has a lifetime control region 206 over the entire surface, and the lifetime control region 206 is provided continuously at the same depth in the transistor section 70 and the diode section 80. Other structures in the semiconductor device 100 of this example are similar to the corresponding structures in the semiconductor device 100 in the multiple embodiments described with reference to Figures 1 to 16, and therefore corresponding reference numerals are used and duplicated descriptions will be omitted.

[0169] Figure 17 shows an example in which the semiconductor substrate 10 has a lifetime control region 206 over the entire surface, and the lifetime control region 206 is provided continuously at the same depth in the transistor section 70 and the diode section 80, as compared to the structure shown in Figure 3. However, even in the structures shown in other figures, the lifetime control region 206 may be provided over the entire surface, and the lifetime control region 206 may be provided continuously at the same depth in the transistor section 70 and the diode section 80.

[0170] 18 is another example of an enlarged view of region D in FIG. 1. The semiconductor device 100 of this example differs from the semiconductor device 100 of the multiple embodiments described with reference to FIGS. 1 to 17 in that the boundary region 200 is a single mesa portion 60. Other structures of the semiconductor device 100 of this example are similar to the corresponding structures of the semiconductor device 100 of the multiple embodiments described with reference to FIGS. 1 to 17, and therefore corresponding reference numerals are used and redundant description will be omitted.

[0171] FIG. 18 shows an example in which the boundary region 200 has one mesa portion 60, based on the structure shown in FIG. 2 . However, the boundary region 200 may also have one mesa portion 60 in the structures shown in other figures. In this example, the contact regions 15 and the base regions 14 are alternately arranged in the Y direction in the mesa portion 60 of the boundary region 200. Instead of providing the contact region 15 over the entire region sandwiched between the base regions 14-e in a top view of the mesa portion 60 of the boundary region 200, as in this example, the contact region 15 may be provided only partially. Even in cases other than this example in which the boundary region 200 has two or more mesa portions 60, the mesa portion 60 may have a contact region 15 partially provided therein. Meanwhile, in this example, the contact region 15 may also be provided over the entire region sandwiched between the base regions 14-e in a top view of the mesa portion 60 of the boundary region 200.

[0172] 19 is another example of an enlarged view of region D in FIG. 1 . The semiconductor device 100 of this example includes a plurality of mesa portions 60 in a boundary region 200. The semiconductor device 100 of this example differs from the semiconductor device 100 of the multiple embodiments described with reference to FIGS. 1 to 18 in that some mesa portions 60 in contact with the front surface 21 of the semiconductor substrate 10 in the boundary region 200 and adjacent to the transistor portion 70 include contact regions 15, while the remaining mesa portions 60 include base regions 14 but do not include contact regions 15. Here, "having base regions 14 but not including contact regions 15" may include a case where the contact regions 15 are provided only in end regions adjacent to the base regions 14-e in the region sandwiched between the base regions 14-e in a top view of the mesa portions 60 in the boundary region 200, or a case where the base regions 14 are provided over the entire surface but no contact regions 15 are provided.

[0173] Other structures in the semiconductor device 100 of this example are similar to the corresponding structures in the semiconductor device 100 in the multiple embodiments described using Figures 1 to 18, so corresponding reference numbers are used and duplicate descriptions are omitted.

[0174] 19 shows an example in which the mesa portion 60 in contact with the front surface 21 of the semiconductor substrate 10 in the boundary region 200 and adjacent to the transistor portion 70 is provided with the contact region 15, and the other mesa portions 60 have the base region 14 but no contact region 15, but even in the structures shown in other figures, some mesa portions 60 adjacent to the transistor portion 70 may be provided with the contact region 15 on the top surface of the boundary region 200, and the other mesa portions 60 may have the base region 14 but no contact region 15. Furthermore, when viewed from above of the mesa portions 60 in the boundary region 200, the boundary region 200 may consist only of mesa portions 60 that have the base region 14 but no contact region 15 in the region sandwiched between the base regions 14-e.

[0175] Figure 20 is a diagram showing an example of the e-e cross section in Figure 19. In the boundary region 200 of this example, a plurality of fourth mesas 64 are provided in the X-axis direction, and in the fourth mesa 64 adjacent to the second transistor region 202, a contact region 15 is provided in contact with the front surface 21 of the semiconductor substrate 10, and a base region 14 is provided between the contact region 15 and the drift region 18. In addition, in the fourth mesa 64 not adjacent to the second transistor region 202 of the boundary region 200 of this example, a base region 14 is provided in contact with the front surface 21 of the semiconductor substrate 10, and the base region 14 is in contact with the drift region 18.

[0176] 3 , the plurality of fourth mesa portions 64 of the present example have fourth regions 304 of the first conductivity type provided between the depth position of the lower end of the base region 14 and the depth position of the lower end of the trench portion. The fourth regions 304 include the accumulation region 16. The fourth regions 304 of the first conductivity type of the fourth mesa portion 64 have a higher doping concentration than the first regions 301 of the first conductivity type of the first mesa portion 61.

[0177] In this example, the boundary region 200 is provided with multiple fourth mesa portions 64 in the X-axis direction, which makes it possible to suppress the influence of the transistor portion 70 on the characteristics of the diode portion 80, for example, the influence of the operation of the gate trench portion 40 and the injection or ejection of holes from the contact region 15 on the forward voltage and reverse recovery characteristics.

[0178] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0179] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0180] 10 semiconductor substrate 12 emitter region 13 plug region 14 base region 15 contact region 16 accumulation region 17 anode region 18 drift region 20 buffer region 21 front surface 22 collector region 23 lower surface 24 collector electrode 29 straight portion 30 dummy trench portion 31 tip portion 32 dummy insulating film 34 dummy conductive portion 38 interlayer insulating film 39 straight portion 40 gate trench portion 41 tip portion 42 gate insulating film 44 gate conductive portion 52 emitter electrode 53 barrier metal 54 contact hole 58 trench contact portion 59 plug portion 60 mesa portion 61 first mesa portion 62 second mesa portion 63 third mesa portion 64 fourth mesa portion 70 transistor portion 80 diode portion 81 Extension region 82 Cathode region 90 Edge termination structure 100 Semiconductor device 130 Peripheral gate wiring 131 Active side gate wiring 160 Active portion 162 Edge 164 Gate pad 200 Boundary region 201 First transistor region 202 Second transistor region 204 Lattice defects 206 Lifetime control region 207 Non-adjusted region 208 Adjusted region 301 First region 302 Second region 303 Third region

Claims

1. A semiconductor device comprising a transistor portion and a diode portion, comprising: a drift region of a first conductivity type provided in a semiconductor substrate; a plurality of trench portions extending on the front surface side of the semiconductor substrate in a predetermined trench extension direction; a base region of a second conductivity type provided above the drift region; an emitter region of the first conductivity type provided on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; and a contact region of a second conductivity type provided above the drift region and having a doping concentration higher than that of the base region, wherein the plurality of trench portions have gate trench portions, and the transistor portion comprises: a first transistor region including the emitter region and the gate trench portion, and a second transistor region including the emitter region and the gate trench portion and provided between the first transistor region and the diode portion, and a first mesa portion of the first transistor region has a first region of the first conductivity type provided between a depth position of a lower end of the base region and a depth position of a lower end of the trench portion, a second mesa portion of the second transistor region is provided between a depth position of a lower end of the base region and a depth position of a lower end of the trench portion, and has a second region of the first conductivity type having a doping concentration higher than that of the first region.

2. The semiconductor device according to claim 1, further comprising an accumulation region of the first conductivity type provided above the drift region and having a doping concentration higher than that of the drift region, the accumulation region being provided from the second mesa portion of the second transistor region to the third mesa portion of the diode region.

3. The semiconductor device according to claim 1, wherein the transistor section has a boundary region that is provided closer to the diode section than the second transistor region.

4. The semiconductor device according to claim 3, further comprising an accumulation region of the first conductivity type provided above the drift region and having a doping concentration higher than that of the drift region, the accumulation region being provided from the second mesa portion in the second transistor region to the fourth mesa portion in the boundary region.

5. The semiconductor device according to claim 4, wherein the front surface of the semiconductor substrate in the boundary region is the contact region.

6. The semiconductor device according to claim 1, wherein the first region is the drift region.

7. The semiconductor device according to claim 1, wherein the peak doping concentration of said second region is greater than the peak doping concentration of said first region.

8. The semiconductor device according to claim 1, wherein the number of peaks of the doping concentration in the second region is greater than the number of peaks of the doping concentration in the first region.

9. The semiconductor device according to claim 1, further comprising an accumulation region of a first conductivity type provided above the drift region and having a doping concentration higher than that of the drift region, wherein the second region and the first region include accumulation regions of the same doping concentration, and wherein the width in the depth direction of the accumulation region in the second region is greater than the width in the depth direction of the accumulation region in the first region.

10. The semiconductor device according to claim 1, wherein an integrated concentration of the dopant of the first conductivity type in said second region is greater than an integrated concentration of the dopant of the first conductivity type in said first region.

11. The semiconductor device according to claim 1, wherein the diode section has an anode region of a second conductivity type provided above the drift region, and the third mesa section of the diode section has a third region of a first conductivity type provided between the depth position of the lower end of the anode region and the depth position of the lower end of the trench section, and the third region has the first conductivity type with a doping concentration higher than that of the drift region.

12. The semiconductor device according to claim 11, wherein the doping concentration of the anode region is equal to or greater than the doping concentration of the base region.

13. The semiconductor device according to claim 11, wherein the doping concentration of the anode region is the same as the doping concentration of the base region.

14. The semiconductor device according to claim 1, further comprising a lifetime control region provided on the front surface side of the semiconductor substrate relative to the center thereof in the depth direction of the semiconductor substrate.

15. The semiconductor device according to claim 14, wherein the lifetime control region extends from the diode portion to the second transistor region.

16. The semiconductor device according to claim 14, further comprising an accumulation region of the first conductivity type provided above the drift region and having a doping concentration higher than that of the drift region, and the lifetime control region is provided below the accumulation region.

17. The semiconductor device according to claim 14, wherein the second transistor region is an adjustment region in which the lifetime control region is provided, and the first transistor region is a non-adjustment region in which the lifetime control region is not provided.

18. The semiconductor device according to claim 1, wherein the semiconductor substrate does not include a lifetime control region.

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