Multi-mode power management integrated circuit

Abstract

A multi-mode power management integrated circuit (PMIC) is provided. Specifically, the multi-mode PMIC can be provided in a wireless communication device to generate an output voltage, which can be an envelope tracking (ET) voltage or an average power tracking (APT) voltage, for amplifying a radio frequency (RF) signal. According to an embodiment disclosed herein, the PMIC replaces a conventional all-analog control circuit with a multi-input hybrid control circuit that includes both analog and digital circuitries. By incorporating the digital circuitry to perform certain processing tasks digitally, it is possible to improve efficiency and reduce the footprint of the multi-mode PMIC.

Description

MULTI-MODE POWER MANAGEMENT INTEGRATED CIRCUITRelated Applications

[0001] This application claims the benefit of U.S. provisional patent application serial number 63 / 634,598, filed on April 16, 2024, the disclosure of which is hereby incorporated herein by reference in its entirety.Field of the Disclosure

[0002] The technology of the disclosure relates generally to a power management integrated circuit (PMIC) for generating an envelope tracking (ET) and / or an average power tracking (APT) voltage.Background

[0003] Fifth generation (5G) new radio (NR) (5G-NR) has been widely regarded as the next generation of wireless communication technology beyond the current third generation (3G) and fourth generation (4G) technologies. In this regard, a wireless communication device capable of supporting the 5G / 5G-NR wireless communication technology is expected to achieve higher data rates, improved coverage range, enhanced signaling efficiency, and reduced latency across a wide range of radio frequency (RF) bands.

[0004] In a 5G / 5G-NR system, the RF signal may be transmitted over a millimeter wave spectrum where the RF signal can be degraded and / or distorted at a receiver due to interferences and propagation losses along an RF transmission path. In this regard, the RF signal must be amplified to a sufficient power level before transmission to help overcome the degradation and distortion. Specifically, in a wireless communication device, a power amplifier circuit is used to amplify the RF signal based on a modulated voltage supplied by a power management integrated circuit (PMIC).

[0005] The RF signal, which is often generated by a transceiver circuit, can be associated with a time-variant power envelope. As such, the PMIC must adapt the modulated voltage in a timely manner to best match the time-variant powerenvelope at the power amplifier circuit to help prevent potential distortion (e.g., ripple and amplitude clipping) in the RF signal and maintain good operating efficiency in the power amplifier circuit. In addition, it is desirable to increase efficiency and reduce the footprint of the PMIC to help improve overall performance of the wireless communication device.

[0006] Embodiments of the disclosure relate to a multi-mode power management integrated circuit (PMIC). Specifically, the multi-mode PMIC can be provided in a wireless communication device to generate an output voltage, which can be an envelope tracking (ET) voltage or an average power tracking (APT) voltage, for amplifying a radio frequency (RF) signal. According to an embodiment disclosed herein, the PMIC replaces a conventional all-analog control circuit with a multi-input hybrid control circuit that includes both analog and digital circuitries. By incorporating the digital circuitry to perform certain processing tasks digitally, it is possible to improve efficiency and reduce the footprint of the multi-mode PMIC.

[0007] In one aspect, a multi-mode PMIC is provided. The multi-mode PMIC includes a multi-mode voltage circuit. The multi-mode voltage circuit is configured to operate in multiple modes. The multi-mode voltage circuit includes a voltage generation circuit. The voltage generation circuit is configured to generate an output voltage in each of the multiple modes based on a target voltage and a low-frequency current. The voltage generation circuit is also configured to generate multiple feedback signals corresponding to the output voltage in each of the multiple operation modes. The multi-mode voltage circuit also includes a current generation circuit. The current generation circuit is configured to generate a low-frequency voltage based on a duty cycle signal and induce the low-frequency current from the low-frequency voltage. The multimode PMIC also includes a first controller and a second controller. The first controller and the second controller are each configured to derive the duty cycle signal from an analog target of the low-frequency voltage in response toreceiving a respective control signal. The multi-mode PMIC also includes a multi-input hybrid control circuit. The multi-input hybrid control circuit is configured to determine the analog target of the low-frequency voltage based on the target voltage and the multiple feedback signals.

[0008] In another aspect, a wireless device is provided. The wireless device includes a multi-mode PMIC. The multi-mode PMIC includes a multi-mode voltage circuit. The multi-mode voltage circuit is configured to operate in multiple operation modes. The multi-mode voltage circuit includes a voltage generation circuit. The voltage generation circuit is configured to generate an output voltage in each of the multiple operation modes based on a target voltage and a low- frequency current. The voltage generation circuit is also configured to generate multiple feedback signals corresponding to the output voltage in each of the multiple operation modes. The multi-mode voltage circuit also includes a current generation circuit. The current generation circuit is configured to generate a low- frequency voltage based on a duty cycle signal and induce the low-frequency current from the low-frequency voltage. The multi-mode PMIC also includes a first controller and a second controller. The first controller and the second controller are each configured to derive the duty cycle signal from an analog target of the low-frequency voltage in response to receiving a respective control signal. The multi-mode PMIC also includes a multi-input hybrid control circuit. The multi-input hybrid control circuit is configured to determine the analog target of the low-frequency voltage based on the target voltage and the multiple feedback signals.

[0009] In another aspect, a method for operating a multi-mode PMIC is provided. The method includes generating an output voltage in each of multiple operation modes based on a target voltage and a low-frequency current. The method also includes generating multiple feedback signals corresponding to the output voltage in each of the multiple operation modes. The method also includes generating a low-frequency voltage based on a duty cycle signal and inducing the low-frequency current from the low-frequency voltage. The method also includes deriving the duty cycle signal from an analog target of the low-frequency voltage in response to receiving a respective control signal. The method also includes determining the analog target of the low-frequency voltage based on the target voltage and the multiple feedback signals.

[0010] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.Brief Description of the Drawing Figures

[0011] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0012] Figure 1 is a schematic diagram of an exemplary multi-mode power management integrated circuit (PMIC) wherein a multi-input hybrid control circuit can be configured according to embodiments of the present disclosure to cause a multi-mode voltage circuit to generate an output voltage in multiple operation modes;

[0013] Figure 2 is a schematic diagram providing an exemplary illustration of the multi-input hybrid control circuit in Figure 1 ;

[0014] Figure 3 is a schematic diagram of an exemplary analog loop control circuit that can be provided in the multi-input hybrid control circuit of Figure 2;

[0015] Figure 4 is a schematic diagram of an exemplary hybrid loop control circuit that can be provided in the multi-input hybrid control circuit of Figure 2;

[0016] Figure 5 is a diagram illustrating some exemplary operating scenarios of the hybrid loop control circuit of Figure 4;

[0017] Figure 6 is a schematic diagram of an exemplary communication device wherein the multi-mode PMIC of Figure 1 can be provided; and

[0018] Figure 7 is a flowchart of an exemplary process for operating the multimode PMIC of Figure 1 .Detailed Description

[0019] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0020] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an elementis referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0022] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0025] Embodiments of the disclosure relate to a multi-mode power management integrated circuit (PMIC). Specifically, the multi-mode PMIC can be provided in a wireless communication device to generate an output voltage, which can be an envelope tracking (ET) voltage or an average power tracking (APT) voltage, for amplifying a radio frequency (RF) signal. According to an embodiment disclosed herein, the PMIC replaces a conventional all-analog control circuit with a multi-input hybrid control circuit that includes both analogand digital circuitries. By incorporating the digital circuitry to perform certain processing tasks digitally, it is possible to improve efficiency and reduce the footprint of the multi-mode PMIC.

[0026] In this regard, Figure 1 is a schematic diagram of an exemplary multimode PMIC 10 wherein a multi-input hybrid control circuit 12 can be configured according to embodiments of the present disclosure to cause a multi-mode voltage circuit 14 to generate an output voltage Vcc in multiple operation modes. Herein, the multi-mode PMIC 10 can be configured to operate in a first operating mode to generate the output voltage Vcc as an APT voltage, or in a second operating mode to accelerate adaptation of the APT voltage within a defined temporal interval (e.g., in between consecutive symbols), or in a third operation mode to generate the output Vcc as an ET voltage, or in a fourth operation mode to generate the ET voltage with a lower modulation bandwidth (e.g., < 50 MHz). As discussed in detail below, the multi-input hybrid control circuit 12 is configured to effectively control the multi-mode PMIC 10 under all of the operation modes.

[0027] Herein, the multi-mode voltage circuit 14 includes a current generation circuit 16 and a voltage generation circuit 18. The current generation circuit 16 includes a multi-level charge pump (MCP) 20 and a power inductor Lp. The MCP 20 is configured to generate a low-frequency voltage VDC, such as a direct- current (DC) voltage, as a function of a battery voltage VBAT. The power inductor Lp, which is coupled in series to the MCP 20, will induce a low-frequency current IDC (e.g., a DC current) based on the low-frequency voltage VDC.

[0028] In a non-limiting example, the MCP 20 is a buck-boost voltage converter that can operate in a buck mode to generate the low-frequency voltage at O XVBAT (a.k.a. 0 V) or 1 XVBAT, or in a boost mode to generate the low- frequency voltage at 2XVBAT. More specifically, the MCP 20 can toggle between O XVBAT, 1 XVBAT, and / or 2XVBAT (e.g., 1 0%@0 XVBAT, 30%@1 XVBAT, and 60%@2XVBAT) in accordance with a duty cycle signal 22 to thereby generate the low-frequency voltage VDC at a desired target value VTGT-DC-A. Hereinafter, the desired target value VTGT-DC-A is referred to interchangeably as an analog target VTGT-DC-A of the low-frequency voltage VDC. Accordingly, the power inductor Lpwill induce the low-frequency current IDC based on the analog target VTGT-DC-A of the low-frequency voltage VDC.

[0029] Herein, the voltage generation circuit 18 is configured to generate the output voltage Vcc in each of the first, second, third, and fourth operation modes. Specifically, the voltage generation circuit 18 includes a voltage amplifier 24 and an offset capacitor GOFF. The voltage amplifier 24 is configured to generate an initial output voltage VAMP based on a target voltage VTGT, which is typically provided by a transceiver circuit (not shown), in conjunction with a feedback voltage VCCFB (a.k.a. “first feedback voltage”) of the output voltage Vcc.

[0030] The offset capacitor COFF is coupled between the voltage amplifier 24 and a voltage output 26. The offset capacitor COFF is configured to raise the initial output voltage VAMP by an offset voltage VOFF to thereby generate the output voltage Vcc (Vcc = VAMP + VOFF) at the voltage output 26.

[0031] In an embodiment, in the first and second operating modes, where the voltage generation circuit 18 is configured to generate the output voltage Vcc as the APT voltage, the low-frequency current IDC is so generated to maintain the offset voltage VOFF at a constant level (e.g., 0.8 V). In contrast, in the third and fourth operating modes, where the voltage generation circuit 18 is configured to generate the output voltage Vcc as the ET voltage, the offset voltage VOFF will be modulated in accordance with an offset target voltage VTGT-OFF to ensure that the output voltage Vcc is aligned with the target voltage VTGT. The exact value of the offset voltage VOFF may be determined inside or outside the multi-mode PMIC 10 by means that are outside the scope of the present disclosure.

[0032] More specifically, in the third operation mode, the output voltage Vcc may be associated with a higher modulation bandwidth (e.g., > 50 MHz), whereas in the fourth operation mode, the output voltage Vcc may be associated with a lower modulation bandwidth (e.g., < 50 MHz). Herein, the modulation bandwidth of the output voltage Vcc is determined by a peak-to-average range of the output voltage Vcc. In this regard, in the third operation mode, the offset voltage VOFF may need to change rapidly to keep up with the larger peak-to- average swing of the output voltage Vcc. As such, the voltage amplifier 24 willsupplement the low-frequency current IDC with a high-frequency current IAC (e.g., an alternating current) to drive the offset voltage VOFF quickly toward the offset target voltage VTGT-OFF. In an embodiment, the voltage amplifier 24 is configured to provide a sensed current ISENSE to indicate an amount of the high-frequency current IAC flowing through the offset capacitor COFF in the third operation mode.

[0033] In contrast, in the fourth operation mode, the offset voltage VOFF will not change as rapidly as in the third operation mode. As such, the low-frequency current IDC may be sufficient to drive the offset voltage VOFF toward the offset target voltage VTGT-OFF. In the meantime, the voltage amplifier 24 may supplement the low-frequency current IDC with a smaller amount of the high- frequency current IAC or not at all, as indicated by the sensed current ISENSE.

[0034] The multi-mode PMIC 10 includes a first controller 28 and a second controller 30. In a non-limiting example, the first controller 28 can be a pulsewidth modulation (PWM) controller and the second controller 30 can be a bangbang controller (BBC). The first controller 28 is activated by a control signal 32 during the first, second, and third operation modes, whereas the second controller 30 is activated by the control signal 32 in the fourth operation mode. When activated, the first controller 28 and the second controller 30 are each configured to determine the duty cycle signal 22 from the analog target VTGT-DC-A of the low-frequency voltage VDC. Specifically, the first controller 28 may determine the duty cycle signal 22 solely from the analog target VTGT-DC-A, whereas the second controller 30 may further factor a sensed voltage VSENSE into the determination of the duty cycle signal 22. In an embodiment, the sensed voltage VSENSE may be generated from the sensed current ISENSE by a current-to- voltage (l- V) converter 34.

[0035] According to an embodiment of the present disclosure, the multi-input hybrid control circuit 12 receives the target voltage VTGT, the offset target voltage VTGT-OFF, the first feedback voltage VCCFB, the sensed current ISENSE, and a feedback voltage VAMPFB (a.k.a. “second feedback voltage”) of the initial output voltage VAMP. AS described below in Figures 2-5, the multi-input hybrid controlcircuit 12 is configured to determine the analog target VTGT-DC-A using a hybrid of analog and digital circuitries.

[0036] Figure 2 is a schematic diagram of the multi-input hybrid control circuit 12 in Figure 1 configured according to an embodiment of the present disclosure. Common elements between Figures 1 and 2 are shown therein with common element numbers and will not be re-described herein.

[0037] In an embodiment, the multi-input hybrid control circuit 12 includes a differential circuit 36, a loop control circuit 38, a digital processing circuit 40, a digital combiner 42, and a dig ital-to-analog converter (DAC) 44. The loop control circuit 38, the digital processing circuit 40, and the DAC 44 are all driven by a same clock signal CLK, which may be generated by an oscillator (not shown) located inside or outside the multi-input hybrid control circuit 12. The differential circuit 36 may include a differential amplifier 46 and a voltage-to-current (V->l) converter 48 (e.g., a transconductor). Specifically, the differential amplifier 46 is configured to determine the offset voltage VOFF across the offset capacitor COFF by subtracting the second feedback voltage VAMPFB from the first feedback voltage VCCFB (VOFF = VCCFB - VAMPFB). The voltage-to-current converter 48, in turn, converts the determined offset voltage VOFF into an offset current IOFF. Notably, the offset current IOFF determined herein reflects a total current flowing through the offset capacitor COFF. AS described earlier, the offset current IOFF may be equivalent to the low-frequency current IDO in the first and second operation modes and may further include the high-frequency current IAC in the third and fourth operation modes. The loop control circuit 38 is configured to generate an integrated digital voltage VI T-D based on the determined offset current IOFF and the sensed current ISENSE.

[0038] The digital processing circuit 40 is configured to digitally process the integrated digital voltage VINT-D to generate a processed integrated digital voltage VPINT-D. In a non-limiting example, the digital processing circuit 40 may add required zeros and / or poles into the integrated digital voltage VI T-D and perform digital integration and / or scaling as needed. The benefit of adding the zeros and / or poles digitally, as opposed to doing so in analog, can help reduce thefootprint of the multi-mode PMIC 10. Moreover, since digital processing is more predictable than analog processing, it is possible to create zeros and / or poles at more precise locations.

[0039] The digital combiner 42 is configured to combine the processed integrated digital voltage VPINT-D with a digital target VTGT-OFF-D of the offset voltage VOFF to thereby generate a digital target VTGT-DC-D of the low-frequency voltage VDC. In an embodiment, the digital target VTGT-OFF-D of the offset voltage VOFF may be generated from the offset target voltage VTGT-OFF via analog-to- digital conversion. The DAC 44, in turn, converts the digital target VTGT-DC-D of the low-frequency voltage VDC into the analog target VTGT-DC-A of the low- frequency voltage VDC and provides the analog target VTGT-DC-A to the first controller 28 and / or the second controller 30 in Figure 1 .

[0040] The multi-input hybrid control circuit 12 may be configured to further include a digital assistant circuit 50. In an embodiment, the digital assistant circuit 50 may be activated in the second operation mode where the output voltage Vcc is an APT voltage that needs to change very rapidly between two adjacent orthogonal frequency division multiplexing (OFDM) symbols. When activated, the digital assistant circuit 50 can generate a digital assistant voltage VASST-D based on the target voltage VTGT and the analog target VTGT-OFF of the offset voltage VOFF. The digital combiner 42, accordingly, adds the assistant voltage VASST-D to the digital target VTGT-DC-D of the low-frequency voltage VDC to help speed up transition of the output voltage Vcc.

[0041] In one embodiment, the loop control circuit 38 may be provided as an analog loop control circuit. In this regard, Figure 3 is a schematic diagram of an exemplary analog loop control circuit 38A that may be provided in the multi-input hybrid control circuit 12 of Figure 2 to function as the loop control circuit 38. Common elements between Figures 2 and 3 are shown therein with common element numbers and will not be re-described herein.

[0042] Herein, the analog loop control circuit 38A includes an analog integrator 52 and an analog-to-digital converter (ADC) 54. The analog integrator 52 includes an operational amplifier 56 and a capacitor C (e.g., 1 pF). Thecapacitor C is coupled between a negative input (denoted as “-“) and an output 58 of the operational amplifier 56. The negative input of the operational amplifier 56 receives a composite current ICOMP that includes the offset current IOFF and the sensed current ISE SE, whereas a positive input (denoted as “+”) of the operational amplifier 56 receives an offset target current ITGT-OFF. In a nonlimiting example, the offset target current ITGT-OFF can be derived from the offset target voltage VTGT-OFF using, for example, a transconductor (not shown). The operational amplifier 56 is configured to output a voltage across the capacitor C as an integrated analog voltage VINT-A. The ADC 54 is driven by the clock signal CLK to convert the integrated analog voltage VINT-A into the integrated digital voltage VINT-D.

[0043] In another embodiment, the loop control circuit 38 may be provided as a hybrid loop control circuit incorporating both analog and digital circuitries. In this regard, Figure 4 is a schematic diagram of an exemplary hybrid loop control circuit 38B that may be provided in the multi-input hybrid control circuit 12 of Figure 2 to function as the loop control circuit 38. Common elements between Figures 2 and 4 are shown therein with common element numbers and will not be re-described herein.

[0044] Herein, the offset current IOFF, the sensed current ISENSE, and the offset target current ITGT-OFF are converged into the composite current ICOMP at a converging node 60. Specifically, the composite current ICOMP can be expressed as in equation (Eq. 1 ) below.ICOMP = ITGT-OFF - IOFF - ISENSE (Eq- 1 )

[0045] The composite current ICOMP charges a capacitor C to thereby provide a cap voltage VCAP to a first comparator 62 and a second comparator 64. The first comparator 62 compares the cap voltage VCAP against a positive threshold voltage Vp and outputs a positive crossing indicator 66P when the cap voltage VCAP is higher than or equal to the positive threshold voltage Vp. In a non-limiting example, the positive crossing indicator 66P can be a digital indicator where abinary “1 ” indicates that the cap voltage VCAP is higher than or equal to the positive threshold voltage Vp and a binary “0” indicates that the cap voltage VCAP is lower than the positive threshold voltage Vp. The second comparator 64 compares the cap voltage VCAP against a negative threshold voltage VN and outputs a negative crossing indicator 66N when the cap voltage VCAP is lower than or equal to the negative threshold voltage VN. In a non-limiting example, the negative crossing indicator 66N can also be a digital indicator where a binary “1 ” indicates that the cap voltage VCAP is lower than or equal to the negative threshold voltage VP and a binary “0” indicates that the cap voltage VCAP is higher than the negative threshold voltage Vp.

[0046] The hybrid loop control circuit 38B includes a digital processing domain 68. The digital processing domain 68 includes a crossing detector 70, a digital counter 72, and a digital post-processor 74. The crossing detector 70 is configured to cause the digital counter 72 to increase by one least-significant bit (LSB) in response to receiving the positive crossing indicator 66P and decrease by one LSB in response to receiving the negative crossing indicator 66N.

[0047] The digital post-processor 74 includes a multiplier circuit 76 and, optionally, an adder circuit 78. The multiplier circuit 76 multiplies a counted number (N) stored in the digital counter 72 by a factor of 2F 1. Herein, F represents a number of binary bits in a digital word that stores the integrated digital voltage VINT-D. The adder circuit 78, when present, may add a fine-tuning voltage term AVFINE to the output (N*2F1) of the multiplier circuit 76 to thereby generate the integrated digital voltage VINT-D.

[0048] In an embodiment, the fine-tuning voltage term AVFINE may be generated by an ADC 80 based on the cap voltage VCAP and the clock signal CLK. In a non-limiting example, the fine-tuning voltage term AVFINE may be defined by equation (Eq. 2) below.AVFINE = 2 * VLSB / 2F(Eq- 2)

[0049] In the equation (Eq. 2), VLSB represents a bitwise voltage of the LSB. Thus, the fine-tuning voltage term VFINE is intended to provide a finer granularity in the LSB.

[0050] In an embodiment, the crossing detector 70 is further configured to cause a decrease in the composite current ICOMP in response to receiving the positive crossing indicator 66P to thereby reduce the cap voltage VCAP to below the positive threshold voltage Vp. The crossing detector 70 is also configured to cause an increase in the composite current ICOMP in response to receiving the negative crossing indicator 66N to thereby raise the cap voltage VCAP to above the negative threshold voltage VN.

[0051] Specifically, the hybrid loop control circuit 38B can further include a current source 82 that is coupled to the converging node 60 by a switch 84. The current source 82 is configured to generate an adjustment current ILSB as defined in equation (Eq. 3) below.ILSB = ± VLSB * CCAP / TCLK (Eq. 3)

[0052] In the equation (Eq. 3), CCAP represents a capacitance (e.g., 1 pF) of the capacitor C and TCLK represents one clock cycle of the clock signal CLK. The sign of the adjustment current ILSB is determined by a sign indicator & = ± 1 . In an embodiment, the crossing detector 70 provides the sign indicator & = -1 and closes the switch 84 in response to receiving the positive crossing indicator 66P. Accordingly, the current source 82 provides a negative adjustment current ILSB to be subtracted from the composite current ICO P. In contrast, the crossing detector 70 provides the sign indicator & = +1 and closes the switch 84 in response to receiving the negative crossing indicator 66N. Accordingly, the current source 82 provides a positive adjustment current ILSB to be added to the composite current ICOMP. Thus, by decreasing or increasing the composite current ICOMP, the cap voltage VCAP can be adjusted to stay below the positive threshold voltage Vp and above the negative threshold voltage VN.

[0053] Figure 5 is a diagram providing an exemplary illustration as to how the cap voltage VCAP can be adjusted in the hybrid loop control circuit 38B of Figure 4. Common elements between Figures 4 and 5 are shown therein with common element numbers and will not be re-described herein.

[0054] In clock cycle TCLKI , the cap voltage VCAP reaches the positive threshold voltage Vp. Accordingly, the crossing detector 70 provides the sign indicator & = -1 to the current source 82 to generate the negative adjustment current ILSB to thereby reduce the cap voltage VCA to below the positive threshold voltage VP. In clock cycle TCLKP, the cap voltage VCAP once again reaches the positive threshold voltage Vp. Accordingly, the crossing detector 70 once again provides the sign indicator & = -1 to the current source 82 to generate the negative adjustment current ILSB to thereby reduce the cap voltage VCAP to below the positive threshold voltage Vp.

[0055] In clock cycle TCLKS, the cap voltage VCAP reaches the negative threshold voltage VN. Accordingly, the crossing detector 70 provides the sign indicator & = +1 to the current source 82 to generate the positive adjustment current ILSB to thereby raise the cap voltage VCAP to above the negative threshold voltage VN. In clock cycle TCLK4, the cap voltage VCAP once again reaches the negative threshold voltage VN. Accordingly, the crossing detector 70 once again provides the sign indicator & = +1 to the current source 82 to generate the positive adjustment current ILSB to thereby raise the cap voltage VCAP to above the negative threshold voltage VN.

[0056] In clock cycle TCLKS, the cap voltage VCAP again reaches the positive threshold voltage Vp. Accordingly, the crossing detector 70 provides the sign indicator & = -1 to the current source 82 to generate the negative adjustment current ILSB to thereby reduce the cap voltage VCAP to below the positive threshold voltage Vp. Herein, the hybrid loop control circuit 38B is configured to repeat the above-described steps in all subsequent clock cycles to maintain the cap voltage VCAP in between the positive threshold voltage Vp and the negative threshold voltage VN.

[0057] The multi-mode PMIC 10 of Figure 1 can be provided in a communication device to support the embodiments described above. In this regard, Figure 6 is a schematic diagram of an exemplary communication device 100 wherein the multi-mode PMIC 10 of Figure 1 can be provided.

[0058] Herein, the communication device 100 can be any type of communication device, such as mobile terminal, smart watch, tablet, computer, navigation device, access point, base station (e.g., eNB, gNB), and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, Ultrawideband (UWB), and near field communications. The communication device 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 110, multiple antennas 1 12, and user interface circuitry 1 14. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 112 and through the antenna switching circuitry 110 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0059] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0060] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 1 12 through the antenna switching circuitry 110. The multiple antennas 1 12 and the replicated transmit and receive circuitries 106, 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0061] In an embodiment, the multi-mode PMIC 10 may be provided in between the transmit circuitry 106 and the antenna switching circuitry 110. In this regard, the transmit circuitry 106 may be configured to provide the target voltage VTGT and the control signal 32 to the multi-mode PMIC 10.

[0062] In an embodiment, the multi-mode PMIC 10 of Figure 1 can be operated in accordance with a process. In this regard, Figure 7 is a flowchart of an exemplary process 200 for operating the multi-mode PMIC 10 of Figure 1.

[0063] Herein, the process 200 includes generating the output voltage Vcc in each of the operation modes based on the target voltage VTGT and the low- frequency current IDC (step 202). The process 200 also includes generating the feedback signals VAMPFB, VCCFB, ISE SE corresponding to the output voltage Vcc in each of the operation modes (step 204). The process 200 also includes generating the low-frequency voltage VDC based on the duty cycle signal 22 and inducing the low-frequency current IDC from the low-frequency voltage VDC (step 206). The process 200 also includes deriving the duty cycle signal 22 from the analog target VTGT DC A of the low-frequency voltage VDC in response to receiving the respective control signal 32 (step 208). The process 200 also includes determining the analog target VTGT-DC-A of the low-frequency voltage VDC based on the target voltage VTGT and the feedback signals VAMPFB, VCCFB, ISENSE (step 210).

[0064] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

ClaimsWhat is claimed is:1 . A multi-mode power management integrated circuit (PMIC) comprising: a multi-mode voltage circuit configured to operate in a plurality of operation modes and comprising: a voltage generation circuit configured to: generate an output voltage in each of the plurality of operation modes based on a target voltage and a low- frequency current; and generate a plurality of feedback signals corresponding to the output voltage in each of the plurality of operation modes; and a current generation circuit configured to generate a low-frequency voltage based on a duty cycle signal and induce the low- frequency current from the low-frequency voltage; a first controller and a second controller each configured to derive the duty cycle signal from an analog target of the low-frequency voltage; and a multi-input hybrid control circuit configured to determine the analog target of the low-frequency voltage based on the target voltage and the plurality of feedback signals.

2. The multi-mode PMIC of claim 1 , wherein the voltage generation circuit is further configured to: generate, in a first one of the plurality of operation modes, an average power tracking (APT) voltage as the output voltage; generate, in a second one of the plurality of operation modes, the APT voltage as the output voltage and adapt the output voltage within a defined temporal interval;generate, in a third one of the plurality of operation modes, an envelope tracking (ET) voltage with a first modulation bandwidth as the output voltage; and generate, in a fourth one of the plurality of operation modes, the ET voltage with a second modulation bandwidth lower than the first modulation bandwidth as the output voltage.

3. The multi-mode PMIC of claim 1 , wherein the current generation circuit comprises: a multi-level charge pump (MCP) configured to generate the low- frequency voltage based on the duty cycle signal; and a power inductor configured to induce the low-frequency current from the low-frequency voltage.

4. The multi-mode PMIC of claim 1 , wherein the voltage generation circuit comprises: a voltage amplifier configured to generate an initial output voltage based on the target voltage; and an offset capacitor configured to raise the initial output voltage by an offset voltage to thereby generate the output voltage.

5. The multi-mode PMIC of claim 4, wherein the voltage generation circuit is further configured to generate the plurality of feedback signals comprising a first feedback voltage indicating the output voltage, a second feedback voltage indicating the initial output voltage, and a sensed current indicating an amount of high-frequency current flowing through the offset capacitor.

6. The multi-mode PMIC of claim 5, wherein the multi-input hybrid control circuit comprises:a differential circuit configured to determine an offset current flowing through the offset capacitor based on the first feedback voltage and the second feedback voltage; a loop control circuit configured to generate an integrated digital voltage based on the determined offset current and the sensed current; a digital processing circuit configured to digitally process the integrated digital voltage to generate a processed integrated digital voltage; a digital combiner configured to combine the processed integrated digital voltage with a digital target of the offset voltage to thereby generate a digital target of the low-frequency voltage; and a digital-to-analog converter (DAC) configured to convert the digital target of the low-frequency voltage into the analog target of the low- frequency voltage.

7. The multi-mode PMIC of claim 6, wherein the multi-input hybrid control circuit further comprises a digital assistant circuit activated in a selected one of the plurality of operation modes to generate a digital assistant voltage and the digital combiner is further configured to add the digital assistant voltage into the digital target of the low-frequency voltage.

8. The multi-mode PMIC of claim 6, wherein the loop control circuit is an analog loop control circuit that comprises: an analog integrator configured to generate an integrated analog voltage based on the determined offset current and the sensed current; and an analog-to-digital converter (ADC) configured to convert the integrated analog voltage into the integrated digital voltage.

9. The multi-mode PMIC of claim 6, wherein the loop control circuit is a hybrid loop control circuit that comprises:a converging node whereat the determined offset current, the sensed current, and an offset target current are merged into a composite current; a capacitor charged by the composite current to provide a cap voltage; a first comparator configured to generate a positive crossing indicator when the cap voltage is higher than or equal to a positive threshold voltage; a second comparator configured to generate a negative crossing indicator when the cap voltage is lower than or equal to a negative threshold voltage; a crossing detector configured to: cause an increment of a digital counter in response to receiving the positive crossing indicator; and cause a decrement of the digital counter in response to receiving the negative crossing indicator; and a digital post-processor comprising a multiplier circuit configured to generate the integrated digital voltage based on a counted number of the digital counter.

10. The multi-mode PMIC of claim 9, wherein: the hybrid loop control circuit further comprises an analog-to-digital converter (ADC) configured to generate a fine-tuning voltage term; and the digital post-processor further comprises an adder circuit configured to add the fine-tuning voltage term into the integrated digital voltage.1 1 . The multi-mode PMIC of claim 9, wherein the crossing detector is further configured to: cause a decrease in the composite current in response to receiving the positive crossing indicator to thereby reduce the cap voltage to below the positive threshold voltage; andcause an increase in the composite current in response to receiving the negative crossing indicator to thereby raise the cap voltage to above the negative threshold voltage.

12. A wireless device comprising a multi-mode power management integrated circuit (PMIC), the multi-mode PMIC comprises: a multi-mode voltage circuit configured to operate in a plurality of operation modes and comprising: a voltage generation circuit configured to: generate an output voltage in each of the plurality of operation modes based on a target voltage and a low- frequency current; and generate a plurality of feedback signals corresponding to the output voltage in each of the plurality of operation modes; and a current generation circuit configured to generate a low-frequency voltage based on a duty cycle signal and induce the low- frequency current from the low-frequency voltage; a first controller and a second controller each configured to derive the duty cycle signal from an analog target of the low-frequency voltage in response to receiving a control signal; and a multi-input hybrid control circuit configured to determine the analog target of the low-frequency voltage based on the target voltage and the plurality of feedback signals.

13. The wireless device of claim 12, further comprising transmit circuitry configured to generate the target voltage and the control signal.

14. The wireless device of claim 12, wherein the voltage generation circuit is further configured to:generate, in a first one of the plurality of operation modes, an average power tracking (APT) voltage as the output voltage; generate, in a second one of the plurality of operation modes, the APT voltage as the output voltage and adapt the output voltage within a defined temporal interval; generate, in a third one of the plurality of operation modes, an envelope tracking (ET) voltage with a first modulation bandwidth as the output voltage; and generate, in a fourth one of the plurality of operation modes, the ET voltage with a second modulation bandwidth lower than the first modulation bandwidth as the output voltage.

15. The wireless device of claim 12, wherein: the current generation circuit comprises: a multi-level charge pump (MCP) configured to generate the low- frequency voltage based on the duty cycle signal; and a power inductor configured to induce the low-frequency current from the low-frequency voltage; and the voltage generation circuit comprises: a voltage amplifier configured to generate an initial output voltage based on the target voltage; and an offset capacitor configured to raise the initial output voltage by an offset voltage to thereby generate the output voltage.

16. The wireless device of claim 15, wherein the voltage generation circuit is further configured to generate the plurality of feedback signals comprising a first feedback voltage indicating the output voltage, a second feedback voltage indicating the initial output voltage, and a sensed current indicating an amount of high-frequency current flowing through the offset capacitor.

17. A method for operating a multi-mode power management integrated circuit (PMIC) comprising: generating an output voltage in each of a plurality of operation modes based on a target voltage and a low-frequency current; generating a plurality of feedback signals corresponding to the output voltage in each of the plurality of operation modes; generating a low-frequency voltage based on a duty cycle signal and inducing the low-frequency current from the low-frequency voltage; deriving the duty cycle signal from an analog target of the low-frequency voltage in response to receiving a respective control signal; and determining the analog target of the low-frequency voltage based on the target voltage and the plurality of feedback signals.

18. The method of claim 17, further comprising: generating, in a first one of the plurality of operation modes, an average power tracking (APT) voltage as the output voltage; generating, in a second one of the plurality of operation modes, the APT voltage as the output voltage and adapting the output voltage within a defined temporal interval; generating, in a third one of the plurality of operation modes, an envelope tracking (ET) voltage with a first modulation bandwidth as the output voltage; and generating, in a fourth one of the plurality of operation modes, the ET voltage with a second modulation bandwidth lower than the first modulation bandwidth as the output voltage.

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