Piezoelectric stack structure and manufacturing method

Abstract

The present application relates to the technical field of semiconductor processes, and in particular to a piezoelectric stack structure and a manufacturing method therefor. The piezoelectric stack structure comprises a substrate, and further comprises a deflection limiting layer, a piezoelectric layer and a structural layer which are sequentially stacked on the front surface of the substrate, the piezoelectric layer bending and deforming towards the substrate, and the structural layer bending and deforming towards the piezoelectric layer. The manufacturing method comprises the steps of: growing a deflection limiting layer on the front surface of a substrate layer; growing a piezoelectric layer on the surface of the deflection limiting layer, under the action of stress, the piezoelectric layer bending towards the substrate, and the front surface of the substrate correspondingly deforming and bending towards the back surface; using a low-temperature PECVD process to deposit a structural layer on the surface of a PZT upper electrode, and the structural layer deforming and bending towards the piezoelectric layer; and patterning the structural layer and the substrate to form a required piezoelectric stack structure. The structural layer grown on the surface of the piezoelectric layer deforms towards the piezoelectric layer, the initial deflection of the stack structure is in a negative direction, the residual stress and the vibration stress of an effective working region are superposed, thereby improving device performance.

Description

A piezoelectric laminate structure and its manufacturing method

[0001] This application claims priority to Chinese Patent Application No. 202410481187.5, filed on April 22, 2024, entitled "A Piezoelectric Stacked Structure and Manufacturing Method", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of piezoelectric stacked structure and manufacturing technology in semiconductor processes, and particularly to a piezoelectric stacked structure and manufacturing method. Background Technology

[0003] Currently, as the core of piezoelectric MEMS sensors, piezoelectric stacked structures often possess residual stress caused by the difference in the thermal expansion coefficients of each layer. These residual stresses, resulting from high-temperature processing, cause the piezoelectric stacked structure to deform and bend in a certain direction. After bending deformation, the position of the cross-section of the piezoelectric stacked structure will change. The deformation of the cross-section in the displacement perpendicular to the axial direction of the stacked structure is called deflection, as shown in Figure 1.

[0004] Typically, in the design and fabrication of piezoelectric MEMS sensors, it is desirable for the piezoelectric stack structure to be sufficiently flat, i.e., with extremely low positive or negative deflection. However, due to the inherent difference in the thermal expansion coefficients of the stack structure, a certain degree of deflection is inevitable. Although the deflection of the piezoelectric stack structure is undesirable in most MEMS devices, it can be utilized in vibration-detecting piezoelectric MEMS sensors, such as microphones, ultrasonic sensors, and acoustic vibration sensors. As shown in Figure 2, the deflection caused by residual stress Se is parabolic, while the contribution of the stress Sb generated by vibration on the stack structure to the deflection is approximately linear. Therefore, the combined stress S increases due to the superposition of Se and Sb on the negative deflection side, while on the positive deflection side, Se and Sb cancel each other out. Therefore, in engineering, it is desirable for the final deflection of the piezoelectric stack to be within the range where the residual stress and vibration stress increase superimposed.

[0005] In piezoelectric stack structures, the structural layer is often several to tens of times thicker than the piezoelectric layer, thus the neutral plane of the piezoelectric stack is located in the structural layer. The braking mechanism of piezoelectric vibrations indicates that the effective working region of the piezoelectric stack is from the neutral plane to the piezoelectric layer. In practice, piezoelectric stacks always have initial deflection, and different deflections have different effects. When the deflection direction is towards the piezoelectric layer (i.e., the piezoelectric layer bulges outward), the residual stress and vibration stress in the region from the neutral plane to the piezoelectric layer are superimposed, while the stress from the neutral plane to the structural layer cancels out. In this case, the stress in the effective working region of the piezoelectric stack is superimposed, allowing the diaphragm to generate higher sensitivity, which is beneficial for improving device performance. However, when the deflection direction of the piezoelectric stack is towards the structural layer (i.e., the structural layer bulges outward), the stress situation is exactly the opposite, which is detrimental to improving device performance.

[0006] Among numerous piezoelectric materials, lead zirconate titanate (PZT) piezoelectric materials, through magnetron sputtering growth, can achieve high film quality, high piezoelectric coefficient, high stability, and high reliability on substrates. However, the PZT film growth process generates significant residual stress. This residual stress manifests as tensile stress and is much greater than the initial deflection of the substrate. On traditional silicon wafers or SOI wafers, after the PZT film layer (piezoelectric layer) is grown, the stacked structure exhibits a large negative directional deflection, meaning the deflection direction of the piezoelectric stack points towards the structural layer direction (as shown in Figure 3A). Therefore, conventional processes struggle to obtain piezoelectric stacks with the deflection direction pointing towards the piezoelectric layer.

[0007] In summary, this application proposes a piezoelectric laminate structure and its manufacturing method to solve the aforementioned problems.

[0008] Application content

[0009] The purpose of this application is to address the problems raised in the background art by proposing a piezoelectric stack structure and its manufacturing process. By utilizing the negative perturbation caused by the residual stress of the piezoelectric layer, the structural layer grown on the surface of the piezoelectric layer is bent and deformed in the direction of the piezoelectric layer, so that the perturbation of the piezoelectric stack structure is negative, and the residual stress and vibration stress in the effective working area are superimposed to improve the device performance.

[0010] This application provides a piezoelectric laminate structure and a manufacturing method thereof.

[0011] A first aspect: a piezoelectric stacked structure, comprising a substrate having a front side and a back side, characterized in that: it further comprises a deflection limiting layer, a piezoelectric layer and a structural layer sequentially stacked on the front side of the substrate, wherein the piezoelectric layer bends and deforms toward the substrate, and the structural layer bends and deforms toward the piezoelectric layer, such that the initial deflection of the piezoelectric stacked structure is in the negative direction, and the residual stress and vibration stress in the effective working area of ​​the piezoelectric stacked structure are superimposed.

[0012] As a further embodiment of this application, a back cavity is formed on the back side of the substrate.

[0013] As a further aspect of this application, the substrate is a silicon wafer substrate.

[0014] As a further embodiment of this application, the piezoelectric layer includes a PZT lower electrode, a PZT thin film, and a PZT upper electrode stacked sequentially, wherein the deflection direction of the PZT thin film is negative.

[0015] As a further aspect of this application, the thickness of the PZT film is 0.1-5 μm.

[0016] As a further aspect of this application, the thickness of the structural layer is greater than the thickness of the PZT film.

[0017] As a further aspect of this application, the surfaces of the lower PZT electrode and the upper PZT electrode are respectively grown with metal layers that facilitate the extraction of the electrodes.

[0018] As a further aspect of this application, the longitudinal projected area of ​​the PZT upper electrode is smaller than the longitudinal projected area of ​​the PZT thin film, and the structural layer is disposed on the surface of the PZT upper electrode and extends to the surface of the PZT thin film.

[0019] As a further aspect of this application, the material of the deflection limiting layer is silicon oxide, and the thickness of the deflection limiting layer is 10-500 nm.

[0020] As a further aspect of this application, the material of the structural layer is silicon oxide and / or silicon nitride, and the thickness of the structural layer is 0.5-25 μm.

[0021] As a further embodiment of this application, the structural layer is a two-layer or three-layer structure composed of silicon oxide and silicon nitride stacked alternately.

[0022] Second aspect: A method for manufacturing a piezoelectric laminate, comprising the following steps:

[0023] S1. A deflection confinement layer is grown on the front side of the substrate by a thermal oxidation process;

[0024] S2. A piezoelectric layer is sputtered and grown on the deflection confinement layer. The piezoelectric layer bends and deforms towards the substrate due to its own stress.

[0025] S3. Pattern the piezoelectric layer;

[0026] S4. A structural layer is grown on the patterned piezoelectric layer, and the structural layer is bent and deformed in the direction of the piezoelectric layer.

[0027] S5. Graphicalize the structural layer;

[0028] S6. Etch the back side of the substrate to form a back cavity;

[0029] The piezoelectric layer bends and deforms towards the substrate, and the structural layer bends and deforms towards the piezoelectric layer, so that the initial deflection of the piezoelectric stack structure is in the negative direction, and the residual stress and vibration stress in the effective working area of ​​the piezoelectric stack structure are superimposed.

[0030] As a further aspect of the manufacturing method of this application, the step S2, which involves sputtering a piezoelectric layer onto the deflection confinement layer, includes:

[0031] S21. A PZT lower electrode is sputtered and grown on the deflection confinement layer;

[0032] S22. A PZT thin film is sputtered and grown on the PZT lower electrode. The PZT thin film bends and deforms towards the PZT lower electrode due to its own stress.

[0033] S23. A PZT top electrode is sputtered and grown on the PZT thin film. The PZT top electrode bends and deforms along the bending direction of the PZT thin film.

[0034] As a further aspect of the manufacturing method of this application, the patterning of the piezoelectric layer in step S3 includes:

[0035] S31, IBE etching is used to pattern the upper electrode of PZT;

[0036] S32 uses wet etching to etch the PZT thin film, exposing a portion of the PZT lower electrode;

[0037] S33 uses IBE etching of the PZT lower electrode to pattern the PZT lower electrode, thereby completing the patterning of the piezoelectric layer.

[0038] As a further aspect of the manufacturing method of this application, it also includes:

[0039] S34, a metal layer is grown on the surface of the piezoelectric layer, and the metal layer covers the exposed areas of the piezoelectric layer and the deflection confinement layer;

[0040] S35, patterned metal layer, retains part of the metal layer on the surface of the PZT lower electrode and the PZT upper electrode.

[0041] As a further embodiment of the manufacturing method of this application, the structural layer is generated using a low-temperature PECVD process, and the structural layer is a two-layer or three-layer structure composed of silicon oxide and silicon nitride stacked alternately.

[0042] As a further embodiment of the manufacturing method of this application, the stress direction and magnitude of the structural layer are controlled by adjusting the temperature, time, power and cavity pressure of the low-temperature PECVD process.

[0043] The beneficial effects of this application are:

[0044] 1. This application uses PECVD process to set a structural layer on the piezoelectric layer. The piezoelectric layer deforms and bends downward due to its own stress. By adjusting the process parameters of PECVD, the stress direction and magnitude of the structural layer can be adjusted to achieve the purpose of deflecting the structural layer towards the piezoelectric layer. In this application, the structural deflection of each layer from the neutral plane of the stacked structure to the piezoelectric layer is in the negative direction. The residual stress and vibration stress in the effective working area are superimposed, and the diaphragm vibration amplitude is increased, which can generate higher sensitivity during detection and improve device performance.

[0045] 2. The structural layer in this application adopts three material layers. The middle layer plays the main role of controlling the neutral surface, the bottom layer mainly plays the role of improving the adhesion of the middle layer and improving the film quality, and the top layer mainly plays the role of enhancing the tensile strength of the middle layer and improving the stability of the entire structural layer. The three-layer structure is more stable and reliable, and improves the yield rate. Attached Figure Description

[0046] Figure 1 is a schematic diagram of the perturbation generated by the piezoelectric stack;

[0047] Figure 2 is a schematic diagram of the residual stress, vibration stress and resultant stress of the piezoelectric stack;

[0048] Figure 3 is a schematic diagram of the piezoelectric stack structure protruding towards the structural layer and the piezoelectric stack structure protruding towards the piezoelectric layer.

[0049] Figure 4 is a schematic diagram of the piezoelectric stacked structure of this application;

[0050] Figure 5 is a schematic diagram of the piezoelectric stack separation structure of this application;

[0051] Figure 6 is a structural schematic diagram of one embodiment of Figure 5;

[0052] Figure 7 is a cross-sectional view of Figure 5 of this application;

[0053] Figure 8 is a cross-sectional view of Figure 6 of this application;

[0054] Figure 9 is a schematic diagram of the structural layers in the preferred embodiment of this application;

[0055] Figures 10-12 are schematic diagrams of the structural layers in various embodiments of this application;

[0056] Figures 13-18 are schematic diagrams of the process flow in Figure 5;

[0057] Figures 13, 14, and 19-22 are schematic diagrams of the process flow in Figure 6.

[0058] In the attached figures, the following are the reference numerals: 1. Piezoelectric layer; 11. PZT lower electrode; 12. PZT thin film; 13. PZT upper electrode; 2. Structural layer; 3. Substrate; 4. Deflection confinement layer; 5. Metal layer. Detailed Implementation

[0059] The embodiments of this application are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar symbols denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0060] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments.

[0061] Example 1:

[0062] As shown in Figures 4, 5 and 7, the piezoelectric stacked structure proposed in this application includes a substrate 3, a deflection limiting layer 4, a piezoelectric layer 1 and a structural layer 2 stacked sequentially. A back cavity is formed at the bottom of the substrate 3, and the regions of the deflection limiting layer 4, the piezoelectric layer 1 and the structural layer 2 on the longitudinal projection area of ​​the back cavity together form a diaphragm.

[0063] In this embodiment, the piezoelectric layer 1 deforms and bends downwards after growth due to stress. The structural layer 2 is formed on the surface of the piezoelectric layer 1 by PECVD process. By adjusting the parameters of PECVD process, the stress direction and magnitude of the structural layer 2 can be adjusted, causing the structural layer 2 to deform and bend towards the piezoelectric layer 1. The structural deflection of each layer from the neutral plane to the piezoelectric layer is in the negative direction. The residual stress and vibration stress in the effective working area are added together, which can generate higher sensitivity during detection and improve device performance.

[0064] Optionally, substrate 3 is made of silicon wafer, which has essentially zero deflection, thus reducing the impact of substrate 3 on the deflection of each layer during the manufacturing process.

[0065] As shown in Figures 4 and 5, the deflection confinement layer 4 can be grown on the front side of the silicon wafer using a thermal oxidation process. The stress of the thermally oxidized silicon oxide will cause the deflection confinement layer 4 to generate negative deflection. However, the thickness of the deflection confinement layer 4 is much smaller than that of the substrate 3. Therefore, the deflection confinement layer 4 has no effect on the deflection of the entire stacked structure. Simultaneously, because the silicon oxide grown by the thermal oxidation process has high density and high Young's modulus, based on the interface effect, the deflection confinement layer 4 limits the deflection of the piezoelectric layer 1 to prevent it from becoming excessive during growth, thus avoiding adverse effects. Optionally, the thickness of the deflection confinement layer 4 is 10-500 nm.

[0066] As shown in Figures 6, 7 and 8, the piezoelectric layer 1 is formed on the surface of the deflection limiting layer 4. The piezoelectric layer 1 includes a PZT lower electrode 11, a PZT thin film 12 and a PZT upper electrode 13 stacked together, wherein the deflection direction of the PZT thin film 12 is the negative direction.

[0067] Optionally, the materials of the PZT upper electrode 13 and the PZT lower electrode 11 are buffer layers formed by metals such as Pt, Au, and Ti, as well as metal compounds; optionally, the thickness of the PZT thin film 12 is 0.1-5 μm.

[0068] Due to the effect of the deflection limiting layer 4, the deflection of the PZT film 12 is affected by its thickness; that is, different thicknesses of PZT film 12 will result in different deflections in the piezoelectric stack structure. Because the growth process of the PZT film 12 generates significant tensile stress, the grown PZT film 12 exhibits negative deflection, causing the piezoelectric stack structure to bend downwards. The combined effect of the deflection limiting layer 4 and the control of the PZT film 12 growth process parameters ensures that the deflection of the PZT film 12 is controlled within an appropriate orientation, preventing reliability issues such as localized stress concentration, abnormal domain distribution, mechanical fatigue, and material nonlinearity. Simultaneously, it also prevents excessive deflection of the PZT film 12, which could affect the growth of the structural layer 2 formed by low-temperature PECVD, leading to risks such as mechanical and electrical nonlinearity and reducing the linear operating range of the device.

[0069] Optionally, the longitudinal projected area of ​​the PZT upper electrode 13 is smaller than the longitudinal projected area of ​​the PZT thin film 12, and the structural layer 2 is disposed on the surface of the PZT upper electrode 13 and extends to the surface of the PZT thin film 12.

[0070] Optionally, the material of structural layer 2 is silicon oxide and / or silicon nitride.

[0071] Optionally, structural layer 2 is a two-layer structure in which silicon nitride and silicon oxide are stacked in sequence, as shown in Figure 9, with the thickness of silicon oxide being much greater than that of silicon nitride.

[0072] Optionally, structural layer 2 is a two-layer structure in which silicon oxide and silicon nitride are stacked in sequence, as shown in Figure 10, and the thickness of silicon nitride is much greater than the thickness of silicon oxide.

[0073] Optionally, structural layer 2 is a three-layer structure consisting of silicon nitride, silicon oxide, and silicon nitride stacked sequentially, as shown in Figure 11, with the thickness of silicon oxide being much greater than that of silicon nitride.

[0074] Optionally, structural layer 2 is a three-layer structure in which silicon oxide, silicon nitride and silicon oxide are stacked in sequence, as shown in Figure 12, and the thickness of silicon nitride is much greater than the thickness of silicon oxide.

[0075] Silicon nitride and silicon oxide have significantly different Young's moduli, and their stresses also differ considerably under PECVD processes. Therefore, the deflection of the PZT thin film 12 in structural layer 2 can be adjusted by controlling the thickness and process conditions of the three layers. In this three-layer structure, the main structure of structural layer 2 is the intermediate layer, and the device performance is primarily determined by the material and thickness of the intermediate layer. The bottom layer mainly improves the adhesion of the intermediate layer and enhances the film quality, while the top layer mainly enhances the tensile strength of the intermediate layer and improves the stability of structural layer 2. The three-layer structure is more stable and reliable, resulting in a higher yield.

[0076] Optionally, the thickness of the structural layer 2 is 0.5-25 μm, and the thickness of the structural layer 2 is greater than that of the PZT film 12. Optionally, the structural layer 2 is deposited on the surface of the piezoelectric layer 1 using a low-temperature PECVD process.

[0077] Optionally, as shown in Figures 6 and 8, a metal layer 5 is provided on the surface of both the lower PZT electrode 11 and the upper PZT electrode 13, and a groove is formed through the structural layer 2 and the PZT thin film 12 to expose the metal layer 5. The material of the metal layer 5 can be an elemental metal such as aluminum or gold, or an alloy or compound such as an aluminum-copper alloy.

[0078] Example 2:

[0079] A preparation method according to an embodiment of this application includes the following steps:

[0080] Please refer to Figure 13, S1. Prepare substrate 3. Substrate 3 has a front side and a back side. A deflection confinement layer 4 is formed on the front side of substrate 3 by a thermal oxidation process to control the position of the neutral layer and confine the deflection of piezoelectric layer 1. Substrate 3 is a low-deflection silicon wafer; the deflection confinement layer 4 is silicon oxide with a thickness of 10-500 nm. The deflection confinement layer 4 is grown on the front side of substrate 3 by a thermal oxidation process.

[0081] Please refer to Figure 14, S2, where a piezoelectric layer 1 is sputtered onto the surface of the deflection confinement layer 4. The piezoelectric layer 1 includes a PZT lower electrode 11, a PZT thin film 12, and a PZT upper electrode 13. The growth sequence is as follows: a PZT lower electrode 11 is sputtered onto the deflection confinement layer 4; a PZT thin film 12 is sputtered onto the PZT lower electrode 11; and a PZT upper electrode 13 is sputtered onto the PZT thin film 12.

[0082] The thickness of the PZT film 12 is 0.1-5 μm. Before the growth of the PZT film 12, the substrate 3, the deflection confinement layer 4, and the PZT lower electrode 11 of the stacked structure are all in a flat state. After the growth of the PZT film 12, due to stress, the entire stacked structure deforms and bends downward.

[0083] Please refer to Figure 15, S3, where the PZT upper electrode 13, PZT thin film 12, and PZT lower electrode 11 are patterned sequentially. The process is as follows:

[0084] S31, IBE etching is used to pattern the upper electrode 13 of PZT.

[0085] S32, wet etching of PZT film 12 is used to expose a portion of PZT lower electrode 11.

[0086] S33, IBE is used to etch the lower PZT electrode 11 to pattern the lower PZT electrode 11, thereby completing the patterning of the piezoelectric layer 1.

[0087] Optionally, as shown in Figure 19, the process also includes:

[0088] S34, a metal layer 5 is grown on the surface of the piezoelectric layer 1, and the metal layer 5 covers the exposed areas of the piezoelectric layer 1 and the deflection limiting layer 4.

[0089] S35, patterned metal layer 5, retaining part of the metal layer 5 on the surface of PZT thin film 12 and PZT upper electrode 13.

[0090] Referring to Figures 16 and 20, S4, a structural layer 2 is grown on the surface of the piezoelectric layer 1. The structural layer 2 is deposited on the surfaces of the PZT upper electrode 13 and the PZT thin film 12 using a low-temperature PECVD process. After deposition, the structural layer 2 deforms towards the PZT thin film 12, achieving the deflection required for a piezoelectric stack structure and improving its performance. The temperature of this low-temperature PECVD process is less than 290°C.

[0091] The thickness of structural layer 2 is 0.5-25um. The material of structural layer 2 is silicon oxide and / or silicon nitride. Among them, silicon oxide is SiO2 and silicon nitride is Si3N4. Silicon nitride and silicon oxide are grown by PECVD. The stress direction and magnitude are controlled by adjusting the process parameters of low-temperature PECVD, such as temperature, time, power and chamber pressure. At the same time, the stress can be controlled relatively precisely.

[0092] Optionally, structural layer 2 is a two-layer structure in which silicon nitride and silicon oxide are stacked sequentially. Keeping the low-temperature PECVD process conditions unchanged, a two-layer structure in which silicon nitride and silicon oxide are stacked sequentially is used. When the thickness of silicon nitride is much greater than the thickness of silicon oxide, the thickness of structural layer 2 is changed, and the deflection of the piezoelectric stack is calculated, as shown in Table 1.

[0093] Table 1. Deflection Calculation of Si3N4-SiO2 Structural Layer and Piezoelectric Stack

[0094] The calculation results in Table 1 show the effect of the thickness variation of structural layer 2 on the piezoelectric stack deflection under different thicknesses of piezoelectric layer 1.

[0095] Optionally, structural layer 2 is a two-layer structure consisting of silicon oxide and silicon nitride stacked sequentially. Keeping the low-temperature PECVD process conditions constant, when using a two-layer structure with silicon oxide and silicon nitride stacked sequentially, if the thickness of silicon oxide is much greater than that of silicon nitride, the thickness of structural layer 2 is varied, and the deflection of the piezoelectric stack is calculated, as shown in Table 2.

[0096] Table 2. Deflection Calculation of SiO2-Si3N4 Structural Layer and Piezoelectric Stack

[0097] The calculation results in Table 2 show the effect of the thickness variation of structural layer 2 on the piezoelectric stack deflection under different thicknesses of piezoelectric layer 1.

[0098] Optionally, structural layer 2 is a three-layer structure consisting of silicon oxide, silicon nitride, and silicon oxide stacked sequentially. Keeping the low-temperature PECVD process conditions constant, when using a three-layer structure with silicon oxide, silicon nitride, and silicon oxide stacked sequentially, the thickness of silicon nitride is much greater than that of silicon oxide. By changing the thickness of structural layer 2, the deflection of the piezoelectric stack was calculated, as shown in Table 3.

[0099] Table 3. Deflection Calculation of SiO2-Si3N4-SiO2 Structural Layer and Piezoelectric Stack

[0100] The calculation results in Table 3 show the effect of the thickness variation of structural layer 2 on the piezoelectric stack deflection under different thicknesses of piezoelectric layer 1.

[0101] Optionally, structural layer 2 is a three-layer structure consisting of silicon nitride, silicon oxide, and silicon nitride stacked sequentially. Keeping the low-temperature PECVD process conditions constant, when using a three-layer structure with silicon nitride, silicon oxide, and silicon nitride stacked sequentially, the thickness of silicon oxide is much greater than the thickness of silicon nitride. By changing the thickness of structural layer 2, the deflection of the piezoelectric stack was calculated, as shown in Table 4.

[0102] Table 4. Deflection Calculation of Si3N4-SiO2-Si3N4 Structural Layer and Piezoelectric Stack

[0103] The calculation results in Table 4 show the effect of the thickness variation of structural layer 2 on the piezoelectric stack deflection under different thicknesses of piezoelectric layer 1.

[0104] As shown in Tables 1-4, a thicker piezoelectric layer 1 results in a greater negative deflection, while a thicker structural layer 2 results in a greater positive deflection. Therefore, the thickness of structural layer 2 can be used to adjust the deflection of the piezoelectric stack. The piezoelectric stack will form a final deflection based on the stress superposition of piezoelectric layer 1 and structural layer 2, and the final deflection is not necessarily negative. Therefore, the thicknesses of piezoelectric layer 1 and structural layer 2 need to be set appropriately to achieve a final negative deflection for the entire piezoelectric stack structure.

[0105] Please refer to Figures 17 and 21, S5, to pattern the structural layer 2 and form the desired piezoelectric stack structure. ICP etching is used to etch the structural layer 2 to expose the PZT upper electrode 13, the PZT lower electrode 11, and a portion of the deflection confinement layer 4.

[0106] Please refer to Figures 18 and 22, S6. The substrate 3 is patterned using dry etching or wet etching to expose the back side of the deflection confinement layer 4 and form a back cavity. The deflection confinement layer 4, piezoelectric layer 1 and structural layer 2, corresponding to the projected area of ​​the back cavity, together form a diaphragm.

[0107] Optionally, when graphically defining structure layer 2, the metal layer 5 is exposed, as shown in Figure 21.

[0108] Optionally, in the embodiments of this application, an encapsulation structure can be adopted to seal the front or back of the stacked structure to form an air or vacuum cavity, thereby adjusting the gas film or mechanical damping and further improving the performance of the device.

[0109] The piezoelectric stack structure and manufacturing method proposed in this application utilize the characteristic that the residual stress during the growth of PZT thin films manifests as tensile stress, giving the stack structure a large negative direction deflection. First, the PZT thin film (piezoelectric layer) is grown and patterned. Then, a structural layer is deposited on the piezoelectric layer using PECVD. By adjusting the PECVD process parameters, the stress direction and magnitude of the structural layer are adjusted, achieving the purpose of deflecting the structural layer towards the piezoelectric layer. This ensures that the effective working range from the neutral plane to the piezoelectric layer satisfies the deflection direction of the structural layer towards the piezoelectric layer, i.e., the piezoelectric layer bulges outward on one side (as shown in Figure 3B), thereby solving the aforementioned problems and obtaining a piezoelectric stack structure that is beneficial to improving device performance.

[0110] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in this application, based on the technical solution and application concept of this application, should be included within the scope of protection of this application.

Claims

1. A piezoelectric multilayer structure, comprising a substrate (3) having opposing front and back sides, characterized in that: It also includes a deflection limiting layer (4), a piezoelectric layer (1) and a structural layer (2) stacked sequentially on the front side of the substrate (3). The piezoelectric layer (1) bends and deforms in the direction of the substrate (3), and the structural layer (2) bends and deforms in the direction of the piezoelectric layer (1), so that the initial deflection of the piezoelectric stack structure is in the negative direction, and the residual stress and vibration stress in the effective working area of ​​the piezoelectric stack structure are superimposed.

2. The piezoelectric multilayer structure according to claim 1, characterized in that, A back cavity is formed on the back side of the substrate.

3. The piezoelectric multilayer structure according to claim 2, characterized in that, The substrate (3) is a silicon wafer substrate.

4. The piezoelectric stacked structure according to claim 3, characterized in that, The piezoelectric layer (1) includes a PZT lower electrode (11), a PZT thin film (12) and a PZT upper electrode (13) stacked sequentially, and the deflection direction of the PZT thin film (12) is negative.

5. The piezoelectric stacked structure according to claim 4, characterized in that, The thickness of the PZT film (12) is 0.1-5 μm.

6. The piezoelectric stacked structure according to claim 4, characterized in that, The thickness of the structural layer (2) is greater than the thickness of the PZT film (12).

7. The piezoelectric stacked structure according to claim 4, characterized in that, The surfaces of the PZT lower electrode (11) and the PZT upper electrode (13) are respectively grown with metal layers (5) to facilitate the extraction of the electrodes.

8. The piezoelectric multilayer structure according to claim 4, characterized in that, The longitudinal projected area of ​​the PZT upper electrode (13) is smaller than the longitudinal projected area of ​​the PZT thin film (12), and the structural layer (2) is disposed on the surface of the PZT upper electrode (13) and extends to the surface of the PZT thin film (12).

9. The piezoelectric stacked structure according to claim 1, characterized in that, The material of the deflection limiting layer (4) is silicon oxide, and the thickness of the deflection limiting layer (4) is 10-500 nm.

10. The piezoelectric multilayer structure according to claim 8, characterized in that, The material of the structural layer (2) is silicon oxide and / or silicon nitride, and the thickness of the structural layer (2) is 0.5-25 μm.

11. The piezoelectric multilayer structure according to claim 10, characterized in that, The structural layer (2) is a two-layer or three-layer structure composed of alternating layers of silicon oxide and silicon nitride.

12. A method for manufacturing a piezoelectric laminate, used to form the piezoelectric laminate structure according to any one of claims 1-11, characterized in that, Including the following steps: S1. A deflection confinement layer (4) is grown on the front side of the substrate (3) by thermal oxidation process; S2. A piezoelectric layer (1) is sputtered and grown on the deflection confinement layer (4). The piezoelectric layer (1) bends and deforms towards the substrate (3) due to its own stress. S3. Pattern the piezoelectric layer (1); S4. A structural layer (2) is grown on the patterned piezoelectric layer (1), and the structural layer (2) is bent and deformed in the direction of the piezoelectric layer (1). S5. Graphicalize the structural layer (2); S6. Etch the back side of the substrate (3) to form a back cavity; The piezoelectric layer (1) is bent and deformed towards the substrate (3), and the structural layer (2) The piezoelectric layer (1) is bent and deformed so that the initial deflection of the piezoelectric stack structure is in the negative direction, and the residual stress and vibration stress in the effective working area of ​​the piezoelectric stack structure are superimposed.

13. The method for manufacturing a piezoelectric laminate according to claim 12, characterized in that, The process of sputtering and growing a piezoelectric layer (1) on the deflection confinement layer (4) in S2 includes: S21. A PZT lower electrode (11) is sputtered and grown on the deflection confinement layer (4); S22. A PZT thin film (12) is sputtered and grown on the PZT lower electrode (11). The PZT thin film (12) bends and deforms in the direction of the PZT lower electrode (11) due to its own stress. S23. A PZT top electrode (13) is sputtered and grown on the PZT thin film (12). The PZT top electrode (13) bends and deforms along the bending direction of the PZT thin film (12).

14. The method for manufacturing a piezoelectric laminate according to claim 12, characterized in that, The step S3 involves patterning the piezoelectric layer (1), including: S31, IBE etching is used to pattern the upper electrode (13) of PZT; S32, wet etching of PZT film (12) is used to expose part of PZT lower electrode (11); S33, IBE is used to etch the lower electrode (11) of PZT to pattern the lower electrode (11) of PZT, thereby completing the patterning of the piezoelectric layer (1).

15. The method for manufacturing a piezoelectric laminate according to claim 14, characterized in that, Also includes: S34, a metal layer (5) is grown on the surface of the piezoelectric layer (1), and the metal layer (5) covers the exposed areas of the piezoelectric layer (1) and the deflection limiting layer (4); S35, patterned metal layer (5), retaining part of the metal layer (5) on the surface of the PZT upper electrode (11) and PZT upper electrode (13).

16. The method for manufacturing a piezoelectric laminate according to claim 12, characterized in that, The structural layer (2) is generated using a low-temperature PECVD process. The structural layer (2) is a two-layer or three-layer structure consisting of silicon oxide and silicon nitride stacked alternately.

17. The method for manufacturing a piezoelectric laminate according to claim 16, characterized in that, The stress direction and magnitude of the structural layer (2) are controlled by adjusting the temperature, time, power and cavity pressure of the low-temperature PECVD process.

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