Display apparatus

Abstract

A display apparatus, comprising a display panel and a display driver circuit, the display driver circuit comprising a plurality of gate driver circuits, wherein X gate driver circuits are spaced between two cascaded gate driver circuits, first clock signals corresponding to the two cascaded gate driver circuits have a phase difference of (X +1) H, and in at least one sub-pixel, the phase difference between effective levels of second gate control signals corresponding to a data transistor and one of two first effective levels of the first clock signals applied to the gate driver circuits corresponding to a compensation transistor is greater than 0 and less than (X +1) H, X being greater than or equal to 1, and H representing a unit duration.

Description

Display device

[0001] This application claims priority to Chinese Patent Application No. 202410502505.1, filed on April 24, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This application relates to the field of display technology, and more specifically to a display device. Background Technology

[0003] To achieve a segmented frequency design where different display areas of the display panel have different display frequencies, the frequency of sub-pixel refresh display data for different display areas can be controlled by controlling the frequency of the gate control signals generated by each stage of the gate drive circuit in the display driver circuit. The multiple gate control signals output by the multi-stage gate drive circuit switch between outputting a gate control signal with valid pulses and outputting a gate control signal without valid pulses, or vice versa; that is, the frequency switching of the multiple gate control signals.

[0004] A multi-stage cascaded gate drive circuit generates voltages corresponding to the effective levels of multiple gate control signals based on a constant power supply voltage. However, when the gate drive circuit needs to output a gate control signal with an effective pulse, the constant power supply acts on the gate drive circuit, causing the load corresponding to the constant power supply to increase instantaneously with a first increase. This results in a decrease in the voltage supplied by the constant power supply (i.e., de-loading), and a decrease in the effective level of the gate control signal generated by the gate drive circuit, leading to a voltage drop problem in the gate control signal output by the gate drive circuit. Conversely, when the gate drive circuit needs to output a gate control signal without an effective pulse, the increase in the load corresponding to the constant power supply will be less than the first increase. Therefore, the load formed by the gate drive circuit that needs to output a gate control signal with an effective pulse is different from that formed by the gate drive circuit that needs to output a gate control signal without an effective pulse on the constant power supply. Consequently, when the display panel uses frequency division display, due to the frequency switching of multiple gate control signals, the load formed by the multi-stage gate drive circuit on the constant power supply is different before and after frequency division, resulting in differences in the voltage drop changes of the gate control signal applied to the sub-pixels near the corresponding frequency division positions. Furthermore, the voltage drop change of the gate control signal is caused by the periodic change of the clock signal used by the gate drive circuit.

[0005] As shown in Figure 1, before frequency division (i.e., when the frequency division control signal NLF is low), the voltage drop problem exhibited by multiple gate control signals is quite severe (as shown by the changes in the multi-level gate control signal Nscan within the dashed box in Figure 1). After frequency division (i.e., when the frequency division control signal NLF is high), the severity of the voltage drop problem in some gate control signals decreases. Therefore, near the corresponding frequency division position, the voltage fluctuation of the gate control signal corresponding to some sub-pixels refreshing display data (as shown in Figure 1, the tw stage represents the sub-pixel data refresh stage) is large, while the voltage fluctuation of the gate control signal corresponding to other sub-pixels refreshing display data is small. This results in charging differences among multiple sub-pixels, leading to differences in display brightness and causing uneven display. Invention Overview

[0006] This application provides a display device that can improve the problem of uneven display.

[0007] This application provides a display device, including a display panel and a display driving circuit. The display panel includes a plurality of sub-pixels, each sub-pixel including a light-emitting device, a driving transistor, a data transistor, and a compensation transistor. The driving transistor is configured to drive the light-emitting device to emit light, and the data transistor and the compensation transistor are configured to transmit data signals to the control terminal of the driving transistor. The display driving circuit is electrically connected to the display panel and is configured to output a plurality of first gate control signals to the control terminals of the compensation transistors of the plurality of sub-pixels, and to output a plurality of second gate control signals to the control terminals of the data transistors of the plurality of sub-pixels. The display driving circuit includes a plurality of gate driving circuits and a plurality of frequency division control lines. The plurality of frequency division control lines are configured to transmit frequency division control signals to the plurality of gate driving circuits to control the level of at least one of the plurality of first gate control signals. Each gate driving circuit is configured to generate the first gate control signal according to a corresponding start signal and a first clock signal. Wherein, the two cascaded gate driving circuits are spaced apart by X gate driving circuits, and the phase difference of the first clock signal corresponding to the two cascaded gate driving circuits is (X+1)H; in at least one sub-pixel, the effective level of the first gate control signal corresponding to the compensation transistor and the effective level of the second gate control signal corresponding to the data transistor at least partially overlap, the effective level of the second gate control signal corresponding to the data transistor is located between the two first effective levels of the first clock signal applied by the gate driving circuit corresponding to the compensation transistor, and the phase difference between the effective level of the second gate control signal corresponding to the data transistor and one of the two first effective levels is greater than 0 and less than (X+1)H; X≥1, H represents unit time. Attached Figure Description

[0008] Figure 1 is a timing diagram of the gate control signals corresponding to some sub-pixels at the frequency division position of the display panel provided in the embodiment of this application;

[0009] Figure 2 is a schematic diagram of the cascaded structure of a multi-stage gate drive circuit in the related technology;

[0010] Figure 3 is a timing diagram of the gate control signal output corresponding to the cascaded structure shown in Figure 2;

[0011] Figure 4 is a schematic diagram of the structure of the display device provided in an embodiment of this application;

[0012] Figures 5A and 5B are schematic diagrams of the sub-pixel structure provided in the embodiments of this application;

[0013] Figure 6 is a schematic diagram of the cascaded structure of the multi-stage gate drive circuit provided in the embodiment of this application;

[0014] Figure 7 is a timing diagram of multiple first gate control signals and multiple second gate control signals provided in an embodiment of this application;

[0015] Figure 8 is a schematic diagram of the gate driving circuit provided in an embodiment of this application;

[0016] Figures 9A and 9B are timing diagrams of the corresponding gate drive circuits provided in the embodiments of this application;

[0017] Figure 10 is a timing diagram of the corresponding sub-pixels provided in an embodiment of this application;

[0018] Figure 11 is a schematic diagram of the high-frequency and low-frequency image display principles provided in the embodiments of this application. Embodiments of the present invention

[0019] To make the objectives, technical solutions, and effects of this application clearer and more explicit, the following detailed description of this application is provided with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining this application and are not intended to limit this application.

[0020] This application provides a display device that, by spacing two cascaded gate driving circuits in a display driving circuit by X gate driving circuits, and setting the phase difference of the first clock signals corresponding to the two cascaded gate driving circuits to (X+1)H, changes the period of voltage drop change of the first gate control signal output by each gate driving circuit from XH to (X+1)H, thereby increasing the interval duration of voltage drop change of the first gate control signal. By ensuring that the effective level of the first gate control signal corresponding to the compensation transistor and the effective level of the second gate control signal corresponding to the data transistor in at least one sub-pixel at least partially overlap, the data transistor and compensation transistor of at least one sub-pixel have a phase of simultaneous conduction, thereby achieving sub-pixel charging. By ensuring that the effective level of the second gate control signal corresponding to the data transistor is located between the two first effective levels of the first clock signal applied by the gate drive circuit corresponding to the compensation transistor, and that the phase difference between the effective level of the second gate control signal corresponding to the data transistor and one of the two first effective levels is greater than 0 and less than (X+1)H, the effective level of the second gate control signal corresponding to the data transistor in the same sub-pixel does not coincide with the moment when the voltage drop occurs in the first gate control signal corresponding to the compensation transistor. This ensures that the effective level of the second gate control signal corresponding to the data transistor in the same sub-pixel is within the interval of the voltage drop change in the first gate control signal corresponding to the compensation transistor. Consequently, the data transistor is turned on in the range where the voltage drop change in the first gate control signal applied by the compensation transistor is small, thereby reducing the charging differences of multiple sub-pixels at the corresponding frequency division position and improving the problem of uneven display.

[0021] Specifically, the purpose of using a zoned frequency display on the display panel is to apply different display modes and corresponding frequencies to different display areas of the same screen. For example, in a video playback interface, the video content is displayed in the middle area of ​​the screen, while the top and bottom areas can be used to display static images. The zoned frequency display technology handles this type of UI screen display by using a 120Hz high refresh rate for the video area, while using a 1Hz low refresh rate for the top and bottom areas displaying static images, thus saving power and reducing energy consumption.

[0022] By controlling the level of the gate control signals received by the compensation transistor and reset transistor in the sub-pixel, frequency division display technology can be achieved. Therefore, at the corresponding frequency division position (i.e., the high-low frequency boundary), the levels of multiple gate control signals received by the compensation transistor and reset transistor of the corresponding sub-pixel will change from having an effective level to having no effective level. The effective level output of this gate control signal is supplied by a constant power supply. During the output level phase, the constant power supply is connected to the output terminal that outputs the gate control signal. From the perspective of RC load, the load on the constant power supply is considered to increase instantaneously, resulting in a voltage drop in the level of the gate control signal output by the current stage gate drive circuit. During high-low frequency switching, the level of multiple gate control signals changes from having an effective level to having no effective level, causing inconsistent voltage drop changes in the gate control signals. Consequently, when the sub-pixel at the corresponding frequency division position refreshes the display data during the corresponding data writing phase, a fixed-width display unevenness problem will occur.

[0023] The inventors discovered that the voltage drop variation of the gate control signal received by the compensation transistor and reset transistor is also caused by the periodic variation of the clock signal used by the gate driving circuit that generates the gate signal. The period of the clock signal used by the gate driving circuit affects the period of voltage drop variation in the gate control signal it generates. Figure 2 is a schematic diagram of the cascaded structure of a multi-stage gate driving circuit in the related art, and Figure 3 is a timing diagram of the gate control signal output by the cascaded structure shown in Figure 2. Here, Nscana is the gate control signal generated by the gate driving circuit before frequency division, and Nscanb is the gate control signal generated by the gate driving circuit after frequency division. If the period of the clock signal used by the gate driving circuit is 4H, then the period of voltage drop variation in the gate control signal generated by the gate driving circuit is 1H. Therefore, each row of sub-pixels near the corresponding frequency division position will have charging differences, resulting in uneven display of multiple rows of sub-pixels.

[0024] Therefore, this application provides a display device to improve the above-mentioned problem of uneven display.

[0025] Figure 4 is a schematic diagram of the structure of the display device provided in an embodiment of this application. This application provides a display device including a display panel DP and a display driving circuit Dc.

[0026] The display panel DP includes multiple sub-pixels (Spi), multiple scan lines, and multiple data lines (DL). The multiple scan lines are electrically connected between the display driver circuit DC and the multiple sub-pixels (Spi). The multiple data lines (DL) are configured to transmit multiple data signals. The multiple data lines (DL) are electrically connected between the source driver circuit SDC and the multiple sub-pixels (Spi). The source driver circuit SDC is configured to generate multiple data signals.

[0027] Figures 5A and 5B are schematic diagrams of the structure of sub-pixels Spi provided in the embodiments of this application. Each sub-pixel Spi includes a light-emitting device Di and a pixel driving circuit that drives the light-emitting device Di to emit light.

[0028] Optionally, the light-emitting device Di includes organic light-emitting diodes, sub-millimeter light-emitting diodes, micro light-emitting diodes, etc.

[0029] The pixel driving circuit includes at least a driving transistor Tdr, a data transistor Tda, and a compensation transistor Tc.

[0030] The driving transistor Tdr is connected in series with the light-emitting device Di between the first voltage terminal Vdd and the second voltage terminal Vss. The driving transistor Tdr is configured to generate a driving current according to the data signal transmitted by the corresponding data line DL to drive the light-emitting device Di to emit light.

[0031] The data transistor Tda and the compensation transistor Tc are configured to transmit data signals to the control terminal of the drive transistor Tdr.

[0032] Optionally, the control terminal of the compensation transistor Tc is configured to receive the corresponding first gate control signal Nscan1, the input terminal of the compensation transistor Tc is electrically connected to the output terminal of the driving transistor Tdr, and the output terminal of the compensation transistor Tc is electrically connected to the control terminal of the driving transistor Tdr.

[0033] The control terminal of the data transistor Tda is configured to receive the corresponding second gate control signal Pscan1. The input terminal of the data transistor Tda is electrically connected to the corresponding data line DL. The input terminal of the data transistor Tda is configured to receive the corresponding data signal. The output terminal of the data transistor Tda is electrically connected to the input terminal of the drive transistor Tdr.

[0034] Optionally, the compensation transistor Tc includes an oxide transistor or a silicon transistor.

[0035] Optionally, the compensation transistor Tc is a P-type transistor or an N-type transistor, and the data transistor Tda is a P-type transistor or an N-type transistor.

[0036] Please refer to Figures 5A and 5B. The pixel driving circuit of at least one sub-pixel Spi includes a reset transistor Tr. The control terminal of the reset transistor Tr is configured to receive the third gate control signal Nscan2. The input terminal of the reset transistor Tr is electrically connected to the reset line. The input terminal of the reset transistor Tr is configured to receive the reset signal Vr. The output terminal of the reset transistor Tr is electrically connected to the control terminal of the driving transistor Tdr.

[0037] Optionally, the reset transistor Tr includes an oxide transistor or a silicon transistor. Optionally, the reset transistor Tr is a P-type transistor or an N-type transistor.

[0038] Optionally, in the same sub-pixel Spi, the effective level of the first gate control signal Nscan1 received by the control terminal of the compensation transistor Tc partially overlaps with the effective level of the third gate control signal Nscan2 received by the control terminal of the reset transistor Tr, so as to reset the potential of the output terminal and the control terminal of the driving transistor Tdr using the reset signal Vr.

[0039] Please refer to Figures 5A and 5B. The pixel driving circuit of each sub-pixel Spi also includes a first initial transistor Ti1. The control terminal of the first initial transistor Ti1 is configured to receive a first scan signal Pscan2. The input terminal of the first initial transistor Ti1 is configured to receive a first reset signal Vi1. The output terminal of the first initial transistor Ti1 is electrically connected to the anode of the light-emitting device Di.

[0040] Optionally, the pixel driving circuit of each sub-pixel Spi further includes a light-emitting control transistor, which is electrically connected between the input terminal of the driving transistor Tdr and the first voltage terminal Vdd, and / or electrically connected between the output terminal of the driving transistor Tdr and the light-emitting device Di.

[0041] Optionally, please continue to refer to Figures 5A-5B. The light-emitting control transistor includes a first light-emitting control transistor Te1 and a second light-emitting control transistor Te2. The input and output terminals of the first light-emitting control transistor Te1 are electrically connected between the first voltage terminal Vdd and the input terminal of the driving transistor Tdr. The input and output terminals of the second light-emitting control transistor Te2 are electrically connected between the light-emitting device Di and the output terminal of the driving transistor Tdr. The control terminals of the first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 are configured to receive the light-emitting control signal EM.

[0042] Please refer to Figures 5A and 5B. The pixel driving circuit of each sub-pixel Spi also includes a first storage capacitor Cst1, which is connected in series between the first voltage terminal Vdd and the control terminal of the driving transistor Tdr.

[0043] Optionally, referring to Figure 5B, the pixel driving circuit for each sub-pixel Spi also includes a second storage capacitor Cst2, which is connected in series between the control terminal of the driving transistor Tdr and the control terminal of the data transistor Tda.

[0044] Optionally, referring to Figure 5B, the pixel driving circuit for each sub-pixel Spi also includes a second initial transistor Ti2. The control terminal of the second initial transistor Ti2 is electrically connected to the corresponding fourth scan line SL4. The input terminal of the second initial transistor Ti2 is configured to receive a second reset signal Vi2. The output terminal of the second initial transistor Ti2 is electrically connected to the input terminal of the driving transistor Tdr.

[0045] Optionally, the control terminals of the first initial transistor Ti1 and the second initial transistor Ti2 are electrically connected so that the first initial transistor Ti1 and the second initial transistor Ti2 are controlled by the same first scan signal Pscan2, thereby achieving synchronous reset of the anode potential of the light-emitting device Di and the input potential of the driving transistor Tdr.

[0046] Please continue to refer to Figures 4 and 5A-5B. The display driving circuit Dc is configured to output multiple first gate control signals Nscan1 to the control terminal of the compensation transistor Tc of multiple sub-pixels Spi, and to output multiple second gate control signals Pscan1 to the control terminal of the data transistor Tda of multiple sub-pixels Spi.

[0047] Optionally, please continue to refer to Figure 4. The multiple scan lines include multiple first scan lines SL1 and multiple second scan lines SL2. Multiple first gate control signals Nscan1 are output to the control terminals of the compensation transistors Tc of multiple sub-pixels Spi via the multiple first scan lines SL1. Multiple second gate control signals Pscan1 are output to the control terminals of the data transistors Tda of multiple sub-pixels Spi via the multiple second scan lines SL2.

[0048] Optionally, the multiple scan lines include multiple third scan lines SL3 and fourth scan lines SL4, and the display panel DP includes multiple light-emitting control lines EML. The multiple third scan lines SL3 are configured to transmit multiple third gate control signals Nscan2, the multiple fourth scan lines SL4 are configured to transmit multiple first scan signals Pscan2, and the multiple light-emitting control lines EML are configured to transmit multiple light-emitting control signals EM. Specifically, the control terminal of the reset transistor Tr is electrically connected to the corresponding third scan line SL3, the control terminal of the first initial transistor Ti1 is electrically connected to the corresponding fourth scan line SL4, and the control terminal of the light-emitting control transistor is electrically connected to the corresponding light-emitting control line EML.

[0049] Figure 6 is a schematic diagram of the cascaded structure of the multi-stage gate driving circuit provided in an embodiment of this application. The display driving circuit Dc includes a first gate driving unit, which is configured to generate multiple first gate control signals Nscan1. The first gate driving unit includes multiple frequency division control lines FL and multiple gate driving circuits GA.

[0050] Multiple frequency division control lines FL are electrically connected to multiple gate drive circuits GA. The multiple frequency division control lines FL are configured to transmit frequency division control signals to the multiple gate drive circuits GA to control the level of at least one of the multiple first gate control signals Nscan1. In this way, the conduction status of the compensation transistor Tc of multiple sub-pixels Spi is controlled by the frequency division control signals applied by the multiple gate drive circuits GA, thereby controlling whether the content displayed by the corresponding sub-pixel Spi changes, so that the display panel DP can achieve segmented frequency display.

[0051] Each gate drive circuit GA is configured to generate multiple first gate control signals Nscan1 based on the corresponding start signal STV and the first clock signal XCK.

[0052] Please refer to Figure 6. There is a gap of X gate drive circuits GA between the two cascaded gate drive circuits GA. The phase difference of the first clock signal XCK corresponding to the two cascaded gate drive circuits GA is (X+1)H, so that the period of voltage drop change of the first gate control signal Nscan1 output by each gate drive circuit GA is changed from XH in the related technology to (X+1)H, which increases the interval of voltage drop change of the first gate control signal Nscan1.

[0053] It should be noted that Figure 6 only shows a schematic diagram of the cascade relationship of multiple gate drive circuits GA when X=1, but it is not intended to limit X to 1. That is, in some embodiments, X can be greater than 1.

[0054] In at least one sub-pixel Spi, the effective level of the first gate control signal Nscan1 corresponding to the compensation transistor Tc at least partially overlaps with the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda. The effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda is located between the two first effective levels of the first clock signal XCK applied by the gate drive circuit GA corresponding to the compensation transistor Tc. The phase difference between the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda and one of the two first effective levels is greater than 0 and less than (X+1)H, so that the data transistor Tda and the compensation transistor Tc of at least one sub-pixel Spi have a stage of simultaneous conduction, realizing the charging of the sub-pixel Spi. Furthermore, since the period of voltage drop change of the first gate control signal Nscan1 is (X+1)H, and when the first clock signal XCK applied by the gate drive circuit GA has an effective level, the first gate control signal Nscan1 generated by the gate drive circuit GA will also have a corresponding voltage drop problem. Therefore, the timing of the voltage drop problem in the first gate control signal Nscan1 corresponds to the point where the first clock signal XCK applied by the gate drive circuit GA that generates the first gate control signal Nscan1 has an effective level, and the point where the phase difference between the first clock signal XCK and the point where it begins to have an effective level is (X+1)H. Therefore, if the effective level of the second gate control signal Pscan1 corresponding to the control data transistor Tda has a phase difference greater than 0 and less than (X+1)H from one of the two first effective levels, the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda in the same sub-pixel Spi can be located within the interval where the voltage drop of the first gate control signal Nscan1 corresponding to the compensation transistor Tc changes. This allows the data transistor Tda to conduct within a range where the voltage drop change of the first gate control signal Nscan1 applied by the compensation transistor Tc is relatively small, thereby reducing the charging differences among multiple sub-pixels Spi at the corresponding frequency division position and improving the display unevenness problem. X≥1, H represents the unit time. Optionally, H can correspond to the row period.

[0055] Optionally, the gate drive circuits GA corresponding to the (X+1)r+1th stage are cascaded, the gate drive circuits GA corresponding to the (X+1)r+2th stage are cascaded, ..., the gate drive circuits GA corresponding to the (X+1)r+(X+1)th stage are cascaded. Where r≥0.

[0056] Figure 7 is a timing diagram of multiple first gate control signals and multiple second gate control signals provided in the embodiments of this application. Please continue to refer to Figures 6 and 7, taking X=1 as an example for explanation. When X=1, there is a gap of 1 gate drive circuit GA between the two cascaded gate drive circuits GA, and the phase difference of the first clock signal XCK corresponding to the two cascaded gate drive circuits GA is 2H. That is, multiple gate drive circuits GA of odd-numbered stages are cascaded, and multiple gate drive circuits GA of even-numbered stages are cascaded. The time difference between the voltage drop change of the first gate control signal Nscan1 output by each gate drive circuit GA is 2H, and the phase difference between the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda and one of the two first effective levels is greater than 0 and less than 2H.

[0057] If the first gate control signal received by the control terminal of the compensation transistor Tc is the third-level first gate control signal Nscan1(3) generated by the third-level gate drive circuit GA(3), and the first clock signal XCK corresponding to the third-level gate drive circuit GA(3) is the third clock signal CK3, and the first clock signal XCK corresponding to the first-level gate drive circuit GA(1) and the fifth-level gate drive circuit GA(5) is the first clock signal CK1, then the second gate control signal Pscan1 corresponding to the data transistor Tda can be the second-level second gate control signal Pscan1(2) generated by the second-level gate drive circuit GA(2), or it can be the fourth-level second gate control signal Pscan1(4) generated by the fourth-level gate drive circuit GA(4). The two first effective levels of the first clock signal XCK applied by the third-level gate drive circuit GA(3) correspond to the ta stage and tb stage in Figure 7. Therefore, when the second gate control signal Pscan1 corresponding to the data transistor Tda is the second-stage second gate control signal Pscan1(2), the phase difference between the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda and the first effective level corresponding to the ta stage is greater than 0 and less than 2H. When the second gate control signal Pscan1 corresponding to the data transistor Tda is the fourth-stage second gate control signal Pscan1(4), the phase difference between the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda and the first effective level corresponding to the tb stage is greater than 0 and less than 2H.

[0058] Optionally, the phase difference between the start signal STV corresponding to the nth-level gate driving circuit GA and the start signal STV corresponding to the (n+1)th-level gate driving circuit GA is 1H, so that the odd-numbered-level gate driving circuit GA and the even-numbered-level gate driving circuit GA sequentially output the first gate control signal Nscan1 to multiple sub-pixels Spi. Here, n is an odd number.

[0059] Optionally, referring to Figure 6, the start signal STV corresponding to the first-stage gate drive circuit GA is the first start signal stv1, the start signal STV corresponding to the second-stage gate drive circuit GA is the second start signal stv2, and the start signal STV corresponding to the u-th stage gate drive circuit GA is the first gate control signal Nscan1 output by the uv-th stage gate drive circuit GA, or the start signal STV corresponding to the u-th stage gate drive circuit GA is the signal of the second node Q2 of the uv-th stage gate drive circuit GA. Where u ≥ 2, v ≥ 1; the uv-th stage gate drive circuit GA represents the gate drive circuit GA cascaded before the u-th stage gate drive circuit GA, and whose stage number difference with the u-th stage gate drive circuit GA is v.

[0060] Optionally, the start signal STV corresponding to the third-stage gate drive circuit GA is the first gate control signal Nscan1 output by the first-stage gate drive circuit GA or the signal of the second node Q2 of the first-stage gate drive circuit GA, and the start signal STV corresponding to the fourth-stage gate drive circuit GA is the first gate control signal Nscan1 output by the second-stage gate drive circuit GA or the signal of the second node Q2 of the second-stage gate drive circuit GA.

[0061] Optionally, the start signal STV corresponding to the u-th stage gate drive circuit GA is the signal of the second node Q2 of the uv-th stage gate drive circuit GA, so that the first gate control signal Nscan1 output by the multi-stage gate drive circuit GA can switch from no effective level output to effective level output, so that the refresh frequency corresponding to the multiple display areas of the display panel DP can switch between high refresh frequency and low refresh frequency.

[0062] Optionally, the phase difference between the first start signal stv1 and the second start signal stv2 is 1H, so that the phase difference between the start signal STV corresponding to the nth stage gate drive circuit GA and the start signal STV corresponding to the (n+1)th stage gate drive circuit GA is 1H.

[0063] Optionally, X can also be greater than 1. For example, if X=2, then the first-stage gate drive circuit GA(1), the fourth-stage gate drive circuit GA(4), the seventh-stage gate drive circuit GA(7) are cascaded, the second-stage gate drive circuit GA(2), the fifth-stage gate drive circuit GA(5), the eighth-stage gate drive circuit GA(8) are cascaded, and the third-stage gate drive circuit GA(3), the sixth-stage gate drive circuit GA(6), the ninth-stage gate drive circuit GA(9) are cascaded.

[0064] Accordingly, the start signal STV corresponding to the first-stage gate drive circuit GA(1) is the first start signal stv1, the start signal STV corresponding to the second-stage gate drive circuit GA(2) is the second start signal stv2, the start signal STV corresponding to the third-stage gate drive circuit GA(3) is the third start signal, the start signal STV corresponding to the fourth-stage gate drive circuit GA(4) is the signal of the second node Q2 of the first-stage gate drive circuit GA(1), the start signal STV corresponding to the fifth-stage gate drive circuit GA(5) is the signal of the second node Q2 of the second-stage gate drive circuit GA(2), the start signal STV corresponding to the sixth-stage gate drive circuit GA(6) is the signal of the second node Q2 of the third-stage gate drive circuit GA(3), and so on, to obtain the cascade relationship of the multi-stage gate drive circuits GA.

[0065] The two cascaded gate drive circuits GA are spaced two gate drive circuits GA apart. The phase difference of the first clock signal XCK corresponding to the two cascaded gate drive circuits GA is 3H. The effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda has a phase difference greater than 0 and less than 3H with one of the two first effective levels.

[0066] Similarly, when X > 2, the cascade relationship of the multi-stage gate drive circuit GA and the relationship between the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda and the phase difference between one of the two first effective levels can also be obtained, which will not be elaborated here.

[0067] Optionally, multiple gate drive circuits GA are electrically connected to Y clock lines, and the Y clock lines are configured to transmit corresponding first clock signals XCK to the multiple gate drive circuits GA; where Y = 2(X+1).

[0068] Optionally, referring to Figure 6, where X=1, multiple gate drive circuits GA are electrically connected to four clock lines (Y=4). These Y clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, and a fourth clock line CKL4. Specifically, the first clock line CKL1 transmits the corresponding first clock signal XCK to the 4k+1 stage gate drive circuit GA; the second clock line CKL2 transmits the corresponding first clock signal XCK to the 4k+2 stage gate drive circuit GA; the third clock line CKL3 transmits the corresponding first clock signal XCK to the 4k+3 stage gate drive circuit GA; and the fourth clock line CKL4 transmits the corresponding first clock signal XCK to the 4k+4 stage gate drive circuit GA; where k≥0.

[0069] Optionally, X=2, and multiple gate drive circuits GA are electrically connected to 6 (i.e., Y=6) clock lines. The Y clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, a fourth clock line CKL4, a fifth clock line, and a sixth clock line. Specifically, the first clock line CKL1 transmits the corresponding first clock signal XCK to the 6k+1 stage gate drive circuit GA; the second clock line CKL2 transmits the corresponding first clock signal XCK to the 6k+2 stage gate drive circuit GA; the third clock line CKL3 transmits the corresponding first clock signal XCK to the 6k+3 stage gate drive circuit GA; the fourth clock line CKL4 transmits the corresponding first clock signal XCK to the 6k+4 stage gate drive circuit GA; the fifth clock line transmits the corresponding first clock signal XCK to the 6k+5 stage gate drive circuit GA; and the sixth clock line transmits the corresponding first clock signal XCK to the 6k+6 stage gate drive circuit GA; where k≥0.

[0070] Optionally, in some embodiments, to further reduce power consumption and shrink the layout space occupied by the display driving circuit Dc, each gate driving circuit GA can be configured to output a second gate control signal Pscan1 in addition to outputting the first gate control signal Nscan1. That is, each gate driving circuit GA is configured to generate multiple second gate control signals Pscan1 according to the corresponding start signal STV, the first clock signal XCK, and the second clock signal CK.

[0071] Optionally, each gate driving circuit GA includes a first output terminal Nout and a second output terminal Pout. The first output terminal Nout is configured to output a first gate control signal Nscan1, and the second output terminal Pout is configured to output a second gate control signal Pscan1. Multiple first scan lines SL1 are electrically connected between the first output terminals Nout of the multiple gate driving circuits GA and the control terminals of the compensation transistors Tc of the multiple sub-pixels Spi. Multiple second scan lines SL2 are electrically connected between the second output terminals Pout of the multiple gate driving circuits GA and the control terminals of the data transistors Tda of the multiple sub-pixels Spi.

[0072] Optionally, to improve display differences, the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda is made to have a phase difference greater than 0 and less than (X+1)H with one of the two first effective levels. This allows the first gate control signal Nscan1 and the second gate control signal Pscan1 corresponding to the same sub-pixel Spi to be generated by gate drive circuits GA at different levels.

[0073] Optionally, in the plurality of sub-pixels Spi located in the m-th row, the control terminal of the compensation transistor Tc is electrically connected to the p-th level gate drive circuit GA(p) to receive the p-th level first gate control signal Nscan1(p) output by the p-th level gate drive circuit GA(p); the control terminal of the data transistor Tda is electrically connected to the p+1-th level gate drive circuit GA(p+1) to receive the p+1-th level second gate control signal Pscan1(p+1) output by the p+1-th level gate drive circuit GA(p+1); where m≥1, p≥1.

[0074] By making the number of stages of the gate drive circuit GA corresponding to the data transistor Tda in the same sub-pixel Spi greater than the number of stages of the gate drive circuit GA corresponding to the compensation transistor Tc, the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda can be located within the time interval during which the voltage drop of the first gate control signal Nscan1 changes, thereby improving the display difference of multiple sub-pixels Spi.

[0075] Optionally, in some embodiments, among the multiple sub-pixels Spi located in the m-th row, the control terminal of the compensation transistor Tc is electrically connected to the first output terminal Nout of the p-th level gate drive circuit GA(p), and the control terminal of the data transistor Tda is electrically connected to the second output terminal Pout of the (p-1)-th level gate drive circuit GA(p-1), so that the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda can be located within the time interval during which the voltage drop of the first gate control signal Nscan1 changes.

[0076] Optionally, in the same sub-pixel Spi, the gate drive circuit GA corresponding to the data transistor Tda and the gate drive circuit GA corresponding to the compensation transistor Tc are not cascaded, so that the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda can be located within the time difference of the voltage drop change of the first gate control signal Nscan1.

[0077] Please refer to Figures 6 and 7. Taking X=1 as an example, in the multiple sub-pixels Spi located in the m-th row, the control terminal of the compensation transistor Tc is electrically connected to the 7th-level gate drive circuit GA(7), and the control terminal of the data transistor Tda can be electrically connected to the second output terminal Pout of the 8th-level gate drive circuit GA(8), the 6th-level gate drive circuit GA(6), the 4th-level gate drive circuit GA(4), or the 2nd-level gate drive circuit GA(2). Among them, the effective level of the first gate control signal Nscan1 output by the 7th-level gate drive circuit GA(7) partially overlaps with the effective level of the second gate control signal Pscan1 output by the 8th-level gate drive circuit GA(8), the 6th-level gate drive circuit GA(6), the 4th-level gate drive circuit GA(4), and the 2nd-level gate drive circuit GA(2). Similarly, when X≥2, the number of gate drive circuits GA that can be matched by the compensation transistor Tc and the data transistor Tda in the same sub-pixel can be obtained.

[0078] Optionally, referring to Figure 6, multiple gate drive circuits GA are electrically connected to Z clock lines, which are configured to transmit corresponding second clock signals CK to the multiple gate drive circuits GA; where Z = 2(X+1).

[0079] Optionally, the Y clock lines can be shared as Z clock lines to reduce the number of clock lines used by the display driver circuit Dc and to help reduce the bezel size of the display panel DP.

[0080] Taking X=1 as an example, the Z clock lines include the first clock line CKL1, the second clock line CKL2, the third clock line CKL3, and the fourth clock line CKL4. Specifically, the third clock line CKL3 transmits the corresponding second clock signal CK to the 4k+1 stage gate driver circuit GA; the fourth clock line CKL4 transmits the corresponding second clock signal CK to the 4k+2 stage gate driver circuit GA; the first clock line CKL1 transmits the corresponding second clock signal CK to the 4k+3 stage gate driver circuit GA; and the second clock line CKL2 transmits the corresponding second clock signal CK to the 4k+4 stage gate driver circuit GA.

[0081] For example, if X=2, the Z clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, a fourth clock line CKL4, a fifth clock line, and a sixth clock line. Specifically, the fourth clock line CKL4 transmits the corresponding second clock signal CK to the 6k+1 level gate driver circuit GA; the fifth clock line transmits the corresponding second clock signal CK to the 6k+2 level gate driver circuit GA; the sixth clock line transmits the corresponding second clock signal CK to the 6k+3 level gate driver circuit GA; the first clock line CKL1 transmits the corresponding second clock signal CK to the 6k+4 level gate driver circuit GA; the second clock line CKL2 transmits the corresponding second clock signal CK to the 6k+5 level gate driver circuit GA; and the third clock line CKL3 transmits the corresponding second clock signal CK to the 6k+6 level gate driver circuit GA.

[0082] Similarly, the matching relationship between the multi-stage gate drive circuit GA and the Z clock lines can also be obtained when X > 2.

[0083] Understandably, the first gate control signal Nscan1 and the second gate control signal Pscan1 can also be provided by different gate driving units. That is, in the display driving circuit Dc, the number of gate driving units can be set to multiple, and the gate driving circuit GA can be set to output only the first gate control signal Nscan1 or the second gate control signal Pscan1. For example, the display device may include two gate driving units. Among them, the multiple first output terminals Nout of one gate driving unit output multiple first gate control signals Nscan1, and the multiple first output terminals Nout of one gate driving unit output multiple second gate control signals Pscan1.

[0084] Optionally, the first gate control signal Nscan1 generated by multiple gate driving circuits GA can be used as the third gate control signal Nscan2 and output to the control terminal of the reset transistor Tr of multiple sub-pixels Spi via multiple third scan lines SL3. The first gate control signal Nscan1 received by the reset transistor Tr and the first gate control signal Nscan1 received by the compensation transistor Tc in the same sub-pixel Spi are generated by gate driving circuits GA at different levels. Optionally, the control terminal of the reset transistor Tr of the sub-pixel Spi located in the m-th row receives the first gate control signal Nscan1(pD) at level pD, and the control terminal of the compensation transistor Tc of the sub-pixel Spi located in the m-th row receives the first gate control signal Nscan1(p+E) at level p+E. Where D≥1, E≥1. For example, in the multiple sub-pixels Spi located in the m-th row, the control terminal of the compensation transistor Tc is electrically connected to the first output terminal Nout of the (p+1)-th level gate driving circuit GA(p+1), and the control terminal of the reset transistor Tc is electrically connected to the first output terminal Nout of the (p-2)-th level gate driving circuit GA.

[0085] For example, in the multiple sub-pixels Spi located in the 8th row, the control terminal of the compensation transistor Tc is electrically connected to the first output terminal Nout of the 9th level gate drive circuit GA(9), and the control terminal of the reset transistor Tr is electrically connected to any one of the second output terminals Pout of the 1st level gate drive circuit GA(1) to the second output terminal Pout of the 7th level gate drive circuit GA(7).

[0086] Optionally, in some embodiments, the first gate control signal Nscan1 received by the compensation transistor Tc in the same sub-pixel Spi and the third gate control signal Nscan2 received by the reset transistor Tr are generated by the gate driving circuits GA included in different gate driving units. For example, a gate driving unit included in the display device generates multiple first gate control signals Nscan1 and outputs them to the control terminals of the compensation transistors Tc of the multiple sub-pixels Spi, while another gate driving unit included in the display driving circuit Dc generates multiple third gate control signals Nscan2 and outputs them to the control terminals of the reset transistors Tr of the multiple sub-pixels Spi. It is understood that the design of the gate driving unit electrically connected to the control terminals of the reset transistors Tr of the multiple sub-pixels Spi can refer to the design of the gate driving unit electrically connected to the control terminals of the compensation transistors Tc of the multiple sub-pixels Spi.

[0087] Optionally, in some embodiments, the second gate control signal Pscan1 generated by the multiple gate drive circuits GA can be used as the first scan signal Pscan2 and output to the control terminal of the first initial transistor Ti1 of the multiple sub-pixels Spi via multiple fourth scan lines SL4.

[0088] Optionally, in some embodiments, a separate gate driving unit may be provided to provide the required first scan signal Pscan2 for the first initial transistor Ti1 of the plurality of sub-pixels Spi.

[0089] Understandably, the display driver circuit Dc can be equipped with a separate gate driving unit to provide the required light emission control signal EM for the light emission control transistors of multiple sub-pixels Spi.

[0090] Figure 8 is a schematic diagram of the gate drive circuit provided in the embodiment of this application. Each gate drive circuit GA includes a node control module 10, a first output module 20, and a first frequency divider module 30.

[0091] The node control module 10 is electrically connected to the first node Q1 and the second node Q2 of the gate drive circuit GA. The node control module 10 is configured to control the signals transmitted to the first node Q1 and the second node Q2 according to the corresponding first clock signal XCK and start signal STV.

[0092] The first output module 20 is electrically connected to the first node Q1. The first output module 20 is configured to output a first gate control signal Nscan1 according to the corresponding frequency division control signal and the signal of the first node Q1.

[0093] The first frequency divider module 30 is electrically connected to the first node Q1, the second node Q2 and the first output module 20. The first frequency divider module 30 is configured to control the signal transmission between the first node Q1 and the first output module 20 according to the corresponding frequency divider control signal and the signal of the second node Q2.

[0094] Optionally, please continue to refer to Figure 8. The node control module 10 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5.

[0095] The control terminal of the first transistor T1 is configured to receive the corresponding start signal STV, and the input terminal of the first transistor T1 is electrically connected to the first power supply terminal NVGL.

[0096] The control terminal of the second transistor T2 is electrically connected to the control terminal of the first transistor T1, the input terminal of the second transistor T2 is electrically connected to the second power supply terminal PVGH, and the output terminal of the second transistor T2 is electrically connected to the output terminal of the first transistor T1.

[0097] The control terminal of the third transistor T3 is configured to receive the corresponding first clock signal XCK. The input terminal of the third transistor T3 is electrically connected to the output terminal of the first transistor T1, and the output terminal of the third transistor T3 is electrically connected to the first node Q1.

[0098] The control terminal of the fourth transistor T4 is electrically connected to the first node Q1, the input terminal of the fourth transistor T4 is electrically connected to the third power supply terminal PVGL, and the output terminal of the fourth transistor T4 is electrically connected to the second node Q2.

[0099] The control terminal of the fifth transistor T5 is electrically connected to the first node Q1, the input terminal of the fifth transistor T5 is electrically connected to the second power supply terminal PVGH, and the output terminal of the fifth transistor T5 is electrically connected to the second node Q2.

[0100] Optionally, the first transistor T1 has two control terminals, and the fourth transistor T4 has two control terminals. The first and second control terminals of the first transistor T1 are configured to receive the corresponding start signal STV, and the first and second control terminals of the fourth transistor T4 are electrically connected to the first node Q1.

[0101] Optionally, the node control module 10 of at least one gate drive circuit GA includes a sixth transistor T6. The control terminal of the sixth transistor T6 is electrically connected to the second node Q2, the input terminal of the sixth transistor T6 is electrically connected to the first power supply terminal NVGL, and the output terminal of the sixth transistor T6 is electrically connected to the first node Q1.

[0102] Optionally, the sixth transistor T6 has two control terminals, and the first and second control terminals of the sixth transistor T6 are electrically connected to the second node Q2.

[0103] Optionally, the node control module 10 of at least one gate drive circuit GA includes a seventh transistor T7 and an eighth transistor T8.

[0104] The control terminal of the seventh transistor T7 is configured to receive the corresponding first clock signal XCK, and the output terminal of the seventh transistor T7 is electrically connected to the first node Q1.

[0105] The control terminal of the eighth transistor T8 is electrically connected to the second node Q2, the input terminal of the eighth transistor T8 is electrically connected to the second power supply terminal PVGH, and the output terminal of the eighth transistor T8 is electrically connected to the input terminal of the seventh transistor T7.

[0106] Optionally, the seventh transistor T7 has two control terminals, and the first and second control terminals of the seventh transistor T7 are configured to receive the corresponding first clock signal XCK.

[0107] Please refer to Figure 8. The first frequency divider module 30 includes a first frequency divider transistor Tf1, a second frequency divider transistor Tf2, and a first capacitor C1.

[0108] The control terminal of the first frequency divider transistor Tf1 is electrically connected to the second node Q2 of the gate drive circuit GA of this stage, and the input terminal of the first frequency divider transistor Tf1 is configured to receive the corresponding frequency division control signal.

[0109] The control terminal of the second frequency divider transistor Tf2 is electrically connected to the output terminal of the first frequency divider transistor Tf1. The input terminal of the second frequency divider transistor Tf2 is electrically connected to the first node Q1. The output terminal of the second frequency divider transistor Tf2 is electrically connected to the first output module 20 through the third node Q3.

[0110] The first terminal of the first capacitor C1 is electrically connected to the control terminal of the second frequency divider transistor Tf2, and the second terminal of the first capacitor C1 is electrically connected to the third node Q3.

[0111] Optionally, to reduce the number of frequency division control lines FL used in the display driver circuit Dc, multiple first frequency division modules 30 can be electrically connected to the same frequency division control line FL, so that the frequency division control signal transmitted through the frequency division control line FL can realize the level control of multiple first gate control signals Nscan1.

[0112] Optionally, the multiple frequency division control lines FL include a first frequency division control line FL1, which is electrically connected to the first frequency division module 30 of the multi-stage gate drive circuit GA. The first frequency division control line FL1 provides a first frequency division control signal NLF to the first frequency division module 30 of the multi-stage gate drive circuit GA.

[0113] Understandably, multiple first frequency divider modules 30 can be electrically connected to multiple frequency divider control lines FL, so as to realize the level control of multiple first gate control signals Nscan1 through multiple frequency divider control signals transmitted through multiple frequency divider control lines FL.

[0114] Please refer to Figure 8. The first output module 20 includes a first output transistor To1 and a second output transistor To2.

[0115] The control terminal of the first output transistor To1 is electrically connected to the third node Q3, and the input terminal of the first output transistor To1 is electrically connected to the fourth power supply terminal NVGH.

[0116] The control terminal of the second output transistor To2 is electrically connected to the first node Q1, the input terminal of the second output transistor To2 is electrically connected to the first power supply terminal NVGL, and the output terminals of the second output transistor To2 and the first output transistor To1 are electrically connected to the first output terminal Nout of the gate drive circuit GA of this stage.

[0117] Optionally, the second output transistor To2 may have two control terminals, namely, the first control terminal and the second control terminal of the second output transistor To2 are electrically connected to the first node Q1.

[0118] Optionally, referring to Figure 8, at least one gate drive circuit GA also includes a first control module 40, which includes a first switching transistor Ts1 and a second switching transistor Ts2, so that the first gate control signal Nscan1 output by the gate drive circuit GA has better stability.

[0119] The control terminal of the first switching transistor Ts1 is configured to receive the corresponding first clock signal XCK, and the output terminal of the first switching transistor Ts1 is electrically connected to the third node Q3.

[0120] The control terminal of the second switching transistor Ts2 is electrically connected to the second node Q2 of the gate drive circuit GA of this stage. The input terminal of the second switching transistor Ts2 is electrically connected to the second power supply terminal PVGH. The output terminal of the second switching transistor Ts2 is electrically connected to the input terminal of the first switching transistor Ts1.

[0121] Optionally, the first switching transistor Ts1 has two control terminals, and the first and second control terminals of the first switching transistor Ts1 are configured to receive the corresponding first clock signal XCK.

[0122] Optionally, when the gate drive circuit GA simultaneously outputs the first gate control signal Nscan1 and the second gate control signal Pscan1, the gate drive circuit GA may further include a second output module 50 for outputting the second gate control signal Pscan1. That is, at least one gate drive circuit GA includes a second output module 50, which is electrically connected to the first node Q1 and the second node Q2. The second output module 50 is configured to output the second gate control signal Pscan1 according to the corresponding second clock signal CK, the signals of the first node Q1 and the second node Q2.

[0123] Optionally, referring to Figure 8, the second output module 50 includes a third output transistor To3, a fourth output transistor To4, and a second capacitor C2.

[0124] The control terminal of the third output transistor To3 is electrically connected to the first node Q1, and the input terminal of the third output transistor To3 is configured to receive the corresponding second clock signal CK.

[0125] The control terminal of the fourth output transistor To4 is electrically connected to the second node Q2, the input terminal of the fourth output transistor To4 is electrically connected to the second power supply terminal PVGH, and the output terminals of the fourth output transistor To4 and the third output transistor To3 are electrically connected to the second output terminal Pout of the gate drive circuit GA of this stage.

[0126] The first terminal of the second capacitor C2 is electrically connected to the control terminal of the third output transistor To3, and the second terminal of the second capacitor C2 is electrically connected to the second output terminal Pout of the gate drive circuit GA of this stage.

[0127] Optionally, in some embodiments, the second output module 50 of at least one gate drive circuit GA includes a third switching transistor Ts3, the control terminal of the third switching transistor Ts3 is configured to receive a switching control signal SC, the input terminal of the third switching transistor Ts3 is electrically connected to the first node Q1, and the output terminal of the third switching transistor Ts3 is electrically connected to the control terminal of the third output transistor To3.

[0128] Optionally, the switch control signal SC received by the control terminal of the third switching transistor Ts3 of the p-th stage gate drive circuit GA(p) corresponds to the signal of the second node Q2 of the pC-th stage gate drive circuit GA(pC). Where C≥1.

[0129] For example, the switch control signal SC received by the control terminal of the eleventh transistor T11 of the first-stage gate drive circuit GA(1) to the fourth-stage gate drive circuit GA(4) corresponds to the low-level signal VGL. The control terminal of the eleventh transistor T11 of each stage of the gate drive circuit GA after the fourth-stage gate drive circuit GA(4) is electrically connected to the second node Q2 in the first three or four stages of the gate drive circuit GA. For example, the switch control signal SC corresponding to the fifth-stage gate drive circuit GA(5) corresponds to the signal of the second node Q2 of the second-stage gate drive circuit GA(2), and the switch control signal SC corresponding to the sixth-stage gate drive circuit GA(6) corresponds to the signal of the second node Q2 of the third-stage gate drive circuit GA(3); or, the switch control signal SC corresponding to the fifth-stage gate drive circuit GA(5) corresponds to the signal of the second node Q2 of the first-stage gate drive circuit GA(1). The switch control signal SC corresponding to the sixth-stage gate drive circuit GA(6) corresponds to the signal of the second node Q2 of the second-stage gate drive circuit GA(2). Similarly, the switch control signals SC corresponding to the other stages of the gate drive circuit GA can also be obtained.

[0130] Optionally, in some embodiments, a second frequency divider module 60 may also be provided in the gate drive circuit GA to control the level of multiple second gate control signals Pscan1.

[0131] Referring to Figure 8, at least one gate drive circuit GA includes a second frequency divider module 60. The second frequency divider module 60 is electrically connected to a first node Q1, a second node Q2, and a second output module 50. The second frequency divider module 60 is configured to control the signal transmission between the first node Q1 and the corresponding second output module 50 based on the corresponding frequency division control signal and the signal of the second node Q2. Accordingly, multiple frequency division control lines FL are configured to transmit frequency division control signals to multiple gate drive circuits GA to control the level of at least one of multiple second gate control signals Pscan1.

[0132] Optionally, the second frequency divider module 60 includes a third frequency divider transistor Tf3, a fourth frequency divider transistor Tf4, and a third capacitor C3.

[0133] The control terminal of the third frequency divider transistor Tf3 is electrically connected to the second node Q2 of the gate drive circuit GA of this stage, and the input terminal of the third frequency divider transistor Tf3 is configured to receive the corresponding frequency division control signal.

[0134] The control terminal of the fourth frequency divider transistor Tf4 is electrically connected to the output terminal of the third frequency divider transistor Tf3, the input terminal of the fourth frequency divider transistor Tf4 is electrically connected to the first node Q1, and the output terminal of the fourth frequency divider transistor Tf4 is electrically connected to the second output module 50.

[0135] The first terminal of the third capacitor C3 is electrically connected to the control terminal of the fourth frequency divider transistor Tf4, and the second terminal of the third capacitor C3 is electrically connected to the output terminal of the fourth frequency divider transistor Tf4.

[0136] Optionally, the output terminal of the fourth frequency divider transistor Tf4 is electrically connected to the input terminal of the third switching transistor Ts3, so as to control the signal transmission between the second output module 50 and the first node Q1 through the fourth frequency divider transistor Tf4 and the third switching transistor Ts3.

[0137] Optionally, to reduce the number of frequency division control lines FL used by the gate control unit, the second frequency division modules of multiple gate drive circuits GA can be electrically connected to the same frequency division control line FL.

[0138] Understandably, the second frequency divider modules of multiple gate drive circuits GA can also be electrically connected to different frequency divider control lines FL, so that the second frequency divider modules of multiple gate drive circuits GA can be controlled independently.

[0139] Optionally, to allow the levels of multiple first gate control signals Nscan1 and multiple second gate control signals Pscan1 to be independently controlled, the first frequency divider module 30 and the second frequency divider module in the same gate drive circuit GA are electrically connected to different frequency divider control lines FL. Optionally, the multiple frequency divider control lines FL include a first frequency divider control line FL1 and a second frequency divider control line FL2. The first frequency divider control line FL1 is electrically connected to the first frequency divider module 30 of the multi-stage gate drive circuit GA, and the second frequency divider control line FL2 is electrically connected to the second frequency divider module 60 of the multi-stage gate drive circuit GA. The second frequency divider control line FL2 transmits a second frequency divider control signal PLF to the second frequency divider module 60 of the multi-stage gate drive circuit GA.

[0140] Optionally, in some embodiments, at least one gate drive circuit GA further includes a second control module 70, which includes a fourth switching transistor Ts4 and a fifth switching transistor Ts5.

[0141] The control terminal of the fourth switching transistor Ts4 is configured to receive the corresponding first clock signal XCK, and the output terminal of the fourth switching transistor Ts4 is electrically connected to the input terminal of the third switching transistor Ts3.

[0142] The control terminal of the fifth switching transistor Ts5 is electrically connected to the second node Q2 of the gate drive circuit GA of this stage. The input terminal of the fifth switching transistor Ts5 is electrically connected to the second power supply terminal PVGH. The output terminal of the fifth switching transistor Ts5 is electrically connected to the input terminal of the fourth switching transistor Ts4.

[0143] Optionally, the fourth switching transistor Ts4 has two control terminals, and the first and second control terminals of the fourth switching transistor Ts4 are configured to receive the corresponding first clock signal XCK.

[0144] Optionally, referring to Figure 8, at least one gate drive circuit GA also includes a reset module 80, which is electrically connected to the first node Q1. The reset module 80 is configured to control the signal transmission between the second power supply terminal PVGH and the first node Q1 according to the reset control signal Ctl.

[0145] Optionally, the reset module 80 includes a reset transistor Tre, the control terminal of the reset transistor Tre is configured to receive a reset control signal Ctl, the input terminal of the reset transistor Tre is electrically connected to the second power supply terminal PVGH, and the output terminal of the reset transistor Tre is electrically connected to the first node Q1.

[0146] Optionally, when the display driver circuit Dc is applied in the display device, the reset module 80 is configured to be enabled when the display device is powered on and / or during the blanking interval.

[0147] Optionally, in some embodiments, the voltage corresponding to the third power supply terminal PVGL is less than the voltage corresponding to the second power supply terminal PVGH, and the voltage corresponding to the first power supply terminal NVGL is less than the voltage corresponding to the fourth power supply terminal NVGH.

[0148] Figures 9A and 9B are timing diagrams of the corresponding gate drive circuits provided in the embodiments of this application. The second transistor T2, third transistor T3, fifth transistor T5, eighth transistor T8, second switching transistor Ts2, third switching transistor Ts3, fifth switching transistor Ts5, first output transistor To1, third output transistors To3 to To4, and first divider transistors Tf1 to Tf4 are P-type transistors. The first transistor T1, fourth transistor T4, sixth transistor T6, seventh transistor T7, first switching transistor Ts1, fourth switching transistor Ts4, and second output transistor To2 are N-type transistors. X=1. The third clock line CKL3 transmits the corresponding first clock signal XCK to the p-th stage gate drive circuit GA. The fourth clock line CK... Taking the following examples—L4 transmitting the corresponding first clock signal XCK to the (p+1)th stage gate driver circuit GA, the first clock line CKL1 transmitting the corresponding first clock signal XCK to the (p+2)th stage gate driver circuit GA, the second clock line CKL2 transmitting the corresponding first clock signal XCK to the (p+3)th stage gate driver circuit GA, the first clock line CKL1 transmitting the corresponding second clock signal CK to the p-th stage gate driver circuit GA, the second clock line CKL2 transmitting the corresponding second clock signal CK to the (p+1)th stage gate driver circuit GA, the third clock line CKL3 transmitting the corresponding second clock signal CK to the (p+2)th stage gate driver circuit GA, and the fourth clock line CKL4 transmitting the corresponding second clock signal CK to the (p+3)th stage gate driver circuit GA—as an example, the working principle of multiple gate driver circuits GA is explained. Here, p is an odd number.

[0149] In the first stage t1, the first clock signal CK1 transmitted by the first clock line CKL1 is high, the second clock signal CK2 transmitted by the second clock line CKL2 is high, the third clock signal CK3 transmitted by the third clock line CKL3 is low, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is high. The second node Q2 of the (p-2)th stage gate drive circuit GA(p-2) to the second node Q2 of the (p-1)th stage gate drive circuit GA(p-1) are high. The first frequency divider control signal NLF and the second frequency divider control signal PLF are low.

[0150] In the p-th stage gate drive circuit GA(p), the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the second frequency divider transistor Tf2, the fourth frequency divider transistor Tf4, and the first output transistor To1 are turned on; the second transistor T2, the fourth transistor T4, the eighth transistor T8, the first switching transistor Ts1, the second switching transistor Ts2, the third switching transistor Ts3, the fourth switching transistor Ts4, the fifth switching transistor Ts5, the first frequency divider transistor Tf1, the third frequency divider transistor Tf3, and the second to fourth output transistors To2 are turned off. The p-th stage first gate control signal Nscan1(p) and the p-th stage second gate control signal Pscan1(p) are at a high level.

[0151] In the gate drive circuit GA(p) located after the p-th stage, and in the gate drive circuit GA where the first clock signal XCK corresponds to a signal not provided by the third clock line CKL3, the third transistor T3 is turned off. In the gate drive circuit GA(p) located after the p-th stage, and in the gate drive circuit GA where the first clock signal XCK corresponds to a signal provided by the third clock line CKL3, the second transistor T2 and the third transistor T3 are turned on. Therefore, the first gate control signal Nscan1(p+1) of the (p+1)th stage to the first gate control signal Nscan1(p+11) of the (p+1)th stage remain at a low level, and the second gate control signal Pscan1(p+1) of the (p+1)th stage to the second gate control signal Pscan1(p+11) of the (p+1)th stage are at a high level.

[0152] In the second stage t2, the first clock signal CK1 transmitted by the first clock line CKL1 is high, the second clock signal CK2 transmitted by the second clock line CKL2 is high, the third clock signal CK3 transmitted by the third clock line CKL3 is high, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is low. The second node Q2 of the (p-2)th stage gate drive circuit GA(p-2) to the second node Q2 of the (p-1)th stage gate drive circuit GA(p-1) are high. The first frequency divider control signal NLF and the second frequency divider control signal PLF are low.

[0153] In the p-th stage gate drive circuit GA(p), the third transistor T3 is turned off, and the p-th stage first gate control signal Nscan1(p) and the p-th stage second gate control signal Pscan1(p) are at a high level.

[0154] The actions performed by the (p+1)th stage gate drive circuit GA(p+1) in the second stage t2 are similar to those performed by the p-th stage gate drive circuit GA(p) in the first stage t1. Similarly, the actions performed by the (p+2)th stage gate drive circuit GA(p+2) in the second stage t2 are similar to those performed by the (p+1)th stage gate drive circuit GA(p+1) in the first stage t1. This process continues, resulting in the steps performed by the (p+3)th to (p+11)th stage gate drive circuits GA(p+3) in the second stage t2. Therefore, the first gate control signal Nscan1(p+1) of the (p+1)th stage is high, the first gate control signals Nscan1(p+2) to (p+11)th stage gate control signals Nscan1(p+11) are low, and the second gate control signals Pscan1(p+1) to (p+11)th stage gate control signals Pscan1(p+11) are high.

[0155] In the third stage t3, the first clock signal CK1 transmitted by the first clock line CKL1 is at a low level, the second clock signal CK2 transmitted by the second clock line CKL2 is at a high level, the third clock signal CK3 transmitted by the third clock line CKL3 is at a high level, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is at a high level. The second node Q2 of the (p-2)th stage gate drive circuit GA(p-2) to the second node Q2 of the (p-1)th stage gate drive circuit GA(p-1) are at a high level. The first frequency divider control signal NLF and the second frequency divider control signal PLF are at a low level.

[0156] In the p-th stage gate drive circuit GA(p), the third transistor T3 is turned off, and the p-th stage first gate control signal Nscan1(p) and the p-th stage second gate control signal Pscan1(p) are at a high level. Furthermore, since the start signal STV corresponding to the p+2 stage gate drive circuit GA(p+2) is provided by the p-th stage gate drive circuit GA(p), and since the operation performed by the p+2 stage gate drive circuit GA(p+2) in the third stage t3 is similar to the operation performed by the p-th stage gate drive circuit GA(p) in the first stage t1, in the third stage t3, the first output terminal Nout of the p+2 stage gate drive circuit GA(p+2) is electrically connected to the fourth power supply terminal NVGH, causing an increase in the load on the fourth power supply terminal NVGH, which in turn causes a voltage drop in the p-th stage first gate control signal Nscan1(p).

[0157] The operation performed by the (p+1)th stage gate drive circuit GA(p+1) in the third stage t3 is similar to the operation performed by the p-th stage gate drive circuit GA(p) in the second stage t2. Similarly, the operation performed by the (p+2)th stage gate drive circuit GA(p+2) in the third stage t3 is similar to the operation performed by the (p+1)th stage gate drive circuit GA(p+1) in the second stage t2. This process continues, resulting in the steps performed by the (p+3)th to (p+11)th stage gate drive circuits GA(p+11) in the third stage t3. Therefore, the first gate control signals Nscan1(p+1) of the (p+1)th stage to Nscan1(p+2) of the (p+2)th stage are at a high level. The first gate control signal Nscan1(p+3) of stage p+3 to the first gate control signal Nscan1(p+11) of stage p+11 are at a low level, and the second gate control signal Pscan1(p+1) of stage p+1 to the second gate control signal Pscan1(p+11) of stage p+11 are at a high level.

[0158] In the fourth stage t4, the first clock signal CK1 transmitted by the first clock line CKL1 is high, the second clock signal CK2 transmitted by the second clock line CKL2 is high, the third clock signal CK3 transmitted by the third clock line CKL3 is low, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is high. The second node Q2 of the (p-2)th stage gate drive circuit GA(p-2) to the second node Q2 of the (p-1)th stage gate drive circuit GA(p-1) are high. The first frequency divider control signal NLF and the second frequency divider control signal PLF are low.

[0159] The operation performed by the p-th stage gate drive circuit GA(p) in the fourth stage t4 is similar to the operation performed by the p-th stage gate drive circuit GA(p) in the first stage t1. Since the start signal STV corresponding to the p+4th stage gate drive circuit GA(p+4) is provided by the p+2th stage gate drive circuit GA(p+2), and since the operation performed by the p+4th stage gate drive circuit GA(p+4) in the fourth stage t4 is similar to the operation performed by the p-th stage gate drive circuit GA(p) in the first stage t1, in the fourth stage t4, the first output terminal Nout of the p+4th stage gate drive circuit GA(p+4) is electrically connected to the fourth power supply terminal NVGH, increasing the load on the fourth power supply terminal NVGH, which in turn causes a voltage drop in the p-th stage first gate control signal Nscan1(p).

[0160] In the gate drive circuit GA(p) located after the p-th stage, and in the gate drive circuit GA where the first clock signal XCK is not provided by the third clock line CKL3, the third transistor T3 is turned off. In the gate drive circuit GA(p) located after the p-th stage, and in the gate drive circuit GA where the first clock signal XCK is provided by the third clock line CKL3, the second transistor T2 and the third transistor T3 are turned on. Therefore, the first gate control signals Nscan1(p+1) to Nscan1(p+4) of the p+1 stage are high, the first gate control signals Nscan1(p+5) to Nscan1(p+11) of the p+5 stage are low, and the second gate control signals Pscan1(p+1) to Pscan1(p+11) of the p+1 stage are high.

[0161] In the fifth stage t5, the first clock signal CK1 transmitted by the first clock line CKL1 is high, the second clock signal CK2 transmitted by the second clock line CKL2 is high, the third clock signal CK3 transmitted by the third clock line CKL3 is high, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is low. The second node Q2 of the (p-2)th stage gate drive circuit GA(p-2) to the second node Q2 of the (p-1)th stage gate drive circuit GA(p-1) are high. The first frequency divider control signal NLF and the second frequency divider control signal PLF are low.

[0162] In the p-th stage gate drive circuit GA(p), the third transistor T3 is turned off, and the p-th stage first gate control signal Nscan1(p) and the p-th stage second gate control signal Pscan1(p) are at a high level.

[0163] The action performed by the (p+1)th stage gate drive circuit GA(p+1) in the fifth stage t5 is similar to the action performed by the p-th stage gate drive circuit GA(p) in the fourth stage t4. The action performed by the (p+2)th stage gate drive circuit GA(p+2) in the fifth stage t5 is similar to the action performed by the (p+1)th stage gate drive circuit GA(p+1) in the fourth stage t4. And so on, the steps performed by the (p+3)th to (p+11)th stage gate drive circuits GA(p+11) in the fifth stage t5 are obtained. Therefore, the first gate control signal Nscan1(p+1) of the (p+1)th stage to the first gate control signal Nscan1(p+5) of the (p+5)th stage are at a high level. The first gate control signal Nscan1(p+6) of stage p+6 to the first gate control signal Nscan1(p+11) of stage p+11 are at a low level, and the second gate control signal Pscan1(p+1) of stage p+1 to the second gate control signal Pscan1(p+11) of stage p+11 are at a high level.

[0164] In stage t6, the first clock signal CK1 transmitted by the first clock line CKL1 is low, the second clock signal CK2 transmitted by the second clock line CKL2 is high, the third clock signal CK3 transmitted by the third clock line CKL3 is high, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is high. The second node Q2 of the (p-2)th stage gate drive circuit GA(p-2) is low, and the second node Q2 of the (p-1)th stage gate drive circuit GA(p-1) is high. The first frequency divider control signal NLF and the second frequency divider control signal PLF are low.

[0165] In the p-th stage gate drive circuit GA(p), the second switching transistor Ts2 and the third output transistor To3 are turned on, the p-th stage first gate control signal Nscan1(p) is high, and the p-th stage second gate control signal Pscan1(p) is low. Furthermore, since the start signal STV corresponding to the p+6-th stage gate drive circuit GA(p+6) is provided by the p+4-th stage gate drive circuit GA(p+4), and since the operation performed by the p+6-th stage gate drive circuit GA(p+6) in the sixth stage t6 is similar to the operation performed by the p-th stage gate drive circuit GA(p) in the first stage t1, in the sixth stage t6, the first output terminal Nout of the p+6-th stage gate drive circuit GA(p+6) is electrically connected to the fourth power supply terminal NVGH, increasing the load on the fourth power supply terminal NVGH, which in turn causes a voltage drop in the p-th stage first gate control signal Nscan1(p).

[0166] The operation performed by the (p+1)th stage gate drive circuit GA(p+1) in stage 6 (t6) is similar to the operation performed by the p-th stage gate drive circuit GA(p) in stage 5 (t5). The operation performed by the (p+2)th stage gate drive circuit GA(p+2) in stage 6 (t6) is similar to the operation performed by the (p+1)th stage gate drive circuit GA(p+1) in stage 5 (t5). This pattern continues, resulting in the steps performed by the (p+3)th to (p+11)th stage gate drive circuits GA(p+11) in stage 6 (t6). Therefore, the first gate control signals Nscan1(p+1) of the (p+1)th stage to the first gate control signals Nscan1(p+6) of the (p+6)th stage are at a high level. The first gate control signal Nscan1(p+7) of stage p+7 to the first gate control signal Nscan1(p+11) of stage p+11 are at a low level, and the second gate control signal Pscan1(p+1) of stage p+1 to the second gate control signal Pscan1(p+11) of stage p+11 are at a high level.

[0167] In stage t7, the first clock signal CK1 transmitted by the first clock line CKL1 is high, the second clock signal CK2 transmitted by the second clock line CKL2 is high, the third clock signal CK3 transmitted by the third clock line CKL3 is low, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is high. The second node Q2 of the (p-2)th stage gate drive circuit GA(p-2) and the second node Q2 of the (p-1)th stage gate drive circuit GA(p-1) are low. The first frequency divider control signal NLF and the second frequency divider control signal PLF are low.

[0168] In the p-th stage gate drive circuit GA(p), the second transistor T2, the third transistor T3, the fourth transistor T4, the second switching transistor Ts2, the first frequency divider transistors Tf1 to Tf4, the second output transistor To2, and the fourth output transistor To4 are turned on. The first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the first switching transistor Ts1, the second switching transistor Ts2, the fourth switching transistor Ts4, the fifth switching transistor Ts5, the first output transistor To1, and the third output transistor To3 are turned off. The p-th stage first gate control signal Nscan1(p) is low, and the p-th stage second gate control signal Pscan1(p) is high.

[0169] The action performed by the (p+1)th stage gate drive circuit GA(p+1) in stage 7 t7 is similar to the action performed by the (p+1)th stage gate drive circuit GA(p+1) in stage 4 t4. The action performed by the (p+2)th stage gate drive circuit GA(p+2) in stage 7 t7 is similar to the action performed by the (p+2)th stage gate drive circuit GA(p+2) in stage 4 t4. And so on, the steps performed by the (p+3)th stage gate drive circuit GA(p+3) to the (p+11)th stage gate drive circuit GA(p+11) in stage 7 t7 are obtained. Therefore, the first gate control signal Nscan1(p+1) of the (p+1)th stage to the first gate control signal Nscan1(p+8) of the (p+8)th stage are at a high level. The first gate control signal Nscan1(p+9) of stage p+9 to the first gate control signal Nscan1(p+11) of stage p+11 are at a low level, the second gate control signal Pscan1(p+1) of stage p+1, the second gate control signal Pscan1(p+3) of stage p+3 to the second gate control signal Pscan1(p+11) of stage p+11 are at a high level, and the second gate control signal Pscan1(p+2) of stage p+2 is at a low level.

[0170] Please refer to Figure 9A. In stage t8, the first clock signal CK1 transmitted by the first clock line CKL1 is low, the second clock signal CK2 transmitted by the second clock line CKL2 is high, the third clock signal CK3 transmitted by the third clock line CKL3 is high, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is high. The first frequency divider control signal NLF is high, and the second frequency divider control signal PLF is low.

[0171] The first gate control signal Nscan1(p) of stage p to the first gate control signal Nscan1(p+2) of stage p+3 to the first gate control signal Nscan1(p+9) of stage p+9 are at a low level, the second gate control signal Pscan1(p+4) of stage p+4 is at a low level, and the second gate control signals Pscan1(p) of stage p to the second gate control signal Pscan1(p+3) of stage p+3 and the second gate control signals Pscan1(p+5) of stage p+5 to the second gate control signal Pscan1(p+9) of stage p+9 are at a high level.

[0172] In the (p+10)th stage gate drive circuit GA, the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the fourth frequency divider transistor Tf4 are turned on; the second transistor T2, the fourth transistor T4, the eighth transistor T8, the first switching transistor Ts1, the fourth switching transistor Ts4, the second switching transistor Ts2, the third switching transistor Ts3, the fifth switching transistor Ts5, the first frequency divider transistor Tf1, the second frequency divider transistor Tf2, the third frequency divider transistor Tf3, and the first output transistors To1 to the fourth output transistors To4 are turned off. The first gate control signal Nscan1(p+10) of the (p+10)th stage is low, and the second gate control signal Pscan1(p+10) of the (p+10)th stage is high.

[0173] In the p+11th stage gate drive circuit GA, the third transistor T3 is turned off, the first gate control signal Nscan1(p+11) of the p+11th stage is at a low level, and the second gate control signal Pscan1(p+11) of the p+11th stage is at a high level.

[0174] Please refer to Figure 9A. In the ninth stage t9, the first clock signal CK1 transmitted by the first clock line CKL1 is at a high level, the second clock signal CK2 transmitted by the second clock line CKL2 is at a low level, the third clock signal CK3 transmitted by the third clock line CKL3 is at a high level, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is at a high level. The first frequency divider control signal NLF is at a high level, and the second frequency divider control signal PLF is at a low level.

[0175] The first gate control signal Nscan1(p) of stage p to the first gate control signal Nscan1(p+3) of stage p+3 are at a low level, the first gate control signal Nscan1(p+4) of stage p+4 to the first gate control signal Nscan1(p+9) of stage p+9 are at a high level, the second gate control signal Pscan1(p+5) of stage p+5 is at a low level, and the second gate control signal Pscan1(p) of stage p to the second gate control signal Pscan1(p+4) of stage p+4 and the second gate control signal Pscan1(p+6) of stage p+9 to the second gate control signal Pscan1(p+9) of stage p+6 are at a high level.

[0176] In the p+10th stage gate drive circuit GA, the third transistor T3 is turned off, the first gate control signal Nscan1(p+10) of the p+10th stage is at a low level, and the second gate control signal Pscan1(p+10) of the p+10th stage is at a high level.

[0177] The operation performed by the (p+11)th stage gate drive circuit GA(p+11) in the ninth stage t9 is similar to the operation performed by the (p+10)th stage gate drive circuit GA(p+10) in the eighth stage t8. Therefore, the first gate control signal Nscan1(p+11) of the (p+11)th stage is at a low level, and the second gate control signal Pscan1(p+11) of the (p+11)th stage is at a high level.

[0178] Please refer to Figure 9B. In stage t8, the first clock signal CK1 transmitted by the first clock line CKL1 is at a low level, the second clock signal CK2 transmitted by the second clock line CKL2 is at a high level, the third clock signal CK3 transmitted by the third clock line CKL3 is at a high level, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is at a high level. The first frequency divider control signal NLF is at a low level, and the second frequency divider control signal PLF is at a high level.

[0179] The first gate control signal Nscan1(p) of stage p to the first gate control signal Nscan1(p+2) of stage p+3 to the first gate control signal Nscan1(p+9) of stage p+9 are at a low level, the second gate control signal Pscan1(p+4) of stage p+4 is at a low level, and the second gate control signals Pscan1(p) of stage p to the second gate control signal Pscan1(p+3) of stage p+3 and the second gate control signals Pscan1(p+5) of stage p+5 to the second gate control signal Pscan1(p+9) of stage p+9 are at a high level.

[0180] In the (p+10)th stage gate drive circuit GA, the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the second frequency divider transistor Tf2, and the first output transistor To1 are turned on; the second transistor T2, the fourth transistor T4, the eighth transistor T8, the first switching transistor Ts1, the fourth switching transistor Ts4, the second switching transistor Ts2, the third switching transistor Ts3, the fifth switching transistor Ts5, the first frequency divider transistor Tf1, the third frequency divider transistor Tf3, the fourth frequency divider transistor Tf4, and the second output transistors To2 to To4 are turned off. The first gate control signal Nscan1(p+10) of the (p+10)th stage is high, and the second gate control signal Pscan1(p+10) of the (p+10)th stage is also high.

[0181] In the p+11th stage gate drive circuit GA, the third transistor T3 is turned off, the first gate control signal Nscan1(p+11) of the p+11th stage is at a low level, and the second gate control signal Pscan1(p+11) of the p+11th stage is at a high level.

[0182] Please refer to Figure 9B. In the ninth stage t9, the first clock signal CK1 transmitted by the first clock line CKL1 is high, the second clock signal CK2 transmitted by the second clock line CKL2 is high, the third clock signal CK3 transmitted by the third clock line CKL3 is low, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is high. The first frequency divider control signal NLF is low, and the second frequency divider control signal PLF is high.

[0183] The first gate control signal Nscan1(p) of stage p to the first gate control signal Nscan1(p+8) of stage p+8 are at a low level, the first gate control signal Nscan1(p+9) of stage p+9 to the first gate control signal Nscan1(p+11) of stage p+11 are at a high level, and the second gate control signal Pscan1(p) of stage p to the second gate control signal Pscan1(p+4) of stage p+9 and the second gate control signal Pscan1(p+11) of stage p+11 are at a high level.

[0184] In the p+10th stage gate drive circuit GA, the fourth frequency divider transistor Tf4 is turned off, and the second gate control signal Pscan1(p+10) of the p+10th stage has a high level.

[0185] Please refer to Figure 9B. In stage 10 t10, the first clock signal CK1 transmitted by the first clock line CKL1 is high, the second clock signal CK2 transmitted by the second clock line CKL2 is high, the third clock signal CK3 transmitted by the third clock line CKL3 is high, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is low. The first frequency divider control signal NLF is low, and the second frequency divider control signal PLF is high.

[0186] The first gate control signal Nscan1(p) of stage p to the first gate control signal Nscan1(p+9) of stage p are at a low level, the first gate control signal Nscan1(p+10) of stage p+10 to the first gate control signal Nscan1(p+11) of stage p+11 are at a high level, and the second gate control signal Pscan1(p) of stage p to the second gate control signal Pscan1(p+10) of stage p are at a high level.

[0187] In the p+11th stage gate drive circuit GA, the fourth frequency divider transistor Tf4 is turned off, and the second gate control signal Pscan1(p+11) of the p+11th stage has a high level.

[0188] Therefore, controlling the level of the first frequency divider control signal NLF can control the level of multiple first gate control signals Nscan1, and controlling the level of the second frequency divider control signal PLF can control the level of multiple second gate control signals Pscan1.

[0189] Similarly, the working principle of the multi-stage gate drive circuit GA can also be obtained when the first frequency division control signal NLF and the second frequency division control signal PLF switch from high level to low level.

[0190] Optionally, the transition times of the first frequency divider control signal NLF and the second frequency divider control signal PLF between high and low levels can be the same or different.

[0191] Figure 10 is a timing diagram of the corresponding sub-pixels provided in an embodiment of this application. Taking the compensation transistor Tc and reset transistor Tr as N-type transistors, and the driving transistor Tdr, first initial transistor Ti1, second initial transistor Ti2, first light-emitting control transistor Te1, and second light-emitting control transistor Te2 as P-type transistors, the working principle of the sub-pixel Spi located in the m-th row is explained. The first gate control signal Nscan1 received by the control terminal of the compensation transistor Tc of the m-th row sub-pixel Spi is output by the first output terminal Nout of the (p+1)-th stage gate driving circuit GA. The second gate control signal Pscan1 received by the control terminal of the data transistor Tda of the m-th row sub-pixel Spi is output by the second output terminal Pout of the (p+2)-th stage gate driving circuit GA. The third gate control signal Nscan2 received by the control terminal of the reset transistor Tr of the m-th row sub-pixel Spi is output by the first output terminal Nout of the (p-2)-th stage gate driving circuit GA. The gate drive circuit GA corresponding to the reset transistor Tr and the gate drive circuit GA corresponding to the compensation transistor Tc can belong to different gate drive units. The gate drive circuit GA corresponding to the data transistor Tda can belong to the same gate drive unit as the gate drive circuit GA corresponding to the compensation transistor Tc; and / or the gate drive circuit GA corresponding to the data transistor Tda can belong to the same gate drive unit as the gate drive circuit GA corresponding to the reset transistor Tr.

[0192] In the first reset phase Si1: the light emission control signal EM corresponding to the m-th row sub-pixel Spi is high, the first scan signal Pscan2 corresponding to the m-th row sub-pixel Spi is low, the first gate control signal Nscan1 corresponding to the m-th row sub-pixel Spi is low, the second gate control signal Pscan1 corresponding to the m-th row sub-pixel Spi is high, and the third gate control signal Nscan2 corresponding to the m-th row sub-pixel Spi is low. The first initial signal Vi1 transmitted by the first initial line is transmitted to the anode of the light-emitting device Di to reset the anode potential of the light-emitting device Di; the second initial signal Vi2 transmitted by the second initial line is transmitted to the input and output terminals of the driving transistor Tdr to reset the potentials of the input and output terminals of the driving transistor Tdr.

[0193] During the second reset phase Si2, the light emission control signal EM corresponding to the m-th row sub-pixel Spi is high, the first scan signal Pscan2 corresponding to the m-th row sub-pixel Spi is high, the first gate control signal Nscan1 corresponding to the m-th row sub-pixel Spi is low, the second gate control signal Pscan1 corresponding to the m-th row sub-pixel Spi is high, and the third gate control signal Nscan2 corresponding to the m-th row sub-pixel Spi is high. The reset transistor Tr is turned on, and the reset signal Vr is transmitted to the gate of the driving transistor Tdr to reset the potential of the control terminal of the driving transistor Tdr.

[0194] During the data writing phase Sw, the light emission control signal EM corresponding to the m-th row sub-pixel Spi is high, the first scan signal Pscan2 corresponding to the m-th row sub-pixel Spi is high, the first gate control signal Nscan1 corresponding to the m-th row sub-pixel Spi is high, the second gate control signal Pscan1 corresponding to the m-th row sub-pixel Spi is low, and the third gate control signal Nscan2 corresponding to the m-th row sub-pixel Spi is low. The data transistor Tda and the compensation transistor Tc are turned on, and the data signal is transmitted to the control terminal of the driving transistor Tdr.

[0195] Between the second reset stage Si2 and the data writing stage Sw, there may also be a stage in which the control reset transistor Tr and the compensation transistor Tc are simultaneously turned on, so that the reset signal Vr can be transmitted to the output and input terminals of the driving transistor Tdr, thereby realizing the potential reset of the output and input terminals of the driving transistor Tdr.

[0196] In the third reset phase Si3, the light-emitting control signal EM corresponding to the m-th row sub-pixel Spi is high, the first scan signal Pscan2 corresponding to the m-th row sub-pixel Spi is low, the first gate control signal Nscan1 corresponding to the m-th row sub-pixel Spi is low, the second gate control signal Pscan1 corresponding to the m-th row sub-pixel Spi is high, and the third gate control signal Nscan2 corresponding to the m-th row sub-pixel Spi is low. The first initial signal Vi1 is transmitted to the anode of the light-emitting device Di, and the second initial signal Vi2 is transmitted to the input and output terminals of the driving transistor Tdr.

[0197] During the light-emitting phase Sd, the light-emitting control signal EM corresponding to the m-th row sub-pixel Spi is low, the first scan signal Pscan2 corresponding to the m-th row sub-pixel Spi is high, the first gate control signal Nscan1 corresponding to the m-th row sub-pixel Spi is low, the second gate control signal Pscan1 corresponding to the m-th row sub-pixel Spi is high, and the third gate control signal Nscan2 corresponding to the m-th row sub-pixel Spi is low. The first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 are turned on, driving transistor Tdr to generate a driving current to drive the corresponding light-emitting device Di to emit light.

[0198] In the fourth reset stage Si4 and the fifth reset stage Si5, the light-emitting control signal EM corresponding to the m-th row sub-pixel Spi is at a high level, the first scan signal Pscan2 corresponding to the m-th row sub-pixel Spi is at a low level, the first gate control signal Nscan1 corresponding to the m-th row sub-pixel Spi is at a low level, the second gate control signal Pscan1 corresponding to the m-th row sub-pixel Spi is at a high level, and the third gate control signal Nscan2 of the p-2 stage is at a low level. The first initial signal is transmitted to the anode of the light-emitting device Di, and the second initial signal is transmitted to the input and output terminals of the driving transistor Tdr.

[0199] The write frame WF includes a first reset stage Si1, a second reset stage Si2, a data write stage Sw, a third reset stage Si3, and a light emission stage Sd, while the hold frame HF includes a fourth reset stage Si4, a fifth reset stage Si5, and a light emission stage Sd.

[0200] Optionally, in some embodiments, the invalid pulse width of the light emission control signal EM in the write frame WF is 60H, the effective pulse width of the first scan signal Pscan2 is 4H, the effective pulse width of the first gate control signal Nscan1 and the third gate control signal Nscan2 is 24H, and the effective pulse width of the second gate control signal Pscan1 is 1H. The phase difference between the moment when the light emission control signal EM begins to have an invalid level in the write frame WF and the moment when the first reset phase Si1 begins is 8H, the phase difference between the first reset phase Si1 and the second reset phase Si2 is 8H, and the phase difference between the third gate control signal Nscan2 and the first gate control signal Nscan1 is 3H. The phase difference between the moment when the first gate control signal Nscan1 transitions from an active level to an inactive level in the corresponding write frame WF and the start of the third reset phase Si3 is 2H. The phase difference between the moment when the third gate control signal Nscan2 transitions from an active level to an inactive level and the moment when the second gate control signal Pscan1 begins to have an active level is 2H. The phase difference between the moment when the second gate control signal Pscan1 begins to have an active level and the moment when the first gate control signal Nscan1 transitions from an active level to an inactive level is 1H. The phase difference between the end of the third reset phase Si3 and the moment when the light emission control signal EM transitions from an inactive level to an active level is 7H.

[0201] As can be seen from the analysis of Figures 9A-9B and Figure 10, when each sub-pixel Spi is used to display refresh data, it corresponds to the time difference in the voltage drop of the first gate control signal Nscan1 applied to it. Therefore, the charging difference of the sub-pixel Spi at the corresponding frequency division position can be improved, thereby improving the display difference problem.

[0202] Figure 11 is a schematic diagram of the high-frequency and low-frequency image display principle provided in the embodiment of this application. Taking the display panel DP to realize a static image display as an example, the write frame WF and the hold frame HF are explained.

[0203] When the display panel DP displays at a high frequency (e.g., 60Hz), the display panel DP needs to perform 60 refresh operations on display data within 1 second, that is, 60 frames are contained within 1 second. Each frame of display refreshes the display data. Correspondingly, the sub-pixel Spi matches the timing of the write frame WF shown in Figure 10 for each frame.

[0204] When the display panel DP displays at a low frequency (e.g., 1Hz), it still contains 60 frames per second, but only the first frame undergoes a refresh operation. Correspondingly, the sub-pixel Spi matches the timing of the write frame WF shown in Figure 10 only in the first frame F1. The subsequent 59 frames retain the frame data signal of the first frame without refreshing the display data. Correspondingly, the sub-pixel Spi matches the timing of the hold frame HF shown in Figure 10 for the subsequent 59 frames.

[0205] Among them, frames that refresh display data can be recorded as write frames (WF), and frames that do not refresh display data can be recorded as hold frames (HF).

[0206] Therefore, in the write frame WF, the first gate control signal Nscan1 corresponding to the compensation transistor Tc, the third gate control signal Nscan2 corresponding to the reset transistor Tr, and the second gate control signal Pscan1 corresponding to the data transistor Tda all need to have an effective level so that the original data signal stored at the control terminal of the driving transistor Tdr can be overwritten by the newly written data signal, so that the sub-pixel Spi can be displayed again in the write frame WF according to the newly written data signal.

[0207] In the hold frame HF, the first gate control signal Nscan1 corresponding to the compensation transistor Tc and the third gate control signal Nscan2 corresponding to the reset transistor Tr of some sub-pixels Spi remain at an invalid level, turning off the compensation transistor Tc and the reset transistor Tr so that no new data signal is stored at the control terminal of the drive transistor Tdr. In the hold frame HF, the second gate control signal Pscan1 corresponding to the data transistor Tda can be maintained at the same frequency as in the write frame WF. Alternatively, in the hold frame HF, the second gate control signal Pscan1 corresponding to the data transistor Tda can be maintained at an invalid level, so that the frequency of the second gate control signal Pscan1 corresponding to the data transistor Tda in the hold frame HF is lower than the frequency in the write frame WF.

[0208] Based on the analysis of Figures 9A-9B, 10 and 11, the principle of frequency division display implemented by the display panel DP using the display driver circuit Dc is explained.

[0209] In the first frame F1 of a display cycle, to ensure that new data signals are written to the control terminals of the driving transistors Tdr of multiple sub-pixels Spi, the first frequency division control signal NLF and the second frequency division control signal PLF must remain at an active level. All rows of sub-pixels Spi within the display panel DP undergo the write frame WF stage shown in Figure 10. A display cycle may include one frame or multiple frames. When a display cycle includes one frame, that frame corresponds to the write frame WF of multiple rows of sub-pixels Spi. When a display cycle includes multiple frames, the first frame F1 corresponds to the write frame WF of multiple rows of sub-pixels Spi.

[0210] In the second frame F2 of a display cycle, if the first row of sub-pixels Spi to the (L-1)th row of sub-pixels Spi of the display panel DP is displayed at a high frequency, and the Lth row of sub-pixels Spi and subsequent rows of sub-pixels Spi are displayed at a low frequency, then the first gate control signal Nscan1, the second gate control signal Pscan1, and the third gate control signal Nscan2 applied to the first row of sub-pixels Spi to the (L-1)th row of sub-pixels Spi must all have valid pulses, so that the first row of sub-pixels Spi to the Lth row of sub-pixels Spi all undergo the write frame WF stage shown in Figure 10. Conversely, the first gate control signal Nscan1, the second gate control signal Pscan1, and the third gate control signal Nscan2 applied to the Lth row of sub-pixels Spi and subsequent rows of sub-pixels Spi do not need to have valid pulses, so that the Lth row of sub-pixels Spi and subsequent rows of sub-pixels Spi all undergo the hold frame HF stage shown in Figure 10. The second frame F2 is located after the first frame F1.

[0211] Therefore, for sub-pixels in rows 1 to (L-1) ...

[0212] Since the effective voltage of the second gate control signal Pscan1 received by the data transistor Tda in each sub-pixel Spi is located within the time interval of the voltage drop change of the first gate control signal Nscan1 received by the compensation transistor Tc, the charging difference of the sub-pixels Spi in the part of the sub-pixels Spi from the first row to the (L-1)th row can be improved, thereby improving the display difference problem.

[0213] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display device, wherein, include: The display panel includes a plurality of sub-pixels, each sub-pixel including a light-emitting device, a driving transistor, a data transistor and a compensation transistor, wherein the driving transistor is configured to drive the light-emitting device to emit light, and the data transistor and the compensation transistor are configured to transmit data signals to the control terminal of the driving transistor. A display driving circuit, electrically connected to the display panel, is configured to output a plurality of first gate control signals to the control terminals of the compensation transistors of the plurality of sub-pixels, and to output a plurality of second gate control signals to the control terminals of the data transistors of the plurality of sub-pixels; the display driving circuit includes a plurality of gate driving circuits and a plurality of frequency division control lines, the plurality of frequency division control lines being configured to transmit frequency division control signals to the plurality of gate driving circuits to control the level of at least one of the plurality of first gate control signals, and each of the gate driving circuits being configured to generate the first gate control signal according to a corresponding start signal and a first clock signal; Wherein, the two cascaded gate driving circuits are spaced apart by X gate driving circuits, and the phase difference of the first clock signal corresponding to the two cascaded gate driving circuits is (X+1)H; in at least one sub-pixel, the effective level of the first gate control signal corresponding to the compensation transistor and the effective level of the second gate control signal corresponding to the data transistor at least partially overlap, the effective level of the second gate control signal corresponding to the data transistor is located between the two first effective levels of the first clock signal applied by the gate driving circuit corresponding to the compensation transistor, and the phase difference between the effective level of the second gate control signal corresponding to the data transistor and one of the two first effective levels is greater than 0 and less than (X+1)H; X≥1, H represents unit time.

2. The display device according to claim 1, wherein, X=1, multiple gate drive circuits of odd-numbered levels are cascaded, and multiple gate drive circuits of even-numbered levels are cascaded. Wherein, the phase difference between the start signal corresponding to the gate drive circuit of the nth stage and the start signal corresponding to the gate drive circuit of the (n+1)th stage is 1H, and n is an odd number.

3. The display device according to claim 1, wherein, The plurality of gate drive circuits are electrically connected to Y clock lines, which are configured to transmit corresponding first clock signals to the plurality of gate drive circuits; wherein, Y = 2(X+1).

4. The display device according to claim 3, wherein, X=1, and the clock lines Y include the first clock line, the second clock line, the third clock line, and the fourth clock line; Wherein, the first clock line transmits the corresponding first clock signal to the gate driving circuit of the 4k+1 stage, the second clock line transmits the corresponding first clock signal to the gate driving circuit of the 4k+2 stage, the third clock line transmits the corresponding first clock signal to the gate driving circuit of the 4k+3 stage, and the fourth clock line transmits the corresponding first clock signal to the gate driving circuit of the 4k+4 stage; wherein, k≥0.

5. The display device according to any one of claims 1 to 4, wherein, Each of the gate drive circuits is configured to generate a plurality of second gate control signals according to the corresponding start signal, the first clock signal, and the second clock signal; The first gate control signal and the second gate control signal corresponding to the same sub-pixel are generated by gate driving circuits at different levels.

6. The display device according to claim 5, wherein, In the plurality of sub-pixels located in the m-th row, the control terminal of the compensation transistor is electrically connected to the gate driving circuit of the p-th stage to receive the first gate control signal output by the gate driving circuit of the p-th stage; the control terminal of the data transistor is electrically connected to the gate driving circuit of the p+1-th stage to receive the second gate control signal output by the gate driving circuit of the p+1-th stage; wherein, m≥1, p≥1.

7. The display device according to claim 5, wherein, The plurality of gate drive circuits are electrically connected to Z clock lines, which are configured to transmit corresponding second clock signals to the plurality of gate drive circuits; wherein, Z = 2(X+1).

8. The display device according to claim 7, wherein, X=1, and the Z clock lines include the first clock line, the second clock line, the third clock line, and the fourth clock line; Specifically, the third clock line transmits the corresponding second clock signal to the gate driving circuit of the 4k+1 stage, the fourth clock line transmits the corresponding second clock signal to the gate driving circuit of the 4k+2 stage, the first clock line transmits the corresponding second clock signal to the gate driving circuit of the 4k+3 stage, and the second clock line transmits the corresponding second clock signal to the gate driving circuit of the 4k+4 stage.

9. The display device according to claim 5, wherein, Each of the gate drive circuits includes: The node control module is electrically connected to the first node and the second node of the gate drive circuit described in this stage, and is configured to control the signals transmitted to the first node and the second node according to the corresponding first clock signal and the start signal; A first output module, electrically connected to the first node, is configured to output the first gate control signal according to the corresponding frequency division control signal and the signal of the first node; and The first frequency divider module is electrically connected to the first node, the second node, and the first output module, and is configured to control the signal transmission between the first node and the first output module according to the corresponding frequency divider control signal and the signal of the second node.

10. The display device according to claim 9, wherein, At least one of the gate drive circuits includes: The second output module is electrically connected to the first node and the second node, and is configured to output the second gate control signal according to the corresponding second clock signal, the signals of the first node and the second node.

11. The display device according to claim 10, wherein, The multiple frequency division control lines are configured to transmit the frequency division control signal to multiple gate drive circuits to control the level of at least one of the multiple second gate control signals; At least one of the gate drive circuits includes: The second frequency divider module is electrically connected to the first node, the second node, and the second output module, and is configured to control the signal transmission between the first node and the corresponding second output module according to the corresponding frequency divider control signal and the signal of the second node.

12. The display device according to claim 11, wherein, The multiple frequency division control lines include a first frequency division control line and a second frequency division control line; The first frequency division control line is electrically connected to the first frequency division module of the multi-stage gate drive circuit, and the second frequency division control line is electrically connected to the second frequency division module of the multi-stage gate drive circuit.

13. The display device according to claim 9, wherein, The node control module includes: A first transistor, wherein the control terminal of the first transistor is configured to receive the corresponding start signal, and the input terminal of the first transistor is electrically connected to a first power supply terminal; The second transistor has its control terminal electrically connected to the control terminal of the first transistor, its input terminal electrically connected to the second power supply terminal, and its output terminal electrically connected to the output terminal of the first transistor. The third transistor, the control terminal of which is configured to receive the corresponding first clock signal, the input terminal of which is electrically connected to the output terminal of the first transistor, and the output terminal of which is electrically connected to the first node; A fourth transistor, wherein the control terminal of the fourth transistor is electrically connected to the first node, the input terminal of the fourth transistor is electrically connected to the third power supply terminal, and the output terminal of the fourth transistor is electrically connected to the second node; and, The fifth transistor has its control terminal electrically connected to the first node, its input terminal electrically connected to the second power supply terminal, and its output terminal electrically connected to the second node.

14. The display device according to claim 9, wherein, The first frequency divider module includes: A first frequency divider transistor, the control terminal of the first frequency divider transistor is electrically connected to the second node, and the input terminal of the first frequency divider transistor is configured to receive the corresponding frequency division control signal; A second frequency divider transistor, wherein the control terminal of the second frequency divider transistor is electrically connected to the output terminal of the first frequency divider transistor, the input terminal of the second frequency divider transistor is electrically connected to the first node, and the output terminal of the second frequency divider transistor is electrically connected to the first output module via a third node; and, A first capacitor, the first end of which is electrically connected to the control terminal of the second frequency divider transistor, and the second end of which is electrically connected to the third node.

15. The display device according to claim 14, wherein, The first output module includes: A first output transistor, the control terminal of which is electrically connected to the third node, and the input terminal of which is electrically connected to the fourth power supply terminal; and The second output transistor has its control terminal electrically connected to the first node, its input terminal electrically connected to the first power supply terminal, and its output terminals and the output terminals of the first output transistor electrically connected to the first output terminal of the gate drive circuit of this stage.

16. The display device according to claim 10, wherein, The second output module includes: The third output transistor has its control terminal electrically connected to the first node, and its input terminal is configured to receive the corresponding second clock signal. A fourth output transistor, wherein the control terminal of the fourth output transistor is electrically connected to the second node, the input terminal of the fourth output transistor is electrically connected to the second power supply terminal, and the output terminals of the fourth output transistor and the third output transistor are electrically connected to the second output terminal of the gate drive circuit of this stage; and, The second capacitor has its first terminal electrically connected to the control terminal of the third output transistor, and its second terminal electrically connected to the second output terminal of the gate drive circuit of this stage.

17. The display device according to claim 16, wherein, The second output module of at least one of the gate drive circuits includes: A third switching transistor, wherein the control terminal of the third switching transistor is configured to receive a switching control signal, the input terminal of the third switching transistor is electrically connected to the first node, and the output terminal of the third switching transistor is electrically connected to the control terminal of the third output transistor.

18. The display device according to claim 11, wherein, The second frequency divider module includes: The third frequency divider transistor has its control terminal electrically connected to the second node, and its input terminal is configured to receive the corresponding frequency division control signal. A fourth frequency divider transistor, wherein the control terminal of the fourth frequency divider transistor is electrically connected to the output terminal of the third frequency divider transistor, the input terminal of the fourth frequency divider transistor is electrically connected to the first node, and the output terminal of the fourth frequency divider transistor is electrically connected to the second output module; and, The third capacitor has its first terminal electrically connected to the control terminal of the fourth frequency divider transistor, and its second terminal electrically connected to the output terminal of the fourth frequency divider transistor.

19. The display device according to claim 1, wherein, At least one of the sub-pixels includes a reset transistor, the input terminal of which is electrically connected to a reset line, and the output terminal of which is electrically connected to the control terminal of the driving transistor. In the same sub-pixel, the effective level of the first gate control signal received by the control terminal of the compensation transistor partially overlaps with the effective level of the third gate control signal received by the control terminal of the reset transistor.

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