Chip and manufacturing method therefor, and semiconductor device and electronic device

Abstract

The present application relates to the technical field of semiconductors. Provided are a chip and a manufacturing method therefor, and a semiconductor device and an electronic device, which can avoid the problem of breakdown between a gate electrode and a source-drain structure due to a void generated at the bottom of a side wall. The chip comprises a field-effect transistor disposed on a substrate. The field-effect transistor comprises: a gate electrode, a first side wall, a second side wall, a source-drain structure and a dielectric structure, wherein the first side wall and the second side wall are sequentially stacked on a side wall of the gate electrode, and the bottom of the first side wall is in contact with the substrate; the source-drain structure comprises a first source-drain portion located in the substrate, and a second source-drain portion protruding from the surface of the substrate; and the dielectric structure protrudes from a side surface of the second source-drain portion towards the gate electrode, and at least part of the structure of the second side wall is disposed on the dielectric structure. The dielectric structure can prevent an etching solution from coming into contact with the bottom of the first side wall, thereby avoiding damage to the bottom of the first side wall.

Description

Chips and their manufacturing methods, semiconductor devices, electronic devices Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip and its manufacturing method, a semiconductor device, and an electronic device. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are a type of field-effect transistor widely used in analog and digital circuits.

[0003] Embedded epitaxial source / drain technology is a technique that can effectively improve the channel mobility of field-effect transistors and is widely used in nodes below 90nm. Referring to Figure 1, this process requires the use of a hard mask to form a trench, in which the source / drain structure (S / D) is epitaxially grown. However, during the removal of the hard mask after the epitaxial growth of the source / drain structure (S / D), insufficient process window can cause structural damage at the bottom of sidewall 1, resulting in a void a at the bottom of sidewall 1. At void a, breakdown from the gate (G) to the source / drain structure (S / D) is likely to occur, leading to device failure. Summary of the Invention

[0004] This application provides a chip and its manufacturing method, a semiconductor device, and an electronic device that can avoid damage to the bottom of the sidewalls, which could lead to breakdown between the gate and the source / drain structure.

[0005] This application provides a chip including a field-effect transistor (FET) disposed on a substrate. The FET includes a gate, a source / drain structure, a first sidewall, a second sidewall, and a dielectric structure disposed on the substrate. The first and second sidewalls are sequentially stacked on the gate sidewall, with the bottom of the first sidewall contacting the substrate. The source / drain structure includes a first source / drain portion located in the substrate and a second source / drain portion protruding from the substrate surface. The dielectric structure protrudes from the side of the second source / drain portion toward the gate, and at least a portion of the second sidewall is disposed on the dielectric structure.

[0006] In the fabrication process of the chip provided in this application, a first hard mask layer and a second hard mask layer are sequentially stacked and covered on the sidewall of the first sidewall, and a portion of the second hard mask layer is left unetched. This results in a dielectric structure protruding towards the gate being formed on the side of the second source / drain portion (i.e., the portion of the source / drain structure that protrudes from the substrate surface). This dielectric structure spans between the second source / drain portion and the first hard mask layer. Thus, during the etching of the second hard mask layer, it can prevent the etching solution from contacting the bottom of the first sidewall, avoiding damage to the bottom of the first sidewall, and thereby avoiding the problem of breakdown between the gate and the source / drain structure.

[0007] In some possible implementations, the ratio between the height of the second source / drain portion and the thickness of the second sidewall is greater than or equal to 1.5. This allows for a reduction in the etching rate of the second hard mask layer on the sides of the second source / drain portion during chip fabrication, thus preserving the bottom of the second hard mask layer as the aforementioned dielectric structure while ensuring normal removal of hard mask layers in other areas.

[0008] In some possible implementations, a second sidewall is used to fill the gap between the dielectric structure and the first sidewall. That is, during chip fabrication, if the gap between the dielectric structure and the first sidewall is relatively large, the second sidewall can fill the gap between the dielectric structure and the first sidewall, thus better suppressing the short-channel effect.

[0009] In some possible implementations, there is a gap between the dielectric structure and the first sidewall. That is, during chip fabrication, the gap between the dielectric structure and the first sidewall is small, and the second sidewall is not filled into the gap between the dielectric structure and the first sidewall.

[0010] In some possible implementations, the second sidewall includes a silicon oxide layer and a silicon nitride layer; the silicon oxide layer is closer to the first sidewall than the silicon nitride layer to suppress short-channel effects.

[0011] In some possible implementations, the silicon oxide layer extends to the surface of the dielectric structure away from the substrate, and there is a gap between the dielectric structure and the first sidewall.

[0012] In some possible implementations, the silicon oxide layer extends to the surface of the dielectric structure away from the substrate, and the silicon oxide layer fills the gap between the dielectric structure and the first sidewall.

[0013] In some possible implementations, the dielectric structure includes silicon nitride.

[0014] In some possible implementations, the field-effect transistor is a P-type field-effect transistor (PMOS). For PMOS, the effective mass of holes is greater than that of electrons, so the mobility of holes is much lower than that of electrons. In order to maintain the N / P balance of the MOSFET and improve the speed of the PMOS, it is necessary to set up an epitaxial structure for the source and drain, which generates compressive stress in the laterally to compress the channel, thereby reducing the lattice constant in the channel, decreasing the effective mass of holes, and thus improving the hole mobility.

[0015] In some possible implementations, the first source / drain portion is formed in a trench on the substrate, which is a sigma trench, meaning the sidewalls of the trench have a Σ-shaped cross-section. Using a sigma trench can enhance the stress exerted on the channel by the embedded source / drain structure (such as germanium-silicon), thus improving hole mobility.

[0016] In some possible implementations, the first source / drain portion is formed in a trench on the substrate, which is a U-shaped trench, meaning the trench has a U-shaped cross-section. Using a U-shaped trench has the advantage of simple fabrication process.

[0017] In some possible implementations, the substrate is a silicon substrate; the source / drain structure is a germanium-silicon epitaxial structure. The epitaxial structure generates compressive stress laterally, compressing the channel and reducing the lattice constant within the channel, thus decreasing the effective hole mass and improving hole mobility.

[0018] This application also provides a method for fabricating a chip, which may include: fabricating a plurality of gates on a substrate, forming a gate hard mask layer on top of the gates, forming a first sidewall on the sidewall of the gates, and then sequentially depositing a first hard mask layer and a second hard mask layer. Etching the substrate located on the sidewall of the gates to form trenches, and performing epitaxial in-situ cleaning on the trenches. Growing source / drain structures in the trenches using an epitaxial growth process; wherein the source / drain structures include a first source / drain portion located in the trench and a second source / drain portion protruding from the substrate surface. Etching the gate hard mask layer and the second hard mask layer to remove the gate hard mask layer, while retaining at least a portion of the second hard mask layer located between the second source / drain portion and the first hard mask layer. Removing the first hard mask layer. Fabricating a second sidewall between the first sidewall and the source / drain structures.

[0019] Using the above-described fabrication method, when etching the gate hard mask layer and the second hard mask layer, after removing the gate hard mask layer, at least a portion of the second hard mask layer located between the second source / drain portion and the first hard mask layer is retained as a dielectric structure. This retained portion of the dielectric structure spans between the second source / drain portion and the first hard mask layer, thereby preventing the etching solution from contacting the bottom of the first sidewall downwards, thus avoiding damage to the bottom of the first sidewall.

[0020] In some possible implementations, the above-described epitaxial growth process for growing source / drain structures in trenches may include: growing source / drain structures in trenches using an epitaxial growth process, and controlling the ratio between the height of the second source / drain portion and the thickness of the second hard mask layer to be greater than or equal to 1.5. In this case, by controlling the epitaxial growth to increase the height of the source / drain structure, the aspect ratio of the second hard mask layer located on the side of the second source / drain portion is increased during hard mask removal, thereby reducing the contact area between the etchant and the bottom of the second hard mask layer, and thus reducing the etching rate at the bottom of the second hard mask layer. In this way, while satisfying the removal of the gate hard mask layer and other areas of the second hard mask layer, a portion of the bottom second hard mask layer can be retained as a dielectric structure.

[0021] In some possible implementations, the etching of the gate hard mask layer and the second hard mask layer may include: using an etching solution containing phosphoric acid to etch the gate hard mask layer and the second hard mask layer.

[0022] In some possible implementations, the removal of the first hard mask layer may include etching the first hard mask layer using an etching solution including hydrofluoric acid to remove the first hard mask layer.

[0023] In some possible implementations, the above-described epitaxial in-situ cleaning of the trench may include: removing oxides from the inner surface of the trench and removing the first hard mask layer covering the substrate surface to expose the bottom of the first sidewall.

[0024] In some possible implementations, the etching of the substrate located on the gate side to form a trench can include: first performing dry etching on the substrate located on the gate side, and then performing wet etching to form a sigma trench. Using sigma trenches can enhance the stress applied to the channel by the embedded source / drain structure (such as germanium-silicon), which is more conducive to improving hole mobility.

[0025] This application also provides a semiconductor device, the memory including a controller and a chip as provided in any of the aforementioned possible implementations; wherein the controller is electrically connected to the chip.

[0026] This application also provides an electronic device, which includes a circuit board and a chip as provided in any of the aforementioned possible implementations; wherein the circuit board and the chip are electrically connected. Attached Figure Description

[0027] Figure 1 is a schematic diagram of the structure of a field-effect transistor in a chip provided in the prior art;

[0028] Figure 2 is a schematic diagram of the manufacturing process of a chip provided in the prior art;

[0029] Figure 3 is a schematic diagram of the manufacturing process of a chip provided in the prior art;

[0030] Figure 4 is a schematic diagram of the structure of a field-effect transistor in a chip provided in an embodiment of this application;

[0031] Figure 5 is a schematic diagram of a chip being manufactured according to an embodiment of this application;

[0032] Figure 6 is a schematic diagram of a chip being manufactured according to an embodiment of this application;

[0033] Figure 7 is a schematic diagram of a chip being manufactured according to an embodiment of this application;

[0034] Figure 8 is a schematic diagram of a trench structure provided in an embodiment of this application;

[0035] Figure 9 is a schematic diagram of a trench structure provided in an embodiment of this application;

[0036] Figure 10 is a flowchart of a chip manufacturing method provided in an embodiment of this application;

[0037] Figure 11 is a schematic diagram of a chip being manufactured according to an embodiment of this application;

[0038] Figure 12 is a schematic diagram of a chip being manufactured according to an embodiment of this application;

[0039] Figure 13 is a schematic diagram of a chip being manufactured according to an embodiment of this application;

[0040] Figure 14 is a schematic diagram of a chip being manufactured according to an embodiment of this application;

[0041] Figure 15 is a schematic diagram of a chip during the manufacturing process according to an embodiment of this application. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0043] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or order. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can indicate three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item)" refers to one or more, and "more" refers to two or more. "Installation," "connection," "linking," etc., should be interpreted broadly, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection or a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium, or a connection within two elements. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, for example, including a series of steps or units. Methods, systems, products, or equipment are not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or equipment. Terms such as “up,” “down,” “left,” and “right” are used only with respect to the orientation of components in the accompanying drawings. These directional terms are relative concepts used for relative description and clarification and may vary accordingly depending on the orientation of the components in the drawings.

[0044] First, based on the existing chip manufacturing process, a simple explanation will be given regarding the reasons for the voids at the bottom of the sidewalls in field-effect transistors.

[0045] As illustrated, the fabrication process of existing chip-based field-effect transistors includes:

[0046] Referring to Figure 2(a), multiple gates G are fabricated on the substrate, and a gate mask layer HM0 is fabricated on top of the gates G. A sidewall 1 is fabricated on the side of the gates G, and then a first hard mask layer HM1 and a second hard mask layer HM2 are fabricated in sequence.

[0047] Next, referring to Figure 2(b), under the masking effect of the first hard mask layer HM1 and the second hard mask layer HM2, the substrate 1 on the side of the gate G is etched to form a trench.

[0048] Next, referring to Figure 2(c), the trench is epitaxially cleaned in situ to remove the native oxide on the inner surface of the trench. However, the first hard mask layer HM1 covering the substrate surface on the side of the trench opening will also be removed, thereby exposing the bottom b of the sidewall 1.

[0049] Next, referring to Figure 3(a), source / drain structures S / D are grown in the trench using an epitaxial growth process.

[0050] Next, referring to Figure 3(b), the second hard mask layer HM2 is removed first, and then the first hard mask layer HM1 is removed.

[0051] Since the material forming the second hard mask layer HM2 is the same as or similar to that of the sidewall 1, when the second hard mask layer HM2 is removed, the etching solution will directly contact the bottom b of the sidewall 1, resulting in a void a at the bottom b of the sidewall 1. The contact path between the etching solution and the bottom of the sidewall 1 can be seen from the arrow shown in Figure 3(a).

[0052] Next, referring to Figure 3(c), sidewall 2 is fabricated in the area where the first hard mask layer HM1 and the second hard mask layer HM2 are removed, as well as other subsequent fabrication processes.

[0053] The chip manufactured using the above process has a void at the bottom of the sidewall 1, which reduces the isolation performance of the device. At the void a, the gate G to the source / drain structure S / D is easily broken down, which can lead to device failure.

[0054] Based on this, this application provides an electronic device that uses a novel chip. During the fabrication of this chip, by controlling the growth height of the source / drain structure S / D, the aspect ratio of the second hard mask layer HM2 located on the side of the source / drain structure S / D is increased during the hard mask removal process. This ensures that when the second hard mask layer HM2 is removed, a portion of the second hard mask layer HM2 is retained as a barrier structure. This barrier structure prevents the etching solution from contacting the bottom of the sidewall 1, thereby avoiding damage to the bottom of the sidewall 1 and thus preventing the breakdown problem between the gate and the source / drain structure.

[0055] This application does not limit the form of the aforementioned electronic device. The electronic device can be any electronic product with a chip, such as consumer electronics, home electronics, automotive electronics, financial terminal products, communication electronics, etc.

[0056] As illustrated, the aforementioned consumer electronics products can include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products can include smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. In-vehicle electronics products can include in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can include automated teller machines (ATMs), self-service electronic devices, etc. Communication electronic products can include servers, storage devices, radar, base stations, and other communication equipment.

[0057] Depending on actual needs, the above-mentioned electronic devices may also include other devices electrically connected to the chip, such as printed circuit boards (PCBs), input / output devices, etc. This application does not impose any restrictions on this.

[0058] The novel chip provided in the embodiments of this application will be described below.

[0059] The chip provided in the embodiments of this application can be a single memory chip or a system on chip (SOC), etc., and this application does not limit it.

[0060] The chip provided in this application can be applied to the field of semiconductor devices such as memory devices and logic devices, and this application does not limit it.

[0061] For example, in some possible implementations, the novel chip provided in this application embodiment can be applied to a memory, such as a dynamic random access memory (DRAM), ferroelectric random access memory (FeRAM), or other independent memory. Of course, as a memory, it can also internally include other devices electrically connected to the chip, such as a controller.

[0062] For example, in some possible implementations, the novel chip provided in the embodiments of this application can be applied to logic chips, such as central processing units (CPUs) and micro-controller units (MCUs).

[0063] The following describes the specific structure of the field-effect transistor in the chip provided in the embodiments of this application, in conjunction with the manufacturing process.

[0064] As illustrated in FIG4, this application provides a chip, which includes a substrate 10 and a field-effect transistor disposed on the substrate 10. The field-effect transistor includes a gate G and a source / drain structure S / D (also referred to as an embedded source / drain epitaxial structure) disposed on the substrate 10. A trench 20 is formed on the side of the gate G on the substrate 10, and the source / drain structure S / D extends outward from the trench 20 to protrude from the surface of the substrate 10; wherein, the portion located in the trench 20 can be referred to as the first source / drain portion 21, and the portion protruding from the surface of the substrate 10 can be referred to as the second source / drain portion 22.

[0065] It should be noted that the aforementioned source / drain structure S / D can be either the source (S) or the drain (D). The source (S) and drain (D) are distributed on both sides of the gate (G), and their structures are basically the same. For the sake of simplicity, the accompanying drawings in this embodiment only show one of the source (S) and drain (D).

[0066] The aforementioned field-effect transistor can be either an N-type field-effect transistor (NMOS) or a P-type field-effect transistor (PMOS), and this application does not impose any restrictions on it.

[0067] It should be understood that the charge carriers in NMOS are electrons, while those in PMOS are holes. Since the effective mass of a hole is greater than that of an electron, the hole mobility is much smaller than that of an electron (approximately 1 / 3). To maintain the N / P balance of the MOSFET and improve the speed of the PMOS, it is necessary to increase the hole mobility. One possible approach is to use an epitaxial structure for the PMOS source / drain structure (S / D), generating compressive stress in the channel to reduce the lattice constant within the channel, thereby decreasing the effective hole mass and ultimately improving the hole mobility. The embodiments in this application are all illustrated using PMOS as an example.

[0068] Referring again to Figure 4, the chip also includes a first sidewall SP1 and a second sidewall SP2 sequentially stacked on the sidewall of the gate G. The first sidewall SP1 is located between the second sidewall SP2 and the gate G, meaning the first sidewall SP1 is closer to the gate G than the second sidewall SP2. The first sidewall SP1 can be called the offset spacer, and the second sidewall SP2 can be called the main spacer. The arrangement of the first sidewall SP1 and the second sidewall SP2 is primarily to suppress short-channel effects.

[0069] Based on this, as shown in Figure 4, in order to solve the problem of voids appearing at the bottom of the first sidewall SP1 in the prior art and to ensure that the bottom of the first sidewall SP1 can contact the substrate 10, the chip provides a dielectric structure c at the bottom of the second sidewall SP2, and the dielectric structure c protrudes from the side of the second source / drain portion 22 toward the gate G side. Indicatively, the dielectric structure c can be a strip-shaped structure protruding from the side of the second source / drain portion 22 toward the gate G side.

[0070] As illustrated in Figure 5, the aforementioned dielectric structure c is a portion of the second hard mask layer HM2 retained on the side of the second source / drain portion 22 during the chip fabrication process, after the removal of the second hard mask layer HM2 (see Figure 3). This retained portion of the second hard mask layer HM2 (i.e., dielectric structure c) spans between the second source / drain portion 22 and the first hard mask layer HM1. In other words, both sides of dielectric structure c contact the second source / drain portion 22 and the first hard mask layer HM1, respectively. This prevents the etching solution from directly contacting the bottom of the first sidewall SP1, avoiding damage to the bottom of the first sidewall SP1 and the resulting voids, which could lead to breakdown between the gate and source / drain structures. For details on the chip fabrication process, please refer to the fabrication method section below.

[0071] It should be understood that the second sidewall SP2 is formed after the removal of the first hard mask layer HM1 and the second hard mask layer HM2 (see Figure 3). Therefore, after the removal of the first hard mask layer HM1, there will be a small gap between the dielectric structure c and the first sidewall SP1. Depending on the size of the gap, when the second sidewall SP2 is formed subsequently, the second sidewall SP2 may not fill the gap (i.e., the gap is retained), or it may partially or completely fill the gap. This application does not impose any restrictions on this, and in practice, it can be manufactured according to the process requirements.

[0072] This application does not impose any restrictions on the structure or materials of the second side wall SP2; in practice, it can be set as needed.

[0073] Schematic, in some possible implementations, referring to Figures 6 and 7, the second sidewall SP2 may include a silicon oxide layer 31 and a silicon nitride layer 32, wherein the silicon oxide layer 31 is closer to the first sidewall SP1 than the silicon nitride layer 32, and the silicon oxide layer 31 extends to the upper surface of the dielectric structure c (i.e., the surface away from the substrate).

[0074] In some embodiments, referring to FIG6, the thickness of the first hard mask layer HM1 is small. After removing the first hard mask layer HM1, the gap formed between the dielectric structure c and the first sidewall SP1 is small. The silicon oxide layer 31 does not fill the gap between the dielectric structure c and the first sidewall SP1. That is, the gap between the dielectric structure c and the first sidewall SP1 will be retained in the final formed chip.

[0075] In some other embodiments, referring to FIG7, the first hard mask layer HM1 has a large thickness. After removing the first hard mask layer HM1, the gap formed between the dielectric structure c and the first sidewall SP1 is large. The aforementioned silicon oxide layer 31 fills the gap between the dielectric structure c and the first sidewall SP1.

[0076] It should be understood that in this application, the aforementioned dielectric structure c is part of the second hard mask layer HM2, therefore the material of the dielectric structure c is the same as the material of the second hard mask layer HM2, and this application does not limit the material used for the dielectric structure c.

[0077] Indicatively, in some possible implementations, the material forming the dielectric structure c includes silicon nitride (SiN), or in other words, the material forming the second hard mask layer HM2 includes silicon nitride (SiN).

[0078] This application does not impose any restrictions on the specific height of the dielectric structure c on the side of the second source / drain portion 22. The second source / drain portion 22 may or may not be in contact with the substrate 10. In practice, it can be fabricated according to the process requirements.

[0079] Furthermore, in this application, to retain the bottom of the second hard mask layer HM2 as the dielectric structure c, during the actual chip fabrication process, the epitaxial height of the second source / drain portion 22 can be increased, thereby increasing the aspect ratio of the second hard mask layer HM2 located on the side of the second source / drain portion 22 during the hard mask removal process (wet process). This reduces the etching rate of the second hard mask layer HM2 on the side of the second source / drain portion 22, thus ensuring normal removal of the hard mask layer in other areas while retaining the bottom of the second hard mask layer HM2 as the aforementioned dielectric structure c. For details, please refer to the fabrication method section below.

[0080] This application does not impose any restrictions on the specific aspect ratio of the second hard mask layer HM2 located on the side of the second source / drain portion 22, as long as at least a portion of the second hard mask layer HM2 is retained as the dielectric structure c while ensuring normal removal of hard mask layers in other areas.

[0081] As illustrated, in some possible implementations, the aspect ratio of the second hard mask layer HM2 located on the side of the second source / drain portion 22 can be controlled to be greater than or equal to 1.5; in this case, the ratio of the height of the second source / drain portion 22 to the width of the second sidewall SP2 is greater than or equal to 1.5.

[0082] This application does not impose any restrictions on the materials used for the substrate 10 and the source / drain structure S / D, as long as they can meet the actual requirements of the chip.

[0083] Illustratively, in some possible implementations, the substrate 10 described above may be a silicon (Si) substrate, but is not limited thereto.

[0084] As illustrated, in some possible implementations, the first source / drain portion 21 in the aforementioned source / drain structure S / D can be a silicon germanium (SiGe) epitaxial structure, and the second source / drain portion 22 can include a SiGe epitaxial portion and a cap layer at the top; this cap layer is used to reduce the contact resistance of the source / drain structure S / D. Of course, the second source / drain portion 22 can also be entirely a cap layer, and this embodiment of the application does not limit this. As illustrated, the cap layer can be a boron silicon (SiB) epitaxial structure, but is not limited to this.

[0085] Of course, if the second source / drain portion 22 may include a SiGe epitaxial portion and a cap layer, the dielectric structure c may be disposed on the side of the SiGe epitaxial portion or on the side of the cap layer. This application does not limit this, and it can be designed as needed in practice.

[0086] As illustrated in Figure 7, the SiGe epitaxial portion in the second source / drain portion 22 is shown as a sloping side, the cap layer is shown as a vertical top side, and the dielectric structure c is located on the side of the SiGe epitaxial portion in the second source / drain portion 22.

[0087] Furthermore, this application does not limit the shape of the groove 20 mentioned above; in practice, it can be set as needed.

[0088] For example, in some possible implementations, as shown in Figure 8, the trench 20 can be a sigma trench, that is, the cross-section of the sidewall of the trench 20 is Σ-shaped.

[0089] For example, in some possible implementations, as shown in Figure 9, the groove 20 can be a U-shaped groove, that is, the cross-section of the groove 20 is U-shaped.

[0090] It should be understood that, compared to U-shaped trenches, using sigma trenches can enhance the stress applied to the channel by embedded source / drain structures (such as germanium-silicon), which is more conducive to improving hole mobility.

[0091] Of course, the chip may also contain other structures, such as a dielectric layer above the gate (G) and source / drain structures (S / D), and contact holes in the dielectric layer. This application does not limit these; the design can be based on the actual chip requirements.

[0092] The following section will further explain the configuration of the aforementioned dielectric structure c, in conjunction with the chip fabrication method.

[0093] As illustrated in Figure 10, this application embodiment provides a method for manufacturing a chip, which may include:

[0094] Step 10: Referring to Figure 11, a plurality of gates G are fabricated on the substrate 10. A gate hard mask layer HM0 is formed on the top of the gates G, and a first sidewall SP1 is formed on the sidewall of the gates G. Then, the first hard mask layer HM1 and the second hard mask layer HM2 are deposited sequentially.

[0095] Indicatively, in some possible implementations, step 10 may include: referring to FIG11, providing a silicon substrate 10 (also referred to as a silicon wafer), and forming a plurality of gates G on the surface of the silicon substrate 10; wherein, the gates G may be made of polysilicon. Then, a gate hard mask layer HM0 is formed on top of the gates G, and a first sidewall SP1 is formed on the sidewalls of the gates G. Subsequently, a first hard mask layer HM1 and a second hard mask layer HM2 are deposited sequentially. The first hard mask layer HM1 may be a silicon oxide layer with a thickness of approximately 1 nm to 6 nm formed using an atomic layer deposition (ALD) process; the second hard mask layer HM2 may be a silicon nitride layer with a thickness of approximately 5 nm to 30 nm formed using a furnace tube deposition process.

[0096] Step 20: Referring to Figure 12, the substrate 10 located on the side of the gate G is etched to form a trench 20, and the trench 20 is epitaxially pre-cleaned.

[0097] Schematic, referring to Figure 12(a), due to the height difference between the gate G and the surface of the substrate 10, the first hard mask layer HM1 and the second hard mask layer HM2 form a recess between the two gates G. Thus, the first hard mask layer HM1 and the second hard mask layer HM2 can be used as masks to etch the substrate 10 along the location of the recess to form a trench 20. Then, referring to Figure 12(b), the trench 20 is epitaxially cleaned in situ to remove the native oxide layer on the inner surface of the trench 20, and simultaneously remove the first hard mask layer HM1 covering the surface of the substrate 10. This exposes the bottom b of the first sidewall SP1.

[0098] Indicatively, in some possible implementations, the process of etching the substrate 10 to form the trench 20 may include: first, dry etching the substrate 10 to form a bowl-shaped or U-shaped groove; wherein the etching gas used in the dry etching can be one or more of chlorine, hydrogen chloride, hydrogen bromide, carbon tetrafluoride, nitrogen trifluoride, etc., and the etching time can be 50s to 150s. Then, wet etching is used to further etch the formed bowl-shaped or U-shaped trench to form a sigma trench; wherein the etching solution used in the wet etching can be one or more of TMAH (tetramethylammonium hydroxide), ammonia, etc., and the etching time can be 100s to 400s.

[0099] Indicatively, in some possible implementations, the above-mentioned epitaxial in-situ cleaning of trench 20 may include: using hydrogen fluoride (HF) and ammonia (NH3) to perform epitaxial in-situ cleaning of the native oxide (such as silicon oxide) on the inner surface of trench 20; at the same time, the first hard mask layer HM1 at the trench opening of trench 20 will be removed, thereby exposing the bottom b of the first sidewall SP1.

[0100] Step 30: Referring to Figure 13, a source / drain structure S / D is grown in the trench 20 by an epitaxial growth process; wherein, the source / drain structure S / D includes a first source / drain portion 21 located in the trench and a second source / drain portion 22 protruding from the surface of the substrate 10.

[0101] Indicatively, in some possible implementations, step 30 may include: referring to FIG13, growing SiGe in trench 20 by SiGe epitaxial growth process, wherein the SiGe epitaxial portion located in trench 20 serves as the first source / drain portion 21, and SiGe can continue to grow above the surface of substrate 10, and then grow a cap layer (SiB) as the second source / drain portion 22; of course, the cap layer (SiB) can also be directly grown above the surface of substrate 10 as the second source / drain portion 22.

[0102] To avoid completely removing the second hard mask layer HM2 in subsequent processes, which would cause the etching solution to contact the bottom b of the first sidewall SP1 and damage the bottom b of the first sidewall SP1, in some possible implementations, referring to Figure 13, the height of the source / drain structure S / D can be increased by controlling epitaxial growth in step 30 above, thereby increasing the aspect ratio (d / w) of the second hard mask layer HM2 located on the side of the second source / drain portion 22. This reduces the contact area between the etching solution and the bottom of the second hard mask layer HM2, thereby reducing the etching rate at the bottom of the second hard mask layer HM2. In this way, while satisfying the removal of the gate hard mask layer HM0 and other areas of the second hard mask layer HM2, only the bottom part of the second hard mask layer HM2 needs to be retained. For details, please refer to step 40 below.

[0103] This application does not impose any limitation on the aspect ratio (d / w) of the second hard mask layer HM2 on the S / D side of the source / drain structure. For example, in some possible implementations, the aspect ratio (d / w) of the second hard mask layer HM2 located on the side of the second source / drain portion 22 can be controlled to be greater than or equal to 1.5; it can also be said that the ratio of the height of the second source / drain portion 22 to the thickness of the second hard mask layer HM2 is greater than or equal to 1.5.

[0104] For example, in some embodiments, the height of the second source / drain portion 22 may be greater than or equal to 30 nm, and the thickness of the second hard mask layer HM2 may be less than or equal to 20 nm; but it is not limited thereto.

[0105] Step 40: Referring to FIG14, the gate hard mask layer HM0 and the second hard mask layer HM2 are etched to remove the gate hard mask layer HM0 and retain at least a portion of the second hard mask layer HM2 (i.e., dielectric structure c) located between the second source / drain portion 22 and the first hard mask layer HM1.

[0106] Schematic, in some possible implementations, referring to Figure 14, step 40 may include: wet etching the gate hard mask layer HM0 and the second hard mask layer HM2 using an etching solution including phosphoric acid, with the etching time controlled between 200s and 500s (but not limited thereto), to remove the gate hard mask layer HM0 and retain at least a portion of the second hard mask layer HM2 at the bottom as the dielectric structure c. In this case, the retained dielectric structure c spans between the second source / drain portion 22 and the first hard mask layer HM1, that is, both sides of the dielectric structure c are in contact with the second source / drain portion 22 and the first hard mask layer HM1, respectively, thereby preventing the etching solution from contacting the bottom of the first sidewall SP1 downwards, thus avoiding damage to the bottom of the first sidewall SP1.

[0107] Step 50: Remove the first hard mask layer HM1.

[0108] Schematic, in some possible implementations, referring to Figure 15, step 50 may include: wet etching the first hard mask layer HM1 using an etching solution including hydrofluoric acid (HF) to remove the first hard mask layer HM1.

[0109] Step 60: Referring to Figure 4, fabricate a second sidewall SP2 between the first sidewall SP1 and the source / drain structure S / D.

[0110] Schematic, referring to Figures 6 and 7, in some possible implementations, step 60 may include: depositing a silicon oxide layer 31 and a silicon nitride layer 32 sequentially between the first sidewall SP1 and the source / drain structure S / D to form a second sidewall SP2.

[0111] It should be understood that after removing the first hard mask layer HM1 in step 50, a gap will be formed between the dielectric structure c and the first sidewall SP1. The second sidewall SP2 formed in step 60 may fill the gap or may not fill the gap, depending on the specific process.

[0112] For example, referring to Figure 6, in some possible implementations, a silicon oxide layer 31 is first fabricated in step 60. Since the gap between the dielectric structure c and the first sidewall SP1 is small, the silicon oxide layer 31 extends from the side of the first sidewall SP1 to cover the upper surface of the dielectric structure c, but does not fill the gap; then, a silicon nitride layer 32 is fabricated.

[0113] For example, referring to Figure 7, in some possible implementations, a silicon oxide layer 31 is first fabricated in step 60. Since the gap between the dielectric structure c and the first sidewall SP1 is large, the silicon oxide layer 31 extends from the side of the first sidewall SP1 to cover the upper surface of the dielectric structure c and fills the gap; then, a silicon nitride layer 32 is fabricated.

[0114] Of course, after completing the second sidewall SP2, other subsequent processes can be carried out according to actual needs and with reference to relevant technologies, and this application does not impose any restrictions on this.

[0115] It should be understood that the present invention can be applied to any chip that requires epitaxial fabrication of source-drain structures, such as memory chips, logic chips, microprocessors, etc.

[0116] It should also be understood that, in the embodiments of this application, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0117] For other related content in the above manufacturing method, please refer to the corresponding parts in the aforementioned chip structure embodiment, which will not be repeated here; for other settings in the aforementioned chip structure embodiment, please refer to the above manufacturing method and related manufacturing methods for adjustment, which will not be repeated here.

[0118] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized in that, Including field-effect transistors disposed on the substrate; The field-effect transistor includes: A gate is disposed on the substrate; A first sidewall and a second sidewall are sequentially stacked on the gate sidewall; wherein the bottom of the first sidewall is in contact with the substrate; The source / drain structure includes a first source / drain portion located in the substrate and a second source / drain portion protruding from the surface of the substrate; The dielectric structure protrudes from the side of the second source / drain portion toward the gate, and at least a portion of the structure of the second sidewall is disposed on the dielectric structure.

2. The chip according to claim 1, characterized in that, The ratio between the height of the second source / drain section and the thickness of the second sidewall is greater than or equal to 1.

5.

3. The chip according to claim 1 or 2, characterized in that, The second sidewall fills the gap between the medium structure and the first sidewall.

4. The chip according to claim 1 or 2, characterized in that, There is a gap between the medium structure and the first sidewall.

5. The chip according to any one of claims 1-4, characterized in that, The second sidewall includes a silicon oxide layer and a silicon nitride layer; the silicon oxide layer is closer to the first sidewall than the silicon nitride layer.

6. The chip according to claim 5, characterized in that, The silicon oxide layer extends to the surface of the dielectric structure away from the substrate, and there is a gap between the dielectric structure and the first sidewall.

7. The chip according to claim 5, characterized in that, The silicon oxide layer extends to the surface of the dielectric structure away from the substrate, and the silicon oxide layer fills the gap between the dielectric structure and the first sidewall.

8. The chip according to any one of claims 1-7, characterized in that, The dielectric structure includes silicon nitride.

9. The chip according to any one of claims 1-8, characterized in that, The field-effect transistor is a P-type field-effect transistor.

10. The chip according to any one of claims 1-9, characterized in that, The first source / drain portion is formed in a trench on the substrate, the trench being a sigma trench.

11. The chip according to any one of claims 1-10, characterized in that, The first source / drain portion is formed in a trench on the substrate, the trench being a U-shaped groove.

12. The chip according to any one of claims 1-11, characterized in that, The substrate is a silicon substrate; The source / drain structure is a germanium-silicon epitaxial structure.

13. A method for manufacturing a chip, characterized in that, include: Multiple gates are fabricated on a substrate, a gate hard mask layer is formed on top of the gates, a first sidewall is formed on the sidewall of the gates, and then a first hard mask layer and a second hard mask layer are deposited sequentially. The substrate located on the side of the gate is etched to form trenches, and the trenches are then epitaxially cleaned in situ. A source / drain structure is grown in the trench using an epitaxial growth process; wherein the source / drain structure includes a first source / drain portion located in the trench and a second source / drain portion protruding from the surface of the substrate; The gate hard mask layer and the second hard mask layer are etched to remove the gate hard mask layer and retain at least a portion of the second hard mask layer located between the second source / drain portion and the first hard mask layer. Remove the first hard mask layer; A second sidewall is fabricated between the first sidewall and the source / drain structure.

14. The method for manufacturing a chip according to claim 13, characterized in that, The epitaxial growth process for growing source-drain structures in the trench includes: The source / drain structure is grown in the trench using an epitaxial growth process, and the ratio between the height of the second source / drain portion and the thickness of the second hard mask layer is controlled to be greater than or equal to 1.

5.

15. The method for manufacturing a chip according to claim 13 or 14, characterized in that, The etching of the gate hard mask layer and the second hard mask layer includes: The gate hard mask layer and the second hard mask layer are etched using an etching solution containing phosphoric acid.

16. The method for manufacturing a chip according to any one of claims 13-15, characterized in that, The removal of the first hard mask layer includes: The first hard mask layer is etched using an etching solution containing hydrofluoric acid to remove it.

17. The method for manufacturing a chip according to any one of claims 13-16, characterized in that, The epitaxial in-situ cleaning of the trench includes: Remove the oxide from the inner surface of the trench and remove the first hard mask layer covering the substrate surface to expose the bottom of the first sidewall.

18. The method for manufacturing a chip according to any one of claims 13-17, characterized in that, The etching of the substrate located on the side of the gate to form trenches includes: The substrate located on the side of the gate is first dry etched and then wet etched to form a sigma trench.

19. A semiconductor device, characterized in that, It includes the chip and controller as described in any one of claims 1-12, wherein the chip is electrically connected to the controller.

20. An electronic device, characterized in that, It includes a circuit board and a chip as described in any one of claims 1-12; wherein the circuit board is electrically connected to the chip.

Images